2 * Status and system control registers for ARM RealView/Versatile boards.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
11 #include "primecell.h"
14 #define LOCK_VALUE 0xa05f
28 static uint32_t arm_sysctl_read(void *opaque
, target_phys_addr_t offset
)
30 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
36 /* General purpose hardware switches.
37 We don't have a useful way of exposing these to the user. */
48 case 0x24: /* 100HZ */
49 /* ??? Implement these. */
51 case 0x28: /* CFGDATA1 */
53 case 0x2c: /* CFGDATA2 */
55 case 0x30: /* FLAGS */
57 case 0x38: /* NVFLAGS */
59 case 0x40: /* RESETCTL */
61 case 0x44: /* PCICTL */
65 case 0x4c: /* FLASH */
69 case 0x54: /* CLCDSER */
71 case 0x58: /* BOOTCS */
73 case 0x5c: /* 24MHz */
74 /* ??? not implemented. */
78 case 0x84: /* PROCID0 */
79 /* ??? Don't know what the proper value for the core tile ID is. */
81 case 0x88: /* PROCID1 */
83 case 0x64: /* DMAPSR0 */
84 case 0x68: /* DMAPSR1 */
85 case 0x6c: /* DMAPSR2 */
86 case 0x70: /* IOSEL */
87 case 0x74: /* PLDCTL */
88 case 0x80: /* BUSID */
89 case 0x8c: /* OSCRESET0 */
90 case 0x90: /* OSCRESET1 */
91 case 0x94: /* OSCRESET2 */
92 case 0x98: /* OSCRESET3 */
93 case 0x9c: /* OSCRESET4 */
94 case 0xc0: /* SYS_TEST_OSC0 */
95 case 0xc4: /* SYS_TEST_OSC1 */
96 case 0xc8: /* SYS_TEST_OSC2 */
97 case 0xcc: /* SYS_TEST_OSC3 */
98 case 0xd0: /* SYS_TEST_OSC4 */
101 printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset
);
106 static void arm_sysctl_write(void *opaque
, target_phys_addr_t offset
,
109 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
114 case 0x0c: /* OSC0 */
115 case 0x10: /* OSC1 */
116 case 0x14: /* OSC2 */
117 case 0x18: /* OSC3 */
118 case 0x1c: /* OSC4 */
121 case 0x20: /* LOCK */
122 if (val
== LOCK_VALUE
)
125 s
->lockval
= val
& 0x7fff;
127 case 0x28: /* CFGDATA1 */
128 /* ??? Need to implement this. */
131 case 0x2c: /* CFGDATA2 */
132 /* ??? Need to implement this. */
135 case 0x30: /* FLAGSSET */
138 case 0x34: /* FLAGSCLR */
141 case 0x38: /* NVFLAGSSET */
144 case 0x3c: /* NVFLAGSCLR */
147 case 0x40: /* RESETCTL */
148 if (s
->lockval
== LOCK_VALUE
) {
151 qemu_system_reset_request ();
154 case 0x44: /* PCICTL */
157 case 0x4c: /* FLASH */
158 case 0x50: /* CLCD */
159 case 0x54: /* CLCDSER */
160 case 0x64: /* DMAPSR0 */
161 case 0x68: /* DMAPSR1 */
162 case 0x6c: /* DMAPSR2 */
163 case 0x70: /* IOSEL */
164 case 0x74: /* PLDCTL */
165 case 0x80: /* BUSID */
166 case 0x84: /* PROCID0 */
167 case 0x88: /* PROCID1 */
168 case 0x8c: /* OSCRESET0 */
169 case 0x90: /* OSCRESET1 */
170 case 0x94: /* OSCRESET2 */
171 case 0x98: /* OSCRESET3 */
172 case 0x9c: /* OSCRESET4 */
175 printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset
);
180 static CPUReadMemoryFunc
* const arm_sysctl_readfn
[] = {
186 static CPUWriteMemoryFunc
* const arm_sysctl_writefn
[] = {
192 static void arm_sysctl_init1(SysBusDevice
*dev
)
194 arm_sysctl_state
*s
= FROM_SYSBUS(arm_sysctl_state
, dev
);
197 /* The MPcore bootloader uses these flags to start secondary CPUs.
198 We don't use a bootloader, so do this here. */
200 iomemtype
= cpu_register_io_memory(arm_sysctl_readfn
,
201 arm_sysctl_writefn
, s
);
202 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
203 /* ??? Save/restore. */
206 /* Legacy helper function. */
207 void arm_sysctl_init(uint32_t base
, uint32_t sys_id
)
211 dev
= qdev_create(NULL
, "realview_sysctl");
212 qdev_prop_set_uint32(dev
, "sys_id", sys_id
);
214 sysbus_mmio_map(sysbus_from_qdev(dev
), 0, base
);
217 static SysBusDeviceInfo arm_sysctl_info
= {
218 .init
= arm_sysctl_init1
,
219 .qdev
.name
= "realview_sysctl",
220 .qdev
.size
= sizeof(arm_sysctl_state
),
221 .qdev
.props
= (Property
[]) {
222 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state
, sys_id
, 0),
223 DEFINE_PROP_END_OF_LIST(),
227 static void arm_sysctl_register_devices(void)
229 sysbus_register_withprop(&arm_sysctl_info
);
232 device_init(arm_sysctl_register_devices
)