target-tricore: Add instructions of RR opcode format, that have 0xb as the first...
[qemu.git] / target-arm / gdbstub64.c
blob8f3b8d1778202dd8d8f9266c1626b4a60ca6e370
1 /*
2 * ARM gdb server stub: AArch64 specific functions.
4 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "config.h"
20 #include "qemu-common.h"
21 #include "exec/gdbstub.h"
23 int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
25 ARMCPU *cpu = ARM_CPU(cs);
26 CPUARMState *env = &cpu->env;
28 if (n < 31) {
29 /* Core integer register. */
30 return gdb_get_reg64(mem_buf, env->xregs[n]);
32 switch (n) {
33 case 31:
34 return gdb_get_reg64(mem_buf, env->xregs[31]);
35 case 32:
36 return gdb_get_reg64(mem_buf, env->pc);
37 case 33:
38 return gdb_get_reg32(mem_buf, pstate_read(env));
40 /* Unknown register. */
41 return 0;
44 int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
46 ARMCPU *cpu = ARM_CPU(cs);
47 CPUARMState *env = &cpu->env;
48 uint64_t tmp;
50 tmp = ldq_p(mem_buf);
52 if (n < 31) {
53 /* Core integer register. */
54 env->xregs[n] = tmp;
55 return 8;
57 switch (n) {
58 case 31:
59 env->xregs[31] = tmp;
60 return 8;
61 case 32:
62 env->pc = tmp;
63 return 8;
64 case 33:
65 /* CPSR */
66 pstate_write(env, tmp);
67 return 4;
69 /* Unknown register. */
70 return 0;