target-tricore: Add instructions of RR opcode format, that have 0xb as the first...
[qemu.git] / target-arm / arm_ldst.h
blobb1ece01731f56bfdab94d30fa120c23345e129e5
1 /*
2 * ARM load/store instructions for code (armeb-user support)
4 * Copyright (c) 2012 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef ARM_LDST_H
21 #define ARM_LDST_H
23 #include "exec/cpu_ldst.h"
24 #include "qemu/bswap.h"
26 /* Load an instruction and return it in the standard little-endian order */
27 static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
28 bool do_swap)
30 uint32_t insn = cpu_ldl_code(env, addr);
31 if (do_swap) {
32 return bswap32(insn);
34 return insn;
37 /* Ditto, for a halfword (Thumb) instruction */
38 static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
39 bool do_swap)
41 uint16_t insn = cpu_lduw_code(env, addr);
42 if (do_swap) {
43 return bswap16(insn);
45 return insn;
48 #endif