target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <assert.h>
  20 #include <stdlib.h>
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 #ifndef CONFIG_USER_ONLY
  25 #include "exec/softmmu_exec.h"
  26
  27 #define MMUSUFFIX _mmu
  28
  29 #define SHIFT 0
  30 #include "exec/softmmu_template.h"
  31
  32 #define SHIFT 1
  33 #include "exec/softmmu_template.h"
  34
  35 #define SHIFT 2
  36 #include "exec/softmmu_template.h"
  37
  38 #define SHIFT 3
  39 #include "exec/softmmu_template.h"
  40
  41 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  42               uintptr_t retaddr)
  43 {
  44     int ret;
  45
  46     ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  47     if (ret) {
  48         /* now we have a real cpu fault */
  49         SuperHCPU *cpu = SUPERH_CPU(cs);
  50         CPUSH4State *env = &cpu->env;
  51
  52         if (retaddr) {
  53             cpu_restore_state(env, retaddr);
  54         }
  55         cpu_loop_exit(env);
  56     }
  57 }
  58
  59 #endif
  60
  61 void helper_ldtlb(CPUSH4State *env)
  62 {
  63 #ifdef CONFIG_USER_ONLY
  64     /* XXXXX */
  65     cpu_abort(env, "Unhandled ldtlb");
  66 #else
  67     cpu_load_tlb(env);
  68 #endif
  69 }
  70
  71 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  72                                                  uintptr_t retaddr)
  73 {
  74     CPUState *cs = CPU(sh_env_get_cpu(env));
  75
  76     cs->exception_index = index;
  77     if (retaddr) {
  78         cpu_restore_state(env, retaddr);
  79     }
  80     cpu_loop_exit(env);
  81 }
  82
  83 void helper_raise_illegal_instruction(CPUSH4State *env)
  84 {
  85     raise_exception(env, 0x180, 0);
  86 }
  87
  88 void helper_raise_slot_illegal_instruction(CPUSH4State *env)
  89 {
  90     raise_exception(env, 0x1a0, 0);
  91 }
  92
  93 void helper_raise_fpu_disable(CPUSH4State *env)
  94 {
  95     raise_exception(env, 0x800, 0);
  96 }
  97
  98 void helper_raise_slot_fpu_disable(CPUSH4State *env)
  99 {
 100     raise_exception(env, 0x820, 0);
 101 }
 102
 103 void helper_debug(CPUSH4State *env)
 104 {
 105     raise_exception(env, EXCP_DEBUG, 0);
 106 }
 107
 108 void helper_sleep(CPUSH4State *env)
 109 {
 110     CPUState *cs = CPU(sh_env_get_cpu(env));
 111
 112     cs->halted = 1;
 113     env->in_sleep = 1;
 114     raise_exception(env, EXCP_HLT, 0);
 115 }
 116
 117 void helper_trapa(CPUSH4State *env, uint32_t tra)
 118 {
 119     env->tra = tra << 2;
 120     raise_exception(env, 0x160, 0);
 121 }
 122
 123 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 124 {
 125     if (cpu_sh4_is_cached (env, address))
 126     {
 127         memory_content *r = malloc (sizeof(memory_content));
 128         r->address = address;
 129         r->value = value;
 130         r->next = NULL;
 131
 132         *(env->movcal_backup_tail) = r;
 133         env->movcal_backup_tail = &(r->next);
 134     }
 135 }
 136
 137 void helper_discard_movcal_backup(CPUSH4State *env)
 138 {
 139     memory_content *current = env->movcal_backup;
 140
 141     while(current)
 142     {
 143         memory_content *next = current->next;
 144         free (current);
 145         env->movcal_backup = current = next;
 146         if (current == NULL)
 147             env->movcal_backup_tail = &(env->movcal_backup);
 148     }
 149 }
 150
 151 void helper_ocbi(CPUSH4State *env, uint32_t address)
 152 {
 153     memory_content **current = &(env->movcal_backup);
 154     while (*current)
 155     {
 156         uint32_t a = (*current)->address;
 157         if ((a & ~0x1F) == (address & ~0x1F))
 158         {
 159             memory_content *next = (*current)->next;
 160             cpu_stl_data(env, a, (*current)->value);
 161
 162             if (next == NULL)
 163             {
 164                 env->movcal_backup_tail = current;
 165             }
 166
 167             free (*current);
 168             *current = next;
 169             break;
 170         }
 171     }
 172 }
 173
 174 #define T (env->sr & SR_T)
 175 #define Q (env->sr & SR_Q ? 1 : 0)
 176 #define M (env->sr & SR_M ? 1 : 0)
 177 #define SETT env->sr |= SR_T
 178 #define CLRT env->sr &= ~SR_T
 179 #define SETQ env->sr |= SR_Q
 180 #define CLRQ env->sr &= ~SR_Q
 181 #define SETM env->sr |= SR_M
 182 #define CLRM env->sr &= ~SR_M
 183
 184 uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 185 {
 186     uint32_t tmp0, tmp2;
 187     uint8_t old_q, tmp1 = 0xff;
 188
 189     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 190     old_q = Q;
 191     if ((0x80000000 & arg1) != 0)
 192         SETQ;
 193     else
 194         CLRQ;
 195     tmp2 = arg0;
 196     arg1 <<= 1;
 197     arg1 |= T;
 198     switch (old_q) {
 199     case 0:
 200         switch (M) {
 201         case 0:
 202             tmp0 = arg1;
 203             arg1 -= tmp2;
 204             tmp1 = arg1 > tmp0;
 205             switch (Q) {
 206             case 0:
 207                 if (tmp1)
 208                     SETQ;
 209                 else
 210                     CLRQ;
 211                 break;
 212             case 1:
 213                 if (tmp1 == 0)
 214                     SETQ;
 215                 else
 216                     CLRQ;
 217                 break;
 218             }
 219             break;
 220         case 1:
 221             tmp0 = arg1;
 222             arg1 += tmp2;
 223             tmp1 = arg1 < tmp0;
 224             switch (Q) {
 225             case 0:
 226                 if (tmp1 == 0)
 227                     SETQ;
 228                 else
 229                     CLRQ;
 230                 break;
 231             case 1:
 232                 if (tmp1)
 233                     SETQ;
 234                 else
 235                     CLRQ;
 236                 break;
 237             }
 238             break;
 239         }
 240         break;
 241     case 1:
 242         switch (M) {
 243         case 0:
 244             tmp0 = arg1;
 245             arg1 += tmp2;
 246             tmp1 = arg1 < tmp0;
 247             switch (Q) {
 248             case 0:
 249                 if (tmp1)
 250                     SETQ;
 251                 else
 252                     CLRQ;
 253                 break;
 254             case 1:
 255                 if (tmp1 == 0)
 256                     SETQ;
 257                 else
 258                     CLRQ;
 259                 break;
 260             }
 261             break;
 262         case 1:
 263             tmp0 = arg1;
 264             arg1 -= tmp2;
 265             tmp1 = arg1 > tmp0;
 266             switch (Q) {
 267             case 0:
 268                 if (tmp1 == 0)
 269                     SETQ;
 270                 else
 271                     CLRQ;
 272                 break;
 273             case 1:
 274                 if (tmp1)
 275                     SETQ;
 276                 else
 277                     CLRQ;
 278                 break;
 279             }
 280             break;
 281         }
 282         break;
 283     }
 284     if (Q == M)
 285         SETT;
 286     else
 287         CLRT;
 288     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 289     return arg1;
 290 }
 291
 292 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 293 {
 294     int64_t res;
 295
 296     res = ((uint64_t) env->mach << 32) | env->macl;
 297     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 298     env->mach = (res >> 32) & 0xffffffff;
 299     env->macl = res & 0xffffffff;
 300     if (env->sr & SR_S) {
 301         if (res < 0)
 302             env->mach |= 0xffff0000;
 303         else
 304             env->mach &= 0x00007fff;
 305     }
 306 }
 307
 308 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 309 {
 310     int64_t res;
 311
 312     res = ((uint64_t) env->mach << 32) | env->macl;
 313     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 314     env->mach = (res >> 32) & 0xffffffff;
 315     env->macl = res & 0xffffffff;
 316     if (env->sr & SR_S) {
 317         if (res < -0x80000000) {
 318             env->mach = 1;
 319             env->macl = 0x80000000;
 320         } else if (res > 0x000000007fffffff) {
 321             env->mach = 1;
 322             env->macl = 0x7fffffff;
 323         }
 324     }
 325 }
 326
 327 static inline void set_t(CPUSH4State *env)
 328 {
 329     env->sr |= SR_T;
 330 }
 331
 332 static inline void clr_t(CPUSH4State *env)
 333 {
 334     env->sr &= ~SR_T;
 335 }
 336
 337 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 338 {
 339     env->fpscr = val & FPSCR_MASK;
 340     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 341         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 342     } else {
 343         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 344     }
 345     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 346 }
 347
 348 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 349 {
 350     int xcpt, cause, enable;
 351
 352     xcpt = get_float_exception_flags(&env->fp_status);
 353
 354     /* Clear the flag entries */
 355     env->fpscr &= ~FPSCR_FLAG_MASK;
 356
 357     if (unlikely(xcpt)) {
 358         if (xcpt & float_flag_invalid) {
 359             env->fpscr |= FPSCR_FLAG_V;
 360         }
 361         if (xcpt & float_flag_divbyzero) {
 362             env->fpscr |= FPSCR_FLAG_Z;
 363         }
 364         if (xcpt & float_flag_overflow) {
 365             env->fpscr |= FPSCR_FLAG_O;
 366         }
 367         if (xcpt & float_flag_underflow) {
 368             env->fpscr |= FPSCR_FLAG_U;
 369         }
 370         if (xcpt & float_flag_inexact) {
 371             env->fpscr |= FPSCR_FLAG_I;
 372         }
 373
 374         /* Accumulate in cause entries */
 375         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 376                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 377
 378         /* Generate an exception if enabled */
 379         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 380         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 381         if (cause & enable) {
 382             raise_exception(env, 0x120, retaddr);
 383         }
 384     }
 385 }
 386
 387 float32 helper_fabs_FT(float32 t0)
 388 {
 389     return float32_abs(t0);
 390 }
 391
 392 float64 helper_fabs_DT(float64 t0)
 393 {
 394     return float64_abs(t0);
 395 }
 396
 397 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 398 {
 399     set_float_exception_flags(0, &env->fp_status);
 400     t0 = float32_add(t0, t1, &env->fp_status);
 401     update_fpscr(env, GETPC());
 402     return t0;
 403 }
 404
 405 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 406 {
 407     set_float_exception_flags(0, &env->fp_status);
 408     t0 = float64_add(t0, t1, &env->fp_status);
 409     update_fpscr(env, GETPC());
 410     return t0;
 411 }
 412
 413 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 414 {
 415     int relation;
 416
 417     set_float_exception_flags(0, &env->fp_status);
 418     relation = float32_compare(t0, t1, &env->fp_status);
 419     if (unlikely(relation == float_relation_unordered)) {
 420         update_fpscr(env, GETPC());
 421     } else if (relation == float_relation_equal) {
 422         set_t(env);
 423     } else {
 424         clr_t(env);
 425     }
 426 }
 427
 428 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 429 {
 430     int relation;
 431
 432     set_float_exception_flags(0, &env->fp_status);
 433     relation = float64_compare(t0, t1, &env->fp_status);
 434     if (unlikely(relation == float_relation_unordered)) {
 435         update_fpscr(env, GETPC());
 436     } else if (relation == float_relation_equal) {
 437         set_t(env);
 438     } else {
 439         clr_t(env);
 440     }
 441 }
 442
 443 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 444 {
 445     int relation;
 446
 447     set_float_exception_flags(0, &env->fp_status);
 448     relation = float32_compare(t0, t1, &env->fp_status);
 449     if (unlikely(relation == float_relation_unordered)) {
 450         update_fpscr(env, GETPC());
 451     } else if (relation == float_relation_greater) {
 452         set_t(env);
 453     } else {
 454         clr_t(env);
 455     }
 456 }
 457
 458 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 459 {
 460     int relation;
 461
 462     set_float_exception_flags(0, &env->fp_status);
 463     relation = float64_compare(t0, t1, &env->fp_status);
 464     if (unlikely(relation == float_relation_unordered)) {
 465         update_fpscr(env, GETPC());
 466     } else if (relation == float_relation_greater) {
 467         set_t(env);
 468     } else {
 469         clr_t(env);
 470     }
 471 }
 472
 473 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 474 {
 475     float64 ret;
 476     set_float_exception_flags(0, &env->fp_status);
 477     ret = float32_to_float64(t0, &env->fp_status);
 478     update_fpscr(env, GETPC());
 479     return ret;
 480 }
 481
 482 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 483 {
 484     float32 ret;
 485     set_float_exception_flags(0, &env->fp_status);
 486     ret = float64_to_float32(t0, &env->fp_status);
 487     update_fpscr(env, GETPC());
 488     return ret;
 489 }
 490
 491 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 492 {
 493     set_float_exception_flags(0, &env->fp_status);
 494     t0 = float32_div(t0, t1, &env->fp_status);
 495     update_fpscr(env, GETPC());
 496     return t0;
 497 }
 498
 499 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 500 {
 501     set_float_exception_flags(0, &env->fp_status);
 502     t0 = float64_div(t0, t1, &env->fp_status);
 503     update_fpscr(env, GETPC());
 504     return t0;
 505 }
 506
 507 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 508 {
 509     float32 ret;
 510     set_float_exception_flags(0, &env->fp_status);
 511     ret = int32_to_float32(t0, &env->fp_status);
 512     update_fpscr(env, GETPC());
 513     return ret;
 514 }
 515
 516 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 517 {
 518     float64 ret;
 519     set_float_exception_flags(0, &env->fp_status);
 520     ret = int32_to_float64(t0, &env->fp_status);
 521     update_fpscr(env, GETPC());
 522     return ret;
 523 }
 524
 525 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 526 {
 527     set_float_exception_flags(0, &env->fp_status);
 528     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 529     update_fpscr(env, GETPC());
 530     return t0;
 531 }
 532
 533 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 534 {
 535     set_float_exception_flags(0, &env->fp_status);
 536     t0 = float32_mul(t0, t1, &env->fp_status);
 537     update_fpscr(env, GETPC());
 538     return t0;
 539 }
 540
 541 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 542 {
 543     set_float_exception_flags(0, &env->fp_status);
 544     t0 = float64_mul(t0, t1, &env->fp_status);
 545     update_fpscr(env, GETPC());
 546     return t0;
 547 }
 548
 549 float32 helper_fneg_T(float32 t0)
 550 {
 551     return float32_chs(t0);
 552 }
 553
 554 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 555 {
 556     set_float_exception_flags(0, &env->fp_status);
 557     t0 = float32_sqrt(t0, &env->fp_status);
 558     update_fpscr(env, GETPC());
 559     return t0;
 560 }
 561
 562 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 563 {
 564     set_float_exception_flags(0, &env->fp_status);
 565     t0 = float64_sqrt(t0, &env->fp_status);
 566     update_fpscr(env, GETPC());
 567     return t0;
 568 }
 569
 570 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 571 {
 572     set_float_exception_flags(0, &env->fp_status);
 573     t0 = float32_sub(t0, t1, &env->fp_status);
 574     update_fpscr(env, GETPC());
 575     return t0;
 576 }
 577
 578 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 579 {
 580     set_float_exception_flags(0, &env->fp_status);
 581     t0 = float64_sub(t0, t1, &env->fp_status);
 582     update_fpscr(env, GETPC());
 583     return t0;
 584 }
 585
 586 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 587 {
 588     uint32_t ret;
 589     set_float_exception_flags(0, &env->fp_status);
 590     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 591     update_fpscr(env, GETPC());
 592     return ret;
 593 }
 594
 595 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 596 {
 597     uint32_t ret;
 598     set_float_exception_flags(0, &env->fp_status);
 599     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 600     update_fpscr(env, GETPC());
 601     return ret;
 602 }
 603
 604 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 605 {
 606     int bank, i;
 607     float32 r, p;
 608
 609     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 610     r = float32_zero;
 611     set_float_exception_flags(0, &env->fp_status);
 612
 613     for (i = 0 ; i < 4 ; i++) {
 614         p = float32_mul(env->fregs[bank + m + i],
 615                         env->fregs[bank + n + i],
 616                         &env->fp_status);
 617         r = float32_add(r, p, &env->fp_status);
 618     }
 619     update_fpscr(env, GETPC());
 620
 621     env->fregs[bank + n + 3] = r;
 622 }
 623
 624 void helper_ftrv(CPUSH4State *env, uint32_t n)
 625 {
 626     int bank_matrix, bank_vector;
 627     int i, j;
 628     float32 r[4];
 629     float32 p;
 630
 631     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 632     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 633     set_float_exception_flags(0, &env->fp_status);
 634     for (i = 0 ; i < 4 ; i++) {
 635         r[i] = float32_zero;
 636         for (j = 0 ; j < 4 ; j++) {
 637             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 638                             env->fregs[bank_vector + j],
 639                             &env->fp_status);
 640             r[i] = float32_add(r[i], p, &env->fp_status);
 641         }
 642     }
 643     update_fpscr(env, GETPC());
 644
 645     for (i = 0 ; i < 4 ; i++) {
 646         env->fregs[bank_vector + i] = r[i];
 647     }
 648 }