4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #define SIGNBIT (uint32_t)0x80000000
23 #define SIGNBIT64 ((uint64_t)1 << 63)
25 static void raise_exception(CPUARMState
*env
, int tt
)
27 env
->exception_index
= tt
;
31 uint32_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t ireg
, uint32_t def
,
32 uint32_t rn
, uint32_t maxindex
)
39 table
= (uint64_t *)&env
->vfp
.regs
[rn
];
41 for (shift
= 0; shift
< 32; shift
+= 8) {
42 index
= (ireg
>> shift
) & 0xff;
43 if (index
< maxindex
) {
44 tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
47 val
|= def
& (0xff << shift
);
53 #if !defined(CONFIG_USER_ONLY)
55 #include "exec/softmmu_exec.h"
57 #define MMUSUFFIX _mmu
60 #include "exec/softmmu_template.h"
63 #include "exec/softmmu_template.h"
66 #include "exec/softmmu_template.h"
69 #include "exec/softmmu_template.h"
71 /* try to fill the TLB and return an exception if error. If retaddr is
72 NULL, it means that the function was called in C code (i.e. not
73 from generated code or from helper.c) */
74 void tlb_fill(CPUARMState
*env
, target_ulong addr
, int is_write
, int mmu_idx
,
79 ret
= cpu_arm_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
);
82 /* now we have a real cpu fault */
83 cpu_restore_state(env
, retaddr
);
85 raise_exception(env
, env
->exception_index
);
90 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
93 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
98 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
100 uint32_t res
= a
+ b
;
101 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
103 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
108 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
110 uint32_t res
= a
- b
;
111 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
113 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
118 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
121 if (val
>= 0x40000000) {
124 } else if (val
<= (int32_t)0xc0000000) {
133 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
135 uint32_t res
= a
+ b
;
143 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
145 uint32_t res
= a
- b
;
153 /* Signed saturation. */
154 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
160 mask
= (1u << shift
) - 1;
164 } else if (top
< -1) {
171 /* Unsigned saturation. */
172 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
176 max
= (1u << shift
) - 1;
180 } else if (val
> max
) {
187 /* Signed saturate. */
188 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
190 return do_ssat(env
, x
, shift
);
193 /* Dual halfword signed saturate. */
194 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
198 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
199 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
203 /* Unsigned saturate. */
204 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
206 return do_usat(env
, x
, shift
);
209 /* Dual halfword unsigned saturate. */
210 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
214 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
215 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
219 void HELPER(wfi
)(CPUARMState
*env
)
221 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
223 env
->exception_index
= EXCP_HLT
;
228 void HELPER(wfe
)(CPUARMState
*env
)
230 /* Don't actually halt the CPU, just yield back to top
233 env
->exception_index
= EXCP_YIELD
;
237 void HELPER(exception
)(CPUARMState
*env
, uint32_t excp
)
239 env
->exception_index
= excp
;
243 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
245 return cpsr_read(env
) & ~CPSR_EXEC
;
248 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
250 cpsr_write(env
, val
, mask
);
253 /* Access to user mode registers from privileged modes. */
254 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
259 val
= env
->banked_r13
[0];
260 } else if (regno
== 14) {
261 val
= env
->banked_r14
[0];
262 } else if (regno
>= 8
263 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
264 val
= env
->usr_regs
[regno
- 8];
266 val
= env
->regs
[regno
];
271 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
274 env
->banked_r13
[0] = val
;
275 } else if (regno
== 14) {
276 env
->banked_r14
[0] = val
;
277 } else if (regno
>= 8
278 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
279 env
->usr_regs
[regno
- 8] = val
;
281 env
->regs
[regno
] = val
;
285 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
)
287 const ARMCPRegInfo
*ri
= rip
;
288 switch (ri
->accessfn(env
, ri
)) {
292 case CP_ACCESS_TRAP_UNCATEGORIZED
:
293 /* These cases will eventually need to generate different
294 * syndrome information.
298 g_assert_not_reached();
300 raise_exception(env
, EXCP_UDEF
);
303 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
305 const ARMCPRegInfo
*ri
= rip
;
307 ri
->writefn(env
, ri
, value
);
310 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
312 const ARMCPRegInfo
*ri
= rip
;
314 return ri
->readfn(env
, ri
);
317 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
319 const ARMCPRegInfo
*ri
= rip
;
321 ri
->writefn(env
, ri
, value
);
324 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
326 const ARMCPRegInfo
*ri
= rip
;
328 return ri
->readfn(env
, ri
);
331 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
333 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
334 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
335 * to catch that case at translate time.
337 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UMA
)) {
338 raise_exception(env
, EXCP_UDEF
);
342 case 0x05: /* SPSel */
343 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
345 case 0x1e: /* DAIFSet */
346 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
348 case 0x1f: /* DAIFClear */
349 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
352 g_assert_not_reached();
356 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
357 The only way to do that in TCG is a conditional branch, which clobbers
358 all our temporaries. For now implement these as helper functions. */
360 /* Similarly for variable shift instructions. */
362 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
364 int shift
= i
& 0xff;
371 } else if (shift
!= 0) {
372 env
->CF
= (x
>> (32 - shift
)) & 1;
378 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
380 int shift
= i
& 0xff;
383 env
->CF
= (x
>> 31) & 1;
387 } else if (shift
!= 0) {
388 env
->CF
= (x
>> (shift
- 1)) & 1;
394 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
396 int shift
= i
& 0xff;
398 env
->CF
= (x
>> 31) & 1;
399 return (int32_t)x
>> 31;
400 } else if (shift
!= 0) {
401 env
->CF
= (x
>> (shift
- 1)) & 1;
402 return (int32_t)x
>> shift
;
407 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
411 shift
= shift1
& 0x1f;
414 env
->CF
= (x
>> 31) & 1;
417 env
->CF
= (x
>> (shift
- 1)) & 1;
418 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));