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mc146818rtc: Move RTC_ISA_IRQ definition
[qemu.git] / target / arm / cpu.c
blob13813fb213544883a6dd0db424b42218b1d14669
1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
28 #include "cpu.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
35 #endif
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
39 #include "kvm_arm.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
42
43 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
44 {
45 ARMCPU *cpu = ARM_CPU(cs);
46 CPUARMState *env = &cpu->env;
47
48 if (is_a64(env)) {
49 env->pc = value;
50 env->thumb = 0;
51 } else {
52 env->regs[15] = value & ~1;
53 env->thumb = value & 1;
54 }
55 }
56
57 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
58 {
59 ARMCPU *cpu = ARM_CPU(cs);
60 CPUARMState *env = &cpu->env;
61
62 /*
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
65 */
66 if (is_a64(env)) {
67 env->pc = tb->pc;
68 } else {
69 env->regs[15] = tb->pc;
70 }
71 }
72
73 static bool arm_cpu_has_work(CPUState *cs)
74 {
75 ARMCPU *cpu = ARM_CPU(cs);
76
77 return (cpu->power_state != PSCI_OFF)
78 && cs->interrupt_request &
79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB);
82 }
83
84 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
85 void *opaque)
86 {
87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
88
89 entry->hook = hook;
90 entry->opaque = opaque;
91
92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
93 }
94
95 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
96 void *opaque)
97 {
98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
99
100 entry->hook = hook;
101 entry->opaque = opaque;
102
103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
104 }
105
106 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
107 {
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo *ri = value;
110 ARMCPU *cpu = opaque;
111
112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
113 return;
114 }
115
116 if (ri->resetfn) {
117 ri->resetfn(&cpu->env, ri);
118 return;
119 }
120
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
125 */
126 if (!ri->fieldoffset) {
127 return;
128 }
129
130 if (cpreg_field_is_64bit(ri)) {
131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
132 } else {
133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
134 }
135 }
136
137 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
138 {
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
143 */
144 ARMCPRegInfo *ri = value;
145 ARMCPU *cpu = opaque;
146 uint64_t oldvalue, newvalue;
147
148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
149 return;
150 }
151
152 oldvalue = read_raw_cp_reg(&cpu->env, ri);
153 cp_reg_reset(key, value, opaque);
154 newvalue = read_raw_cp_reg(&cpu->env, ri);
155 assert(oldvalue == newvalue);
156 }
157
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState *s)
160 {
161 ARMCPU *cpu = ARM_CPU(s);
162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
163 CPUARMState *env = &cpu->env;
164
165 acc->parent_reset(s);
166
167 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
168
169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
171
172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
176
177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
178 s->halted = cpu->start_powered_off;
179
180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
182 }
183
184 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
185 /* 64 bit CPUs always start in 64 bit mode */
186 env->aarch64 = 1;
187 #if defined(CONFIG_USER_ONLY)
188 env->pstate = PSTATE_MODE_EL0t;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
191 /* Enable all PAC keys. */
192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
193 SCTLR_EnDA | SCTLR_EnDB);
194 /* Enable all PAC instructions */
195 env->cp15.hcr_el2 |= HCR_API;
196 env->cp15.scr_el3 |= SCR_API;
197 /* and to the FP/Neon instructions */
198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
199 /* and to the SVE instructions */
200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
201 env->cp15.cptr_el[3] |= CPTR_EZ;
202 /* with maximum vector length */
203 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
204 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
205 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
206 /*
207 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
208 * turning on both here will produce smaller code and otherwise
209 * make no difference to the user-level emulation.
210 */
211 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
212 #else
213 /* Reset into the highest available EL */
214 if (arm_feature(env, ARM_FEATURE_EL3)) {
215 env->pstate = PSTATE_MODE_EL3h;
216 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
217 env->pstate = PSTATE_MODE_EL2h;
218 } else {
219 env->pstate = PSTATE_MODE_EL1h;
220 }
221 env->pc = cpu->rvbar;
222 #endif
223 } else {
224 #if defined(CONFIG_USER_ONLY)
225 /* Userspace expects access to cp10 and cp11 for FP/Neon */
226 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
227 #endif
228 }
229
230 #if defined(CONFIG_USER_ONLY)
231 env->uncached_cpsr = ARM_CPU_MODE_USR;
232 /* For user mode we must enable access to coprocessors */
233 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
234 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
235 env->cp15.c15_cpar = 3;
236 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
237 env->cp15.c15_cpar = 1;
238 }
239 #else
240
241 /*
242 * If the highest available EL is EL2, AArch32 will start in Hyp
243 * mode; otherwise it starts in SVC. Note that if we start in
244 * AArch64 then these values in the uncached_cpsr will be ignored.
245 */
246 if (arm_feature(env, ARM_FEATURE_EL2) &&
247 !arm_feature(env, ARM_FEATURE_EL3)) {
248 env->uncached_cpsr = ARM_CPU_MODE_HYP;
249 } else {
250 env->uncached_cpsr = ARM_CPU_MODE_SVC;
251 }
252 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
253
254 if (arm_feature(env, ARM_FEATURE_M)) {
255 uint32_t initial_msp; /* Loaded from 0x0 */
256 uint32_t initial_pc; /* Loaded from 0x4 */
257 uint8_t *rom;
258 uint32_t vecbase;
259
260 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
261 env->v7m.secure = true;
262 } else {
263 /* This bit resets to 0 if security is supported, but 1 if
264 * it is not. The bit is not present in v7M, but we set it
265 * here so we can avoid having to make checks on it conditional
266 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
267 */
268 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
269 /*
270 * Set NSACR to indicate "NS access permitted to everything";
271 * this avoids having to have all the tests of it being
272 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
273 * v8.1M the guest-visible value of NSACR in a CPU without the
274 * Security Extension is 0xcff.
275 */
276 env->v7m.nsacr = 0xcff;
277 }
278
279 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
280 * that it resets to 1, so QEMU always does that rather than making
281 * it dependent on CPU model. In v8M it is RES1.
282 */
283 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
284 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
285 if (arm_feature(env, ARM_FEATURE_V8)) {
286 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
289 }
290 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
291 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
292 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
293 }
294
295 if (arm_feature(env, ARM_FEATURE_VFP)) {
296 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
297 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
298 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
299 }
300 /* Unlike A/R profile, M profile defines the reset LR value */
301 env->regs[14] = 0xffffffff;
302
303 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
304
305 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
306 vecbase = env->v7m.vecbase[env->v7m.secure];
307 rom = rom_ptr(vecbase, 8);
308 if (rom) {
309 /* Address zero is covered by ROM which hasn't yet been
310 * copied into physical memory.
311 */
312 initial_msp = ldl_p(rom);
313 initial_pc = ldl_p(rom + 4);
314 } else {
315 /* Address zero not covered by a ROM blob, or the ROM blob
316 * is in non-modifiable memory and this is a second reset after
317 * it got copied into memory. In the latter case, rom_ptr
318 * will return a NULL pointer and we should use ldl_phys instead.
319 */
320 initial_msp = ldl_phys(s->as, vecbase);
321 initial_pc = ldl_phys(s->as, vecbase + 4);
322 }
323
324 env->regs[13] = initial_msp & 0xFFFFFFFC;
325 env->regs[15] = initial_pc & ~1;
326 env->thumb = initial_pc & 1;
327 }
328
329 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
330 * executing as AArch32 then check if highvecs are enabled and
331 * adjust the PC accordingly.
332 */
333 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
334 env->regs[15] = 0xFFFF0000;
335 }
336
337 /* M profile requires that reset clears the exclusive monitor;
338 * A profile does not, but clearing it makes more sense than having it
339 * set with an exclusive access on address zero.
340 */
341 arm_clear_exclusive(env);
342
343 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
344 #endif
345
346 if (arm_feature(env, ARM_FEATURE_PMSA)) {
347 if (cpu->pmsav7_dregion > 0) {
348 if (arm_feature(env, ARM_FEATURE_V8)) {
349 memset(env->pmsav8.rbar[M_REG_NS], 0,
350 sizeof(*env->pmsav8.rbar[M_REG_NS])
351 * cpu->pmsav7_dregion);
352 memset(env->pmsav8.rlar[M_REG_NS], 0,
353 sizeof(*env->pmsav8.rlar[M_REG_NS])
354 * cpu->pmsav7_dregion);
355 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
356 memset(env->pmsav8.rbar[M_REG_S], 0,
357 sizeof(*env->pmsav8.rbar[M_REG_S])
358 * cpu->pmsav7_dregion);
359 memset(env->pmsav8.rlar[M_REG_S], 0,
360 sizeof(*env->pmsav8.rlar[M_REG_S])
361 * cpu->pmsav7_dregion);
362 }
363 } else if (arm_feature(env, ARM_FEATURE_V7)) {
364 memset(env->pmsav7.drbar, 0,
365 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
366 memset(env->pmsav7.drsr, 0,
367 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
368 memset(env->pmsav7.dracr, 0,
369 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
370 }
371 }
372 env->pmsav7.rnr[M_REG_NS] = 0;
373 env->pmsav7.rnr[M_REG_S] = 0;
374 env->pmsav8.mair0[M_REG_NS] = 0;
375 env->pmsav8.mair0[M_REG_S] = 0;
376 env->pmsav8.mair1[M_REG_NS] = 0;
377 env->pmsav8.mair1[M_REG_S] = 0;
378 }
379
380 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
381 if (cpu->sau_sregion > 0) {
382 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
383 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
384 }
385 env->sau.rnr = 0;
386 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
387 * the Cortex-M33 does.
388 */
389 env->sau.ctrl = 0;
390 }
391
392 set_flush_to_zero(1, &env->vfp.standard_fp_status);
393 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
394 set_default_nan_mode(1, &env->vfp.standard_fp_status);
395 set_float_detect_tininess(float_tininess_before_rounding,
396 &env->vfp.fp_status);
397 set_float_detect_tininess(float_tininess_before_rounding,
398 &env->vfp.standard_fp_status);
399 set_float_detect_tininess(float_tininess_before_rounding,
400 &env->vfp.fp_status_f16);
401 #ifndef CONFIG_USER_ONLY
402 if (kvm_enabled()) {
403 kvm_arm_reset_vcpu(cpu);
404 }
405 #endif
406
407 hw_breakpoint_update_all(cpu);
408 hw_watchpoint_update_all(cpu);
409 }
410
411 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
412 {
413 CPUClass *cc = CPU_GET_CLASS(cs);
414 CPUARMState *env = cs->env_ptr;
415 uint32_t cur_el = arm_current_el(env);
416 bool secure = arm_is_secure(env);
417 uint32_t target_el;
418 uint32_t excp_idx;
419 bool ret = false;
420
421 if (interrupt_request & CPU_INTERRUPT_FIQ) {
422 excp_idx = EXCP_FIQ;
423 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
424 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
425 cs->exception_index = excp_idx;
426 env->exception.target_el = target_el;
427 cc->do_interrupt(cs);
428 ret = true;
429 }
430 }
431 if (interrupt_request & CPU_INTERRUPT_HARD) {
432 excp_idx = EXCP_IRQ;
433 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
434 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
435 cs->exception_index = excp_idx;
436 env->exception.target_el = target_el;
437 cc->do_interrupt(cs);
438 ret = true;
439 }
440 }
441 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
442 excp_idx = EXCP_VIRQ;
443 target_el = 1;
444 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
445 cs->exception_index = excp_idx;
446 env->exception.target_el = target_el;
447 cc->do_interrupt(cs);
448 ret = true;
449 }
450 }
451 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
452 excp_idx = EXCP_VFIQ;
453 target_el = 1;
454 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
455 cs->exception_index = excp_idx;
456 env->exception.target_el = target_el;
457 cc->do_interrupt(cs);
458 ret = true;
459 }
460 }
461
462 return ret;
463 }
464
465 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
466 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
467 {
468 CPUClass *cc = CPU_GET_CLASS(cs);
469 ARMCPU *cpu = ARM_CPU(cs);
470 CPUARMState *env = &cpu->env;
471 bool ret = false;
472
473 /* ARMv7-M interrupt masking works differently than -A or -R.
474 * There is no FIQ/IRQ distinction. Instead of I and F bits
475 * masking FIQ and IRQ interrupts, an exception is taken only
476 * if it is higher priority than the current execution priority
477 * (which depends on state like BASEPRI, FAULTMASK and the
478 * currently active exception).
479 */
480 if (interrupt_request & CPU_INTERRUPT_HARD
481 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
482 cs->exception_index = EXCP_IRQ;
483 cc->do_interrupt(cs);
484 ret = true;
485 }
486 return ret;
487 }
488 #endif
489
490 void arm_cpu_update_virq(ARMCPU *cpu)
491 {
492 /*
493 * Update the interrupt level for VIRQ, which is the logical OR of
494 * the HCR_EL2.VI bit and the input line level from the GIC.
495 */
496 CPUARMState *env = &cpu->env;
497 CPUState *cs = CPU(cpu);
498
499 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
500 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
501
502 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
503 if (new_state) {
504 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
505 } else {
506 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
507 }
508 }
509 }
510
511 void arm_cpu_update_vfiq(ARMCPU *cpu)
512 {
513 /*
514 * Update the interrupt level for VFIQ, which is the logical OR of
515 * the HCR_EL2.VF bit and the input line level from the GIC.
516 */
517 CPUARMState *env = &cpu->env;
518 CPUState *cs = CPU(cpu);
519
520 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
521 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
522
523 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
524 if (new_state) {
525 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
526 } else {
527 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
528 }
529 }
530 }
531
532 #ifndef CONFIG_USER_ONLY
533 static void arm_cpu_set_irq(void *opaque, int irq, int level)
534 {
535 ARMCPU *cpu = opaque;
536 CPUARMState *env = &cpu->env;
537 CPUState *cs = CPU(cpu);
538 static const int mask[] = {
539 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
540 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
541 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
542 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
543 };
544
545 if (level) {
546 env->irq_line_state |= mask[irq];
547 } else {
548 env->irq_line_state &= ~mask[irq];
549 }
550
551 switch (irq) {
552 case ARM_CPU_VIRQ:
553 assert(arm_feature(env, ARM_FEATURE_EL2));
554 arm_cpu_update_virq(cpu);
555 break;
556 case ARM_CPU_VFIQ:
557 assert(arm_feature(env, ARM_FEATURE_EL2));
558 arm_cpu_update_vfiq(cpu);
559 break;
560 case ARM_CPU_IRQ:
561 case ARM_CPU_FIQ:
562 if (level) {
563 cpu_interrupt(cs, mask[irq]);
564 } else {
565 cpu_reset_interrupt(cs, mask[irq]);
566 }
567 break;
568 default:
569 g_assert_not_reached();
570 }
571 }
572
573 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
574 {
575 #ifdef CONFIG_KVM
576 ARMCPU *cpu = opaque;
577 CPUARMState *env = &cpu->env;
578 CPUState *cs = CPU(cpu);
579 uint32_t linestate_bit;
580 int irq_id;
581
582 switch (irq) {
583 case ARM_CPU_IRQ:
584 irq_id = KVM_ARM_IRQ_CPU_IRQ;
585 linestate_bit = CPU_INTERRUPT_HARD;
586 break;
587 case ARM_CPU_FIQ:
588 irq_id = KVM_ARM_IRQ_CPU_FIQ;
589 linestate_bit = CPU_INTERRUPT_FIQ;
590 break;
591 default:
592 g_assert_not_reached();
593 }
594
595 if (level) {
596 env->irq_line_state |= linestate_bit;
597 } else {
598 env->irq_line_state &= ~linestate_bit;
599 }
600 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
601 #endif
602 }
603
604 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
605 {
606 ARMCPU *cpu = ARM_CPU(cs);
607 CPUARMState *env = &cpu->env;
608
609 cpu_synchronize_state(cs);
610 return arm_cpu_data_is_big_endian(env);
611 }
612
613 #endif
614
615 static inline void set_feature(CPUARMState *env, int feature)
616 {
617 env->features |= 1ULL << feature;
618 }
619
620 static inline void unset_feature(CPUARMState *env, int feature)
621 {
622 env->features &= ~(1ULL << feature);
623 }
624
625 static int
626 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
627 {
628 return print_insn_arm(pc | 1, info);
629 }
630
631 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
632 {
633 ARMCPU *ac = ARM_CPU(cpu);
634 CPUARMState *env = &ac->env;
635 bool sctlr_b;
636
637 if (is_a64(env)) {
638 /* We might not be compiled with the A64 disassembler
639 * because it needs a C++ compiler. Leave print_insn
640 * unset in this case to use the caller default behaviour.
641 */
642 #if defined(CONFIG_ARM_A64_DIS)
643 info->print_insn = print_insn_arm_a64;
644 #endif
645 info->cap_arch = CS_ARCH_ARM64;
646 info->cap_insn_unit = 4;
647 info->cap_insn_split = 4;
648 } else {
649 int cap_mode;
650 if (env->thumb) {
651 info->print_insn = print_insn_thumb1;
652 info->cap_insn_unit = 2;
653 info->cap_insn_split = 4;
654 cap_mode = CS_MODE_THUMB;
655 } else {
656 info->print_insn = print_insn_arm;
657 info->cap_insn_unit = 4;
658 info->cap_insn_split = 4;
659 cap_mode = CS_MODE_ARM;
660 }
661 if (arm_feature(env, ARM_FEATURE_V8)) {
662 cap_mode |= CS_MODE_V8;
663 }
664 if (arm_feature(env, ARM_FEATURE_M)) {
665 cap_mode |= CS_MODE_MCLASS;
666 }
667 info->cap_arch = CS_ARCH_ARM;
668 info->cap_mode = cap_mode;
669 }
670
671 sctlr_b = arm_sctlr_b(env);
672 if (bswap_code(sctlr_b)) {
673 #ifdef TARGET_WORDS_BIGENDIAN
674 info->endian = BFD_ENDIAN_LITTLE;
675 #else
676 info->endian = BFD_ENDIAN_BIG;
677 #endif
678 }
679 info->flags &= ~INSN_ARM_BE32;
680 #ifndef CONFIG_USER_ONLY
681 if (sctlr_b) {
682 info->flags |= INSN_ARM_BE32;
683 }
684 #endif
685 }
686
687 #ifdef TARGET_AARCH64
688
689 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
690 {
691 ARMCPU *cpu = ARM_CPU(cs);
692 CPUARMState *env = &cpu->env;
693 uint32_t psr = pstate_read(env);
694 int i;
695 int el = arm_current_el(env);
696 const char *ns_status;
697
698 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
699 for (i = 0; i < 32; i++) {
700 if (i == 31) {
701 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
702 } else {
703 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
704 (i + 2) % 3 ? " " : "\n");
705 }
706 }
707
708 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
709 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
710 } else {
711 ns_status = "";
712 }
713 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
714 psr,
715 psr & PSTATE_N ? 'N' : '-',
716 psr & PSTATE_Z ? 'Z' : '-',
717 psr & PSTATE_C ? 'C' : '-',
718 psr & PSTATE_V ? 'V' : '-',
719 ns_status,
720 el,
721 psr & PSTATE_SP ? 'h' : 't');
722
723 if (cpu_isar_feature(aa64_bti, cpu)) {
724 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
725 }
726 if (!(flags & CPU_DUMP_FPU)) {
727 qemu_fprintf(f, "\n");
728 return;
729 }
730 if (fp_exception_el(env, el) != 0) {
731 qemu_fprintf(f, " FPU disabled\n");
732 return;
733 }
734 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
735 vfp_get_fpcr(env), vfp_get_fpsr(env));
736
737 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
738 int j, zcr_len = sve_zcr_len_for_el(env, el);
739
740 for (i = 0; i <= FFR_PRED_NUM; i++) {
741 bool eol;
742 if (i == FFR_PRED_NUM) {
743 qemu_fprintf(f, "FFR=");
744 /* It's last, so end the line. */
745 eol = true;
746 } else {
747 qemu_fprintf(f, "P%02d=", i);
748 switch (zcr_len) {
749 case 0:
750 eol = i % 8 == 7;
751 break;
752 case 1:
753 eol = i % 6 == 5;
754 break;
755 case 2:
756 case 3:
757 eol = i % 3 == 2;
758 break;
759 default:
760 /* More than one quadword per predicate. */
761 eol = true;
762 break;
763 }
764 }
765 for (j = zcr_len / 4; j >= 0; j--) {
766 int digits;
767 if (j * 4 + 4 <= zcr_len + 1) {
768 digits = 16;
769 } else {
770 digits = (zcr_len % 4 + 1) * 4;
771 }
772 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
773 env->vfp.pregs[i].p[j],
774 j ? ":" : eol ? "\n" : " ");
775 }
776 }
777
778 for (i = 0; i < 32; i++) {
779 if (zcr_len == 0) {
780 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
781 i, env->vfp.zregs[i].d[1],
782 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
783 } else if (zcr_len == 1) {
784 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
785 ":%016" PRIx64 ":%016" PRIx64 "\n",
786 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
787 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
788 } else {
789 for (j = zcr_len; j >= 0; j--) {
790 bool odd = (zcr_len - j) % 2 != 0;
791 if (j == zcr_len) {
792 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
793 } else if (!odd) {
794 if (j > 0) {
795 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
796 } else {
797 qemu_fprintf(f, " [%x]=", j);
798 }
799 }
800 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
801 env->vfp.zregs[i].d[j * 2 + 1],
802 env->vfp.zregs[i].d[j * 2],
803 odd || j == 0 ? "\n" : ":");
804 }
805 }
806 }
807 } else {
808 for (i = 0; i < 32; i++) {
809 uint64_t *q = aa64_vfp_qreg(env, i);
810 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
811 i, q[1], q[0], (i & 1 ? "\n" : " "));
812 }
813 }
814 }
815
816 #else
817
818 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
819 {
820 g_assert_not_reached();
821 }
822
823 #endif
824
825 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
826 {
827 ARMCPU *cpu = ARM_CPU(cs);
828 CPUARMState *env = &cpu->env;
829 int i;
830
831 if (is_a64(env)) {
832 aarch64_cpu_dump_state(cs, f, flags);
833 return;
834 }
835
836 for (i = 0; i < 16; i++) {
837 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
838 if ((i % 4) == 3) {
839 qemu_fprintf(f, "\n");
840 } else {
841 qemu_fprintf(f, " ");
842 }
843 }
844
845 if (arm_feature(env, ARM_FEATURE_M)) {
846 uint32_t xpsr = xpsr_read(env);
847 const char *mode;
848 const char *ns_status = "";
849
850 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
851 ns_status = env->v7m.secure ? "S " : "NS ";
852 }
853
854 if (xpsr & XPSR_EXCP) {
855 mode = "handler";
856 } else {
857 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
858 mode = "unpriv-thread";
859 } else {
860 mode = "priv-thread";
861 }
862 }
863
864 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
865 xpsr,
866 xpsr & XPSR_N ? 'N' : '-',
867 xpsr & XPSR_Z ? 'Z' : '-',
868 xpsr & XPSR_C ? 'C' : '-',
869 xpsr & XPSR_V ? 'V' : '-',
870 xpsr & XPSR_T ? 'T' : 'A',
871 ns_status,
872 mode);
873 } else {
874 uint32_t psr = cpsr_read(env);
875 const char *ns_status = "";
876
877 if (arm_feature(env, ARM_FEATURE_EL3) &&
878 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
879 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
880 }
881
882 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
883 psr,
884 psr & CPSR_N ? 'N' : '-',
885 psr & CPSR_Z ? 'Z' : '-',
886 psr & CPSR_C ? 'C' : '-',
887 psr & CPSR_V ? 'V' : '-',
888 psr & CPSR_T ? 'T' : 'A',
889 ns_status,
890 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
891 }
892
893 if (flags & CPU_DUMP_FPU) {
894 int numvfpregs = 0;
895 if (arm_feature(env, ARM_FEATURE_VFP)) {
896 numvfpregs += 16;
897 }
898 if (arm_feature(env, ARM_FEATURE_VFP3)) {
899 numvfpregs += 16;
900 }
901 for (i = 0; i < numvfpregs; i++) {
902 uint64_t v = *aa32_vfp_dreg(env, i);
903 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
904 i * 2, (uint32_t)v,
905 i * 2 + 1, (uint32_t)(v >> 32),
906 i, v);
907 }
908 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
909 }
910 }
911
912 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
913 {
914 uint32_t Aff1 = idx / clustersz;
915 uint32_t Aff0 = idx % clustersz;
916 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
917 }
918
919 static void cpreg_hashtable_data_destroy(gpointer data)
920 {
921 /*
922 * Destroy function for cpu->cp_regs hashtable data entries.
923 * We must free the name string because it was g_strdup()ed in
924 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
925 * from r->name because we know we definitely allocated it.
926 */
927 ARMCPRegInfo *r = data;
928
929 g_free((void *)r->name);
930 g_free(r);
931 }
932
933 static void arm_cpu_initfn(Object *obj)
934 {
935 ARMCPU *cpu = ARM_CPU(obj);
936
937 cpu_set_cpustate_pointers(cpu);
938 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
939 g_free, cpreg_hashtable_data_destroy);
940
941 QLIST_INIT(&cpu->pre_el_change_hooks);
942 QLIST_INIT(&cpu->el_change_hooks);
943
944 #ifndef CONFIG_USER_ONLY
945 /* Our inbound IRQ and FIQ lines */
946 if (kvm_enabled()) {
947 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
948 * the same interface as non-KVM CPUs.
949 */
950 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
951 } else {
952 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
953 }
954
955 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
956 ARRAY_SIZE(cpu->gt_timer_outputs));
957
958 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
959 "gicv3-maintenance-interrupt", 1);
960 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
961 "pmu-interrupt", 1);
962 #endif
963
964 /* DTB consumers generally don't in fact care what the 'compatible'
965 * string is, so always provide some string and trust that a hypothetical
966 * picky DTB consumer will also provide a helpful error message.
967 */
968 cpu->dtb_compatible = "qemu,unknown";
969 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
970 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
971
972 if (tcg_enabled()) {
973 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
974 }
975 }
976
977 static Property arm_cpu_reset_cbar_property =
978 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
979
980 static Property arm_cpu_reset_hivecs_property =
981 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
982
983 static Property arm_cpu_rvbar_property =
984 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
985
986 static Property arm_cpu_has_el2_property =
987 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
988
989 static Property arm_cpu_has_el3_property =
990 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
991
992 static Property arm_cpu_cfgend_property =
993 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
994
995 static Property arm_cpu_has_vfp_property =
996 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
997
998 static Property arm_cpu_has_neon_property =
999 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1000
1001 static Property arm_cpu_has_dsp_property =
1002 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1003
1004 static Property arm_cpu_has_mpu_property =
1005 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1006
1007 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1008 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1009 * the right value for that particular CPU type, and we don't want
1010 * to override that with an incorrect constant value.
1011 */
1012 static Property arm_cpu_pmsav7_dregion_property =
1013 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1014 pmsav7_dregion,
1015 qdev_prop_uint32, uint32_t);
1016
1017 static bool arm_get_pmu(Object *obj, Error **errp)
1018 {
1019 ARMCPU *cpu = ARM_CPU(obj);
1020
1021 return cpu->has_pmu;
1022 }
1023
1024 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1025 {
1026 ARMCPU *cpu = ARM_CPU(obj);
1027
1028 if (value) {
1029 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
1030 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1031 return;
1032 }
1033 set_feature(&cpu->env, ARM_FEATURE_PMU);
1034 } else {
1035 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1036 }
1037 cpu->has_pmu = value;
1038 }
1039
1040 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
1041 void *opaque, Error **errp)
1042 {
1043 ARMCPU *cpu = ARM_CPU(obj);
1044
1045 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1046 }
1047
1048 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
1049 void *opaque, Error **errp)
1050 {
1051 ARMCPU *cpu = ARM_CPU(obj);
1052
1053 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1054 }
1055
1056 void arm_cpu_post_init(Object *obj)
1057 {
1058 ARMCPU *cpu = ARM_CPU(obj);
1059
1060 /* M profile implies PMSA. We have to do this here rather than
1061 * in realize with the other feature-implication checks because
1062 * we look at the PMSA bit to see if we should add some properties.
1063 */
1064 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1065 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1066 }
1067 /* Similarly for the VFP feature bits */
1068 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
1069 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1070 }
1071 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
1072 set_feature(&cpu->env, ARM_FEATURE_VFP);
1073 }
1074
1075 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1076 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1077 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
1078 &error_abort);
1079 }
1080
1081 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1082 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
1083 &error_abort);
1084 }
1085
1086 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1087 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
1088 &error_abort);
1089 }
1090
1091 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1092 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1093 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1094 */
1095 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
1096 &error_abort);
1097
1098 #ifndef CONFIG_USER_ONLY
1099 object_property_add_link(obj, "secure-memory",
1100 TYPE_MEMORY_REGION,
1101 (Object **)&cpu->secure_memory,
1102 qdev_prop_allow_set_link_before_realize,
1103 OBJ_PROP_LINK_STRONG,
1104 &error_abort);
1105 #endif
1106 }
1107
1108 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1109 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
1110 &error_abort);
1111 }
1112
1113 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1114 cpu->has_pmu = true;
1115 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
1116 &error_abort);
1117 }
1118
1119 /*
1120 * Allow user to turn off VFP and Neon support, but only for TCG --
1121 * KVM does not currently allow us to lie to the guest about its
1122 * ID/feature registers, so the guest always sees what the host has.
1123 */
1124 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1125 cpu->has_vfp = true;
1126 if (!kvm_enabled()) {
1127 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property,
1128 &error_abort);
1129 }
1130 }
1131
1132 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1133 cpu->has_neon = true;
1134 if (!kvm_enabled()) {
1135 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property,
1136 &error_abort);
1137 }
1138 }
1139
1140 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1141 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1142 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property,
1143 &error_abort);
1144 }
1145
1146 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1147 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
1148 &error_abort);
1149 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1150 qdev_property_add_static(DEVICE(obj),
1151 &arm_cpu_pmsav7_dregion_property,
1152 &error_abort);
1153 }
1154 }
1155
1156 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1157 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1158 qdev_prop_allow_set_link_before_realize,
1159 OBJ_PROP_LINK_STRONG,
1160 &error_abort);
1161 /*
1162 * M profile: initial value of the Secure VTOR. We can't just use
1163 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1164 * the property to be set after realize.
1165 */
1166 object_property_add(obj, "init-svtor", "uint32",
1167 arm_get_init_svtor, arm_set_init_svtor,
1168 NULL, NULL, &error_abort);
1169 }
1170
1171 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
1172 &error_abort);
1173 }
1174
1175 static void arm_cpu_finalizefn(Object *obj)
1176 {
1177 ARMCPU *cpu = ARM_CPU(obj);
1178 ARMELChangeHook *hook, *next;
1179
1180 g_hash_table_destroy(cpu->cp_regs);
1181
1182 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1183 QLIST_REMOVE(hook, node);
1184 g_free(hook);
1185 }
1186 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1187 QLIST_REMOVE(hook, node);
1188 g_free(hook);
1189 }
1190 #ifndef CONFIG_USER_ONLY
1191 if (cpu->pmu_timer) {
1192 timer_del(cpu->pmu_timer);
1193 timer_deinit(cpu->pmu_timer);
1194 timer_free(cpu->pmu_timer);
1195 }
1196 #endif
1197 }
1198
1199 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1200 {
1201 CPUState *cs = CPU(dev);
1202 ARMCPU *cpu = ARM_CPU(dev);
1203 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1204 CPUARMState *env = &cpu->env;
1205 int pagebits;
1206 Error *local_err = NULL;
1207 bool no_aa32 = false;
1208
1209 /* If we needed to query the host kernel for the CPU features
1210 * then it's possible that might have failed in the initfn, but
1211 * this is the first point where we can report it.
1212 */
1213 if (cpu->host_cpu_probe_failed) {
1214 if (!kvm_enabled()) {
1215 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1216 } else {
1217 error_setg(errp, "Failed to retrieve host CPU features");
1218 }
1219 return;
1220 }
1221
1222 #ifndef CONFIG_USER_ONLY
1223 /* The NVIC and M-profile CPU are two halves of a single piece of
1224 * hardware; trying to use one without the other is a command line
1225 * error and will result in segfaults if not caught here.
1226 */
1227 if (arm_feature(env, ARM_FEATURE_M)) {
1228 if (!env->nvic) {
1229 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1230 return;
1231 }
1232 } else {
1233 if (env->nvic) {
1234 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1235 return;
1236 }
1237 }
1238
1239 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1240 arm_gt_ptimer_cb, cpu);
1241 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1242 arm_gt_vtimer_cb, cpu);
1243 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1244 arm_gt_htimer_cb, cpu);
1245 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1246 arm_gt_stimer_cb, cpu);
1247 #endif
1248
1249 cpu_exec_realizefn(cs, &local_err);
1250 if (local_err != NULL) {
1251 error_propagate(errp, local_err);
1252 return;
1253 }
1254
1255 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1256 cpu->has_vfp != cpu->has_neon) {
1257 /*
1258 * This is an architectural requirement for AArch64; AArch32 is
1259 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1260 */
1261 error_setg(errp,
1262 "AArch64 CPUs must have both VFP and Neon or neither");
1263 return;
1264 }
1265
1266 if (!cpu->has_vfp) {
1267 uint64_t t;
1268 uint32_t u;
1269
1270 unset_feature(env, ARM_FEATURE_VFP);
1271 unset_feature(env, ARM_FEATURE_VFP3);
1272 unset_feature(env, ARM_FEATURE_VFP4);
1273
1274 t = cpu->isar.id_aa64isar1;
1275 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1276 cpu->isar.id_aa64isar1 = t;
1277
1278 t = cpu->isar.id_aa64pfr0;
1279 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1280 cpu->isar.id_aa64pfr0 = t;
1281
1282 u = cpu->isar.id_isar6;
1283 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1284 cpu->isar.id_isar6 = u;
1285
1286 u = cpu->isar.mvfr0;
1287 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1288 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1289 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1290 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1291 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1292 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1293 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1294 cpu->isar.mvfr0 = u;
1295
1296 u = cpu->isar.mvfr1;
1297 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1298 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1299 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1300 cpu->isar.mvfr1 = u;
1301
1302 u = cpu->isar.mvfr2;
1303 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1304 cpu->isar.mvfr2 = u;
1305 }
1306
1307 if (!cpu->has_neon) {
1308 uint64_t t;
1309 uint32_t u;
1310
1311 unset_feature(env, ARM_FEATURE_NEON);
1312
1313 t = cpu->isar.id_aa64isar0;
1314 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1315 cpu->isar.id_aa64isar0 = t;
1316
1317 t = cpu->isar.id_aa64isar1;
1318 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1319 cpu->isar.id_aa64isar1 = t;
1320
1321 t = cpu->isar.id_aa64pfr0;
1322 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1323 cpu->isar.id_aa64pfr0 = t;
1324
1325 u = cpu->isar.id_isar5;
1326 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1327 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1328 cpu->isar.id_isar5 = u;
1329
1330 u = cpu->isar.id_isar6;
1331 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1332 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1333 cpu->isar.id_isar6 = u;
1334
1335 u = cpu->isar.mvfr1;
1336 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1337 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1338 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1339 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1340 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1341 cpu->isar.mvfr1 = u;
1342
1343 u = cpu->isar.mvfr2;
1344 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1345 cpu->isar.mvfr2 = u;
1346 }
1347
1348 if (!cpu->has_neon && !cpu->has_vfp) {
1349 uint64_t t;
1350 uint32_t u;
1351
1352 t = cpu->isar.id_aa64isar0;
1353 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1354 cpu->isar.id_aa64isar0 = t;
1355
1356 t = cpu->isar.id_aa64isar1;
1357 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1358 cpu->isar.id_aa64isar1 = t;
1359
1360 u = cpu->isar.mvfr0;
1361 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1362 cpu->isar.mvfr0 = u;
1363 }
1364
1365 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1366 uint32_t u;
1367
1368 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1369
1370 u = cpu->isar.id_isar1;
1371 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1372 cpu->isar.id_isar1 = u;
1373
1374 u = cpu->isar.id_isar2;
1375 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1376 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1377 cpu->isar.id_isar2 = u;
1378
1379 u = cpu->isar.id_isar3;
1380 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1381 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1382 cpu->isar.id_isar3 = u;
1383 }
1384
1385 /* Some features automatically imply others: */
1386 if (arm_feature(env, ARM_FEATURE_V8)) {
1387 if (arm_feature(env, ARM_FEATURE_M)) {
1388 set_feature(env, ARM_FEATURE_V7);
1389 } else {
1390 set_feature(env, ARM_FEATURE_V7VE);
1391 }
1392 }
1393
1394 /*
1395 * There exist AArch64 cpus without AArch32 support. When KVM
1396 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1397 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1398 * As a general principle, we also do not make ID register
1399 * consistency checks anywhere unless using TCG, because only
1400 * for TCG would a consistency-check failure be a QEMU bug.
1401 */
1402 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1403 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1404 }
1405
1406 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1407 /* v7 Virtualization Extensions. In real hardware this implies
1408 * EL2 and also the presence of the Security Extensions.
1409 * For QEMU, for backwards-compatibility we implement some
1410 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1411 * include the various other features that V7VE implies.
1412 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1413 * Security Extensions is ARM_FEATURE_EL3.
1414 */
1415 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
1416 set_feature(env, ARM_FEATURE_LPAE);
1417 set_feature(env, ARM_FEATURE_V7);
1418 }
1419 if (arm_feature(env, ARM_FEATURE_V7)) {
1420 set_feature(env, ARM_FEATURE_VAPA);
1421 set_feature(env, ARM_FEATURE_THUMB2);
1422 set_feature(env, ARM_FEATURE_MPIDR);
1423 if (!arm_feature(env, ARM_FEATURE_M)) {
1424 set_feature(env, ARM_FEATURE_V6K);
1425 } else {
1426 set_feature(env, ARM_FEATURE_V6);
1427 }
1428
1429 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1430 * non-EL3 configs. This is needed by some legacy boards.
1431 */
1432 set_feature(env, ARM_FEATURE_VBAR);
1433 }
1434 if (arm_feature(env, ARM_FEATURE_V6K)) {
1435 set_feature(env, ARM_FEATURE_V6);
1436 set_feature(env, ARM_FEATURE_MVFR);
1437 }
1438 if (arm_feature(env, ARM_FEATURE_V6)) {
1439 set_feature(env, ARM_FEATURE_V5);
1440 if (!arm_feature(env, ARM_FEATURE_M)) {
1441 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
1442 set_feature(env, ARM_FEATURE_AUXCR);
1443 }
1444 }
1445 if (arm_feature(env, ARM_FEATURE_V5)) {
1446 set_feature(env, ARM_FEATURE_V4T);
1447 }
1448 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1449 set_feature(env, ARM_FEATURE_V7MP);
1450 set_feature(env, ARM_FEATURE_PXN);
1451 }
1452 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1453 set_feature(env, ARM_FEATURE_CBAR);
1454 }
1455 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1456 !arm_feature(env, ARM_FEATURE_M)) {
1457 set_feature(env, ARM_FEATURE_THUMB_DSP);
1458 }
1459
1460 /*
1461 * We rely on no XScale CPU having VFP so we can use the same bits in the
1462 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1463 */
1464 assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
1465 arm_feature(env, ARM_FEATURE_XSCALE)));
1466
1467 if (arm_feature(env, ARM_FEATURE_V7) &&
1468 !arm_feature(env, ARM_FEATURE_M) &&
1469 !arm_feature(env, ARM_FEATURE_PMSA)) {
1470 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1471 * can use 4K pages.
1472 */
1473 pagebits = 12;
1474 } else {
1475 /* For CPUs which might have tiny 1K pages, or which have an
1476 * MPU and might have small region sizes, stick with 1K pages.
1477 */
1478 pagebits = 10;
1479 }
1480 if (!set_preferred_target_page_bits(pagebits)) {
1481 /* This can only ever happen for hotplugging a CPU, or if
1482 * the board code incorrectly creates a CPU which it has
1483 * promised via minimum_page_size that it will not.
1484 */
1485 error_setg(errp, "This CPU requires a smaller page size than the "
1486 "system is using");
1487 return;
1488 }
1489
1490 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1491 * We don't support setting cluster ID ([16..23]) (known as Aff2
1492 * in later ARM ARM versions), or any of the higher affinity level fields,
1493 * so these bits always RAZ.
1494 */
1495 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1496 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1497 ARM_DEFAULT_CPUS_PER_CLUSTER);
1498 }
1499
1500 if (cpu->reset_hivecs) {
1501 cpu->reset_sctlr |= (1 << 13);
1502 }
1503
1504 if (cpu->cfgend) {
1505 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1506 cpu->reset_sctlr |= SCTLR_EE;
1507 } else {
1508 cpu->reset_sctlr |= SCTLR_B;
1509 }
1510 }
1511
1512 if (!cpu->has_el3) {
1513 /* If the has_el3 CPU property is disabled then we need to disable the
1514 * feature.
1515 */
1516 unset_feature(env, ARM_FEATURE_EL3);
1517
1518 /* Disable the security extension feature bits in the processor feature
1519 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1520 */
1521 cpu->id_pfr1 &= ~0xf0;
1522 cpu->isar.id_aa64pfr0 &= ~0xf000;
1523 }
1524
1525 if (!cpu->has_el2) {
1526 unset_feature(env, ARM_FEATURE_EL2);
1527 }
1528
1529 if (!cpu->has_pmu) {
1530 unset_feature(env, ARM_FEATURE_PMU);
1531 }
1532 if (arm_feature(env, ARM_FEATURE_PMU)) {
1533 pmu_init(cpu);
1534
1535 if (!kvm_enabled()) {
1536 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1537 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1538 }
1539
1540 #ifndef CONFIG_USER_ONLY
1541 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1542 cpu);
1543 #endif
1544 } else {
1545 cpu->id_aa64dfr0 &= ~0xf00;
1546 cpu->id_dfr0 &= ~(0xf << 24);
1547 cpu->pmceid0 = 0;
1548 cpu->pmceid1 = 0;
1549 }
1550
1551 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1552 /* Disable the hypervisor feature bits in the processor feature
1553 * registers if we don't have EL2. These are id_pfr1[15:12] and
1554 * id_aa64pfr0_el1[11:8].
1555 */
1556 cpu->isar.id_aa64pfr0 &= ~0xf00;
1557 cpu->id_pfr1 &= ~0xf000;
1558 }
1559
1560 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1561 * to false or by setting pmsav7-dregion to 0.
1562 */
1563 if (!cpu->has_mpu) {
1564 cpu->pmsav7_dregion = 0;
1565 }
1566 if (cpu->pmsav7_dregion == 0) {
1567 cpu->has_mpu = false;
1568 }
1569
1570 if (arm_feature(env, ARM_FEATURE_PMSA) &&
1571 arm_feature(env, ARM_FEATURE_V7)) {
1572 uint32_t nr = cpu->pmsav7_dregion;
1573
1574 if (nr > 0xff) {
1575 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1576 return;
1577 }
1578
1579 if (nr) {
1580 if (arm_feature(env, ARM_FEATURE_V8)) {
1581 /* PMSAv8 */
1582 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1583 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1584 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1585 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1586 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1587 }
1588 } else {
1589 env->pmsav7.drbar = g_new0(uint32_t, nr);
1590 env->pmsav7.drsr = g_new0(uint32_t, nr);
1591 env->pmsav7.dracr = g_new0(uint32_t, nr);
1592 }
1593 }
1594 }
1595
1596 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1597 uint32_t nr = cpu->sau_sregion;
1598
1599 if (nr > 0xff) {
1600 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1601 return;
1602 }
1603
1604 if (nr) {
1605 env->sau.rbar = g_new0(uint32_t, nr);
1606 env->sau.rlar = g_new0(uint32_t, nr);
1607 }
1608 }
1609
1610 if (arm_feature(env, ARM_FEATURE_EL3)) {
1611 set_feature(env, ARM_FEATURE_VBAR);
1612 }
1613
1614 register_cp_regs_for_features(cpu);
1615 arm_cpu_register_gdb_regs_for_features(cpu);
1616
1617 init_cpreg_list(cpu);
1618
1619 #ifndef CONFIG_USER_ONLY
1620 MachineState *ms = MACHINE(qdev_get_machine());
1621 unsigned int smp_cpus = ms->smp.cpus;
1622
1623 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1624 cs->num_ases = 2;
1625
1626 if (!cpu->secure_memory) {
1627 cpu->secure_memory = cs->memory;
1628 }
1629 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1630 cpu->secure_memory);
1631 } else {
1632 cs->num_ases = 1;
1633 }
1634 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1635
1636 /* No core_count specified, default to smp_cpus. */
1637 if (cpu->core_count == -1) {
1638 cpu->core_count = smp_cpus;
1639 }
1640 #endif
1641
1642 qemu_init_vcpu(cs);
1643 cpu_reset(cs);
1644
1645 acc->parent_realize(dev, errp);
1646 }
1647
1648 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1649 {
1650 ObjectClass *oc;
1651 char *typename;
1652 char **cpuname;
1653 const char *cpunamestr;
1654
1655 cpuname = g_strsplit(cpu_model, ",", 1);
1656 cpunamestr = cpuname[0];
1657 #ifdef CONFIG_USER_ONLY
1658 /* For backwards compatibility usermode emulation allows "-cpu any",
1659 * which has the same semantics as "-cpu max".
1660 */
1661 if (!strcmp(cpunamestr, "any")) {
1662 cpunamestr = "max";
1663 }
1664 #endif
1665 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1666 oc = object_class_by_name(typename);
1667 g_strfreev(cpuname);
1668 g_free(typename);
1669 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1670 object_class_is_abstract(oc)) {
1671 return NULL;
1672 }
1673 return oc;
1674 }
1675
1676 /* CPU models. These are not needed for the AArch64 linux-user build. */
1677 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1678
1679 static void arm926_initfn(Object *obj)
1680 {
1681 ARMCPU *cpu = ARM_CPU(obj);
1682
1683 cpu->dtb_compatible = "arm,arm926";
1684 set_feature(&cpu->env, ARM_FEATURE_V5);
1685 set_feature(&cpu->env, ARM_FEATURE_VFP);
1686 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1687 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1688 cpu->midr = 0x41069265;
1689 cpu->reset_fpsid = 0x41011090;
1690 cpu->ctr = 0x1dd20d2;
1691 cpu->reset_sctlr = 0x00090078;
1692
1693 /*
1694 * ARMv5 does not have the ID_ISAR registers, but we can still
1695 * set the field to indicate Jazelle support within QEMU.
1696 */
1697 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1698 /*
1699 * Similarly, we need to set MVFR0 fields to enable double precision
1700 * and short vector support even though ARMv5 doesn't have this register.
1701 */
1702 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1703 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1704 }
1705
1706 static void arm946_initfn(Object *obj)
1707 {
1708 ARMCPU *cpu = ARM_CPU(obj);
1709
1710 cpu->dtb_compatible = "arm,arm946";
1711 set_feature(&cpu->env, ARM_FEATURE_V5);
1712 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1713 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1714 cpu->midr = 0x41059461;
1715 cpu->ctr = 0x0f004006;
1716 cpu->reset_sctlr = 0x00000078;
1717 }
1718
1719 static void arm1026_initfn(Object *obj)
1720 {
1721 ARMCPU *cpu = ARM_CPU(obj);
1722
1723 cpu->dtb_compatible = "arm,arm1026";
1724 set_feature(&cpu->env, ARM_FEATURE_V5);
1725 set_feature(&cpu->env, ARM_FEATURE_VFP);
1726 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1727 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1728 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1729 cpu->midr = 0x4106a262;
1730 cpu->reset_fpsid = 0x410110a0;
1731 cpu->ctr = 0x1dd20d2;
1732 cpu->reset_sctlr = 0x00090078;
1733 cpu->reset_auxcr = 1;
1734
1735 /*
1736 * ARMv5 does not have the ID_ISAR registers, but we can still
1737 * set the field to indicate Jazelle support within QEMU.
1738 */
1739 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1740 /*
1741 * Similarly, we need to set MVFR0 fields to enable double precision
1742 * and short vector support even though ARMv5 doesn't have this register.
1743 */
1744 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1745 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
1746
1747 {
1748 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1749 ARMCPRegInfo ifar = {
1750 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1751 .access = PL1_RW,
1752 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1753 .resetvalue = 0
1754 };
1755 define_one_arm_cp_reg(cpu, &ifar);
1756 }
1757 }
1758
1759 static void arm1136_r2_initfn(Object *obj)
1760 {
1761 ARMCPU *cpu = ARM_CPU(obj);
1762 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1763 * older core than plain "arm1136". In particular this does not
1764 * have the v6K features.
1765 * These ID register values are correct for 1136 but may be wrong
1766 * for 1136_r2 (in particular r0p2 does not actually implement most
1767 * of the ID registers).
1768 */
1769
1770 cpu->dtb_compatible = "arm,arm1136";
1771 set_feature(&cpu->env, ARM_FEATURE_V6);
1772 set_feature(&cpu->env, ARM_FEATURE_VFP);
1773 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1774 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1775 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1776 cpu->midr = 0x4107b362;
1777 cpu->reset_fpsid = 0x410120b4;
1778 cpu->isar.mvfr0 = 0x11111111;
1779 cpu->isar.mvfr1 = 0x00000000;
1780 cpu->ctr = 0x1dd20d2;
1781 cpu->reset_sctlr = 0x00050078;
1782 cpu->id_pfr0 = 0x111;
1783 cpu->id_pfr1 = 0x1;
1784 cpu->id_dfr0 = 0x2;
1785 cpu->id_afr0 = 0x3;
1786 cpu->id_mmfr0 = 0x01130003;
1787 cpu->id_mmfr1 = 0x10030302;
1788 cpu->id_mmfr2 = 0x01222110;
1789 cpu->isar.id_isar0 = 0x00140011;
1790 cpu->isar.id_isar1 = 0x12002111;
1791 cpu->isar.id_isar2 = 0x11231111;
1792 cpu->isar.id_isar3 = 0x01102131;
1793 cpu->isar.id_isar4 = 0x141;
1794 cpu->reset_auxcr = 7;
1795 }
1796
1797 static void arm1136_initfn(Object *obj)
1798 {
1799 ARMCPU *cpu = ARM_CPU(obj);
1800
1801 cpu->dtb_compatible = "arm,arm1136";
1802 set_feature(&cpu->env, ARM_FEATURE_V6K);
1803 set_feature(&cpu->env, ARM_FEATURE_V6);
1804 set_feature(&cpu->env, ARM_FEATURE_VFP);
1805 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1806 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1807 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1808 cpu->midr = 0x4117b363;
1809 cpu->reset_fpsid = 0x410120b4;
1810 cpu->isar.mvfr0 = 0x11111111;
1811 cpu->isar.mvfr1 = 0x00000000;
1812 cpu->ctr = 0x1dd20d2;
1813 cpu->reset_sctlr = 0x00050078;
1814 cpu->id_pfr0 = 0x111;
1815 cpu->id_pfr1 = 0x1;
1816 cpu->id_dfr0 = 0x2;
1817 cpu->id_afr0 = 0x3;
1818 cpu->id_mmfr0 = 0x01130003;
1819 cpu->id_mmfr1 = 0x10030302;
1820 cpu->id_mmfr2 = 0x01222110;
1821 cpu->isar.id_isar0 = 0x00140011;
1822 cpu->isar.id_isar1 = 0x12002111;
1823 cpu->isar.id_isar2 = 0x11231111;
1824 cpu->isar.id_isar3 = 0x01102131;
1825 cpu->isar.id_isar4 = 0x141;
1826 cpu->reset_auxcr = 7;
1827 }
1828
1829 static void arm1176_initfn(Object *obj)
1830 {
1831 ARMCPU *cpu = ARM_CPU(obj);
1832
1833 cpu->dtb_compatible = "arm,arm1176";
1834 set_feature(&cpu->env, ARM_FEATURE_V6K);
1835 set_feature(&cpu->env, ARM_FEATURE_VFP);
1836 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1837 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1838 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1839 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1840 set_feature(&cpu->env, ARM_FEATURE_EL3);
1841 cpu->midr = 0x410fb767;
1842 cpu->reset_fpsid = 0x410120b5;
1843 cpu->isar.mvfr0 = 0x11111111;
1844 cpu->isar.mvfr1 = 0x00000000;
1845 cpu->ctr = 0x1dd20d2;
1846 cpu->reset_sctlr = 0x00050078;
1847 cpu->id_pfr0 = 0x111;
1848 cpu->id_pfr1 = 0x11;
1849 cpu->id_dfr0 = 0x33;
1850 cpu->id_afr0 = 0;
1851 cpu->id_mmfr0 = 0x01130003;
1852 cpu->id_mmfr1 = 0x10030302;
1853 cpu->id_mmfr2 = 0x01222100;
1854 cpu->isar.id_isar0 = 0x0140011;
1855 cpu->isar.id_isar1 = 0x12002111;
1856 cpu->isar.id_isar2 = 0x11231121;
1857 cpu->isar.id_isar3 = 0x01102131;
1858 cpu->isar.id_isar4 = 0x01141;
1859 cpu->reset_auxcr = 7;
1860 }
1861
1862 static void arm11mpcore_initfn(Object *obj)
1863 {
1864 ARMCPU *cpu = ARM_CPU(obj);
1865
1866 cpu->dtb_compatible = "arm,arm11mpcore";
1867 set_feature(&cpu->env, ARM_FEATURE_V6K);
1868 set_feature(&cpu->env, ARM_FEATURE_VFP);
1869 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1870 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1871 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1872 cpu->midr = 0x410fb022;
1873 cpu->reset_fpsid = 0x410120b4;
1874 cpu->isar.mvfr0 = 0x11111111;
1875 cpu->isar.mvfr1 = 0x00000000;
1876 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1877 cpu->id_pfr0 = 0x111;
1878 cpu->id_pfr1 = 0x1;
1879 cpu->id_dfr0 = 0;
1880 cpu->id_afr0 = 0x2;
1881 cpu->id_mmfr0 = 0x01100103;
1882 cpu->id_mmfr1 = 0x10020302;
1883 cpu->id_mmfr2 = 0x01222000;
1884 cpu->isar.id_isar0 = 0x00100011;
1885 cpu->isar.id_isar1 = 0x12002111;
1886 cpu->isar.id_isar2 = 0x11221011;
1887 cpu->isar.id_isar3 = 0x01102131;
1888 cpu->isar.id_isar4 = 0x141;
1889 cpu->reset_auxcr = 1;
1890 }
1891
1892 static void cortex_m0_initfn(Object *obj)
1893 {
1894 ARMCPU *cpu = ARM_CPU(obj);
1895 set_feature(&cpu->env, ARM_FEATURE_V6);
1896 set_feature(&cpu->env, ARM_FEATURE_M);
1897
1898 cpu->midr = 0x410cc200;
1899 }
1900
1901 static void cortex_m3_initfn(Object *obj)
1902 {
1903 ARMCPU *cpu = ARM_CPU(obj);
1904 set_feature(&cpu->env, ARM_FEATURE_V7);
1905 set_feature(&cpu->env, ARM_FEATURE_M);
1906 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1907 cpu->midr = 0x410fc231;
1908 cpu->pmsav7_dregion = 8;
1909 cpu->id_pfr0 = 0x00000030;
1910 cpu->id_pfr1 = 0x00000200;
1911 cpu->id_dfr0 = 0x00100000;
1912 cpu->id_afr0 = 0x00000000;
1913 cpu->id_mmfr0 = 0x00000030;
1914 cpu->id_mmfr1 = 0x00000000;
1915 cpu->id_mmfr2 = 0x00000000;
1916 cpu->id_mmfr3 = 0x00000000;
1917 cpu->isar.id_isar0 = 0x01141110;
1918 cpu->isar.id_isar1 = 0x02111000;
1919 cpu->isar.id_isar2 = 0x21112231;
1920 cpu->isar.id_isar3 = 0x01111110;
1921 cpu->isar.id_isar4 = 0x01310102;
1922 cpu->isar.id_isar5 = 0x00000000;
1923 cpu->isar.id_isar6 = 0x00000000;
1924 }
1925
1926 static void cortex_m4_initfn(Object *obj)
1927 {
1928 ARMCPU *cpu = ARM_CPU(obj);
1929
1930 set_feature(&cpu->env, ARM_FEATURE_V7);
1931 set_feature(&cpu->env, ARM_FEATURE_M);
1932 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1933 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1934 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1935 cpu->midr = 0x410fc240; /* r0p0 */
1936 cpu->pmsav7_dregion = 8;
1937 cpu->isar.mvfr0 = 0x10110021;
1938 cpu->isar.mvfr1 = 0x11000011;
1939 cpu->isar.mvfr2 = 0x00000000;
1940 cpu->id_pfr0 = 0x00000030;
1941 cpu->id_pfr1 = 0x00000200;
1942 cpu->id_dfr0 = 0x00100000;
1943 cpu->id_afr0 = 0x00000000;
1944 cpu->id_mmfr0 = 0x00000030;
1945 cpu->id_mmfr1 = 0x00000000;
1946 cpu->id_mmfr2 = 0x00000000;
1947 cpu->id_mmfr3 = 0x00000000;
1948 cpu->isar.id_isar0 = 0x01141110;
1949 cpu->isar.id_isar1 = 0x02111000;
1950 cpu->isar.id_isar2 = 0x21112231;
1951 cpu->isar.id_isar3 = 0x01111110;
1952 cpu->isar.id_isar4 = 0x01310102;
1953 cpu->isar.id_isar5 = 0x00000000;
1954 cpu->isar.id_isar6 = 0x00000000;
1955 }
1956
1957 static void cortex_m33_initfn(Object *obj)
1958 {
1959 ARMCPU *cpu = ARM_CPU(obj);
1960
1961 set_feature(&cpu->env, ARM_FEATURE_V8);
1962 set_feature(&cpu->env, ARM_FEATURE_M);
1963 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1964 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1965 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1966 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1967 cpu->midr = 0x410fd213; /* r0p3 */
1968 cpu->pmsav7_dregion = 16;
1969 cpu->sau_sregion = 8;
1970 cpu->isar.mvfr0 = 0x10110021;
1971 cpu->isar.mvfr1 = 0x11000011;
1972 cpu->isar.mvfr2 = 0x00000040;
1973 cpu->id_pfr0 = 0x00000030;
1974 cpu->id_pfr1 = 0x00000210;
1975 cpu->id_dfr0 = 0x00200000;
1976 cpu->id_afr0 = 0x00000000;
1977 cpu->id_mmfr0 = 0x00101F40;
1978 cpu->id_mmfr1 = 0x00000000;
1979 cpu->id_mmfr2 = 0x01000000;
1980 cpu->id_mmfr3 = 0x00000000;
1981 cpu->isar.id_isar0 = 0x01101110;
1982 cpu->isar.id_isar1 = 0x02212000;
1983 cpu->isar.id_isar2 = 0x20232232;
1984 cpu->isar.id_isar3 = 0x01111131;
1985 cpu->isar.id_isar4 = 0x01310132;
1986 cpu->isar.id_isar5 = 0x00000000;
1987 cpu->isar.id_isar6 = 0x00000000;
1988 cpu->clidr = 0x00000000;
1989 cpu->ctr = 0x8000c000;
1990 }
1991
1992 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1993 {
1994 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1995 CPUClass *cc = CPU_CLASS(oc);
1996
1997 acc->info = data;
1998 #ifndef CONFIG_USER_ONLY
1999 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
2000 #endif
2001
2002 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
2003 }
2004
2005 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
2006 /* Dummy the TCM region regs for the moment */
2007 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2008 .access = PL1_RW, .type = ARM_CP_CONST },
2009 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2010 .access = PL1_RW, .type = ARM_CP_CONST },
2011 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
2012 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
2013 REGINFO_SENTINEL
2014 };
2015
2016 static void cortex_r5_initfn(Object *obj)
2017 {
2018 ARMCPU *cpu = ARM_CPU(obj);
2019
2020 set_feature(&cpu->env, ARM_FEATURE_V7);
2021 set_feature(&cpu->env, ARM_FEATURE_V7MP);
2022 set_feature(&cpu->env, ARM_FEATURE_PMSA);
2023 cpu->midr = 0x411fc153; /* r1p3 */
2024 cpu->id_pfr0 = 0x0131;
2025 cpu->id_pfr1 = 0x001;
2026 cpu->id_dfr0 = 0x010400;
2027 cpu->id_afr0 = 0x0;
2028 cpu->id_mmfr0 = 0x0210030;
2029 cpu->id_mmfr1 = 0x00000000;
2030 cpu->id_mmfr2 = 0x01200000;
2031 cpu->id_mmfr3 = 0x0211;
2032 cpu->isar.id_isar0 = 0x02101111;
2033 cpu->isar.id_isar1 = 0x13112111;
2034 cpu->isar.id_isar2 = 0x21232141;
2035 cpu->isar.id_isar3 = 0x01112131;
2036 cpu->isar.id_isar4 = 0x0010142;
2037 cpu->isar.id_isar5 = 0x0;
2038 cpu->isar.id_isar6 = 0x0;
2039 cpu->mp_is_up = true;
2040 cpu->pmsav7_dregion = 16;
2041 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
2042 }
2043
2044 static void cortex_r5f_initfn(Object *obj)
2045 {
2046 ARMCPU *cpu = ARM_CPU(obj);
2047
2048 cortex_r5_initfn(obj);
2049 set_feature(&cpu->env, ARM_FEATURE_VFP3);
2050 cpu->isar.mvfr0 = 0x10110221;
2051 cpu->isar.mvfr1 = 0x00000011;
2052 }
2053
2054 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
2055 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
2056 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2057 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2058 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2059 REGINFO_SENTINEL
2060 };
2061
2062 static void cortex_a8_initfn(Object *obj)
2063 {
2064 ARMCPU *cpu = ARM_CPU(obj);
2065
2066 cpu->dtb_compatible = "arm,cortex-a8";
2067 set_feature(&cpu->env, ARM_FEATURE_V7);
2068 set_feature(&cpu->env, ARM_FEATURE_VFP3);
2069 set_feature(&cpu->env, ARM_FEATURE_NEON);
2070 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2071 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2072 set_feature(&cpu->env, ARM_FEATURE_EL3);
2073 cpu->midr = 0x410fc080;
2074 cpu->reset_fpsid = 0x410330c0;
2075 cpu->isar.mvfr0 = 0x11110222;
2076 cpu->isar.mvfr1 = 0x00011111;
2077 cpu->ctr = 0x82048004;
2078 cpu->reset_sctlr = 0x00c50078;
2079 cpu->id_pfr0 = 0x1031;
2080 cpu->id_pfr1 = 0x11;
2081 cpu->id_dfr0 = 0x400;
2082 cpu->id_afr0 = 0;
2083 cpu->id_mmfr0 = 0x31100003;
2084 cpu->id_mmfr1 = 0x20000000;
2085 cpu->id_mmfr2 = 0x01202000;
2086 cpu->id_mmfr3 = 0x11;
2087 cpu->isar.id_isar0 = 0x00101111;
2088 cpu->isar.id_isar1 = 0x12112111;
2089 cpu->isar.id_isar2 = 0x21232031;
2090 cpu->isar.id_isar3 = 0x11112131;
2091 cpu->isar.id_isar4 = 0x00111142;
2092 cpu->dbgdidr = 0x15141000;
2093 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2094 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2095 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2096 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2097 cpu->reset_auxcr = 2;
2098 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
2099 }
2100
2101 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
2102 /* power_control should be set to maximum latency. Again,
2103 * default to 0 and set by private hook
2104 */
2105 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2106 .access = PL1_RW, .resetvalue = 0,
2107 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
2108 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
2109 .access = PL1_RW, .resetvalue = 0,
2110 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
2111 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
2112 .access = PL1_RW, .resetvalue = 0,
2113 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
2114 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2115 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2116 /* TLB lockdown control */
2117 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
2118 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2119 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
2120 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2121 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
2122 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2123 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
2124 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2125 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
2126 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2127 REGINFO_SENTINEL
2128 };
2129
2130 static void cortex_a9_initfn(Object *obj)
2131 {
2132 ARMCPU *cpu = ARM_CPU(obj);
2133
2134 cpu->dtb_compatible = "arm,cortex-a9";
2135 set_feature(&cpu->env, ARM_FEATURE_V7);
2136 set_feature(&cpu->env, ARM_FEATURE_VFP3);
2137 set_feature(&cpu->env, ARM_FEATURE_NEON);
2138 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2139 set_feature(&cpu->env, ARM_FEATURE_EL3);
2140 /* Note that A9 supports the MP extensions even for
2141 * A9UP and single-core A9MP (which are both different
2142 * and valid configurations; we don't model A9UP).
2143 */
2144 set_feature(&cpu->env, ARM_FEATURE_V7MP);
2145 set_feature(&cpu->env, ARM_FEATURE_CBAR);
2146 cpu->midr = 0x410fc090;
2147 cpu->reset_fpsid = 0x41033090;
2148 cpu->isar.mvfr0 = 0x11110222;
2149 cpu->isar.mvfr1 = 0x01111111;
2150 cpu->ctr = 0x80038003;
2151 cpu->reset_sctlr = 0x00c50078;
2152 cpu->id_pfr0 = 0x1031;
2153 cpu->id_pfr1 = 0x11;
2154 cpu->id_dfr0 = 0x000;
2155 cpu->id_afr0 = 0;
2156 cpu->id_mmfr0 = 0x00100103;
2157 cpu->id_mmfr1 = 0x20000000;
2158 cpu->id_mmfr2 = 0x01230000;
2159 cpu->id_mmfr3 = 0x00002111;
2160 cpu->isar.id_isar0 = 0x00101111;
2161 cpu->isar.id_isar1 = 0x13112111;
2162 cpu->isar.id_isar2 = 0x21232041;
2163 cpu->isar.id_isar3 = 0x11112131;
2164 cpu->isar.id_isar4 = 0x00111142;
2165 cpu->dbgdidr = 0x35141000;
2166 cpu->clidr = (1 << 27) | (1 << 24) | 3;
2167 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2168 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
2169 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
2170 }
2171
2172 #ifndef CONFIG_USER_ONLY
2173 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2174 {
2175 MachineState *ms = MACHINE(qdev_get_machine());
2176
2177 /* Linux wants the number of processors from here.
2178 * Might as well set the interrupt-controller bit too.
2179 */
2180 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
2181 }
2182 #endif
2183
2184 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2185 #ifndef CONFIG_USER_ONLY
2186 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2187 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2188 .writefn = arm_cp_write_ignore, },
2189 #endif
2190 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2191 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2192 REGINFO_SENTINEL
2193 };
2194
2195 static void cortex_a7_initfn(Object *obj)
2196 {
2197 ARMCPU *cpu = ARM_CPU(obj);
2198
2199 cpu->dtb_compatible = "arm,cortex-a7";
2200 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2201 set_feature(&cpu->env, ARM_FEATURE_VFP4);
2202 set_feature(&cpu->env, ARM_FEATURE_NEON);
2203 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2204 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2205 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2206 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2207 set_feature(&cpu->env, ARM_FEATURE_EL2);
2208 set_feature(&cpu->env, ARM_FEATURE_EL3);
2209 set_feature(&cpu->env, ARM_FEATURE_PMU);
2210 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2211 cpu->midr = 0x410fc075;
2212 cpu->reset_fpsid = 0x41023075;
2213 cpu->isar.mvfr0 = 0x10110222;
2214 cpu->isar.mvfr1 = 0x11111111;
2215 cpu->ctr = 0x84448003;
2216 cpu->reset_sctlr = 0x00c50078;
2217 cpu->id_pfr0 = 0x00001131;
2218 cpu->id_pfr1 = 0x00011011;
2219 cpu->id_dfr0 = 0x02010555;
2220 cpu->id_afr0 = 0x00000000;
2221 cpu->id_mmfr0 = 0x10101105;
2222 cpu->id_mmfr1 = 0x40000000;
2223 cpu->id_mmfr2 = 0x01240000;
2224 cpu->id_mmfr3 = 0x02102211;
2225 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2226 * table 4-41 gives 0x02101110, which includes the arm div insns.
2227 */
2228 cpu->isar.id_isar0 = 0x02101110;
2229 cpu->isar.id_isar1 = 0x13112111;
2230 cpu->isar.id_isar2 = 0x21232041;
2231 cpu->isar.id_isar3 = 0x11112131;
2232 cpu->isar.id_isar4 = 0x10011142;
2233 cpu->dbgdidr = 0x3515f005;
2234 cpu->clidr = 0x0a200023;
2235 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2236 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2237 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2238 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2239 }
2240
2241 static void cortex_a15_initfn(Object *obj)
2242 {
2243 ARMCPU *cpu = ARM_CPU(obj);
2244
2245 cpu->dtb_compatible = "arm,cortex-a15";
2246 set_feature(&cpu->env, ARM_FEATURE_V7VE);
2247 set_feature(&cpu->env, ARM_FEATURE_VFP4);
2248 set_feature(&cpu->env, ARM_FEATURE_NEON);
2249 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
2250 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2251 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2252 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
2253 set_feature(&cpu->env, ARM_FEATURE_EL2);
2254 set_feature(&cpu->env, ARM_FEATURE_EL3);
2255 set_feature(&cpu->env, ARM_FEATURE_PMU);
2256 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
2257 cpu->midr = 0x412fc0f1;
2258 cpu->reset_fpsid = 0x410430f0;
2259 cpu->isar.mvfr0 = 0x10110222;
2260 cpu->isar.mvfr1 = 0x11111111;
2261 cpu->ctr = 0x8444c004;
2262 cpu->reset_sctlr = 0x00c50078;
2263 cpu->id_pfr0 = 0x00001131;
2264 cpu->id_pfr1 = 0x00011011;
2265 cpu->id_dfr0 = 0x02010555;
2266 cpu->id_afr0 = 0x00000000;
2267 cpu->id_mmfr0 = 0x10201105;
2268 cpu->id_mmfr1 = 0x20000000;
2269 cpu->id_mmfr2 = 0x01240000;
2270 cpu->id_mmfr3 = 0x02102211;
2271 cpu->isar.id_isar0 = 0x02101110;
2272 cpu->isar.id_isar1 = 0x13112111;
2273 cpu->isar.id_isar2 = 0x21232041;
2274 cpu->isar.id_isar3 = 0x11112131;
2275 cpu->isar.id_isar4 = 0x10011142;
2276 cpu->dbgdidr = 0x3515f021;
2277 cpu->clidr = 0x0a200023;
2278 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2279 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2280 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2281 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
2282 }
2283
2284 static void ti925t_initfn(Object *obj)
2285 {
2286 ARMCPU *cpu = ARM_CPU(obj);
2287 set_feature(&cpu->env, ARM_FEATURE_V4T);
2288 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
2289 cpu->midr = ARM_CPUID_TI925T;
2290 cpu->ctr = 0x5109149;
2291 cpu->reset_sctlr = 0x00000070;
2292 }
2293
2294 static void sa1100_initfn(Object *obj)
2295 {
2296 ARMCPU *cpu = ARM_CPU(obj);
2297
2298 cpu->dtb_compatible = "intel,sa1100";
2299 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2300 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2301 cpu->midr = 0x4401A11B;
2302 cpu->reset_sctlr = 0x00000070;
2303 }
2304
2305 static void sa1110_initfn(Object *obj)
2306 {
2307 ARMCPU *cpu = ARM_CPU(obj);
2308 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
2309 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2310 cpu->midr = 0x6901B119;
2311 cpu->reset_sctlr = 0x00000070;
2312 }
2313
2314 static void pxa250_initfn(Object *obj)
2315 {
2316 ARMCPU *cpu = ARM_CPU(obj);
2317
2318 cpu->dtb_compatible = "marvell,xscale";
2319 set_feature(&cpu->env, ARM_FEATURE_V5);
2320 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2321 cpu->midr = 0x69052100;
2322 cpu->ctr = 0xd172172;
2323 cpu->reset_sctlr = 0x00000078;
2324 }
2325
2326 static void pxa255_initfn(Object *obj)
2327 {
2328 ARMCPU *cpu = ARM_CPU(obj);
2329
2330 cpu->dtb_compatible = "marvell,xscale";
2331 set_feature(&cpu->env, ARM_FEATURE_V5);
2332 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2333 cpu->midr = 0x69052d00;
2334 cpu->ctr = 0xd172172;
2335 cpu->reset_sctlr = 0x00000078;
2336 }
2337
2338 static void pxa260_initfn(Object *obj)
2339 {
2340 ARMCPU *cpu = ARM_CPU(obj);
2341
2342 cpu->dtb_compatible = "marvell,xscale";
2343 set_feature(&cpu->env, ARM_FEATURE_V5);
2344 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2345 cpu->midr = 0x69052903;
2346 cpu->ctr = 0xd172172;
2347 cpu->reset_sctlr = 0x00000078;
2348 }
2349
2350 static void pxa261_initfn(Object *obj)
2351 {
2352 ARMCPU *cpu = ARM_CPU(obj);
2353
2354 cpu->dtb_compatible = "marvell,xscale";
2355 set_feature(&cpu->env, ARM_FEATURE_V5);
2356 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2357 cpu->midr = 0x69052d05;
2358 cpu->ctr = 0xd172172;
2359 cpu->reset_sctlr = 0x00000078;
2360 }
2361
2362 static void pxa262_initfn(Object *obj)
2363 {
2364 ARMCPU *cpu = ARM_CPU(obj);
2365
2366 cpu->dtb_compatible = "marvell,xscale";
2367 set_feature(&cpu->env, ARM_FEATURE_V5);
2368 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2369 cpu->midr = 0x69052d06;
2370 cpu->ctr = 0xd172172;
2371 cpu->reset_sctlr = 0x00000078;
2372 }
2373
2374 static void pxa270a0_initfn(Object *obj)
2375 {
2376 ARMCPU *cpu = ARM_CPU(obj);
2377
2378 cpu->dtb_compatible = "marvell,xscale";
2379 set_feature(&cpu->env, ARM_FEATURE_V5);
2380 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2381 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2382 cpu->midr = 0x69054110;
2383 cpu->ctr = 0xd172172;
2384 cpu->reset_sctlr = 0x00000078;
2385 }
2386
2387 static void pxa270a1_initfn(Object *obj)
2388 {
2389 ARMCPU *cpu = ARM_CPU(obj);
2390
2391 cpu->dtb_compatible = "marvell,xscale";
2392 set_feature(&cpu->env, ARM_FEATURE_V5);
2393 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2394 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2395 cpu->midr = 0x69054111;
2396 cpu->ctr = 0xd172172;
2397 cpu->reset_sctlr = 0x00000078;
2398 }
2399
2400 static void pxa270b0_initfn(Object *obj)
2401 {
2402 ARMCPU *cpu = ARM_CPU(obj);
2403
2404 cpu->dtb_compatible = "marvell,xscale";
2405 set_feature(&cpu->env, ARM_FEATURE_V5);
2406 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2407 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2408 cpu->midr = 0x69054112;
2409 cpu->ctr = 0xd172172;
2410 cpu->reset_sctlr = 0x00000078;
2411 }
2412
2413 static void pxa270b1_initfn(Object *obj)
2414 {
2415 ARMCPU *cpu = ARM_CPU(obj);
2416
2417 cpu->dtb_compatible = "marvell,xscale";
2418 set_feature(&cpu->env, ARM_FEATURE_V5);
2419 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2420 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2421 cpu->midr = 0x69054113;
2422 cpu->ctr = 0xd172172;
2423 cpu->reset_sctlr = 0x00000078;
2424 }
2425
2426 static void pxa270c0_initfn(Object *obj)
2427 {
2428 ARMCPU *cpu = ARM_CPU(obj);
2429
2430 cpu->dtb_compatible = "marvell,xscale";
2431 set_feature(&cpu->env, ARM_FEATURE_V5);
2432 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2433 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2434 cpu->midr = 0x69054114;
2435 cpu->ctr = 0xd172172;
2436 cpu->reset_sctlr = 0x00000078;
2437 }
2438
2439 static void pxa270c5_initfn(Object *obj)
2440 {
2441 ARMCPU *cpu = ARM_CPU(obj);
2442
2443 cpu->dtb_compatible = "marvell,xscale";
2444 set_feature(&cpu->env, ARM_FEATURE_V5);
2445 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2446 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
2447 cpu->midr = 0x69054117;
2448 cpu->ctr = 0xd172172;
2449 cpu->reset_sctlr = 0x00000078;
2450 }
2451
2452 #ifndef TARGET_AARCH64
2453 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2454 * otherwise, a CPU with as many features enabled as our emulation supports.
2455 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2456 * this only needs to handle 32 bits.
2457 */
2458 static void arm_max_initfn(Object *obj)
2459 {
2460 ARMCPU *cpu = ARM_CPU(obj);
2461
2462 if (kvm_enabled()) {
2463 kvm_arm_set_cpu_features_from_host(cpu);
2464 } else {
2465 cortex_a15_initfn(obj);
2466
2467 /* old-style VFP short-vector support */
2468 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2469
2470 #ifdef CONFIG_USER_ONLY
2471 /* We don't set these in system emulation mode for the moment,
2472 * since we don't correctly set (all of) the ID registers to
2473 * advertise them.
2474 */
2475 set_feature(&cpu->env, ARM_FEATURE_V8);
2476 {
2477 uint32_t t;
2478
2479 t = cpu->isar.id_isar5;
2480 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2481 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2482 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2483 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2484 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2485 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2486 cpu->isar.id_isar5 = t;
2487
2488 t = cpu->isar.id_isar6;
2489 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2490 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2491 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2492 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2493 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2494 cpu->isar.id_isar6 = t;
2495
2496 t = cpu->isar.mvfr1;
2497 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
2498 cpu->isar.mvfr1 = t;
2499
2500 t = cpu->isar.mvfr2;
2501 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2502 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2503 cpu->isar.mvfr2 = t;
2504
2505 t = cpu->id_mmfr4;
2506 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2507 cpu->id_mmfr4 = t;
2508 }
2509 #endif
2510 }
2511 }
2512 #endif
2513
2514 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2515
2516 struct ARMCPUInfo {
2517 const char *name;
2518 void (*initfn)(Object *obj);
2519 void (*class_init)(ObjectClass *oc, void *data);
2520 };
2521
2522 static const ARMCPUInfo arm_cpus[] = {
2523 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2524 { .name = "arm926", .initfn = arm926_initfn },
2525 { .name = "arm946", .initfn = arm946_initfn },
2526 { .name = "arm1026", .initfn = arm1026_initfn },
2527 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2528 * older core than plain "arm1136". In particular this does not
2529 * have the v6K features.
2530 */
2531 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
2532 { .name = "arm1136", .initfn = arm1136_initfn },
2533 { .name = "arm1176", .initfn = arm1176_initfn },
2534 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
2535 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
2536 .class_init = arm_v7m_class_init },
2537 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
2538 .class_init = arm_v7m_class_init },
2539 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
2540 .class_init = arm_v7m_class_init },
2541 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
2542 .class_init = arm_v7m_class_init },
2543 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
2544 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
2545 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
2546 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2547 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2548 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2549 { .name = "ti925t", .initfn = ti925t_initfn },
2550 { .name = "sa1100", .initfn = sa1100_initfn },
2551 { .name = "sa1110", .initfn = sa1110_initfn },
2552 { .name = "pxa250", .initfn = pxa250_initfn },
2553 { .name = "pxa255", .initfn = pxa255_initfn },
2554 { .name = "pxa260", .initfn = pxa260_initfn },
2555 { .name = "pxa261", .initfn = pxa261_initfn },
2556 { .name = "pxa262", .initfn = pxa262_initfn },
2557 /* "pxa270" is an alias for "pxa270-a0" */
2558 { .name = "pxa270", .initfn = pxa270a0_initfn },
2559 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
2560 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
2561 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
2562 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
2563 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
2564 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
2565 #ifndef TARGET_AARCH64
2566 { .name = "max", .initfn = arm_max_initfn },
2567 #endif
2568 #ifdef CONFIG_USER_ONLY
2569 { .name = "any", .initfn = arm_max_initfn },
2570 #endif
2571 #endif
2572 { .name = NULL }
2573 };
2574
2575 static Property arm_cpu_properties[] = {
2576 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2577 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2578 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2579 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2580 mp_affinity, ARM64_AFFINITY_INVALID),
2581 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2582 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2583 DEFINE_PROP_END_OF_LIST()
2584 };
2585
2586 static gchar *arm_gdb_arch_name(CPUState *cs)
2587 {
2588 ARMCPU *cpu = ARM_CPU(cs);
2589 CPUARMState *env = &cpu->env;
2590
2591 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2592 return g_strdup("iwmmxt");
2593 }
2594 return g_strdup("arm");
2595 }
2596
2597 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2598 {
2599 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2600 CPUClass *cc = CPU_CLASS(acc);
2601 DeviceClass *dc = DEVICE_CLASS(oc);
2602
2603 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2604 &acc->parent_realize);
2605 dc->props = arm_cpu_properties;
2606
2607 acc->parent_reset = cc->reset;
2608 cc->reset = arm_cpu_reset;
2609
2610 cc->class_by_name = arm_cpu_class_by_name;
2611 cc->has_work = arm_cpu_has_work;
2612 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2613 cc->dump_state = arm_cpu_dump_state;
2614 cc->set_pc = arm_cpu_set_pc;
2615 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
2616 cc->gdb_read_register = arm_cpu_gdb_read_register;
2617 cc->gdb_write_register = arm_cpu_gdb_write_register;
2618 #ifndef CONFIG_USER_ONLY
2619 cc->do_interrupt = arm_cpu_do_interrupt;
2620 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2621 cc->asidx_from_attrs = arm_asidx_from_attrs;
2622 cc->vmsd = &vmstate_arm_cpu;
2623 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2624 cc->write_elf64_note = arm_cpu_write_elf64_note;
2625 cc->write_elf32_note = arm_cpu_write_elf32_note;
2626 #endif
2627 cc->gdb_num_core_regs = 26;
2628 cc->gdb_core_xml_file = "arm-core.xml";
2629 cc->gdb_arch_name = arm_gdb_arch_name;
2630 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2631 cc->gdb_stop_before_watchpoint = true;
2632 cc->disas_set_info = arm_disas_set_info;
2633 #ifdef CONFIG_TCG
2634 cc->tcg_initialize = arm_translate_init;
2635 cc->tlb_fill = arm_cpu_tlb_fill;
2636 cc->debug_excp_handler = arm_debug_excp_handler;
2637 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2638 #if !defined(CONFIG_USER_ONLY)
2639 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2640 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2641 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2642 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2643 #endif
2644 }
2645
2646 #ifdef CONFIG_KVM
2647 static void arm_host_initfn(Object *obj)
2648 {
2649 ARMCPU *cpu = ARM_CPU(obj);
2650
2651 kvm_arm_set_cpu_features_from_host(cpu);
2652 arm_cpu_post_init(obj);
2653 }
2654
2655 static const TypeInfo host_arm_cpu_type_info = {
2656 .name = TYPE_ARM_HOST_CPU,
2657 #ifdef TARGET_AARCH64
2658 .parent = TYPE_AARCH64_CPU,
2659 #else
2660 .parent = TYPE_ARM_CPU,
2661 #endif
2662 .instance_init = arm_host_initfn,
2663 };
2664
2665 #endif
2666
2667 static void arm_cpu_instance_init(Object *obj)
2668 {
2669 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2670
2671 acc->info->initfn(obj);
2672 arm_cpu_post_init(obj);
2673 }
2674
2675 static void cpu_register_class_init(ObjectClass *oc, void *data)
2676 {
2677 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2678
2679 acc->info = data;
2680 }
2681
2682 static void cpu_register(const ARMCPUInfo *info)
2683 {
2684 TypeInfo type_info = {
2685 .parent = TYPE_ARM_CPU,
2686 .instance_size = sizeof(ARMCPU),
2687 .instance_init = arm_cpu_instance_init,
2688 .class_size = sizeof(ARMCPUClass),
2689 .class_init = info->class_init ?: cpu_register_class_init,
2690 .class_data = (void *)info,
2691 };
2692
2693 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2694 type_register(&type_info);
2695 g_free((void *)type_info.name);
2696 }
2697
2698 static const TypeInfo arm_cpu_type_info = {
2699 .name = TYPE_ARM_CPU,
2700 .parent = TYPE_CPU,
2701 .instance_size = sizeof(ARMCPU),
2702 .instance_init = arm_cpu_initfn,
2703 .instance_finalize = arm_cpu_finalizefn,
2704 .abstract = true,
2705 .class_size = sizeof(ARMCPUClass),
2706 .class_init = arm_cpu_class_init,
2707 };
2708
2709 static const TypeInfo idau_interface_type_info = {
2710 .name = TYPE_IDAU_INTERFACE,
2711 .parent = TYPE_INTERFACE,
2712 .class_size = sizeof(IDAUInterfaceClass),
2713 };
2714
2715 static void arm_cpu_register_types(void)
2716 {
2717 const ARMCPUInfo *info = arm_cpus;
2718
2719 type_register_static(&arm_cpu_type_info);
2720 type_register_static(&idau_interface_type_info);
2721
2722 while (info->name) {
2723 cpu_register(info);
2724 info++;
2725 }
2726
2727 #ifdef CONFIG_KVM
2728 type_register_static(&host_arm_cpu_type_info);
2729 #endif
2730 }
2731
2732 type_init(arm_cpu_register_types)
QEmu