include/hw/pci-host/spapr.h

   1 /*
   2  * QEMU SPAPR PCI BUS definitions
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PCI_HOST_SPAPR_H
  21 #define PCI_HOST_SPAPR_H
  22
  23 #include "hw/ppc/spapr.h"
  24 #include "hw/pci/pci.h"
  25 #include "hw/pci/pci_host.h"
  26 #include "hw/ppc/xics.h"
  27
  28 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
  29
  30 #define SPAPR_PCI_HOST_BRIDGE(obj) \
  31     OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
  32
  33 #define SPAPR_PCI_DMA_MAX_WINDOWS    2
  34
  35 typedef struct sPAPRPHBState sPAPRPHBState;
  36
  37 typedef struct spapr_pci_msi {
  38     uint32_t first_irq;
  39     uint32_t num;
  40 } spapr_pci_msi;
  41
  42 typedef struct spapr_pci_msi_mig {
  43     uint32_t key;
  44     spapr_pci_msi value;
  45 } spapr_pci_msi_mig;
  46
  47 struct sPAPRPHBState {
  48     PCIHostState parent_obj;
  49
  50     uint32_t index;
  51     uint64_t buid;
  52     char *dtbusname;
  53     bool dr_enabled;
  54
  55     MemoryRegion memspace, iospace;
  56     hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
  57     MemoryRegion memwindow, iowindow, msiwindow;
  58
  59     uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
  60     hwaddr dma_win_addr, dma_win_size;
  61     AddressSpace iommu_as;
  62     MemoryRegion iommu_root;
  63
  64     struct spapr_pci_lsi {
  65         uint32_t irq;
  66     } lsi_table[PCI_NUM_PINS];
  67
  68     GHashTable *msi;
  69     /* Temporary cache for migration purposes */
  70     int32_t msi_devs_num;
  71     spapr_pci_msi_mig *msi_devs;
  72
  73     QLIST_ENTRY(sPAPRPHBState) list;
  74
  75     bool ddw_enabled;
  76     uint64_t page_size_mask;
  77     uint64_t dma64_win_addr;
  78 };
  79
  80 #define SPAPR_PCI_MAX_INDEX          255
  81
  82 #define SPAPR_PCI_BASE_BUID          0x800000020000000ULL
  83
  84 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
  85
  86 #define SPAPR_PCI_WINDOW_BASE        0x10000000000ULL
  87 #define SPAPR_PCI_WINDOW_SPACING     0x1000000000ULL
  88 #define SPAPR_PCI_MMIO_WIN_OFF       0xA0000000
  89 #define SPAPR_PCI_MMIO_WIN_SIZE      (SPAPR_PCI_WINDOW_SPACING - \
  90                                      SPAPR_PCI_MEM_WIN_BUS_OFFSET)
  91 #define SPAPR_PCI_IO_WIN_OFF         0x80000000
  92 #define SPAPR_PCI_IO_WIN_SIZE        0x10000
  93
  94 #define SPAPR_PCI_MSI_WINDOW         0x40000000000ULL
  95
  96 static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
  97 {
  98     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  99
 100     return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
 101 }
 102
 103 PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
 104
 105 int spapr_populate_pci_dt(sPAPRPHBState *phb,
 106                           uint32_t xics_phandle,
 107                           void *fdt);
 108
 109 void spapr_pci_rtas_init(void);
 110
 111 sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
 112 PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
 113                               uint32_t config_addr);
 114
 115 /* VFIO EEH hooks */
 116 #ifdef CONFIG_LINUX
 117 bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
 118 int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
 119                                   unsigned int addr, int option);
 120 int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
 121 int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
 122 int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
 123 void spapr_phb_vfio_reset(DeviceState *qdev);
 124 #else
 125 static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
 126 {
 127     return false;
 128 }
 129 static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
 130                                                 unsigned int addr, int option)
 131 {
 132     return RTAS_OUT_HW_ERROR;
 133 }
 134 static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
 135                                                int *state)
 136 {
 137     return RTAS_OUT_HW_ERROR;
 138 }
 139 static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
 140 {
 141     return RTAS_OUT_HW_ERROR;
 142 }
 143 static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
 144 {
 145     return RTAS_OUT_HW_ERROR;
 146 }
 147 static inline void spapr_phb_vfio_reset(DeviceState *qdev)
 148 {
 149 }
 150 #endif
 151
 152 void spapr_phb_dma_reset(sPAPRPHBState *sphb);
 153
 154 #endif /* PCI_HOST_SPAPR_H */