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pci: pci bridge related clean up.
[qemu.git] / hw / pci.c
blobe26b3d0341bb72d322ce457bdff22b0512613e4a
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "monitor.h"
27 #include "net.h"
28 #include "sysemu.h"
29
30 //#define DEBUG_PCI
31 #ifdef DEBUG_PCI
32 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
33 #else
34 # define PCI_DPRINTF(format, ...) do { } while (0)
35 #endif
36
37 struct PCIBus {
38 BusState qbus;
39 int devfn_min;
40 pci_set_irq_fn set_irq;
41 pci_map_irq_fn map_irq;
42 pci_hotplug_fn hotplug;
43 uint32_t config_reg; /* XXX: suppress */
44 void *irq_opaque;
45 PCIDevice *devices[256];
46 PCIDevice *parent_dev;
47
48 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
49 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
50
51 /* The bus IRQ state is the logical OR of the connected devices.
52 Keep a count of the number of devices with raised IRQs. */
53 int nirq;
54 int *irq_count;
55 };
56
57 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
58
59 static struct BusInfo pci_bus_info = {
60 .name = "PCI",
61 .size = sizeof(PCIBus),
62 .print_dev = pcibus_dev_print,
63 .props = (Property[]) {
64 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
65 DEFINE_PROP_END_OF_LIST()
66 }
67 };
68
69 static void pci_update_mappings(PCIDevice *d);
70 static void pci_set_irq(void *opaque, int irq_num, int level);
71
72 target_phys_addr_t pci_mem_base;
73 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
74 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
75
76 struct PCIHostBus {
77 int domain;
78 struct PCIBus *bus;
79 QLIST_ENTRY(PCIHostBus) next;
80 };
81 static QLIST_HEAD(, PCIHostBus) host_buses;
82
83 static const VMStateDescription vmstate_pcibus = {
84 .name = "PCIBUS",
85 .version_id = 1,
86 .minimum_version_id = 1,
87 .minimum_version_id_old = 1,
88 .fields = (VMStateField []) {
89 VMSTATE_INT32_EQUAL(nirq, PCIBus),
90 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
91 VMSTATE_END_OF_LIST()
92 }
93 };
94
95 static int pci_bar(PCIDevice *d, int reg)
96 {
97 uint8_t type;
98
99 if (reg != PCI_ROM_SLOT)
100 return PCI_BASE_ADDRESS_0 + reg * 4;
101
102 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
103 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
104 }
105
106 static void pci_device_reset(PCIDevice *dev)
107 {
108 int r;
109
110 memset(dev->irq_state, 0, sizeof dev->irq_state);
111 dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
112 PCI_COMMAND_MASTER);
113 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
114 dev->config[PCI_INTERRUPT_LINE] = 0x0;
115 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
116 if (!dev->io_regions[r].size) {
117 continue;
118 }
119 pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
120 }
121 pci_update_mappings(dev);
122 }
123
124 static void pci_bus_reset(void *opaque)
125 {
126 PCIBus *bus = opaque;
127 int i;
128
129 for (i = 0; i < bus->nirq; i++) {
130 bus->irq_count[i] = 0;
131 }
132 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
133 if (bus->devices[i]) {
134 pci_device_reset(bus->devices[i]);
135 }
136 }
137 }
138
139 static void pci_host_bus_register(int domain, PCIBus *bus)
140 {
141 struct PCIHostBus *host;
142 host = qemu_mallocz(sizeof(*host));
143 host->domain = domain;
144 host->bus = bus;
145 QLIST_INSERT_HEAD(&host_buses, host, next);
146 }
147
148 PCIBus *pci_find_root_bus(int domain)
149 {
150 struct PCIHostBus *host;
151
152 QLIST_FOREACH(host, &host_buses, next) {
153 if (host->domain == domain) {
154 return host->bus;
155 }
156 }
157
158 return NULL;
159 }
160
161 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
162 const char *name, int devfn_min)
163 {
164 static int nbus = 0;
165
166 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
167 bus->devfn_min = devfn_min;
168
169 /* host bridge */
170 QLIST_INIT(&bus->child);
171 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
172
173 vmstate_register(nbus++, &vmstate_pcibus, bus);
174 qemu_register_reset(pci_bus_reset, bus);
175 }
176
177 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
178 {
179 PCIBus *bus;
180
181 bus = qemu_mallocz(sizeof(*bus));
182 bus->qbus.qdev_allocated = 1;
183 pci_bus_new_inplace(bus, parent, name, devfn_min);
184 return bus;
185 }
186
187 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
188 void *irq_opaque, int nirq)
189 {
190 bus->set_irq = set_irq;
191 bus->map_irq = map_irq;
192 bus->irq_opaque = irq_opaque;
193 bus->nirq = nirq;
194 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
195 }
196
197 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
198 {
199 bus->qbus.allow_hotplug = 1;
200 bus->hotplug = hotplug;
201 }
202
203 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
204 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
205 void *irq_opaque, int devfn_min, int nirq)
206 {
207 PCIBus *bus;
208
209 bus = pci_bus_new(parent, name, devfn_min);
210 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
211 return bus;
212 }
213
214 static void pci_register_secondary_bus(PCIBus *parent,
215 PCIBus *bus,
216 PCIDevice *dev,
217 pci_map_irq_fn map_irq,
218 const char *name)
219 {
220 qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
221 bus->map_irq = map_irq;
222 bus->parent_dev = dev;
223
224 QLIST_INIT(&bus->child);
225 QLIST_INSERT_HEAD(&parent->child, bus, sibling);
226 }
227
228 static void pci_unregister_secondary_bus(PCIBus *bus)
229 {
230 assert(QLIST_EMPTY(&bus->child));
231 QLIST_REMOVE(bus, sibling);
232 }
233
234 int pci_bus_num(PCIBus *s)
235 {
236 if (!s->parent_dev)
237 return 0; /* pci host bridge */
238 return s->parent_dev->config[PCI_SECONDARY_BUS];
239 }
240
241 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
242 {
243 PCIDevice *s = container_of(pv, PCIDevice, config);
244 uint8_t *config;
245 int i;
246
247 assert(size == pci_config_size(s));
248 config = qemu_malloc(size);
249
250 qemu_get_buffer(f, config, size);
251 for (i = 0; i < size; ++i) {
252 if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
253 qemu_free(config);
254 return -EINVAL;
255 }
256 }
257 memcpy(s->config, config, size);
258
259 pci_update_mappings(s);
260
261 qemu_free(config);
262 return 0;
263 }
264
265 /* just put buffer */
266 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
267 {
268 const uint8_t **v = pv;
269 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
270 qemu_put_buffer(f, *v, size);
271 }
272
273 static VMStateInfo vmstate_info_pci_config = {
274 .name = "pci config",
275 .get = get_pci_config_device,
276 .put = put_pci_config_device,
277 };
278
279 const VMStateDescription vmstate_pci_device = {
280 .name = "PCIDevice",
281 .version_id = 2,
282 .minimum_version_id = 1,
283 .minimum_version_id_old = 1,
284 .fields = (VMStateField []) {
285 VMSTATE_INT32_LE(version_id, PCIDevice),
286 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
287 vmstate_info_pci_config,
288 PCI_CONFIG_SPACE_SIZE),
289 VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
290 VMSTATE_END_OF_LIST()
291 }
292 };
293
294 const VMStateDescription vmstate_pcie_device = {
295 .name = "PCIDevice",
296 .version_id = 2,
297 .minimum_version_id = 1,
298 .minimum_version_id_old = 1,
299 .fields = (VMStateField []) {
300 VMSTATE_INT32_LE(version_id, PCIDevice),
301 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
302 vmstate_info_pci_config,
303 PCIE_CONFIG_SPACE_SIZE),
304 VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
305 VMSTATE_END_OF_LIST()
306 }
307 };
308
309 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
310 {
311 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
312 }
313
314 void pci_device_save(PCIDevice *s, QEMUFile *f)
315 {
316 vmstate_save_state(f, pci_get_vmstate(s), s);
317 }
318
319 int pci_device_load(PCIDevice *s, QEMUFile *f)
320 {
321 return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
322 }
323
324 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
325 {
326 uint16_t *id;
327
328 id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
329 id[0] = cpu_to_le16(pci_default_sub_vendor_id);
330 id[1] = cpu_to_le16(pci_default_sub_device_id);
331 return 0;
332 }
333
334 /*
335 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
336 */
337 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
338 {
339 const char *p;
340 char *e;
341 unsigned long val;
342 unsigned long dom = 0, bus = 0;
343 unsigned slot = 0;
344
345 p = addr;
346 val = strtoul(p, &e, 16);
347 if (e == p)
348 return -1;
349 if (*e == ':') {
350 bus = val;
351 p = e + 1;
352 val = strtoul(p, &e, 16);
353 if (e == p)
354 return -1;
355 if (*e == ':') {
356 dom = bus;
357 bus = val;
358 p = e + 1;
359 val = strtoul(p, &e, 16);
360 if (e == p)
361 return -1;
362 }
363 }
364
365 if (dom > 0xffff || bus > 0xff || val > 0x1f)
366 return -1;
367
368 slot = val;
369
370 if (*e)
371 return -1;
372
373 /* Note: QEMU doesn't implement domains other than 0 */
374 if (!pci_find_bus(pci_find_root_bus(dom), bus))
375 return -1;
376
377 *domp = dom;
378 *busp = bus;
379 *slotp = slot;
380 return 0;
381 }
382
383 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
384 unsigned *slotp)
385 {
386 /* strip legacy tag */
387 if (!strncmp(addr, "pci_addr=", 9)) {
388 addr += 9;
389 }
390 if (pci_parse_devaddr(addr, domp, busp, slotp)) {
391 monitor_printf(mon, "Invalid pci address\n");
392 return -1;
393 }
394 return 0;
395 }
396
397 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
398 {
399 int dom, bus;
400 unsigned slot;
401
402 if (!devaddr) {
403 *devfnp = -1;
404 return pci_find_bus(pci_find_root_bus(0), 0);
405 }
406
407 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
408 return NULL;
409 }
410
411 *devfnp = slot << 3;
412 return pci_find_bus(pci_find_root_bus(0), bus);
413 }
414
415 static void pci_init_cmask(PCIDevice *dev)
416 {
417 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
418 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
419 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
420 dev->cmask[PCI_REVISION_ID] = 0xff;
421 dev->cmask[PCI_CLASS_PROG] = 0xff;
422 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
423 dev->cmask[PCI_HEADER_TYPE] = 0xff;
424 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
425 }
426
427 static void pci_init_wmask(PCIDevice *dev)
428 {
429 int config_size = pci_config_size(dev);
430
431 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
432 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
433 pci_set_word(dev->wmask + PCI_COMMAND,
434 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
435
436 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
437 config_size - PCI_CONFIG_HEADER_SIZE);
438 }
439
440 static void pci_init_wmask_bridge(PCIDevice *d)
441 {
442 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
443 PCI_SEC_LETENCY_TIMER */
444 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
445
446 /* base and limit */
447 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
448 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
449 pci_set_word(d->wmask + PCI_MEMORY_BASE,
450 PCI_MEMORY_RANGE_MASK & 0xffff);
451 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
452 PCI_MEMORY_RANGE_MASK & 0xffff);
453 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
454 PCI_PREF_RANGE_MASK & 0xffff);
455 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
456 PCI_PREF_RANGE_MASK & 0xffff);
457
458 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
459 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
460
461 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
462 }
463
464 static void pci_config_alloc(PCIDevice *pci_dev)
465 {
466 int config_size = pci_config_size(pci_dev);
467
468 pci_dev->config = qemu_mallocz(config_size);
469 pci_dev->cmask = qemu_mallocz(config_size);
470 pci_dev->wmask = qemu_mallocz(config_size);
471 pci_dev->used = qemu_mallocz(config_size);
472 }
473
474 static void pci_config_free(PCIDevice *pci_dev)
475 {
476 qemu_free(pci_dev->config);
477 qemu_free(pci_dev->cmask);
478 qemu_free(pci_dev->wmask);
479 qemu_free(pci_dev->used);
480 }
481
482 /* -1 for devfn means auto assign */
483 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
484 const char *name, int devfn,
485 PCIConfigReadFunc *config_read,
486 PCIConfigWriteFunc *config_write,
487 uint8_t header_type)
488 {
489 if (devfn < 0) {
490 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
491 devfn += 8) {
492 if (!bus->devices[devfn])
493 goto found;
494 }
495 hw_error("PCI: no devfn available for %s, all in use\n", name);
496 found: ;
497 } else if (bus->devices[devfn]) {
498 hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
499 name, bus->devices[devfn]->name);
500 }
501 pci_dev->bus = bus;
502 pci_dev->devfn = devfn;
503 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
504 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
505 pci_config_alloc(pci_dev);
506
507 header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
508 if (header_type == PCI_HEADER_TYPE_NORMAL) {
509 pci_set_default_subsystem_id(pci_dev);
510 }
511 pci_init_cmask(pci_dev);
512 pci_init_wmask(pci_dev);
513 if (header_type == PCI_HEADER_TYPE_BRIDGE) {
514 pci_init_wmask_bridge(pci_dev);
515 }
516
517 if (!config_read)
518 config_read = pci_default_read_config;
519 if (!config_write)
520 config_write = pci_default_write_config;
521 pci_dev->config_read = config_read;
522 pci_dev->config_write = config_write;
523 bus->devices[devfn] = pci_dev;
524 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
525 pci_dev->version_id = 2; /* Current pci device vmstate version */
526 return pci_dev;
527 }
528
529 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
530 int instance_size, int devfn,
531 PCIConfigReadFunc *config_read,
532 PCIConfigWriteFunc *config_write)
533 {
534 PCIDevice *pci_dev;
535
536 pci_dev = qemu_mallocz(instance_size);
537 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
538 config_read, config_write,
539 PCI_HEADER_TYPE_NORMAL);
540 return pci_dev;
541 }
542 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
543 {
544 return addr + pci_mem_base;
545 }
546
547 static void pci_unregister_io_regions(PCIDevice *pci_dev)
548 {
549 PCIIORegion *r;
550 int i;
551
552 for(i = 0; i < PCI_NUM_REGIONS; i++) {
553 r = &pci_dev->io_regions[i];
554 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
555 continue;
556 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
557 isa_unassign_ioport(r->addr, r->filtered_size);
558 } else {
559 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
560 r->filtered_size,
561 IO_MEM_UNASSIGNED);
562 }
563 }
564 }
565
566 static int pci_unregister_device(DeviceState *dev)
567 {
568 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
569 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
570 int ret = 0;
571
572 if (info->exit)
573 ret = info->exit(pci_dev);
574 if (ret)
575 return ret;
576
577 pci_unregister_io_regions(pci_dev);
578
579 qemu_free_irqs(pci_dev->irq);
580 pci_dev->bus->devices[pci_dev->devfn] = NULL;
581 pci_config_free(pci_dev);
582 return 0;
583 }
584
585 void pci_register_bar(PCIDevice *pci_dev, int region_num,
586 pcibus_t size, int type,
587 PCIMapIORegionFunc *map_func)
588 {
589 PCIIORegion *r;
590 uint32_t addr;
591 pcibus_t wmask;
592
593 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
594 return;
595
596 if (size & (size-1)) {
597 fprintf(stderr, "ERROR: PCI region size must be pow2 "
598 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
599 exit(1);
600 }
601
602 r = &pci_dev->io_regions[region_num];
603 r->addr = PCI_BAR_UNMAPPED;
604 r->size = size;
605 r->filtered_size = size;
606 r->type = type;
607 r->map_func = map_func;
608
609 wmask = ~(size - 1);
610 addr = pci_bar(pci_dev, region_num);
611 if (region_num == PCI_ROM_SLOT) {
612 /* ROM enable bit is writeable */
613 wmask |= PCI_ROM_ADDRESS_ENABLE;
614 }
615 pci_set_long(pci_dev->config + addr, type);
616 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
617 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
618 pci_set_quad(pci_dev->wmask + addr, wmask);
619 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
620 } else {
621 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
622 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
623 }
624 }
625
626 static uint32_t pci_config_get_io_base(PCIDevice *d,
627 uint32_t base, uint32_t base_upper16)
628 {
629 uint32_t val;
630
631 val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
632 if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
633 val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
634 }
635 return val;
636 }
637
638 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
639 {
640 return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
641 << 16;
642 }
643
644 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
645 uint32_t base, uint32_t upper)
646 {
647 pcibus_t tmp;
648 pcibus_t val;
649
650 tmp = (pcibus_t)pci_get_word(d->config + base);
651 val = (tmp & PCI_PREF_RANGE_MASK) << 16;
652 if (tmp & PCI_PREF_RANGE_TYPE_64) {
653 val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
654 }
655 return val;
656 }
657
658 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
659 {
660 pcibus_t base;
661 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
662 base = pci_config_get_io_base(bridge,
663 PCI_IO_BASE, PCI_IO_BASE_UPPER16);
664 } else {
665 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
666 base = pci_config_get_pref_base(
667 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
668 } else {
669 base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
670 }
671 }
672
673 return base;
674 }
675
676 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
677 {
678 pcibus_t limit;
679 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
680 limit = pci_config_get_io_base(bridge,
681 PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
682 limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
683 } else {
684 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
685 limit = pci_config_get_pref_base(
686 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
687 } else {
688 limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
689 }
690 limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
691 }
692 return limit;
693 }
694
695 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
696 uint8_t type)
697 {
698 pcibus_t base = *addr;
699 pcibus_t limit = *addr + *size - 1;
700 PCIDevice *br;
701
702 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
703 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
704
705 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
706 if (!(cmd & PCI_COMMAND_IO)) {
707 goto no_map;
708 }
709 } else {
710 if (!(cmd & PCI_COMMAND_MEMORY)) {
711 goto no_map;
712 }
713 }
714
715 base = MAX(base, pci_bridge_get_base(br, type));
716 limit = MIN(limit, pci_bridge_get_limit(br, type));
717 }
718
719 if (base > limit) {
720 no_map:
721 *addr = PCI_BAR_UNMAPPED;
722 *size = 0;
723 } else {
724 *addr = base;
725 *size = limit - base + 1;
726 }
727 }
728
729 static pcibus_t pci_bar_address(PCIDevice *d,
730 int reg, uint8_t type, pcibus_t size)
731 {
732 pcibus_t new_addr, last_addr;
733 int bar = pci_bar(d, reg);
734 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
735
736 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
737 if (!(cmd & PCI_COMMAND_IO)) {
738 return PCI_BAR_UNMAPPED;
739 }
740 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
741 last_addr = new_addr + size - 1;
742 /* NOTE: we have only 64K ioports on PC */
743 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
744 return PCI_BAR_UNMAPPED;
745 }
746 return new_addr;
747 }
748
749 if (!(cmd & PCI_COMMAND_MEMORY)) {
750 return PCI_BAR_UNMAPPED;
751 }
752 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
753 new_addr = pci_get_quad(d->config + bar);
754 } else {
755 new_addr = pci_get_long(d->config + bar);
756 }
757 /* the ROM slot has a specific enable bit */
758 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
759 return PCI_BAR_UNMAPPED;
760 }
761 new_addr &= ~(size - 1);
762 last_addr = new_addr + size - 1;
763 /* NOTE: we do not support wrapping */
764 /* XXX: as we cannot support really dynamic
765 mappings, we handle specific values as invalid
766 mappings. */
767 if (last_addr <= new_addr || new_addr == 0 ||
768 last_addr == PCI_BAR_UNMAPPED) {
769 return PCI_BAR_UNMAPPED;
770 }
771
772 /* Now pcibus_t is 64bit.
773 * Check if 32 bit BAR wraps around explicitly.
774 * Without this, PC ide doesn't work well.
775 * TODO: remove this work around.
776 */
777 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
778 return PCI_BAR_UNMAPPED;
779 }
780
781 /*
782 * OS is allowed to set BAR beyond its addressable
783 * bits. For example, 32 bit OS can set 64bit bar
784 * to >4G. Check it. TODO: we might need to support
785 * it in the future for e.g. PAE.
786 */
787 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
788 return PCI_BAR_UNMAPPED;
789 }
790
791 return new_addr;
792 }
793
794 static void pci_update_mappings(PCIDevice *d)
795 {
796 PCIIORegion *r;
797 int i;
798 pcibus_t new_addr, filtered_size;
799
800 for(i = 0; i < PCI_NUM_REGIONS; i++) {
801 r = &d->io_regions[i];
802
803 /* this region isn't registered */
804 if (!r->size)
805 continue;
806
807 new_addr = pci_bar_address(d, i, r->type, r->size);
808
809 /* bridge filtering */
810 filtered_size = r->size;
811 if (new_addr != PCI_BAR_UNMAPPED) {
812 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
813 }
814
815 /* This bar isn't changed */
816 if (new_addr == r->addr && filtered_size == r->filtered_size)
817 continue;
818
819 /* now do the real mapping */
820 if (r->addr != PCI_BAR_UNMAPPED) {
821 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
822 int class;
823 /* NOTE: specific hack for IDE in PC case:
824 only one byte must be mapped. */
825 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
826 if (class == 0x0101 && r->size == 4) {
827 isa_unassign_ioport(r->addr + 2, 1);
828 } else {
829 isa_unassign_ioport(r->addr, r->filtered_size);
830 }
831 } else {
832 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
833 r->filtered_size,
834 IO_MEM_UNASSIGNED);
835 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
836 }
837 }
838 r->addr = new_addr;
839 r->filtered_size = filtered_size;
840 if (r->addr != PCI_BAR_UNMAPPED) {
841 /*
842 * TODO: currently almost all the map funcions assumes
843 * filtered_size == size and addr & ~(size - 1) == addr.
844 * However with bridge filtering, they aren't always true.
845 * Teach them such cases, such that filtered_size < size and
846 * addr & (size - 1) != 0.
847 */
848 r->map_func(d, i, r->addr, r->filtered_size, r->type);
849 }
850 }
851 }
852
853 uint32_t pci_default_read_config(PCIDevice *d,
854 uint32_t address, int len)
855 {
856 uint32_t val = 0;
857 assert(len == 1 || len == 2 || len == 4);
858 len = MIN(len, pci_config_size(d) - address);
859 memcpy(&val, d->config + address, len);
860 return le32_to_cpu(val);
861 }
862
863 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
864 {
865 int i;
866 uint32_t config_size = pci_config_size(d);
867
868 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
869 uint8_t wmask = d->wmask[addr + i];
870 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
871 }
872 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
873 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
874 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
875 range_covers_byte(addr, l, PCI_COMMAND))
876 pci_update_mappings(d);
877 }
878
879 /***********************************************************/
880 /* generic PCI irq support */
881
882 /* 0 <= irq_num <= 3. level must be 0 or 1 */
883 static void pci_set_irq(void *opaque, int irq_num, int level)
884 {
885 PCIDevice *pci_dev = opaque;
886 PCIBus *bus;
887 int change;
888
889 change = level - pci_dev->irq_state[irq_num];
890 if (!change)
891 return;
892
893 pci_dev->irq_state[irq_num] = level;
894 for (;;) {
895 bus = pci_dev->bus;
896 irq_num = bus->map_irq(pci_dev, irq_num);
897 if (bus->set_irq)
898 break;
899 pci_dev = bus->parent_dev;
900 }
901 bus->irq_count[irq_num] += change;
902 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
903 }
904
905 /***********************************************************/
906 /* monitor info on PCI */
907
908 typedef struct {
909 uint16_t class;
910 const char *desc;
911 } pci_class_desc;
912
913 static const pci_class_desc pci_class_descriptions[] =
914 {
915 { 0x0100, "SCSI controller"},
916 { 0x0101, "IDE controller"},
917 { 0x0102, "Floppy controller"},
918 { 0x0103, "IPI controller"},
919 { 0x0104, "RAID controller"},
920 { 0x0106, "SATA controller"},
921 { 0x0107, "SAS controller"},
922 { 0x0180, "Storage controller"},
923 { 0x0200, "Ethernet controller"},
924 { 0x0201, "Token Ring controller"},
925 { 0x0202, "FDDI controller"},
926 { 0x0203, "ATM controller"},
927 { 0x0280, "Network controller"},
928 { 0x0300, "VGA controller"},
929 { 0x0301, "XGA controller"},
930 { 0x0302, "3D controller"},
931 { 0x0380, "Display controller"},
932 { 0x0400, "Video controller"},
933 { 0x0401, "Audio controller"},
934 { 0x0402, "Phone"},
935 { 0x0480, "Multimedia controller"},
936 { 0x0500, "RAM controller"},
937 { 0x0501, "Flash controller"},
938 { 0x0580, "Memory controller"},
939 { 0x0600, "Host bridge"},
940 { 0x0601, "ISA bridge"},
941 { 0x0602, "EISA bridge"},
942 { 0x0603, "MC bridge"},
943 { 0x0604, "PCI bridge"},
944 { 0x0605, "PCMCIA bridge"},
945 { 0x0606, "NUBUS bridge"},
946 { 0x0607, "CARDBUS bridge"},
947 { 0x0608, "RACEWAY bridge"},
948 { 0x0680, "Bridge"},
949 { 0x0c03, "USB controller"},
950 { 0, NULL}
951 };
952
953 static void pci_info_device(PCIBus *bus, PCIDevice *d)
954 {
955 Monitor *mon = cur_mon;
956 int i, class;
957 PCIIORegion *r;
958 const pci_class_desc *desc;
959
960 monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
961 pci_bus_num(d->bus),
962 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
963 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
964 monitor_printf(mon, " ");
965 desc = pci_class_descriptions;
966 while (desc->desc && class != desc->class)
967 desc++;
968 if (desc->desc) {
969 monitor_printf(mon, "%s", desc->desc);
970 } else {
971 monitor_printf(mon, "Class %04x", class);
972 }
973 monitor_printf(mon, ": PCI device %04x:%04x\n",
974 pci_get_word(d->config + PCI_VENDOR_ID),
975 pci_get_word(d->config + PCI_DEVICE_ID));
976
977 if (d->config[PCI_INTERRUPT_PIN] != 0) {
978 monitor_printf(mon, " IRQ %d.\n",
979 d->config[PCI_INTERRUPT_LINE]);
980 }
981 if (class == 0x0604) {
982 uint64_t base;
983 uint64_t limit;
984
985 monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
986 monitor_printf(mon, " secondary bus %d.\n",
987 d->config[PCI_SECONDARY_BUS]);
988 monitor_printf(mon, " subordinate bus %d.\n",
989 d->config[PCI_SUBORDINATE_BUS]);
990
991 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
992 limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
993 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
994 base, limit);
995
996 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
997 limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
998 monitor_printf(mon,
999 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1000 base, limit);
1001
1002 base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1003 PCI_BASE_ADDRESS_MEM_PREFETCH);
1004 limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1005 PCI_BASE_ADDRESS_MEM_PREFETCH);
1006 monitor_printf(mon, " prefetchable memory range "
1007 "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
1008 }
1009 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1010 r = &d->io_regions[i];
1011 if (r->size != 0) {
1012 monitor_printf(mon, " BAR%d: ", i);
1013 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1014 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1015 " [0x%04"FMT_PCIBUS"].\n",
1016 r->addr, r->addr + r->size - 1);
1017 } else {
1018 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1019 "64 bit" : "32 bit";
1020 const char *prefetch =
1021 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1022 " prefetchable" : "";
1023
1024 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1025 " [0x%08"FMT_PCIBUS"].\n",
1026 type, prefetch,
1027 r->addr, r->addr + r->size - 1);
1028 }
1029 }
1030 }
1031 monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1032 if (class == 0x0604 && d->config[0x19] != 0) {
1033 pci_for_each_device(bus, d->config[0x19], pci_info_device);
1034 }
1035 }
1036
1037 static void pci_for_each_device_under_bus(PCIBus *bus,
1038 void (*fn)(PCIBus *b, PCIDevice *d))
1039 {
1040 PCIDevice *d;
1041 int devfn;
1042
1043 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1044 d = bus->devices[devfn];
1045 if (d)
1046 fn(bus, d);
1047 }
1048 }
1049
1050 void pci_for_each_device(PCIBus *bus, int bus_num,
1051 void (*fn)(PCIBus *b, PCIDevice *d))
1052 {
1053 bus = pci_find_bus(bus, bus_num);
1054
1055 if (bus) {
1056 pci_for_each_device_under_bus(bus, fn);
1057 }
1058 }
1059
1060 void pci_info(Monitor *mon)
1061 {
1062 struct PCIHostBus *host;
1063 QLIST_FOREACH(host, &host_buses, next) {
1064 pci_for_each_device(host->bus, 0, pci_info_device);
1065 }
1066 }
1067
1068 static const char * const pci_nic_models[] = {
1069 "ne2k_pci",
1070 "i82551",
1071 "i82557b",
1072 "i82559er",
1073 "rtl8139",
1074 "e1000",
1075 "pcnet",
1076 "virtio",
1077 NULL
1078 };
1079
1080 static const char * const pci_nic_names[] = {
1081 "ne2k_pci",
1082 "i82551",
1083 "i82557b",
1084 "i82559er",
1085 "rtl8139",
1086 "e1000",
1087 "pcnet",
1088 "virtio-net-pci",
1089 NULL
1090 };
1091
1092 /* Initialize a PCI NIC. */
1093 /* FIXME callers should check for failure, but don't */
1094 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1095 const char *default_devaddr)
1096 {
1097 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1098 PCIBus *bus;
1099 int devfn;
1100 PCIDevice *pci_dev;
1101 DeviceState *dev;
1102 int i;
1103
1104 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1105 if (i < 0)
1106 return NULL;
1107
1108 bus = pci_get_bus_devfn(&devfn, devaddr);
1109 if (!bus) {
1110 qemu_error("Invalid PCI device address %s for device %s\n",
1111 devaddr, pci_nic_names[i]);
1112 return NULL;
1113 }
1114
1115 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1116 dev = &pci_dev->qdev;
1117 if (nd->name)
1118 dev->id = qemu_strdup(nd->name);
1119 qdev_set_nic_properties(dev, nd);
1120 if (qdev_init(dev) < 0)
1121 return NULL;
1122 return pci_dev;
1123 }
1124
1125 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1126 const char *default_devaddr)
1127 {
1128 PCIDevice *res;
1129
1130 if (qemu_show_nic_models(nd->model, pci_nic_models))
1131 exit(0);
1132
1133 res = pci_nic_init(nd, default_model, default_devaddr);
1134 if (!res)
1135 exit(1);
1136 return res;
1137 }
1138
1139 typedef struct {
1140 PCIDevice dev;
1141 PCIBus bus;
1142 uint32_t vid;
1143 uint32_t did;
1144 } PCIBridge;
1145
1146
1147 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1148 {
1149 pci_update_mappings(d);
1150 }
1151
1152 static void pci_bridge_update_mappings(PCIBus *b)
1153 {
1154 PCIBus *child;
1155
1156 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1157
1158 QLIST_FOREACH(child, &b->child, sibling) {
1159 pci_bridge_update_mappings(child);
1160 }
1161 }
1162
1163 static void pci_bridge_write_config(PCIDevice *d,
1164 uint32_t address, uint32_t val, int len)
1165 {
1166 pci_default_write_config(d, address, val, len);
1167
1168 if (/* io base/limit */
1169 ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1170
1171 /* memory base/limit, prefetchable base/limit and
1172 io base/limit upper 16 */
1173 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1174 pci_bridge_update_mappings(d->bus);
1175 }
1176 }
1177
1178 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1179 {
1180 PCIBus *sec;
1181
1182 if (!bus)
1183 return NULL;
1184
1185 if (pci_bus_num(bus) == bus_num) {
1186 return bus;
1187 }
1188
1189 /* try child bus */
1190 QLIST_FOREACH(sec, &bus->child, sibling) {
1191
1192 if (!bus->parent_dev /* pci host bridge */
1193 || (pci_bus_num(sec) <= bus_num &&
1194 bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1195 return pci_find_bus(sec, bus_num);
1196 }
1197 }
1198
1199 return NULL;
1200 }
1201
1202 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1203 {
1204 bus = pci_find_bus(bus, bus_num);
1205
1206 if (!bus)
1207 return NULL;
1208
1209 return bus->devices[PCI_DEVFN(slot, function)];
1210 }
1211
1212 static int pci_bridge_initfn(PCIDevice *dev)
1213 {
1214 PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1215
1216 pci_config_set_vendor_id(s->dev.config, s->vid);
1217 pci_config_set_device_id(s->dev.config, s->did);
1218
1219 /* TODO: intial value
1220 * command register:
1221 * According to PCI bridge spec, after reset
1222 * bus master bit is off
1223 * memory space enable bit is off
1224 * According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
1225 * the reset value should be zero unless the boot pin is tied high
1226 * (which is tru) and thus it should be PCI_COMMAND_MEMORY.
1227 *
1228 * For now, don't touch the value.
1229 * Later command register will be set to zero and apb_pci.c will
1230 * override the value.
1231 * Same for latency timer, and multi function bit of header type.
1232 */
1233 pci_set_word(dev->config + PCI_COMMAND,
1234 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1235
1236 pci_set_word(dev->config + PCI_STATUS,
1237 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1238 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1239 dev->config[PCI_LATENCY_TIMER] = 0x10;
1240 dev->config[PCI_HEADER_TYPE] =
1241 PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE;
1242 pci_set_word(dev->config + PCI_SEC_STATUS,
1243 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1244 return 0;
1245 }
1246
1247 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1248 {
1249 PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1250 PCIBus *bus = &s->bus;
1251 pci_unregister_secondary_bus(bus);
1252 return 0;
1253 }
1254
1255 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1256 pci_map_irq_fn map_irq, const char *name)
1257 {
1258 PCIDevice *dev;
1259 PCIBridge *s;
1260
1261 dev = pci_create(bus, devfn, "pci-bridge");
1262 qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1263 qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1264 qdev_init_nofail(&dev->qdev);
1265
1266 s = DO_UPCAST(PCIBridge, dev, dev);
1267 pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1268 return &s->bus;
1269 }
1270
1271 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1272 {
1273 PCIDevice *pci_dev = (PCIDevice *)qdev;
1274 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1275 PCIBus *bus;
1276 int devfn, rc;
1277
1278 /* initialize cap_present for pci_is_express() and pci_config_size() */
1279 if (info->is_express) {
1280 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1281 }
1282
1283 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1284 devfn = pci_dev->devfn;
1285 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1286 info->config_read, info->config_write,
1287 info->header_type);
1288 rc = info->init(pci_dev);
1289 if (rc != 0)
1290 return rc;
1291 if (qdev->hotplugged)
1292 bus->hotplug(pci_dev, 1);
1293 return 0;
1294 }
1295
1296 static int pci_unplug_device(DeviceState *qdev)
1297 {
1298 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1299
1300 dev->bus->hotplug(dev, 0);
1301 return 0;
1302 }
1303
1304 void pci_qdev_register(PCIDeviceInfo *info)
1305 {
1306 info->qdev.init = pci_qdev_init;
1307 info->qdev.unplug = pci_unplug_device;
1308 info->qdev.exit = pci_unregister_device;
1309 info->qdev.bus_info = &pci_bus_info;
1310 qdev_register(&info->qdev);
1311 }
1312
1313 void pci_qdev_register_many(PCIDeviceInfo *info)
1314 {
1315 while (info->qdev.name) {
1316 pci_qdev_register(info);
1317 info++;
1318 }
1319 }
1320
1321 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1322 {
1323 DeviceState *dev;
1324
1325 dev = qdev_create(&bus->qbus, name);
1326 qdev_prop_set_uint32(dev, "addr", devfn);
1327 return DO_UPCAST(PCIDevice, qdev, dev);
1328 }
1329
1330 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1331 {
1332 PCIDevice *dev = pci_create(bus, devfn, name);
1333 qdev_init_nofail(&dev->qdev);
1334 return dev;
1335 }
1336
1337 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1338 {
1339 int config_size = pci_config_size(pdev);
1340 int offset = PCI_CONFIG_HEADER_SIZE;
1341 int i;
1342 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1343 if (pdev->used[i])
1344 offset = i + 1;
1345 else if (i - offset + 1 == size)
1346 return offset;
1347 return 0;
1348 }
1349
1350 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1351 uint8_t *prev_p)
1352 {
1353 uint8_t next, prev;
1354
1355 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1356 return 0;
1357
1358 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1359 prev = next + PCI_CAP_LIST_NEXT)
1360 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1361 break;
1362
1363 if (prev_p)
1364 *prev_p = prev;
1365 return next;
1366 }
1367
1368 /* Reserve space and add capability to the linked list in pci config space */
1369 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1370 {
1371 uint8_t offset = pci_find_space(pdev, size);
1372 uint8_t *config = pdev->config + offset;
1373 if (!offset)
1374 return -ENOSPC;
1375 config[PCI_CAP_LIST_ID] = cap_id;
1376 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1377 pdev->config[PCI_CAPABILITY_LIST] = offset;
1378 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1379 memset(pdev->used + offset, 0xFF, size);
1380 /* Make capability read-only by default */
1381 memset(pdev->wmask + offset, 0, size);
1382 /* Check capability by default */
1383 memset(pdev->cmask + offset, 0xFF, size);
1384 return offset;
1385 }
1386
1387 /* Unlink capability from the pci config space. */
1388 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1389 {
1390 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1391 if (!offset)
1392 return;
1393 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1394 /* Make capability writeable again */
1395 memset(pdev->wmask + offset, 0xff, size);
1396 /* Clear cmask as device-specific registers can't be checked */
1397 memset(pdev->cmask + offset, 0, size);
1398 memset(pdev->used + offset, 0, size);
1399
1400 if (!pdev->config[PCI_CAPABILITY_LIST])
1401 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1402 }
1403
1404 /* Reserve space for capability at a known offset (to call after load). */
1405 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1406 {
1407 memset(pdev->used + offset, 0xff, size);
1408 }
1409
1410 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1411 {
1412 return pci_find_capability_list(pdev, cap_id, NULL);
1413 }
1414
1415 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1416 {
1417 PCIDevice *d = (PCIDevice *)dev;
1418 const pci_class_desc *desc;
1419 char ctxt[64];
1420 PCIIORegion *r;
1421 int i, class;
1422
1423 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1424 desc = pci_class_descriptions;
1425 while (desc->desc && class != desc->class)
1426 desc++;
1427 if (desc->desc) {
1428 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1429 } else {
1430 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1431 }
1432
1433 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1434 "pci id %04x:%04x (sub %04x:%04x)\n",
1435 indent, "", ctxt,
1436 d->config[PCI_SECONDARY_BUS],
1437 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1438 pci_get_word(d->config + PCI_VENDOR_ID),
1439 pci_get_word(d->config + PCI_DEVICE_ID),
1440 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1441 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1442 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1443 r = &d->io_regions[i];
1444 if (!r->size)
1445 continue;
1446 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1447 " [0x%"FMT_PCIBUS"]\n",
1448 indent, "",
1449 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1450 r->addr, r->addr + r->size - 1);
1451 }
1452 }
1453
1454 static PCIDeviceInfo bridge_info = {
1455 .qdev.name = "pci-bridge",
1456 .qdev.size = sizeof(PCIBridge),
1457 .init = pci_bridge_initfn,
1458 .exit = pci_bridge_exitfn,
1459 .config_write = pci_bridge_write_config,
1460 .qdev.props = (Property[]) {
1461 DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1462 DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1463 DEFINE_PROP_END_OF_LIST(),
1464 }
1465 };
1466
1467 static void pci_register_devices(void)
1468 {
1469 pci_qdev_register(&bridge_info);
1470 }
1471
1472 device_init(pci_register_devices)
QEmu