hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/ppc_mac.h>
  27 #include <hw/mac_dbdma.h>
  28 #include "block.h"
  29 #include "block_int.h"
  30 #include "dma.h"
  31
  32 #include <hw/ide/internal.h>
  33
  34 /***********************************************************/
  35 /* MacIO based PowerPC IDE */
  36
  37 typedef struct MACIOIDEState {
  38     IDEBus bus;
  39     BlockDriverAIOCB *aiocb;
  40 } MACIOIDEState;
  41
  42 #define MACIO_PAGE_SIZE 4096
  43
  44 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  45 {
  46     DBDMA_io *io = opaque;
  47     MACIOIDEState *m = io->opaque;
  48     IDEState *s = idebus_active_if(&m->bus);
  49
  50     if (ret < 0) {
  51         m->aiocb = NULL;
  52         qemu_sglist_destroy(&s->sg);
  53         ide_atapi_io_error(s, ret);
  54         io->dma_end(opaque);
  55         return;
  56     }
  57
  58     if (s->io_buffer_size > 0) {
  59         m->aiocb = NULL;
  60         qemu_sglist_destroy(&s->sg);
  61
  62         s->packet_transfer_size -= s->io_buffer_size;
  63
  64         s->io_buffer_index += s->io_buffer_size;
  65         s->lba += s->io_buffer_index >> 11;
  66         s->io_buffer_index &= 0x7ff;
  67     }
  68
  69     if (s->packet_transfer_size <= 0)
  70         ide_atapi_cmd_ok(s);
  71
  72     if (io->len == 0) {
  73         io->dma_end(opaque);
  74         return;
  75     }
  76
  77     /* launch next transfer */
  78
  79     s->io_buffer_size = io->len;
  80
  81     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
  82     qemu_sglist_add(&s->sg, io->addr, io->len);
  83     io->addr += io->len;
  84     io->len = 0;
  85
  86     m->aiocb = dma_bdrv_read(s->bs, &s->sg,
  87                              (int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
  88                              pmac_ide_atapi_transfer_cb, io);
  89     if (!m->aiocb) {
  90         qemu_sglist_destroy(&s->sg);
  91         /* Note: media not present is the most likely case */
  92         ide_atapi_cmd_error(s, SENSE_NOT_READY,
  93                             ASC_MEDIUM_NOT_PRESENT);
  94         io->dma_end(opaque);
  95         return;
  96     }
  97 }
  98
  99 static void pmac_ide_transfer_cb(void *opaque, int ret)
 100 {
 101     DBDMA_io *io = opaque;
 102     MACIOIDEState *m = io->opaque;
 103     IDEState *s = idebus_active_if(&m->bus);
 104     int n;
 105     int64_t sector_num;
 106
 107     if (ret < 0) {
 108         m->aiocb = NULL;
 109         qemu_sglist_destroy(&s->sg);
 110         ide_dma_error(s);
 111         io->dma_end(io);
 112         return;
 113     }
 114
 115     sector_num = ide_get_sector(s);
 116     if (s->io_buffer_size > 0) {
 117         m->aiocb = NULL;
 118         qemu_sglist_destroy(&s->sg);
 119         n = (s->io_buffer_size + 0x1ff) >> 9;
 120         sector_num += n;
 121         ide_set_sector(s, sector_num);
 122         s->nsector -= n;
 123     }
 124
 125     /* end of transfer ? */
 126     if (s->nsector == 0) {
 127         s->status = READY_STAT | SEEK_STAT;
 128         ide_set_irq(s->bus);
 129     }
 130
 131     /* end of DMA ? */
 132
 133     if (io->len == 0) {
 134         io->dma_end(io);
 135         return;
 136     }
 137
 138     /* launch next transfer */
 139
 140     s->io_buffer_index = 0;
 141     s->io_buffer_size = io->len;
 142
 143     qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
 144     qemu_sglist_add(&s->sg, io->addr, io->len);
 145     io->addr += io->len;
 146     io->len = 0;
 147
 148     switch (s->dma_cmd) {
 149     case IDE_DMA_READ:
 150         m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
 151                                  pmac_ide_transfer_cb, io);
 152         break;
 153     case IDE_DMA_WRITE:
 154         m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
 155                                   pmac_ide_transfer_cb, io);
 156         break;
 157     case IDE_DMA_TRIM:
 158         m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
 159                                ide_issue_trim, pmac_ide_transfer_cb, s, 1);
 160         break;
 161     }
 162
 163     if (!m->aiocb)
 164         pmac_ide_transfer_cb(io, -1);
 165 }
 166
 167 static void pmac_ide_transfer(DBDMA_io *io)
 168 {
 169     MACIOIDEState *m = io->opaque;
 170     IDEState *s = idebus_active_if(&m->bus);
 171
 172     s->io_buffer_size = 0;
 173     if (s->drive_kind == IDE_CD) {
 174         pmac_ide_atapi_transfer_cb(io, 0);
 175         return;
 176     }
 177
 178     pmac_ide_transfer_cb(io, 0);
 179 }
 180
 181 static void pmac_ide_flush(DBDMA_io *io)
 182 {
 183     MACIOIDEState *m = io->opaque;
 184
 185     if (m->aiocb)
 186         qemu_aio_flush();
 187 }
 188
 189 /* PowerMac IDE memory IO */
 190 static void pmac_ide_writeb (void *opaque,
 191                              target_phys_addr_t addr, uint32_t val)
 192 {
 193     MACIOIDEState *d = opaque;
 194
 195     addr = (addr & 0xFFF) >> 4;
 196     switch (addr) {
 197     case 1 ... 7:
 198         ide_ioport_write(&d->bus, addr, val);
 199         break;
 200     case 8:
 201     case 22:
 202         ide_cmd_write(&d->bus, 0, val);
 203         break;
 204     default:
 205         break;
 206     }
 207 }
 208
 209 static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
 210 {
 211     uint8_t retval;
 212     MACIOIDEState *d = opaque;
 213
 214     addr = (addr & 0xFFF) >> 4;
 215     switch (addr) {
 216     case 1 ... 7:
 217         retval = ide_ioport_read(&d->bus, addr);
 218         break;
 219     case 8:
 220     case 22:
 221         retval = ide_status_read(&d->bus, 0);
 222         break;
 223     default:
 224         retval = 0xFF;
 225         break;
 226     }
 227     return retval;
 228 }
 229
 230 static void pmac_ide_writew (void *opaque,
 231                              target_phys_addr_t addr, uint32_t val)
 232 {
 233     MACIOIDEState *d = opaque;
 234
 235     addr = (addr & 0xFFF) >> 4;
 236     val = bswap16(val);
 237     if (addr == 0) {
 238         ide_data_writew(&d->bus, 0, val);
 239     }
 240 }
 241
 242 static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
 243 {
 244     uint16_t retval;
 245     MACIOIDEState *d = opaque;
 246
 247     addr = (addr & 0xFFF) >> 4;
 248     if (addr == 0) {
 249         retval = ide_data_readw(&d->bus, 0);
 250     } else {
 251         retval = 0xFFFF;
 252     }
 253     retval = bswap16(retval);
 254     return retval;
 255 }
 256
 257 static void pmac_ide_writel (void *opaque,
 258                              target_phys_addr_t addr, uint32_t val)
 259 {
 260     MACIOIDEState *d = opaque;
 261
 262     addr = (addr & 0xFFF) >> 4;
 263     val = bswap32(val);
 264     if (addr == 0) {
 265         ide_data_writel(&d->bus, 0, val);
 266     }
 267 }
 268
 269 static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
 270 {
 271     uint32_t retval;
 272     MACIOIDEState *d = opaque;
 273
 274     addr = (addr & 0xFFF) >> 4;
 275     if (addr == 0) {
 276         retval = ide_data_readl(&d->bus, 0);
 277     } else {
 278         retval = 0xFFFFFFFF;
 279     }
 280     retval = bswap32(retval);
 281     return retval;
 282 }
 283
 284 static CPUWriteMemoryFunc * const pmac_ide_write[] = {
 285     pmac_ide_writeb,
 286     pmac_ide_writew,
 287     pmac_ide_writel,
 288 };
 289
 290 static CPUReadMemoryFunc * const pmac_ide_read[] = {
 291     pmac_ide_readb,
 292     pmac_ide_readw,
 293     pmac_ide_readl,
 294 };
 295
 296 static const VMStateDescription vmstate_pmac = {
 297     .name = "ide",
 298     .version_id = 3,
 299     .minimum_version_id = 0,
 300     .minimum_version_id_old = 0,
 301     .fields      = (VMStateField []) {
 302         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 303         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static void pmac_ide_reset(void *opaque)
 309 {
 310     MACIOIDEState *d = opaque;
 311
 312     ide_bus_reset(&d->bus);
 313 }
 314
 315 /* hd_table must contain 4 block drivers */
 316 /* PowerMac uses memory mapped registers, not I/O. Return the memory
 317    I/O index to access the ide. */
 318 int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
 319                    void *dbdma, int channel, qemu_irq dma_irq)
 320 {
 321     MACIOIDEState *d;
 322     int pmac_ide_memory;
 323
 324     d = qemu_mallocz(sizeof(MACIOIDEState));
 325     ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
 326
 327     if (dbdma)
 328         DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
 329
 330     pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
 331                                              pmac_ide_write, d,
 332                                              DEVICE_NATIVE_ENDIAN);
 333     vmstate_register(NULL, 0, &vmstate_pmac, d);
 334     qemu_register_reset(pmac_ide_reset, d);
 335
 336     return pmac_ide_memory;
 337 }