target-s390x/mmu_helper.c

   1 /*
   2  * S390x MMU related functions
   3  *
   4  * Copyright (c) 2011 Alexander Graf
   5  * Copyright (c) 2015 Thomas Huth, IBM Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include "cpu.h"
  19
  20 /* #define DEBUG_S390 */
  21 /* #define DEBUG_S390_PTE */
  22 /* #define DEBUG_S390_STDOUT */
  23
  24 #ifdef DEBUG_S390
  25 #ifdef DEBUG_S390_STDOUT
  26 #define DPRINTF(fmt, ...) \
  27     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  28          qemu_log(fmt, ##__VA_ARGS__); } while (0)
  29 #else
  30 #define DPRINTF(fmt, ...) \
  31     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  32 #endif
  33 #else
  34 #define DPRINTF(fmt, ...) \
  35     do { } while (0)
  36 #endif
  37
  38 #ifdef DEBUG_S390_PTE
  39 #define PTE_DPRINTF DPRINTF
  40 #else
  41 #define PTE_DPRINTF(fmt, ...) \
  42     do { } while (0)
  43 #endif
  44
  45 /* Fetch/store bits in the translation exception code: */
  46 #define FS_READ  0x800
  47 #define FS_WRITE 0x400
  48
  49 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
  50                                uint64_t asc, int rw, bool exc)
  51 {
  52     CPUState *cs = CPU(s390_env_get_cpu(env));
  53     uint64_t tec;
  54
  55     tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | 4 | asc >> 46;
  56
  57     DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec);
  58
  59     if (!exc) {
  60         return;
  61     }
  62
  63     stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  64     trigger_pgm_exception(env, PGM_PROTECTION, ILEN_LATER_INC);
  65 }
  66
  67 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
  68                                uint32_t type, uint64_t asc, int rw, bool exc)
  69 {
  70     CPUState *cs = CPU(s390_env_get_cpu(env));
  71     int ilen = ILEN_LATER;
  72     uint64_t tec;
  73
  74     tec = vaddr | (rw == 1 ? FS_WRITE : FS_READ) | asc >> 46;
  75
  76     DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
  77
  78     if (!exc) {
  79         return;
  80     }
  81
  82     /* Code accesses have an undefined ilc.  */
  83     if (rw == 2) {
  84         ilen = 2;
  85     }
  86
  87     stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
  88     trigger_pgm_exception(env, type, ilen);
  89 }
  90
  91 /**
  92  * Translate real address to absolute (= physical)
  93  * address by taking care of the prefix mapping.
  94  */
  95 static target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
  96 {
  97     if (raddr < 0x2000) {
  98         return raddr + env->psa;    /* Map the lowcore. */
  99     } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
 100         return raddr - env->psa;    /* Map the 0 page. */
 101     }
 102     return raddr;
 103 }
 104
 105 /* Decode page table entry (normal 4KB page) */
 106 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr,
 107                              uint64_t asc, uint64_t asce,
 108                              target_ulong *raddr, int *flags, int rw, bool exc)
 109 {
 110     if (asce & _PAGE_INVALID) {
 111         DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, asce);
 112         trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc);
 113         return -1;
 114     }
 115
 116     if (asce & _PAGE_RO) {
 117         *flags &= ~PAGE_WRITE;
 118     }
 119
 120     *raddr = asce & _ASCE_ORIGIN;
 121
 122     PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, asce);
 123
 124     return 0;
 125 }
 126
 127 #define VADDR_PX    0xff000         /* Page index bits */
 128
 129 /* Decode segment table entry */
 130 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr,
 131                                  uint64_t asc, uint64_t st_entry,
 132                                  target_ulong *raddr, int *flags, int rw,
 133                                  bool exc)
 134 {
 135     CPUState *cs = CPU(s390_env_get_cpu(env));
 136     uint64_t origin, offs, pt_entry;
 137
 138     if (st_entry & _SEGMENT_ENTRY_RO) {
 139         *flags &= ~PAGE_WRITE;
 140     }
 141
 142     if ((st_entry & _SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) {
 143         /* Decode EDAT1 segment frame absolute address (1MB page) */
 144         *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff);
 145         PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry);
 146         return 0;
 147     }
 148
 149     /* Look up 4KB page entry */
 150     origin = st_entry & _SEGMENT_ENTRY_ORIGIN;
 151     offs  = (vaddr & VADDR_PX) >> 9;
 152     pt_entry = ldq_phys(cs->as, origin + offs);
 153     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 154                 __func__, origin, offs, pt_entry);
 155     return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc);
 156 }
 157
 158 /* Decode region table entries */
 159 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr,
 160                                 uint64_t asc, uint64_t entry, int level,
 161                                 target_ulong *raddr, int *flags, int rw,
 162                                 bool exc)
 163 {
 164     CPUState *cs = CPU(s390_env_get_cpu(env));
 165     uint64_t origin, offs, new_entry;
 166     const int pchks[4] = {
 167         PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS,
 168         PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS
 169     };
 170
 171     PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry);
 172
 173     origin = entry & _REGION_ENTRY_ORIGIN;
 174     offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8;
 175
 176     new_entry = ldq_phys(cs->as, origin + offs);
 177     PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
 178                 __func__, origin, offs, new_entry);
 179
 180     if ((new_entry & _REGION_ENTRY_INV) != 0) {
 181         /* XXX different regions have different faults */
 182         DPRINTF("%s: invalid region\n", __func__);
 183         trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 184         return -1;
 185     }
 186
 187     if ((new_entry & _REGION_ENTRY_TYPE_MASK) != level) {
 188         trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc);
 189         return -1;
 190     }
 191
 192     /* XXX region protection flags */
 193     /* *flags &= ~PAGE_WRITE */
 194
 195     if (level == _ASCE_TYPE_SEGMENT) {
 196         return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags,
 197                                      rw, exc);
 198     }
 199
 200     /* Check region table offset and length */
 201     offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3;
 202     if (offs < ((new_entry & _REGION_ENTRY_TF) >> 6)
 203         || offs > (new_entry & _REGION_ENTRY_LENGTH)) {
 204         DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry);
 205         trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc);
 206         return -1;
 207     }
 208
 209     /* yet another region */
 210     return mmu_translate_region(env, vaddr, asc, new_entry, level - 4,
 211                                 raddr, flags, rw, exc);
 212 }
 213
 214 static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
 215                              uint64_t asc, target_ulong *raddr, int *flags,
 216                              int rw, bool exc)
 217 {
 218     uint64_t asce = 0;
 219     int level;
 220     int r;
 221
 222     switch (asc) {
 223     case PSW_ASC_PRIMARY:
 224         PTE_DPRINTF("%s: asc=primary\n", __func__);
 225         asce = env->cregs[1];
 226         break;
 227     case PSW_ASC_SECONDARY:
 228         PTE_DPRINTF("%s: asc=secondary\n", __func__);
 229         asce = env->cregs[7];
 230         break;
 231     case PSW_ASC_HOME:
 232         PTE_DPRINTF("%s: asc=home\n", __func__);
 233         asce = env->cregs[13];
 234         break;
 235     }
 236
 237     if (asce & _ASCE_REAL_SPACE) {
 238         /* direct mapping */
 239         *raddr = vaddr;
 240         return 0;
 241     }
 242
 243     level = asce & _ASCE_TYPE_MASK;
 244     switch (level) {
 245     case _ASCE_TYPE_REGION1:
 246         if ((vaddr >> 62) > (asce & _ASCE_TABLE_LENGTH)) {
 247             trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc);
 248             return -1;
 249         }
 250         break;
 251     case _ASCE_TYPE_REGION2:
 252         if (vaddr & 0xffe0000000000000ULL) {
 253             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 254                     " 0xffe0000000000000ULL\n", __func__, vaddr);
 255             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 256             return -1;
 257         }
 258         if ((vaddr >> 51 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 259             trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc);
 260             return -1;
 261         }
 262         break;
 263     case _ASCE_TYPE_REGION3:
 264         if (vaddr & 0xfffffc0000000000ULL) {
 265             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 266                     " 0xfffffc0000000000ULL\n", __func__, vaddr);
 267             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 268             return -1;
 269         }
 270         if ((vaddr >> 40 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 271             trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc);
 272             return -1;
 273         }
 274         break;
 275     case _ASCE_TYPE_SEGMENT:
 276         if (vaddr & 0xffffffff80000000ULL) {
 277             DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
 278                     " 0xffffffff80000000ULL\n", __func__, vaddr);
 279             trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc);
 280             return -1;
 281         }
 282         if ((vaddr >> 29 & 3) > (asce & _ASCE_TABLE_LENGTH)) {
 283             trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc);
 284             return -1;
 285         }
 286         break;
 287     }
 288
 289     r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw,
 290                              exc);
 291     if ((rw == 1) && !(*flags & PAGE_WRITE)) {
 292         trigger_prot_fault(env, vaddr, asc, rw, exc);
 293         return -1;
 294     }
 295
 296     return r;
 297 }
 298
 299 /**
 300  * Translate a virtual (logical) address into a physical (absolute) address.
 301  * @param vaddr  the virtual address
 302  * @param rw     0 = read, 1 = write, 2 = code fetch
 303  * @param asc    address space control (one of the PSW_ASC_* modes)
 304  * @param raddr  the translated address is stored to this pointer
 305  * @param flags  the PAGE_READ/WRITE/EXEC flags are stored to this pointer
 306  * @param exc    true = inject a program check if a fault occured
 307  * @return       0 if the translation was successfull, -1 if a fault occured
 308  */
 309 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 310                   target_ulong *raddr, int *flags, bool exc)
 311 {
 312     int r = -1;
 313     uint8_t *sk;
 314
 315     *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 316     vaddr &= TARGET_PAGE_MASK;
 317
 318     if (!(env->psw.mask & PSW_MASK_DAT)) {
 319         *raddr = vaddr;
 320         r = 0;
 321         goto out;
 322     }
 323
 324     switch (asc) {
 325     case PSW_ASC_PRIMARY:
 326     case PSW_ASC_HOME:
 327         r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw, exc);
 328         break;
 329     case PSW_ASC_SECONDARY:
 330         /*
 331          * Instruction: Primary
 332          * Data: Secondary
 333          */
 334         if (rw == 2) {
 335             r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
 336                                   rw, exc);
 337             *flags &= ~(PAGE_READ | PAGE_WRITE);
 338         } else {
 339             r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
 340                                   rw, exc);
 341             *flags &= ~(PAGE_EXEC);
 342         }
 343         break;
 344     case PSW_ASC_ACCREG:
 345     default:
 346         hw_error("guest switched to unknown asc mode\n");
 347         break;
 348     }
 349
 350  out:
 351     /* Convert real address -> absolute address */
 352     *raddr = mmu_real2abs(env, *raddr);
 353
 354     if (*raddr <= ram_size) {
 355         sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
 356         if (*flags & PAGE_READ) {
 357             *sk |= SK_R;
 358         }
 359
 360         if (*flags & PAGE_WRITE) {
 361             *sk |= SK_C;
 362         }
 363     }
 364
 365     return r;
 366 }