4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pcie.h"
25 #include "hw/pci/msix.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pcie_regs.h"
29 #include "qemu/range.h"
33 # define PCIE_DPRINTF(fmt, ...) \
34 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
38 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
39 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
42 /***************************************************************************
43 * pci express capability helper functions
45 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
, uint8_t port
)
50 assert(pci_is_express(dev
));
52 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
57 dev
->exp
.exp_cap
= pos
;
58 exp_cap
= dev
->config
+ pos
;
60 /* capability register
61 interrupt message number defaults to 0 */
62 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
63 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
66 /* device capability register
68 * roll based error reporting bit must be set by all
69 * Functions conforming to the ECN, PCI Express Base
70 * Specification, Revision 1.1., or subsequent PCI Express Base
71 * Specification revisions.
73 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
75 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
76 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
77 PCI_EXP_LNKCAP_ASPMS_0S
|
81 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
82 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
|PCI_EXP_LNKSTA_DLLLA
);
84 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
85 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
87 pci_set_word(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
, PCI_EXP_DEVCTL2_EETLPPB
);
91 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
93 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
96 * Windows guests will report Code 10, device cannot start, if
97 * a regular Endpoint type is exposed on a root complex. These
98 * should instead be Root Complex Integrated Endpoints.
100 if (pci_bus_is_express(dev
->bus
) && pci_bus_is_root(dev
->bus
)) {
101 type
= PCI_EXP_TYPE_RC_END
;
104 return pcie_cap_init(dev
, offset
, type
, 0);
107 void pcie_cap_exit(PCIDevice
*dev
)
109 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
112 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
114 uint32_t pos
= dev
->exp
.exp_cap
;
116 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
117 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
121 /* pci express interrupt message number */
122 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
123 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
125 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
127 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
128 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
129 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
132 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
134 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
135 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
138 void pcie_cap_deverr_init(PCIDevice
*dev
)
140 uint32_t pos
= dev
->exp
.exp_cap
;
141 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
142 PCI_EXP_DEVCAP_RBER
);
143 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
144 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
145 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
146 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
147 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
148 PCI_EXP_DEVSTA_FED
| PCI_EXP_DEVSTA_URD
);
151 void pcie_cap_deverr_reset(PCIDevice
*dev
)
153 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
154 pci_long_test_and_clear_mask(devctl
,
155 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
156 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
159 static void hotplug_event_update_event_status(PCIDevice
*dev
)
161 uint32_t pos
= dev
->exp
.exp_cap
;
162 uint8_t *exp_cap
= dev
->config
+ pos
;
163 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
164 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
166 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
167 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
170 static void hotplug_event_notify(PCIDevice
*dev
)
172 bool prev
= dev
->exp
.hpev_notified
;
174 hotplug_event_update_event_status(dev
);
176 if (prev
== dev
->exp
.hpev_notified
) {
180 /* Note: the logic above does not take into account whether interrupts
181 * are masked. The result is that interrupt will be sent when it is
182 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
183 * The Port may optionally send an MSI when there are hot-plug events that
184 * occur while interrupt generation is disabled, and interrupt generation is
185 * subsequently enabled. */
186 if (msix_enabled(dev
)) {
187 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
188 } else if (msi_enabled(dev
)) {
189 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
191 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
195 static void hotplug_event_clear(PCIDevice
*dev
)
197 hotplug_event_update_event_status(dev
);
198 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
199 pci_irq_deassert(dev
);
204 * A PCI Express Hot-Plug Event has occurred, so update slot status register
205 * and notify OS of the event if necessary.
207 * 6.7.3 PCI Express Hot-Plug Events
208 * 6.7.3.4 Software Notification of Hot-Plug Events
210 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
212 /* Minor optimization: if nothing changed - no event is needed. */
213 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
214 PCI_EXP_SLTSTA
, event
)) {
217 hotplug_event_notify(dev
);
220 static void pcie_cap_slot_hotplug_common(PCIDevice
*hotplug_dev
,
222 uint8_t **exp_cap
, Error
**errp
)
224 *exp_cap
= hotplug_dev
->config
+ hotplug_dev
->exp
.exp_cap
;
225 uint16_t sltsta
= pci_get_word(*exp_cap
+ PCI_EXP_SLTSTA
);
227 PCIE_DEV_PRINTF(PCI_DEVICE(dev
), "hotplug state: 0x%x\n", sltsta
);
228 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
229 /* the slot is electromechanically locked.
230 * This error is propagated up to qdev and then to HMP/QMP.
232 error_setg_errno(errp
, EBUSY
, "slot is electromechanically locked");
236 void pcie_cap_slot_hotplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
240 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
242 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
244 /* Don't send event when device is enabled during qemu machine creation:
245 * it is present on boot, no hotplug event is necessary. We do send an
246 * event when the device is disabled later. */
247 if (!dev
->hotplugged
) {
248 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
253 /* To enable multifunction hot-plug, we just ensure the function
254 * 0 added last. When function 0 is added, we set the sltsta and
255 * inform OS via event notification.
257 if (pci_get_function_0(pci_dev
)) {
258 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
260 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev
),
261 PCI_EXP_HP_EV_PDC
| PCI_EXP_HP_EV_ABP
);
265 static void pcie_unplug_device(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
267 object_unparent(OBJECT(dev
));
270 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler
*hotplug_dev
,
271 DeviceState
*dev
, Error
**errp
)
274 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
275 PCIBus
*bus
= pci_dev
->bus
;
277 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
279 /* In case user cancel the operation of multi-function hot-add,
280 * remove the function that is unexposed to guest individually,
281 * without interaction with guest.
283 if (pci_dev
->devfn
&&
285 pcie_unplug_device(bus
, pci_dev
, NULL
);
290 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev
));
293 /* pci express slot for pci express root/downstream port
294 PCI express capability slot registers */
295 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
297 uint32_t pos
= dev
->exp
.exp_cap
;
299 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
302 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
303 ~PCI_EXP_SLTCAP_PSN
);
304 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
305 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
313 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
314 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
316 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
318 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
322 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
325 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
326 PCI_EXP_SLTCTL_PIC_OFF
|
327 PCI_EXP_SLTCTL_AIC_OFF
);
328 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
331 PCI_EXP_SLTCTL_HPIE
|
332 PCI_EXP_SLTCTL_CCIE
|
333 PCI_EXP_SLTCTL_PDCE
|
334 PCI_EXP_SLTCTL_ABPE
);
335 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
336 * make the bit writable here in order to detect 1b is written.
337 * pcie_cap_slot_write_config() test-and-clear the bit, so
338 * this bit always returns 0 to the guest.
340 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
343 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
344 PCI_EXP_HP_EV_SUPPORTED
);
346 dev
->exp
.hpev_notified
= false;
348 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))),
352 void pcie_cap_slot_reset(PCIDevice
*dev
)
354 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
355 uint8_t port_type
= pcie_cap_get_type(dev
);
357 assert(port_type
== PCI_EXP_TYPE_DOWNSTREAM
||
358 port_type
== PCI_EXP_TYPE_ROOT_PORT
);
360 PCIE_DEV_PRINTF(dev
, "reset\n");
362 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
366 PCI_EXP_SLTCTL_HPIE
|
367 PCI_EXP_SLTCTL_CCIE
|
368 PCI_EXP_SLTCTL_PDCE
|
369 PCI_EXP_SLTCTL_ABPE
);
370 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
371 PCI_EXP_SLTCTL_AIC_OFF
);
373 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
374 /* Downstream ports enforce device number 0. */
375 bool populated
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))->devices
[0];
379 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
382 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
386 pic
= populated
? PCI_EXP_SLTCTL_PIC_ON
: PCI_EXP_SLTCTL_PIC_OFF
;
387 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
, pic
);
390 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
391 PCI_EXP_SLTSTA_EIS
|/* on reset,
392 the lock is released */
397 hotplug_event_update_event_status(dev
);
400 void pcie_cap_slot_write_config(PCIDevice
*dev
,
401 uint32_t addr
, uint32_t val
, int len
)
403 uint32_t pos
= dev
->exp
.exp_cap
;
404 uint8_t *exp_cap
= dev
->config
+ pos
;
405 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
407 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
408 hotplug_event_clear(dev
);
411 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
415 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
416 PCI_EXP_SLTCTL_EIC
)) {
417 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
418 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
419 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
420 "sltsta -> 0x%02"PRIx16
"\n",
425 * If the slot is polulated, power indicator is off and power
426 * controller is off, it is safe to detach the devices.
428 if ((sltsta
& PCI_EXP_SLTSTA_PDS
) && (val
& PCI_EXP_SLTCTL_PCC
) &&
429 ((val
& PCI_EXP_SLTCTL_PIC_OFF
) == PCI_EXP_SLTCTL_PIC_OFF
)) {
430 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
431 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
432 pcie_unplug_device
, NULL
);
434 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
436 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
440 hotplug_event_notify(dev
);
443 * 6.7.3.2 Command Completed Events
445 * Software issues a command to a hot-plug capable Downstream Port by
446 * issuing a write transaction that targets any portion of the Port’s Slot
447 * Control register. A single write to the Slot Control register is
448 * considered to be a single command, even if the write affects more than
449 * one field in the Slot Control register. In response to this transaction,
450 * the Port must carry out the requested actions and then set the
451 * associated status field for the command completed event. */
453 /* Real hardware might take a while to complete requested command because
454 * physical movement would be involved like locking the electromechanical
455 * lock. However in our case, command is completed instantaneously above,
456 * so send a command completion event right now.
458 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
461 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
463 PCIDevice
*dev
= opaque
;
464 hotplug_event_update_event_status(dev
);
468 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
470 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
473 /* root control/capabilities/status. PME isn't emulated for now */
474 void pcie_cap_root_init(PCIDevice
*dev
)
476 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
477 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
478 PCI_EXP_RTCTL_SEFEE
);
481 void pcie_cap_root_reset(PCIDevice
*dev
)
483 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
486 /* function level reset(FLR) */
487 void pcie_cap_flr_init(PCIDevice
*dev
)
489 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
492 /* Although reading BCR_FLR returns always 0,
493 * the bit is made writable here in order to detect the 1b is written
494 * pcie_cap_flr_write_config() test-and-clear the bit, so
495 * this bit always returns 0 to the guest.
497 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
498 PCI_EXP_DEVCTL_BCR_FLR
);
501 void pcie_cap_flr_write_config(PCIDevice
*dev
,
502 uint32_t addr
, uint32_t val
, int len
)
504 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
505 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
506 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
507 so the handler can detect FLR by looking at this bit. */
508 pci_device_reset(dev
);
509 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
513 /* Alternative Routing-ID Interpretation (ARI)
514 * forwarding support for root and downstream ports
516 void pcie_cap_arifwd_init(PCIDevice
*dev
)
518 uint32_t pos
= dev
->exp
.exp_cap
;
519 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
520 PCI_EXP_DEVCAP2_ARI
);
521 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
522 PCI_EXP_DEVCTL2_ARI
);
525 void pcie_cap_arifwd_reset(PCIDevice
*dev
)
527 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
528 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
531 bool pcie_cap_is_arifwd_enabled(const PCIDevice
*dev
)
533 if (!pci_is_express(dev
)) {
536 if (!dev
->exp
.exp_cap
) {
540 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
544 /**************************************************************************
545 * pci express extended capability list management functions
546 * uint16_t ext_cap_id (16 bit)
547 * uint8_t cap_ver (4 bit)
548 * uint16_t cap_offset (12 bit)
549 * uint16_t ext_cap_size
552 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint16_t cap_id
,
557 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
560 /* no extended capability */
564 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
565 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
567 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
568 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
570 header
= pci_get_long(dev
->config
+ next
);
571 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
583 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
585 return pcie_find_capability_list(dev
, cap_id
, NULL
);
588 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
590 uint32_t header
= pci_get_long(dev
->config
+ pos
);
591 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
592 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
593 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
594 pci_set_long(dev
->config
+ pos
, header
);
598 * caller must supply valid (offset, size) * such that the range shouldn't
599 * overlap with other capability or other registers.
600 * This function doesn't check it.
602 void pcie_add_capability(PCIDevice
*dev
,
603 uint16_t cap_id
, uint8_t cap_ver
,
604 uint16_t offset
, uint16_t size
)
609 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
610 assert(offset
< offset
+ size
);
611 assert(offset
+ size
<= PCIE_CONFIG_SPACE_SIZE
);
613 assert(pci_is_express(dev
));
615 if (offset
== PCI_CONFIG_SPACE_SIZE
) {
616 header
= pci_get_long(dev
->config
+ offset
);
617 next
= PCI_EXT_CAP_NEXT(header
);
621 /* 0 is reserved cap id. use internally to find the last capability
622 in the linked list */
623 next
= pcie_find_capability_list(dev
, 0, &prev
);
625 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
627 pcie_ext_cap_set_next(dev
, prev
, offset
);
629 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, next
));
631 /* Make capability read-only by default */
632 memset(dev
->wmask
+ offset
, 0, size
);
633 memset(dev
->w1cmask
+ offset
, 0, size
);
634 /* Check capability by default */
635 memset(dev
->cmask
+ offset
, 0xFF, size
);
638 /**************************************************************************
639 * pci express extended capability helper functions
643 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
645 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
646 offset
, PCI_ARI_SIZEOF
);
647 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, (nextfn
& 0xff) << 8);