hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "hw/sysbus.h"
  21 #include "sysemu/char.h"
  22 #include "qemu/timer.h"
  23 #include "qemu/log.h"
  24 #include "hw/char/cadence_uart.h"
  25
  26 #ifdef CADENCE_UART_ERR_DEBUG
  27 #define DB_PRINT(...) do { \
  28     fprintf(stderr,  ": %s: ", __func__); \
  29     fprintf(stderr, ## __VA_ARGS__); \
  30     } while (0);
  31 #else
  32     #define DB_PRINT(...)
  33 #endif
  34
  35 #define UART_SR_INTR_RTRIG     0x00000001
  36 #define UART_SR_INTR_REMPTY    0x00000002
  37 #define UART_SR_INTR_RFUL      0x00000004
  38 #define UART_SR_INTR_TEMPTY    0x00000008
  39 #define UART_SR_INTR_TFUL      0x00000010
  40 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
  41 #define UART_SR_TTRIG          0x00002000
  42 #define UART_INTR_TTRIG        0x00000400
  43 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  44  * SR, then the same bit in CISR is set high too */
  45 #define UART_SR_TO_CISR_MASK   0x0000001F
  46
  47 #define UART_INTR_ROVR         0x00000020
  48 #define UART_INTR_FRAME        0x00000040
  49 #define UART_INTR_PARE         0x00000080
  50 #define UART_INTR_TIMEOUT      0x00000100
  51 #define UART_INTR_DMSI         0x00000200
  52 #define UART_INTR_TOVR         0x00001000
  53
  54 #define UART_SR_RACTIVE    0x00000400
  55 #define UART_SR_TACTIVE    0x00000800
  56 #define UART_SR_FDELT      0x00001000
  57
  58 #define UART_CR_RXRST       0x00000001
  59 #define UART_CR_TXRST       0x00000002
  60 #define UART_CR_RX_EN       0x00000004
  61 #define UART_CR_RX_DIS      0x00000008
  62 #define UART_CR_TX_EN       0x00000010
  63 #define UART_CR_TX_DIS      0x00000020
  64 #define UART_CR_RST_TO      0x00000040
  65 #define UART_CR_STARTBRK    0x00000080
  66 #define UART_CR_STOPBRK     0x00000100
  67
  68 #define UART_MR_CLKS            0x00000001
  69 #define UART_MR_CHRL            0x00000006
  70 #define UART_MR_CHRL_SH         1
  71 #define UART_MR_PAR             0x00000038
  72 #define UART_MR_PAR_SH          3
  73 #define UART_MR_NBSTOP          0x000000C0
  74 #define UART_MR_NBSTOP_SH       6
  75 #define UART_MR_CHMODE          0x00000300
  76 #define UART_MR_CHMODE_SH       8
  77 #define UART_MR_UCLKEN          0x00000400
  78 #define UART_MR_IRMODE          0x00000800
  79
  80 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  81 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  82 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  83 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  84 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  85 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  86 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  87 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  88 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  89 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  90
  91 #define UART_INPUT_CLK         50000000
  92
  93 #define R_CR       (0x00/4)
  94 #define R_MR       (0x04/4)
  95 #define R_IER      (0x08/4)
  96 #define R_IDR      (0x0C/4)
  97 #define R_IMR      (0x10/4)
  98 #define R_CISR     (0x14/4)
  99 #define R_BRGR     (0x18/4)
 100 #define R_RTOR     (0x1C/4)
 101 #define R_RTRIG    (0x20/4)
 102 #define R_MCR      (0x24/4)
 103 #define R_MSR      (0x28/4)
 104 #define R_SR       (0x2C/4)
 105 #define R_TX_RX    (0x30/4)
 106 #define R_BDIV     (0x34/4)
 107 #define R_FDEL     (0x38/4)
 108 #define R_PMIN     (0x3C/4)
 109 #define R_PWID     (0x40/4)
 110 #define R_TTRIG    (0x44/4)
 111
 112
 113 static void uart_update_status(CadenceUARTState *s)
 114 {
 115     s->r[R_SR] = 0;
 116
 117     s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
 118                                                            : 0;
 119     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 120     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 121
 122     s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
 123                                                            : 0;
 124     s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
 125     s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
 126
 127     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 128     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
 129     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 130 }
 131
 132 static void fifo_trigger_update(void *opaque)
 133 {
 134     CadenceUARTState *s = opaque;
 135
 136     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 137
 138     uart_update_status(s);
 139 }
 140
 141 static void uart_rx_reset(CadenceUARTState *s)
 142 {
 143     s->rx_wpos = 0;
 144     s->rx_count = 0;
 145     qemu_chr_fe_accept_input(&s->chr);
 146 }
 147
 148 static void uart_tx_reset(CadenceUARTState *s)
 149 {
 150     s->tx_count = 0;
 151 }
 152
 153 static void uart_send_breaks(CadenceUARTState *s)
 154 {
 155     int break_enabled = 1;
 156
 157     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 158                       &break_enabled);
 159 }
 160
 161 static void uart_parameters_setup(CadenceUARTState *s)
 162 {
 163     QEMUSerialSetParams ssp;
 164     unsigned int baud_rate, packet_size;
 165
 166     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 167             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 168
 169     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 170     packet_size = 1;
 171
 172     switch (s->r[R_MR] & UART_MR_PAR) {
 173     case UART_PARITY_EVEN:
 174         ssp.parity = 'E';
 175         packet_size++;
 176         break;
 177     case UART_PARITY_ODD:
 178         ssp.parity = 'O';
 179         packet_size++;
 180         break;
 181     default:
 182         ssp.parity = 'N';
 183         break;
 184     }
 185
 186     switch (s->r[R_MR] & UART_MR_CHRL) {
 187     case UART_DATA_BITS_6:
 188         ssp.data_bits = 6;
 189         break;
 190     case UART_DATA_BITS_7:
 191         ssp.data_bits = 7;
 192         break;
 193     default:
 194         ssp.data_bits = 8;
 195         break;
 196     }
 197
 198     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 199     case UART_STOP_BITS_1:
 200         ssp.stop_bits = 1;
 201         break;
 202     default:
 203         ssp.stop_bits = 2;
 204         break;
 205     }
 206
 207     packet_size += ssp.data_bits + ssp.stop_bits;
 208     s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
 209     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 210 }
 211
 212 static int uart_can_receive(void *opaque)
 213 {
 214     CadenceUARTState *s = opaque;
 215     int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
 216     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 217
 218     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 219         ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
 220     }
 221     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 222         ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
 223     }
 224     return ret;
 225 }
 226
 227 static void uart_ctrl_update(CadenceUARTState *s)
 228 {
 229     if (s->r[R_CR] & UART_CR_TXRST) {
 230         uart_tx_reset(s);
 231     }
 232
 233     if (s->r[R_CR] & UART_CR_RXRST) {
 234         uart_rx_reset(s);
 235     }
 236
 237     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 238
 239     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 240         uart_send_breaks(s);
 241     }
 242 }
 243
 244 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 245 {
 246     CadenceUARTState *s = opaque;
 247     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 248     int i;
 249
 250     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 251         return;
 252     }
 253
 254     if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
 255         s->r[R_CISR] |= UART_INTR_ROVR;
 256     } else {
 257         for (i = 0; i < size; i++) {
 258             s->rx_fifo[s->rx_wpos] = buf[i];
 259             s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
 260             s->rx_count++;
 261         }
 262         timer_mod(s->fifo_trigger_handle, new_rx_time +
 263                                                 (s->char_tx_time * 4));
 264     }
 265     uart_update_status(s);
 266 }
 267
 268 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
 269                                   void *opaque)
 270 {
 271     CadenceUARTState *s = opaque;
 272     int ret;
 273
 274     /* instant drain the fifo when there's no back-end */
 275     if (!qemu_chr_fe_get_driver(&s->chr)) {
 276         s->tx_count = 0;
 277         return FALSE;
 278     }
 279
 280     if (!s->tx_count) {
 281         return FALSE;
 282     }
 283
 284     ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count);
 285
 286     if (ret >= 0) {
 287         s->tx_count -= ret;
 288         memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
 289     }
 290
 291     if (s->tx_count) {
 292         guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 293                                         cadence_uart_xmit, s);
 294         if (!r) {
 295             s->tx_count = 0;
 296             return FALSE;
 297         }
 298     }
 299
 300     uart_update_status(s);
 301     return FALSE;
 302 }
 303
 304 static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
 305                                int size)
 306 {
 307     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 308         return;
 309     }
 310
 311     if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
 312         size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
 313         /*
 314          * This can only be a guest error via a bad tx fifo register push,
 315          * as can_receive() should stop remote loop and echo modes ever getting
 316          * us to here.
 317          */
 318         qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
 319         s->r[R_CISR] |= UART_INTR_ROVR;
 320     }
 321
 322     memcpy(s->tx_fifo + s->tx_count, buf, size);
 323     s->tx_count += size;
 324
 325     cadence_uart_xmit(NULL, G_IO_OUT, s);
 326 }
 327
 328 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 329 {
 330     CadenceUARTState *s = opaque;
 331     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 332
 333     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 334         uart_write_rx_fifo(opaque, buf, size);
 335     }
 336     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 337         uart_write_tx_fifo(s, buf, size);
 338     }
 339 }
 340
 341 static void uart_event(void *opaque, int event)
 342 {
 343     CadenceUARTState *s = opaque;
 344     uint8_t buf = '\0';
 345
 346     if (event == CHR_EVENT_BREAK) {
 347         uart_write_rx_fifo(opaque, &buf, 1);
 348     }
 349
 350     uart_update_status(s);
 351 }
 352
 353 static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
 354 {
 355     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 356         return;
 357     }
 358
 359     if (s->rx_count) {
 360         uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
 361                             s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
 362         *c = s->rx_fifo[rx_rpos];
 363         s->rx_count--;
 364
 365         qemu_chr_fe_accept_input(&s->chr);
 366     } else {
 367         *c = 0;
 368     }
 369
 370     uart_update_status(s);
 371 }
 372
 373 static void uart_write(void *opaque, hwaddr offset,
 374                           uint64_t value, unsigned size)
 375 {
 376     CadenceUARTState *s = opaque;
 377
 378     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 379     offset >>= 2;
 380     if (offset >= CADENCE_UART_R_MAX) {
 381         return;
 382     }
 383     switch (offset) {
 384     case R_IER: /* ier (wts imr) */
 385         s->r[R_IMR] |= value;
 386         break;
 387     case R_IDR: /* idr (wtc imr) */
 388         s->r[R_IMR] &= ~value;
 389         break;
 390     case R_IMR: /* imr (read only) */
 391         break;
 392     case R_CISR: /* cisr (wtc) */
 393         s->r[R_CISR] &= ~value;
 394         break;
 395     case R_TX_RX: /* UARTDR */
 396         switch (s->r[R_MR] & UART_MR_CHMODE) {
 397         case NORMAL_MODE:
 398             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 399             break;
 400         case LOCAL_LOOPBACK:
 401             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 402             break;
 403         }
 404         break;
 405     default:
 406         s->r[offset] = value;
 407     }
 408
 409     switch (offset) {
 410     case R_CR:
 411         uart_ctrl_update(s);
 412         break;
 413     case R_MR:
 414         uart_parameters_setup(s);
 415         break;
 416     }
 417     uart_update_status(s);
 418 }
 419
 420 static uint64_t uart_read(void *opaque, hwaddr offset,
 421         unsigned size)
 422 {
 423     CadenceUARTState *s = opaque;
 424     uint32_t c = 0;
 425
 426     offset >>= 2;
 427     if (offset >= CADENCE_UART_R_MAX) {
 428         c = 0;
 429     } else if (offset == R_TX_RX) {
 430         uart_read_rx_fifo(s, &c);
 431     } else {
 432        c = s->r[offset];
 433     }
 434
 435     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 436     return c;
 437 }
 438
 439 static const MemoryRegionOps uart_ops = {
 440     .read = uart_read,
 441     .write = uart_write,
 442     .endianness = DEVICE_NATIVE_ENDIAN,
 443 };
 444
 445 static void cadence_uart_reset(DeviceState *dev)
 446 {
 447     CadenceUARTState *s = CADENCE_UART(dev);
 448
 449     s->r[R_CR] = 0x00000128;
 450     s->r[R_IMR] = 0;
 451     s->r[R_CISR] = 0;
 452     s->r[R_RTRIG] = 0x00000020;
 453     s->r[R_BRGR] = 0x0000028B;
 454     s->r[R_BDIV] = 0x0000000F;
 455     s->r[R_TTRIG] = 0x00000020;
 456
 457     uart_rx_reset(s);
 458     uart_tx_reset(s);
 459
 460     uart_update_status(s);
 461 }
 462
 463 static void cadence_uart_realize(DeviceState *dev, Error **errp)
 464 {
 465     CadenceUARTState *s = CADENCE_UART(dev);
 466
 467     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 468                                           fifo_trigger_update, s);
 469
 470     qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
 471                              uart_event, s, NULL, true);
 472 }
 473
 474 static void cadence_uart_init(Object *obj)
 475 {
 476     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 477     CadenceUARTState *s = CADENCE_UART(obj);
 478
 479     memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
 480     sysbus_init_mmio(sbd, &s->iomem);
 481     sysbus_init_irq(sbd, &s->irq);
 482
 483     s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
 484 }
 485
 486 static int cadence_uart_post_load(void *opaque, int version_id)
 487 {
 488     CadenceUARTState *s = opaque;
 489
 490     uart_parameters_setup(s);
 491     uart_update_status(s);
 492     return 0;
 493 }
 494
 495 static const VMStateDescription vmstate_cadence_uart = {
 496     .name = "cadence_uart",
 497     .version_id = 2,
 498     .minimum_version_id = 2,
 499     .post_load = cadence_uart_post_load,
 500     .fields = (VMStateField[]) {
 501         VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
 502         VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
 503                             CADENCE_UART_RX_FIFO_SIZE),
 504         VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
 505                             CADENCE_UART_TX_FIFO_SIZE),
 506         VMSTATE_UINT32(rx_count, CadenceUARTState),
 507         VMSTATE_UINT32(tx_count, CadenceUARTState),
 508         VMSTATE_UINT32(rx_wpos, CadenceUARTState),
 509         VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
 510         VMSTATE_END_OF_LIST()
 511     }
 512 };
 513
 514 static Property cadence_uart_properties[] = {
 515     DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
 516     DEFINE_PROP_END_OF_LIST(),
 517 };
 518
 519 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 520 {
 521     DeviceClass *dc = DEVICE_CLASS(klass);
 522
 523     dc->realize = cadence_uart_realize;
 524     dc->vmsd = &vmstate_cadence_uart;
 525     dc->reset = cadence_uart_reset;
 526     dc->props = cadence_uart_properties;
 527   }
 528
 529 static const TypeInfo cadence_uart_info = {
 530     .name          = TYPE_CADENCE_UART,
 531     .parent        = TYPE_SYS_BUS_DEVICE,
 532     .instance_size = sizeof(CadenceUARTState),
 533     .instance_init = cadence_uart_init,
 534     .class_init    = cadence_uart_class_init,
 535 };
 536
 537 static void cadence_uart_register_types(void)
 538 {
 539     type_register_static(&cadence_uart_info);
 540 }
 541
 542 type_init(cadence_uart_register_types)