cpu.c

   1 /*
   2  * Target-specific parts of the CPU object
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "qapi/error.h"
  23
  24 #include "exec/target_page.h"
  25 #include "hw/qdev-core.h"
  26 #include "hw/qdev-properties.h"
  27 #include "qemu/error-report.h"
  28 #include "migration/vmstate.h"
  29 #ifdef CONFIG_USER_ONLY
  30 #include "qemu.h"
  31 #else
  32 #include "hw/core/sysemu-cpu-ops.h"
  33 #include "exec/address-spaces.h"
  34 #endif
  35 #include "sysemu/tcg.h"
  36 #include "sysemu/kvm.h"
  37 #include "sysemu/replay.h"
  38 #include "exec/translate-all.h"
  39 #include "exec/log.h"
  40 #include "hw/core/accel-cpu.h"
  41 #include "trace/trace-root.h"
  42
  43 uintptr_t qemu_host_page_size;
  44 intptr_t qemu_host_page_mask;
  45
  46 #ifndef CONFIG_USER_ONLY
  47 static int cpu_common_post_load(void *opaque, int version_id)
  48 {
  49     CPUState *cpu = opaque;
  50
  51     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
  52        version_id is increased. */
  53     cpu->interrupt_request &= ~0x01;
  54     tlb_flush(cpu);
  55
  56     /* loadvm has just updated the content of RAM, bypassing the
  57      * usual mechanisms that ensure we flush TBs for writes to
  58      * memory we've translated code from. So we must flush all TBs,
  59      * which will now be stale.
  60      */
  61     tb_flush(cpu);
  62
  63     return 0;
  64 }
  65
  66 static int cpu_common_pre_load(void *opaque)
  67 {
  68     CPUState *cpu = opaque;
  69
  70     cpu->exception_index = -1;
  71
  72     return 0;
  73 }
  74
  75 static bool cpu_common_exception_index_needed(void *opaque)
  76 {
  77     CPUState *cpu = opaque;
  78
  79     return tcg_enabled() && cpu->exception_index != -1;
  80 }
  81
  82 static const VMStateDescription vmstate_cpu_common_exception_index = {
  83     .name = "cpu_common/exception_index",
  84     .version_id = 1,
  85     .minimum_version_id = 1,
  86     .needed = cpu_common_exception_index_needed,
  87     .fields = (VMStateField[]) {
  88         VMSTATE_INT32(exception_index, CPUState),
  89         VMSTATE_END_OF_LIST()
  90     }
  91 };
  92
  93 static bool cpu_common_crash_occurred_needed(void *opaque)
  94 {
  95     CPUState *cpu = opaque;
  96
  97     return cpu->crash_occurred;
  98 }
  99
 100 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
 101     .name = "cpu_common/crash_occurred",
 102     .version_id = 1,
 103     .minimum_version_id = 1,
 104     .needed = cpu_common_crash_occurred_needed,
 105     .fields = (VMStateField[]) {
 106         VMSTATE_BOOL(crash_occurred, CPUState),
 107         VMSTATE_END_OF_LIST()
 108     }
 109 };
 110
 111 const VMStateDescription vmstate_cpu_common = {
 112     .name = "cpu_common",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .pre_load = cpu_common_pre_load,
 116     .post_load = cpu_common_post_load,
 117     .fields = (VMStateField[]) {
 118         VMSTATE_UINT32(halted, CPUState),
 119         VMSTATE_UINT32(interrupt_request, CPUState),
 120         VMSTATE_END_OF_LIST()
 121     },
 122     .subsections = (const VMStateDescription*[]) {
 123         &vmstate_cpu_common_exception_index,
 124         &vmstate_cpu_common_crash_occurred,
 125         NULL
 126     }
 127 };
 128 #endif
 129
 130 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
 131 {
 132 #ifndef CONFIG_USER_ONLY
 133     CPUClass *cc = CPU_GET_CLASS(cpu);
 134 #endif
 135
 136     cpu_list_add(cpu);
 137     if (!accel_cpu_realizefn(cpu, errp)) {
 138         return;
 139     }
 140     /* NB: errp parameter is unused currently */
 141     if (tcg_enabled()) {
 142         tcg_exec_realizefn(cpu, errp);
 143     }
 144
 145 #ifdef CONFIG_USER_ONLY
 146     assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
 147            qdev_get_vmsd(DEVICE(cpu))->unmigratable);
 148 #else
 149     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 150         vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
 151     }
 152     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 153         vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
 154     }
 155 #endif /* CONFIG_USER_ONLY */
 156 }
 157
 158 void cpu_exec_unrealizefn(CPUState *cpu)
 159 {
 160 #ifndef CONFIG_USER_ONLY
 161     CPUClass *cc = CPU_GET_CLASS(cpu);
 162
 163     if (cc->sysemu_ops->legacy_vmsd != NULL) {
 164         vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
 165     }
 166     if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
 167         vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
 168     }
 169 #endif
 170     if (tcg_enabled()) {
 171         tcg_exec_unrealizefn(cpu);
 172     }
 173
 174     cpu_list_remove(cpu);
 175 }
 176
 177 static Property cpu_common_props[] = {
 178 #ifndef CONFIG_USER_ONLY
 179     /*
 180      * Create a memory property for softmmu CPU object,
 181      * so users can wire up its memory. (This can't go in hw/core/cpu.c
 182      * because that file is compiled only once for both user-mode
 183      * and system builds.) The default if no link is set up is to use
 184      * the system address space.
 185      */
 186     DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
 187                      MemoryRegion *),
 188 #endif
 189     DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
 190     DEFINE_PROP_END_OF_LIST(),
 191 };
 192
 193 void cpu_class_init_props(DeviceClass *dc)
 194 {
 195     device_class_set_props(dc, cpu_common_props);
 196 }
 197
 198 void cpu_exec_initfn(CPUState *cpu)
 199 {
 200     cpu->as = NULL;
 201     cpu->num_ases = 0;
 202
 203 #ifndef CONFIG_USER_ONLY
 204     cpu->thread_id = qemu_get_thread_id();
 205     cpu->memory = get_system_memory();
 206     object_ref(OBJECT(cpu->memory));
 207 #endif
 208 }
 209
 210 const char *parse_cpu_option(const char *cpu_option)
 211 {
 212     ObjectClass *oc;
 213     CPUClass *cc;
 214     gchar **model_pieces;
 215     const char *cpu_type;
 216
 217     model_pieces = g_strsplit(cpu_option, ",", 2);
 218     if (!model_pieces[0]) {
 219         error_report("-cpu option cannot be empty");
 220         exit(1);
 221     }
 222
 223     oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
 224     if (oc == NULL) {
 225         error_report("unable to find CPU model '%s'", model_pieces[0]);
 226         g_strfreev(model_pieces);
 227         exit(EXIT_FAILURE);
 228     }
 229
 230     cpu_type = object_class_get_name(oc);
 231     cc = CPU_CLASS(oc);
 232     cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
 233     g_strfreev(model_pieces);
 234     return cpu_type;
 235 }
 236
 237 #if defined(CONFIG_USER_ONLY)
 238 void tb_invalidate_phys_addr(target_ulong addr)
 239 {
 240     mmap_lock();
 241     tb_invalidate_phys_page_range(addr, addr + 1);
 242     mmap_unlock();
 243 }
 244 #else
 245 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 246 {
 247     ram_addr_t ram_addr;
 248     MemoryRegion *mr;
 249     hwaddr l = 1;
 250
 251     if (!tcg_enabled()) {
 252         return;
 253     }
 254
 255     RCU_READ_LOCK_GUARD();
 256     mr = address_space_translate(as, addr, &addr, &l, false, attrs);
 257     if (!(memory_region_is_ram(mr)
 258           || memory_region_is_romd(mr))) {
 259         return;
 260     }
 261     ram_addr = memory_region_get_ram_addr(mr) + addr;
 262     tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
 263 }
 264 #endif
 265
 266 /* Add a breakpoint.  */
 267 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 268                           CPUBreakpoint **breakpoint)
 269 {
 270     CPUClass *cc = CPU_GET_CLASS(cpu);
 271     CPUBreakpoint *bp;
 272
 273     if (cc->gdb_adjust_breakpoint) {
 274         pc = cc->gdb_adjust_breakpoint(cpu, pc);
 275     }
 276
 277     bp = g_malloc(sizeof(*bp));
 278
 279     bp->pc = pc;
 280     bp->flags = flags;
 281
 282     /* keep all GDB-injected breakpoints in front */
 283     if (flags & BP_GDB) {
 284         QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
 285     } else {
 286         QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
 287     }
 288
 289     if (breakpoint) {
 290         *breakpoint = bp;
 291     }
 292
 293     trace_breakpoint_insert(cpu->cpu_index, pc, flags);
 294     return 0;
 295 }
 296
 297 /* Remove a specific breakpoint.  */
 298 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
 299 {
 300     CPUClass *cc = CPU_GET_CLASS(cpu);
 301     CPUBreakpoint *bp;
 302
 303     if (cc->gdb_adjust_breakpoint) {
 304         pc = cc->gdb_adjust_breakpoint(cpu, pc);
 305     }
 306
 307     QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
 308         if (bp->pc == pc && bp->flags == flags) {
 309             cpu_breakpoint_remove_by_ref(cpu, bp);
 310             return 0;
 311         }
 312     }
 313     return -ENOENT;
 314 }
 315
 316 /* Remove a specific breakpoint by reference.  */
 317 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
 318 {
 319     QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
 320
 321     trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
 322     g_free(bp);
 323 }
 324
 325 /* Remove all matching breakpoints. */
 326 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
 327 {
 328     CPUBreakpoint *bp, *next;
 329
 330     QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
 331         if (bp->flags & mask) {
 332             cpu_breakpoint_remove_by_ref(cpu, bp);
 333         }
 334     }
 335 }
 336
 337 /* enable or disable single step mode. EXCP_DEBUG is returned by the
 338    CPU loop after each instruction */
 339 void cpu_single_step(CPUState *cpu, int enabled)
 340 {
 341     if (cpu->singlestep_enabled != enabled) {
 342         cpu->singlestep_enabled = enabled;
 343         if (kvm_enabled()) {
 344             kvm_update_guest_debug(cpu, 0);
 345         }
 346         trace_breakpoint_singlestep(cpu->cpu_index, enabled);
 347     }
 348 }
 349
 350 void cpu_abort(CPUState *cpu, const char *fmt, ...)
 351 {
 352     va_list ap;
 353     va_list ap2;
 354
 355     va_start(ap, fmt);
 356     va_copy(ap2, ap);
 357     fprintf(stderr, "qemu: fatal: ");
 358     vfprintf(stderr, fmt, ap);
 359     fprintf(stderr, "\n");
 360     cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 361     if (qemu_log_separate()) {
 362         FILE *logfile = qemu_log_lock();
 363         qemu_log("qemu: fatal: ");
 364         qemu_log_vprintf(fmt, ap2);
 365         qemu_log("\n");
 366         log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
 367         qemu_log_flush();
 368         qemu_log_unlock(logfile);
 369         qemu_log_close();
 370     }
 371     va_end(ap2);
 372     va_end(ap);
 373     replay_finish();
 374 #if defined(CONFIG_USER_ONLY)
 375     {
 376         struct sigaction act;
 377         sigfillset(&act.sa_mask);
 378         act.sa_handler = SIG_DFL;
 379         act.sa_flags = 0;
 380         sigaction(SIGABRT, &act, NULL);
 381     }
 382 #endif
 383     abort();
 384 }
 385
 386 /* physical memory access (slow version, mainly for debug) */
 387 #if defined(CONFIG_USER_ONLY)
 388 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
 389                         void *ptr, target_ulong len, bool is_write)
 390 {
 391     int flags;
 392     target_ulong l, page;
 393     void * p;
 394     uint8_t *buf = ptr;
 395
 396     while (len > 0) {
 397         page = addr & TARGET_PAGE_MASK;
 398         l = (page + TARGET_PAGE_SIZE) - addr;
 399         if (l > len)
 400             l = len;
 401         flags = page_get_flags(page);
 402         if (!(flags & PAGE_VALID))
 403             return -1;
 404         if (is_write) {
 405             if (!(flags & PAGE_WRITE))
 406                 return -1;
 407             /* XXX: this code should not depend on lock_user */
 408             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
 409                 return -1;
 410             memcpy(p, buf, l);
 411             unlock_user(p, addr, l);
 412         } else {
 413             if (!(flags & PAGE_READ))
 414                 return -1;
 415             /* XXX: this code should not depend on lock_user */
 416             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
 417                 return -1;
 418             memcpy(buf, p, l);
 419             unlock_user(p, addr, 0);
 420         }
 421         len -= l;
 422         buf += l;
 423         addr += l;
 424     }
 425     return 0;
 426 }
 427 #endif
 428
 429 bool target_words_bigendian(void)
 430 {
 431 #if defined(TARGET_WORDS_BIGENDIAN)
 432     return true;
 433 #else
 434     return false;
 435 #endif
 436 }
 437
 438 void page_size_init(void)
 439 {
 440     /* NOTE: we can always suppose that qemu_host_page_size >=
 441        TARGET_PAGE_SIZE */
 442     if (qemu_host_page_size == 0) {
 443         qemu_host_page_size = qemu_real_host_page_size;
 444     }
 445     if (qemu_host_page_size < TARGET_PAGE_SIZE) {
 446         qemu_host_page_size = TARGET_PAGE_SIZE;
 447     }
 448     qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
 449 }