hw/ppc/spapr_iommu.c

   1 /*
   2  * QEMU sPAPR IOMMU (TCE) code
   3  *
   4  * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu/error-report.h"
  21 #include "hw/hw.h"
  22 #include "qemu/log.h"
  23 #include "sysemu/kvm.h"
  24 #include "hw/qdev.h"
  25 #include "kvm_ppc.h"
  26 #include "sysemu/dma.h"
  27 #include "exec/address-spaces.h"
  28 #include "trace.h"
  29
  30 #include "hw/ppc/spapr.h"
  31 #include "hw/ppc/spapr_vio.h"
  32
  33 #include <libfdt.h>
  34
  35 enum sPAPRTCEAccess {
  36     SPAPR_TCE_FAULT = 0,
  37     SPAPR_TCE_RO = 1,
  38     SPAPR_TCE_WO = 2,
  39     SPAPR_TCE_RW = 3,
  40 };
  41
  42 #define IOMMU_PAGE_SIZE(shift)      (1ULL << (shift))
  43 #define IOMMU_PAGE_MASK(shift)      (~(IOMMU_PAGE_SIZE(shift) - 1))
  44
  45 static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables;
  46
  47 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn)
  48 {
  49     sPAPRTCETable *tcet;
  50
  51     if (liobn & 0xFFFFFFFF00000000ULL) {
  52         hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
  53                       liobn);
  54         return NULL;
  55     }
  56
  57     QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
  58         if (tcet->liobn == (uint32_t)liobn) {
  59             return tcet;
  60         }
  61     }
  62
  63     return NULL;
  64 }
  65
  66 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
  67 {
  68     switch (tce & SPAPR_TCE_RW) {
  69     case SPAPR_TCE_FAULT:
  70         return IOMMU_NONE;
  71     case SPAPR_TCE_RO:
  72         return IOMMU_RO;
  73     case SPAPR_TCE_WO:
  74         return IOMMU_WO;
  75     default: /* SPAPR_TCE_RW */
  76         return IOMMU_RW;
  77     }
  78 }
  79
  80 static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
  81                                        uint32_t page_shift,
  82                                        uint64_t bus_offset,
  83                                        uint32_t nb_table,
  84                                        int *fd,
  85                                        bool need_vfio)
  86 {
  87     uint64_t *table = NULL;
  88
  89     if (kvm_enabled()) {
  90         table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
  91                                         fd, need_vfio);
  92     }
  93
  94     if (!table) {
  95         *fd = -1;
  96         table = g_malloc0(nb_table * sizeof(uint64_t));
  97     }
  98
  99     trace_spapr_iommu_new_table(liobn, table, *fd);
 100
 101     return table;
 102 }
 103
 104 static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
 105 {
 106     if (!kvm_enabled() ||
 107         (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
 108         g_free(table);
 109     }
 110 }
 111
 112 /* Called from RCU critical section */
 113 static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
 114                                                hwaddr addr,
 115                                                IOMMUAccessFlags flag)
 116 {
 117     sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
 118     uint64_t tce;
 119     IOMMUTLBEntry ret = {
 120         .target_as = &address_space_memory,
 121         .iova = 0,
 122         .translated_addr = 0,
 123         .addr_mask = ~(hwaddr)0,
 124         .perm = IOMMU_NONE,
 125     };
 126
 127     if ((addr >> tcet->page_shift) < tcet->nb_table) {
 128         /* Check if we are in bound */
 129         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 130
 131         tce = tcet->table[addr >> tcet->page_shift];
 132         ret.iova = addr & page_mask;
 133         ret.translated_addr = tce & page_mask;
 134         ret.addr_mask = ~page_mask;
 135         ret.perm = spapr_tce_iommu_access_flags(tce);
 136     }
 137     trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm,
 138                             ret.addr_mask);
 139
 140     return ret;
 141 }
 142
 143 static int spapr_tce_table_pre_save(void *opaque)
 144 {
 145     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
 146
 147     tcet->mig_table = tcet->table;
 148     tcet->mig_nb_table = tcet->nb_table;
 149
 150     trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
 151                                tcet->bus_offset, tcet->page_shift);
 152
 153     return 0;
 154 }
 155
 156 static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
 157 {
 158     sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu);
 159
 160     return 1ULL << tcet->page_shift;
 161 }
 162
 163 static void spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
 164                                           IOMMUNotifierFlag old,
 165                                           IOMMUNotifierFlag new)
 166 {
 167     struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu);
 168
 169     if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
 170         spapr_tce_set_need_vfio(tbl, true);
 171     } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
 172         spapr_tce_set_need_vfio(tbl, false);
 173     }
 174 }
 175
 176 static int spapr_tce_table_post_load(void *opaque, int version_id)
 177 {
 178     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque);
 179     uint32_t old_nb_table = tcet->nb_table;
 180     uint64_t old_bus_offset = tcet->bus_offset;
 181     uint32_t old_page_shift = tcet->page_shift;
 182
 183     if (tcet->vdev) {
 184         spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
 185     }
 186
 187     if (tcet->mig_nb_table != tcet->nb_table) {
 188         spapr_tce_table_disable(tcet);
 189     }
 190
 191     if (tcet->mig_nb_table) {
 192         if (!tcet->nb_table) {
 193             spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
 194                                    tcet->mig_nb_table);
 195         }
 196
 197         memcpy(tcet->table, tcet->mig_table,
 198                tcet->nb_table * sizeof(tcet->table[0]));
 199
 200         free(tcet->mig_table);
 201         tcet->mig_table = NULL;
 202     }
 203
 204     trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
 205                                 tcet->bus_offset, tcet->page_shift);
 206
 207     return 0;
 208 }
 209
 210 static bool spapr_tce_table_ex_needed(void *opaque)
 211 {
 212     sPAPRTCETable *tcet = opaque;
 213
 214     return tcet->bus_offset || tcet->page_shift != 0xC;
 215 }
 216
 217 static const VMStateDescription vmstate_spapr_tce_table_ex = {
 218     .name = "spapr_iommu_ex",
 219     .version_id = 1,
 220     .minimum_version_id = 1,
 221     .needed = spapr_tce_table_ex_needed,
 222     .fields = (VMStateField[]) {
 223         VMSTATE_UINT64(bus_offset, sPAPRTCETable),
 224         VMSTATE_UINT32(page_shift, sPAPRTCETable),
 225         VMSTATE_END_OF_LIST()
 226     },
 227 };
 228
 229 static const VMStateDescription vmstate_spapr_tce_table = {
 230     .name = "spapr_iommu",
 231     .version_id = 2,
 232     .minimum_version_id = 2,
 233     .pre_save = spapr_tce_table_pre_save,
 234     .post_load = spapr_tce_table_post_load,
 235     .fields      = (VMStateField []) {
 236         /* Sanity check */
 237         VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable, NULL),
 238
 239         /* IOMMU state */
 240         VMSTATE_UINT32(mig_nb_table, sPAPRTCETable),
 241         VMSTATE_BOOL(bypass, sPAPRTCETable),
 242         VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0,
 243                                     vmstate_info_uint64, uint64_t),
 244
 245         VMSTATE_END_OF_LIST()
 246     },
 247     .subsections = (const VMStateDescription*[]) {
 248         &vmstate_spapr_tce_table_ex,
 249         NULL
 250     }
 251 };
 252
 253 static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
 254 {
 255     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 256     Object *tcetobj = OBJECT(tcet);
 257     gchar *tmp;
 258
 259     tcet->fd = -1;
 260     tcet->need_vfio = false;
 261     tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
 262     memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
 263     g_free(tmp);
 264
 265     tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
 266     memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
 267                              TYPE_SPAPR_IOMMU_MEMORY_REGION,
 268                              tcetobj, tmp, 0);
 269     g_free(tmp);
 270
 271     QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
 272
 273     vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table,
 274                      tcet);
 275 }
 276
 277 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio)
 278 {
 279     size_t table_size = tcet->nb_table * sizeof(uint64_t);
 280     uint64_t *oldtable;
 281     int newfd = -1;
 282
 283     g_assert(need_vfio != tcet->need_vfio);
 284
 285     tcet->need_vfio = need_vfio;
 286
 287     oldtable = tcet->table;
 288
 289     tcet->table = spapr_tce_alloc_table(tcet->liobn,
 290                                         tcet->page_shift,
 291                                         tcet->bus_offset,
 292                                         tcet->nb_table,
 293                                         &newfd,
 294                                         need_vfio);
 295     memcpy(tcet->table, oldtable, table_size);
 296
 297     spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
 298
 299     tcet->fd = newfd;
 300 }
 301
 302 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
 303 {
 304     sPAPRTCETable *tcet;
 305     gchar *tmp;
 306
 307     if (spapr_tce_find_by_liobn(liobn)) {
 308         error_report("Attempted to create TCE table with duplicate"
 309                 " LIOBN 0x%x", liobn);
 310         return NULL;
 311     }
 312
 313     tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
 314     tcet->liobn = liobn;
 315
 316     tmp = g_strdup_printf("tce-table-%x", liobn);
 317     object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL);
 318     g_free(tmp);
 319     object_unref(OBJECT(tcet));
 320
 321     object_property_set_bool(OBJECT(tcet), true, "realized", NULL);
 322
 323     return tcet;
 324 }
 325
 326 void spapr_tce_table_enable(sPAPRTCETable *tcet,
 327                             uint32_t page_shift, uint64_t bus_offset,
 328                             uint32_t nb_table)
 329 {
 330     if (tcet->nb_table) {
 331         warn_report("trying to enable already enabled TCE table");
 332         return;
 333     }
 334
 335     tcet->bus_offset = bus_offset;
 336     tcet->page_shift = page_shift;
 337     tcet->nb_table = nb_table;
 338     tcet->table = spapr_tce_alloc_table(tcet->liobn,
 339                                         tcet->page_shift,
 340                                         tcet->bus_offset,
 341                                         tcet->nb_table,
 342                                         &tcet->fd,
 343                                         tcet->need_vfio);
 344
 345     memory_region_set_size(MEMORY_REGION(&tcet->iommu),
 346                            (uint64_t)tcet->nb_table << tcet->page_shift);
 347     memory_region_add_subregion(&tcet->root, tcet->bus_offset,
 348                                 MEMORY_REGION(&tcet->iommu));
 349 }
 350
 351 void spapr_tce_table_disable(sPAPRTCETable *tcet)
 352 {
 353     if (!tcet->nb_table) {
 354         return;
 355     }
 356
 357     memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
 358     memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
 359
 360     spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
 361     tcet->fd = -1;
 362     tcet->table = NULL;
 363     tcet->bus_offset = 0;
 364     tcet->page_shift = 0;
 365     tcet->nb_table = 0;
 366 }
 367
 368 static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp)
 369 {
 370     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 371
 372     vmstate_unregister(DEVICE(tcet), &vmstate_spapr_tce_table, tcet);
 373
 374     QLIST_REMOVE(tcet, list);
 375
 376     spapr_tce_table_disable(tcet);
 377 }
 378
 379 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet)
 380 {
 381     return &tcet->root;
 382 }
 383
 384 static void spapr_tce_reset(DeviceState *dev)
 385 {
 386     sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev);
 387     size_t table_size = tcet->nb_table * sizeof(uint64_t);
 388
 389     if (tcet->nb_table) {
 390         memset(tcet->table, 0, table_size);
 391     }
 392 }
 393
 394 static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
 395                                 target_ulong tce)
 396 {
 397     IOMMUTLBEntry entry;
 398     hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 399     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 400
 401     if (index >= tcet->nb_table) {
 402         hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
 403                       TARGET_FMT_lx "\n", ioba);
 404         return H_PARAMETER;
 405     }
 406
 407     tcet->table[index] = tce;
 408
 409     entry.target_as = &address_space_memory,
 410     entry.iova = (ioba - tcet->bus_offset) & page_mask;
 411     entry.translated_addr = tce & page_mask;
 412     entry.addr_mask = ~page_mask;
 413     entry.perm = spapr_tce_iommu_access_flags(tce);
 414     memory_region_notify_iommu(&tcet->iommu, entry);
 415
 416     return H_SUCCESS;
 417 }
 418
 419 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
 420                                        sPAPRMachineState *spapr,
 421                                        target_ulong opcode, target_ulong *args)
 422 {
 423     int i;
 424     target_ulong liobn = args[0];
 425     target_ulong ioba = args[1];
 426     target_ulong ioba1 = ioba;
 427     target_ulong tce_list = args[2];
 428     target_ulong npages = args[3];
 429     target_ulong ret = H_PARAMETER, tce = 0;
 430     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 431     CPUState *cs = CPU(cpu);
 432     hwaddr page_mask, page_size;
 433
 434     if (!tcet) {
 435         return H_PARAMETER;
 436     }
 437
 438     if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
 439         return H_PARAMETER;
 440     }
 441
 442     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 443     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 444     ioba &= page_mask;
 445
 446     for (i = 0; i < npages; ++i, ioba += page_size) {
 447         tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
 448
 449         ret = put_tce_emu(tcet, ioba, tce);
 450         if (ret) {
 451             break;
 452         }
 453     }
 454
 455     /* Trace last successful or the first problematic entry */
 456     i = i ? (i - 1) : 0;
 457     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 458         trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
 459     } else {
 460         trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
 461     }
 462     return ret;
 463 }
 464
 465 static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 466                               target_ulong opcode, target_ulong *args)
 467 {
 468     int i;
 469     target_ulong liobn = args[0];
 470     target_ulong ioba = args[1];
 471     target_ulong tce_value = args[2];
 472     target_ulong npages = args[3];
 473     target_ulong ret = H_PARAMETER;
 474     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 475     hwaddr page_mask, page_size;
 476
 477     if (!tcet) {
 478         return H_PARAMETER;
 479     }
 480
 481     if (npages > tcet->nb_table) {
 482         return H_PARAMETER;
 483     }
 484
 485     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 486     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 487     ioba &= page_mask;
 488
 489     for (i = 0; i < npages; ++i, ioba += page_size) {
 490         ret = put_tce_emu(tcet, ioba, tce_value);
 491         if (ret) {
 492             break;
 493         }
 494     }
 495     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 496         trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
 497     } else {
 498         trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
 499     }
 500
 501     return ret;
 502 }
 503
 504 static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 505                               target_ulong opcode, target_ulong *args)
 506 {
 507     target_ulong liobn = args[0];
 508     target_ulong ioba = args[1];
 509     target_ulong tce = args[2];
 510     target_ulong ret = H_PARAMETER;
 511     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 512
 513     if (tcet) {
 514         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 515
 516         ioba &= page_mask;
 517
 518         ret = put_tce_emu(tcet, ioba, tce);
 519     }
 520     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 521         trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
 522     } else {
 523         trace_spapr_iommu_put(liobn, ioba, tce, ret);
 524     }
 525
 526     return ret;
 527 }
 528
 529 static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba,
 530                                 target_ulong *tce)
 531 {
 532     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 533
 534     if (index >= tcet->nb_table) {
 535         hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
 536                       TARGET_FMT_lx "\n", ioba);
 537         return H_PARAMETER;
 538     }
 539
 540     *tce = tcet->table[index];
 541
 542     return H_SUCCESS;
 543 }
 544
 545 static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 546                               target_ulong opcode, target_ulong *args)
 547 {
 548     target_ulong liobn = args[0];
 549     target_ulong ioba = args[1];
 550     target_ulong tce = 0;
 551     target_ulong ret = H_PARAMETER;
 552     sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn);
 553
 554     if (tcet) {
 555         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 556
 557         ioba &= page_mask;
 558
 559         ret = get_tce_emu(tcet, ioba, &tce);
 560         if (!ret) {
 561             args[0] = tce;
 562         }
 563     }
 564     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 565         trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
 566     } else {
 567         trace_spapr_iommu_get(liobn, ioba, ret, tce);
 568     }
 569
 570     return ret;
 571 }
 572
 573 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 574                  uint32_t liobn, uint64_t window, uint32_t size)
 575 {
 576     uint32_t dma_prop[5];
 577     int ret;
 578
 579     dma_prop[0] = cpu_to_be32(liobn);
 580     dma_prop[1] = cpu_to_be32(window >> 32);
 581     dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
 582     dma_prop[3] = 0; /* window size is 32 bits */
 583     dma_prop[4] = cpu_to_be32(size);
 584
 585     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
 586     if (ret < 0) {
 587         return ret;
 588     }
 589
 590     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
 591     if (ret < 0) {
 592         return ret;
 593     }
 594
 595     ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
 596     if (ret < 0) {
 597         return ret;
 598     }
 599
 600     return 0;
 601 }
 602
 603 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 604                       sPAPRTCETable *tcet)
 605 {
 606     if (!tcet) {
 607         return 0;
 608     }
 609
 610     return spapr_dma_dt(fdt, node_off, propname,
 611                         tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
 612 }
 613
 614 static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
 615 {
 616     DeviceClass *dc = DEVICE_CLASS(klass);
 617     dc->realize = spapr_tce_table_realize;
 618     dc->reset = spapr_tce_reset;
 619     dc->unrealize = spapr_tce_table_unrealize;
 620     /* Reason: This is just an internal device for handling the hypercalls */
 621     dc->user_creatable = false;
 622
 623     QLIST_INIT(&spapr_tce_tables);
 624
 625     /* hcall-tce */
 626     spapr_register_hypercall(H_PUT_TCE, h_put_tce);
 627     spapr_register_hypercall(H_GET_TCE, h_get_tce);
 628     spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
 629     spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
 630 }
 631
 632 static TypeInfo spapr_tce_table_info = {
 633     .name = TYPE_SPAPR_TCE_TABLE,
 634     .parent = TYPE_DEVICE,
 635     .instance_size = sizeof(sPAPRTCETable),
 636     .class_init = spapr_tce_table_class_init,
 637 };
 638
 639 static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 640 {
 641     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 642
 643     imrc->translate = spapr_tce_translate_iommu;
 644     imrc->get_min_page_size = spapr_tce_get_min_page_size;
 645     imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
 646 }
 647
 648 static const TypeInfo spapr_iommu_memory_region_info = {
 649     .parent = TYPE_IOMMU_MEMORY_REGION,
 650     .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
 651     .class_init = spapr_iommu_memory_region_class_init,
 652 };
 653
 654 static void register_types(void)
 655 {
 656     type_register_static(&spapr_tce_table_info);
 657     type_register_static(&spapr_iommu_memory_region_info);
 658 }
 659
 660 type_init(register_types);