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Make tb_alloc static
[qemu.git] / target-arm / translate.c
blob3087a5dcdd999dc87fad7a4a1595b9b755ee03cb
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_5J 0
38 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
39 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
40 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
41 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
42
43 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
44
45 /* internal defines */
46 typedef struct DisasContext {
47 target_ulong pc;
48 int is_jmp;
49 /* Nonzero if this instruction has been conditionally skipped. */
50 int condjmp;
51 /* The label that will be jumped to when the instruction is skipped. */
52 int condlabel;
53 /* Thumb-2 condtional execution bits. */
54 int condexec_mask;
55 int condexec_cond;
56 struct TranslationBlock *tb;
57 int singlestep_enabled;
58 int thumb;
59 #if !defined(CONFIG_USER_ONLY)
60 int user;
61 #endif
62 int vfp_enabled;
63 int vec_len;
64 int vec_stride;
65 } DisasContext;
66
67 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
68
69 #if defined(CONFIG_USER_ONLY)
70 #define IS_USER(s) 1
71 #else
72 #define IS_USER(s) (s->user)
73 #endif
74
75 /* These instructions trap after executing, so defer them until after the
76 conditional executions state has been updated. */
77 #define DISAS_WFI 4
78 #define DISAS_SWI 5
79
80 static TCGv_ptr cpu_env;
81 /* We reuse the same 64-bit temporaries for efficiency. */
82 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
83 static TCGv_i32 cpu_R[16];
84 static TCGv_i32 cpu_exclusive_addr;
85 static TCGv_i32 cpu_exclusive_val;
86 static TCGv_i32 cpu_exclusive_high;
87 #ifdef CONFIG_USER_ONLY
88 static TCGv_i32 cpu_exclusive_test;
89 static TCGv_i32 cpu_exclusive_info;
90 #endif
91
92 /* FIXME: These should be removed. */
93 static TCGv cpu_F0s, cpu_F1s;
94 static TCGv_i64 cpu_F0d, cpu_F1d;
95
96 #include "gen-icount.h"
97
98 static const char *regnames[] =
99 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
101
102 /* initialize TCG globals. */
103 void arm_translate_init(void)
104 {
105 int i;
106
107 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
108
109 for (i = 0; i < 16; i++) {
110 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
111 offsetof(CPUState, regs[i]),
112 regnames[i]);
113 }
114 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, exclusive_addr), "exclusive_addr");
116 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
117 offsetof(CPUState, exclusive_val), "exclusive_val");
118 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_high), "exclusive_high");
120 #ifdef CONFIG_USER_ONLY
121 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUState, exclusive_test), "exclusive_test");
123 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
124 offsetof(CPUState, exclusive_info), "exclusive_info");
125 #endif
126
127 #define GEN_HELPER 2
128 #include "helpers.h"
129 }
130
131 static int num_temps;
132
133 /* Allocate a temporary variable. */
134 static TCGv_i32 new_tmp(void)
135 {
136 num_temps++;
137 return tcg_temp_new_i32();
138 }
139
140 /* Release a temporary variable. */
141 static void dead_tmp(TCGv tmp)
142 {
143 tcg_temp_free(tmp);
144 num_temps--;
145 }
146
147 static inline TCGv load_cpu_offset(int offset)
148 {
149 TCGv tmp = new_tmp();
150 tcg_gen_ld_i32(tmp, cpu_env, offset);
151 return tmp;
152 }
153
154 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
155
156 static inline void store_cpu_offset(TCGv var, int offset)
157 {
158 tcg_gen_st_i32(var, cpu_env, offset);
159 dead_tmp(var);
160 }
161
162 #define store_cpu_field(var, name) \
163 store_cpu_offset(var, offsetof(CPUState, name))
164
165 /* Set a variable to the value of a CPU register. */
166 static void load_reg_var(DisasContext *s, TCGv var, int reg)
167 {
168 if (reg == 15) {
169 uint32_t addr;
170 /* normaly, since we updated PC, we need only to add one insn */
171 if (s->thumb)
172 addr = (long)s->pc + 2;
173 else
174 addr = (long)s->pc + 4;
175 tcg_gen_movi_i32(var, addr);
176 } else {
177 tcg_gen_mov_i32(var, cpu_R[reg]);
178 }
179 }
180
181 /* Create a new temporary and set it to the value of a CPU register. */
182 static inline TCGv load_reg(DisasContext *s, int reg)
183 {
184 TCGv tmp = new_tmp();
185 load_reg_var(s, tmp, reg);
186 return tmp;
187 }
188
189 /* Set a CPU register. The source must be a temporary and will be
190 marked as dead. */
191 static void store_reg(DisasContext *s, int reg, TCGv var)
192 {
193 if (reg == 15) {
194 tcg_gen_andi_i32(var, var, ~1);
195 s->is_jmp = DISAS_JUMP;
196 }
197 tcg_gen_mov_i32(cpu_R[reg], var);
198 dead_tmp(var);
199 }
200
201 /* Value extensions. */
202 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
203 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
204 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
205 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
206
207 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
208 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
209
210
211 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
212 {
213 TCGv tmp_mask = tcg_const_i32(mask);
214 gen_helper_cpsr_write(var, tmp_mask);
215 tcg_temp_free_i32(tmp_mask);
216 }
217 /* Set NZCV flags from the high 4 bits of var. */
218 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
219
220 static void gen_exception(int excp)
221 {
222 TCGv tmp = new_tmp();
223 tcg_gen_movi_i32(tmp, excp);
224 gen_helper_exception(tmp);
225 dead_tmp(tmp);
226 }
227
228 static void gen_smul_dual(TCGv a, TCGv b)
229 {
230 TCGv tmp1 = new_tmp();
231 TCGv tmp2 = new_tmp();
232 tcg_gen_ext16s_i32(tmp1, a);
233 tcg_gen_ext16s_i32(tmp2, b);
234 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
235 dead_tmp(tmp2);
236 tcg_gen_sari_i32(a, a, 16);
237 tcg_gen_sari_i32(b, b, 16);
238 tcg_gen_mul_i32(b, b, a);
239 tcg_gen_mov_i32(a, tmp1);
240 dead_tmp(tmp1);
241 }
242
243 /* Byteswap each halfword. */
244 static void gen_rev16(TCGv var)
245 {
246 TCGv tmp = new_tmp();
247 tcg_gen_shri_i32(tmp, var, 8);
248 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
249 tcg_gen_shli_i32(var, var, 8);
250 tcg_gen_andi_i32(var, var, 0xff00ff00);
251 tcg_gen_or_i32(var, var, tmp);
252 dead_tmp(tmp);
253 }
254
255 /* Byteswap low halfword and sign extend. */
256 static void gen_revsh(TCGv var)
257 {
258 tcg_gen_ext16u_i32(var, var);
259 tcg_gen_bswap16_i32(var, var);
260 tcg_gen_ext16s_i32(var, var);
261 }
262
263 /* Unsigned bitfield extract. */
264 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
265 {
266 if (shift)
267 tcg_gen_shri_i32(var, var, shift);
268 tcg_gen_andi_i32(var, var, mask);
269 }
270
271 /* Signed bitfield extract. */
272 static void gen_sbfx(TCGv var, int shift, int width)
273 {
274 uint32_t signbit;
275
276 if (shift)
277 tcg_gen_sari_i32(var, var, shift);
278 if (shift + width < 32) {
279 signbit = 1u << (width - 1);
280 tcg_gen_andi_i32(var, var, (1u << width) - 1);
281 tcg_gen_xori_i32(var, var, signbit);
282 tcg_gen_subi_i32(var, var, signbit);
283 }
284 }
285
286 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
287 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
288 {
289 tcg_gen_andi_i32(val, val, mask);
290 tcg_gen_shli_i32(val, val, shift);
291 tcg_gen_andi_i32(base, base, ~(mask << shift));
292 tcg_gen_or_i32(dest, base, val);
293 }
294
295 /* Return (b << 32) + a. Mark inputs as dead */
296 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
297 {
298 TCGv_i64 tmp64 = tcg_temp_new_i64();
299
300 tcg_gen_extu_i32_i64(tmp64, b);
301 dead_tmp(b);
302 tcg_gen_shli_i64(tmp64, tmp64, 32);
303 tcg_gen_add_i64(a, tmp64, a);
304
305 tcg_temp_free_i64(tmp64);
306 return a;
307 }
308
309 /* Return (b << 32) - a. Mark inputs as dead. */
310 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
311 {
312 TCGv_i64 tmp64 = tcg_temp_new_i64();
313
314 tcg_gen_extu_i32_i64(tmp64, b);
315 dead_tmp(b);
316 tcg_gen_shli_i64(tmp64, tmp64, 32);
317 tcg_gen_sub_i64(a, tmp64, a);
318
319 tcg_temp_free_i64(tmp64);
320 return a;
321 }
322
323 /* FIXME: Most targets have native widening multiplication.
324 It would be good to use that instead of a full wide multiply. */
325 /* 32x32->64 multiply. Marks inputs as dead. */
326 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
327 {
328 TCGv_i64 tmp1 = tcg_temp_new_i64();
329 TCGv_i64 tmp2 = tcg_temp_new_i64();
330
331 tcg_gen_extu_i32_i64(tmp1, a);
332 dead_tmp(a);
333 tcg_gen_extu_i32_i64(tmp2, b);
334 dead_tmp(b);
335 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
336 tcg_temp_free_i64(tmp2);
337 return tmp1;
338 }
339
340 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
341 {
342 TCGv_i64 tmp1 = tcg_temp_new_i64();
343 TCGv_i64 tmp2 = tcg_temp_new_i64();
344
345 tcg_gen_ext_i32_i64(tmp1, a);
346 dead_tmp(a);
347 tcg_gen_ext_i32_i64(tmp2, b);
348 dead_tmp(b);
349 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
350 tcg_temp_free_i64(tmp2);
351 return tmp1;
352 }
353
354 /* Swap low and high halfwords. */
355 static void gen_swap_half(TCGv var)
356 {
357 TCGv tmp = new_tmp();
358 tcg_gen_shri_i32(tmp, var, 16);
359 tcg_gen_shli_i32(var, var, 16);
360 tcg_gen_or_i32(var, var, tmp);
361 dead_tmp(tmp);
362 }
363
364 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
365 tmp = (t0 ^ t1) & 0x8000;
366 t0 &= ~0x8000;
367 t1 &= ~0x8000;
368 t0 = (t0 + t1) ^ tmp;
369 */
370
371 static void gen_add16(TCGv t0, TCGv t1)
372 {
373 TCGv tmp = new_tmp();
374 tcg_gen_xor_i32(tmp, t0, t1);
375 tcg_gen_andi_i32(tmp, tmp, 0x8000);
376 tcg_gen_andi_i32(t0, t0, ~0x8000);
377 tcg_gen_andi_i32(t1, t1, ~0x8000);
378 tcg_gen_add_i32(t0, t0, t1);
379 tcg_gen_xor_i32(t0, t0, tmp);
380 dead_tmp(tmp);
381 dead_tmp(t1);
382 }
383
384 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
385
386 /* Set CF to the top bit of var. */
387 static void gen_set_CF_bit31(TCGv var)
388 {
389 TCGv tmp = new_tmp();
390 tcg_gen_shri_i32(tmp, var, 31);
391 gen_set_CF(tmp);
392 dead_tmp(tmp);
393 }
394
395 /* Set N and Z flags from var. */
396 static inline void gen_logic_CC(TCGv var)
397 {
398 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
399 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
400 }
401
402 /* T0 += T1 + CF. */
403 static void gen_adc(TCGv t0, TCGv t1)
404 {
405 TCGv tmp;
406 tcg_gen_add_i32(t0, t0, t1);
407 tmp = load_cpu_field(CF);
408 tcg_gen_add_i32(t0, t0, tmp);
409 dead_tmp(tmp);
410 }
411
412 /* dest = T0 + T1 + CF. */
413 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
414 {
415 TCGv tmp;
416 tcg_gen_add_i32(dest, t0, t1);
417 tmp = load_cpu_field(CF);
418 tcg_gen_add_i32(dest, dest, tmp);
419 dead_tmp(tmp);
420 }
421
422 /* dest = T0 - T1 + CF - 1. */
423 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
424 {
425 TCGv tmp;
426 tcg_gen_sub_i32(dest, t0, t1);
427 tmp = load_cpu_field(CF);
428 tcg_gen_add_i32(dest, dest, tmp);
429 tcg_gen_subi_i32(dest, dest, 1);
430 dead_tmp(tmp);
431 }
432
433 /* FIXME: Implement this natively. */
434 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
435
436 static void shifter_out_im(TCGv var, int shift)
437 {
438 TCGv tmp = new_tmp();
439 if (shift == 0) {
440 tcg_gen_andi_i32(tmp, var, 1);
441 } else {
442 tcg_gen_shri_i32(tmp, var, shift);
443 if (shift != 31)
444 tcg_gen_andi_i32(tmp, tmp, 1);
445 }
446 gen_set_CF(tmp);
447 dead_tmp(tmp);
448 }
449
450 /* Shift by immediate. Includes special handling for shift == 0. */
451 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
452 {
453 switch (shiftop) {
454 case 0: /* LSL */
455 if (shift != 0) {
456 if (flags)
457 shifter_out_im(var, 32 - shift);
458 tcg_gen_shli_i32(var, var, shift);
459 }
460 break;
461 case 1: /* LSR */
462 if (shift == 0) {
463 if (flags) {
464 tcg_gen_shri_i32(var, var, 31);
465 gen_set_CF(var);
466 }
467 tcg_gen_movi_i32(var, 0);
468 } else {
469 if (flags)
470 shifter_out_im(var, shift - 1);
471 tcg_gen_shri_i32(var, var, shift);
472 }
473 break;
474 case 2: /* ASR */
475 if (shift == 0)
476 shift = 32;
477 if (flags)
478 shifter_out_im(var, shift - 1);
479 if (shift == 32)
480 shift = 31;
481 tcg_gen_sari_i32(var, var, shift);
482 break;
483 case 3: /* ROR/RRX */
484 if (shift != 0) {
485 if (flags)
486 shifter_out_im(var, shift - 1);
487 tcg_gen_rotri_i32(var, var, shift); break;
488 } else {
489 TCGv tmp = load_cpu_field(CF);
490 if (flags)
491 shifter_out_im(var, 0);
492 tcg_gen_shri_i32(var, var, 1);
493 tcg_gen_shli_i32(tmp, tmp, 31);
494 tcg_gen_or_i32(var, var, tmp);
495 dead_tmp(tmp);
496 }
497 }
498 };
499
500 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
501 TCGv shift, int flags)
502 {
503 if (flags) {
504 switch (shiftop) {
505 case 0: gen_helper_shl_cc(var, var, shift); break;
506 case 1: gen_helper_shr_cc(var, var, shift); break;
507 case 2: gen_helper_sar_cc(var, var, shift); break;
508 case 3: gen_helper_ror_cc(var, var, shift); break;
509 }
510 } else {
511 switch (shiftop) {
512 case 0: gen_helper_shl(var, var, shift); break;
513 case 1: gen_helper_shr(var, var, shift); break;
514 case 2: gen_helper_sar(var, var, shift); break;
515 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
516 tcg_gen_rotr_i32(var, var, shift); break;
517 }
518 }
519 dead_tmp(shift);
520 }
521
522 #define PAS_OP(pfx) \
523 switch (op2) { \
524 case 0: gen_pas_helper(glue(pfx,add16)); break; \
525 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
526 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
527 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
528 case 4: gen_pas_helper(glue(pfx,add8)); break; \
529 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
530 }
531 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
532 {
533 TCGv_ptr tmp;
534
535 switch (op1) {
536 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
537 case 1:
538 tmp = tcg_temp_new_ptr();
539 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
540 PAS_OP(s)
541 tcg_temp_free_ptr(tmp);
542 break;
543 case 5:
544 tmp = tcg_temp_new_ptr();
545 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
546 PAS_OP(u)
547 tcg_temp_free_ptr(tmp);
548 break;
549 #undef gen_pas_helper
550 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 case 2:
552 PAS_OP(q);
553 break;
554 case 3:
555 PAS_OP(sh);
556 break;
557 case 6:
558 PAS_OP(uq);
559 break;
560 case 7:
561 PAS_OP(uh);
562 break;
563 #undef gen_pas_helper
564 }
565 }
566 #undef PAS_OP
567
568 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
569 #define PAS_OP(pfx) \
570 switch (op1) { \
571 case 0: gen_pas_helper(glue(pfx,add8)); break; \
572 case 1: gen_pas_helper(glue(pfx,add16)); break; \
573 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
574 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
575 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
576 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
577 }
578 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
579 {
580 TCGv_ptr tmp;
581
582 switch (op2) {
583 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
584 case 0:
585 tmp = tcg_temp_new_ptr();
586 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
587 PAS_OP(s)
588 tcg_temp_free_ptr(tmp);
589 break;
590 case 4:
591 tmp = tcg_temp_new_ptr();
592 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
593 PAS_OP(u)
594 tcg_temp_free_ptr(tmp);
595 break;
596 #undef gen_pas_helper
597 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 case 1:
599 PAS_OP(q);
600 break;
601 case 2:
602 PAS_OP(sh);
603 break;
604 case 5:
605 PAS_OP(uq);
606 break;
607 case 6:
608 PAS_OP(uh);
609 break;
610 #undef gen_pas_helper
611 }
612 }
613 #undef PAS_OP
614
615 static void gen_test_cc(int cc, int label)
616 {
617 TCGv tmp;
618 TCGv tmp2;
619 int inv;
620
621 switch (cc) {
622 case 0: /* eq: Z */
623 tmp = load_cpu_field(ZF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 1: /* ne: !Z */
627 tmp = load_cpu_field(ZF);
628 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
629 break;
630 case 2: /* cs: C */
631 tmp = load_cpu_field(CF);
632 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
633 break;
634 case 3: /* cc: !C */
635 tmp = load_cpu_field(CF);
636 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
637 break;
638 case 4: /* mi: N */
639 tmp = load_cpu_field(NF);
640 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
641 break;
642 case 5: /* pl: !N */
643 tmp = load_cpu_field(NF);
644 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
645 break;
646 case 6: /* vs: V */
647 tmp = load_cpu_field(VF);
648 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
649 break;
650 case 7: /* vc: !V */
651 tmp = load_cpu_field(VF);
652 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
653 break;
654 case 8: /* hi: C && !Z */
655 inv = gen_new_label();
656 tmp = load_cpu_field(CF);
657 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
658 dead_tmp(tmp);
659 tmp = load_cpu_field(ZF);
660 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
661 gen_set_label(inv);
662 break;
663 case 9: /* ls: !C || Z */
664 tmp = load_cpu_field(CF);
665 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
666 dead_tmp(tmp);
667 tmp = load_cpu_field(ZF);
668 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
669 break;
670 case 10: /* ge: N == V -> N ^ V == 0 */
671 tmp = load_cpu_field(VF);
672 tmp2 = load_cpu_field(NF);
673 tcg_gen_xor_i32(tmp, tmp, tmp2);
674 dead_tmp(tmp2);
675 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
676 break;
677 case 11: /* lt: N != V -> N ^ V != 0 */
678 tmp = load_cpu_field(VF);
679 tmp2 = load_cpu_field(NF);
680 tcg_gen_xor_i32(tmp, tmp, tmp2);
681 dead_tmp(tmp2);
682 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
683 break;
684 case 12: /* gt: !Z && N == V */
685 inv = gen_new_label();
686 tmp = load_cpu_field(ZF);
687 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
688 dead_tmp(tmp);
689 tmp = load_cpu_field(VF);
690 tmp2 = load_cpu_field(NF);
691 tcg_gen_xor_i32(tmp, tmp, tmp2);
692 dead_tmp(tmp2);
693 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
694 gen_set_label(inv);
695 break;
696 case 13: /* le: Z || N != V */
697 tmp = load_cpu_field(ZF);
698 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
699 dead_tmp(tmp);
700 tmp = load_cpu_field(VF);
701 tmp2 = load_cpu_field(NF);
702 tcg_gen_xor_i32(tmp, tmp, tmp2);
703 dead_tmp(tmp2);
704 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
705 break;
706 default:
707 fprintf(stderr, "Bad condition code 0x%x\n", cc);
708 abort();
709 }
710 dead_tmp(tmp);
711 }
712
713 static const uint8_t table_logic_cc[16] = {
714 1, /* and */
715 1, /* xor */
716 0, /* sub */
717 0, /* rsb */
718 0, /* add */
719 0, /* adc */
720 0, /* sbc */
721 0, /* rsc */
722 1, /* andl */
723 1, /* xorl */
724 0, /* cmp */
725 0, /* cmn */
726 1, /* orr */
727 1, /* mov */
728 1, /* bic */
729 1, /* mvn */
730 };
731
732 /* Set PC and Thumb state from an immediate address. */
733 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
734 {
735 TCGv tmp;
736
737 s->is_jmp = DISAS_UPDATE;
738 if (s->thumb != (addr & 1)) {
739 tmp = new_tmp();
740 tcg_gen_movi_i32(tmp, addr & 1);
741 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
742 dead_tmp(tmp);
743 }
744 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
745 }
746
747 /* Set PC and Thumb state from var. var is marked as dead. */
748 static inline void gen_bx(DisasContext *s, TCGv var)
749 {
750 s->is_jmp = DISAS_UPDATE;
751 tcg_gen_andi_i32(cpu_R[15], var, ~1);
752 tcg_gen_andi_i32(var, var, 1);
753 store_cpu_field(var, thumb);
754 }
755
756 /* Variant of store_reg which uses branch&exchange logic when storing
757 to r15 in ARM architecture v7 and above. The source must be a temporary
758 and will be marked as dead. */
759 static inline void store_reg_bx(CPUState *env, DisasContext *s,
760 int reg, TCGv var)
761 {
762 if (reg == 15 && ENABLE_ARCH_7) {
763 gen_bx(s, var);
764 } else {
765 store_reg(s, reg, var);
766 }
767 }
768
769 static inline TCGv gen_ld8s(TCGv addr, int index)
770 {
771 TCGv tmp = new_tmp();
772 tcg_gen_qemu_ld8s(tmp, addr, index);
773 return tmp;
774 }
775 static inline TCGv gen_ld8u(TCGv addr, int index)
776 {
777 TCGv tmp = new_tmp();
778 tcg_gen_qemu_ld8u(tmp, addr, index);
779 return tmp;
780 }
781 static inline TCGv gen_ld16s(TCGv addr, int index)
782 {
783 TCGv tmp = new_tmp();
784 tcg_gen_qemu_ld16s(tmp, addr, index);
785 return tmp;
786 }
787 static inline TCGv gen_ld16u(TCGv addr, int index)
788 {
789 TCGv tmp = new_tmp();
790 tcg_gen_qemu_ld16u(tmp, addr, index);
791 return tmp;
792 }
793 static inline TCGv gen_ld32(TCGv addr, int index)
794 {
795 TCGv tmp = new_tmp();
796 tcg_gen_qemu_ld32u(tmp, addr, index);
797 return tmp;
798 }
799 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
800 {
801 TCGv_i64 tmp = tcg_temp_new_i64();
802 tcg_gen_qemu_ld64(tmp, addr, index);
803 return tmp;
804 }
805 static inline void gen_st8(TCGv val, TCGv addr, int index)
806 {
807 tcg_gen_qemu_st8(val, addr, index);
808 dead_tmp(val);
809 }
810 static inline void gen_st16(TCGv val, TCGv addr, int index)
811 {
812 tcg_gen_qemu_st16(val, addr, index);
813 dead_tmp(val);
814 }
815 static inline void gen_st32(TCGv val, TCGv addr, int index)
816 {
817 tcg_gen_qemu_st32(val, addr, index);
818 dead_tmp(val);
819 }
820 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
821 {
822 tcg_gen_qemu_st64(val, addr, index);
823 tcg_temp_free_i64(val);
824 }
825
826 static inline void gen_set_pc_im(uint32_t val)
827 {
828 tcg_gen_movi_i32(cpu_R[15], val);
829 }
830
831 /* Force a TB lookup after an instruction that changes the CPU state. */
832 static inline void gen_lookup_tb(DisasContext *s)
833 {
834 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
835 s->is_jmp = DISAS_UPDATE;
836 }
837
838 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
839 TCGv var)
840 {
841 int val, rm, shift, shiftop;
842 TCGv offset;
843
844 if (!(insn & (1 << 25))) {
845 /* immediate */
846 val = insn & 0xfff;
847 if (!(insn & (1 << 23)))
848 val = -val;
849 if (val != 0)
850 tcg_gen_addi_i32(var, var, val);
851 } else {
852 /* shift/register */
853 rm = (insn) & 0xf;
854 shift = (insn >> 7) & 0x1f;
855 shiftop = (insn >> 5) & 3;
856 offset = load_reg(s, rm);
857 gen_arm_shift_im(offset, shiftop, shift, 0);
858 if (!(insn & (1 << 23)))
859 tcg_gen_sub_i32(var, var, offset);
860 else
861 tcg_gen_add_i32(var, var, offset);
862 dead_tmp(offset);
863 }
864 }
865
866 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
867 int extra, TCGv var)
868 {
869 int val, rm;
870 TCGv offset;
871
872 if (insn & (1 << 22)) {
873 /* immediate */
874 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
875 if (!(insn & (1 << 23)))
876 val = -val;
877 val += extra;
878 if (val != 0)
879 tcg_gen_addi_i32(var, var, val);
880 } else {
881 /* register */
882 if (extra)
883 tcg_gen_addi_i32(var, var, extra);
884 rm = (insn) & 0xf;
885 offset = load_reg(s, rm);
886 if (!(insn & (1 << 23)))
887 tcg_gen_sub_i32(var, var, offset);
888 else
889 tcg_gen_add_i32(var, var, offset);
890 dead_tmp(offset);
891 }
892 }
893
894 #define VFP_OP2(name) \
895 static inline void gen_vfp_##name(int dp) \
896 { \
897 if (dp) \
898 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
899 else \
900 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
901 }
902
903 VFP_OP2(add)
904 VFP_OP2(sub)
905 VFP_OP2(mul)
906 VFP_OP2(div)
907
908 #undef VFP_OP2
909
910 static inline void gen_vfp_abs(int dp)
911 {
912 if (dp)
913 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
914 else
915 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
916 }
917
918 static inline void gen_vfp_neg(int dp)
919 {
920 if (dp)
921 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
922 else
923 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
924 }
925
926 static inline void gen_vfp_sqrt(int dp)
927 {
928 if (dp)
929 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
930 else
931 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
932 }
933
934 static inline void gen_vfp_cmp(int dp)
935 {
936 if (dp)
937 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
938 else
939 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
940 }
941
942 static inline void gen_vfp_cmpe(int dp)
943 {
944 if (dp)
945 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
946 else
947 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
948 }
949
950 static inline void gen_vfp_F1_ld0(int dp)
951 {
952 if (dp)
953 tcg_gen_movi_i64(cpu_F1d, 0);
954 else
955 tcg_gen_movi_i32(cpu_F1s, 0);
956 }
957
958 static inline void gen_vfp_uito(int dp)
959 {
960 if (dp)
961 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
962 else
963 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
964 }
965
966 static inline void gen_vfp_sito(int dp)
967 {
968 if (dp)
969 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
970 else
971 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
972 }
973
974 static inline void gen_vfp_toui(int dp)
975 {
976 if (dp)
977 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
978 else
979 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
980 }
981
982 static inline void gen_vfp_touiz(int dp)
983 {
984 if (dp)
985 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
986 else
987 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
988 }
989
990 static inline void gen_vfp_tosi(int dp)
991 {
992 if (dp)
993 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
994 else
995 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
996 }
997
998 static inline void gen_vfp_tosiz(int dp)
999 {
1000 if (dp)
1001 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1002 else
1003 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1004 }
1005
1006 #define VFP_GEN_FIX(name) \
1007 static inline void gen_vfp_##name(int dp, int shift) \
1008 { \
1009 TCGv tmp_shift = tcg_const_i32(shift); \
1010 if (dp) \
1011 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1012 else \
1013 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1014 tcg_temp_free_i32(tmp_shift); \
1015 }
1016 VFP_GEN_FIX(tosh)
1017 VFP_GEN_FIX(tosl)
1018 VFP_GEN_FIX(touh)
1019 VFP_GEN_FIX(toul)
1020 VFP_GEN_FIX(shto)
1021 VFP_GEN_FIX(slto)
1022 VFP_GEN_FIX(uhto)
1023 VFP_GEN_FIX(ulto)
1024 #undef VFP_GEN_FIX
1025
1026 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1027 {
1028 if (dp)
1029 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1030 else
1031 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1032 }
1033
1034 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1035 {
1036 if (dp)
1037 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1038 else
1039 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1040 }
1041
1042 static inline long
1043 vfp_reg_offset (int dp, int reg)
1044 {
1045 if (dp)
1046 return offsetof(CPUARMState, vfp.regs[reg]);
1047 else if (reg & 1) {
1048 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1049 + offsetof(CPU_DoubleU, l.upper);
1050 } else {
1051 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1052 + offsetof(CPU_DoubleU, l.lower);
1053 }
1054 }
1055
1056 /* Return the offset of a 32-bit piece of a NEON register.
1057 zero is the least significant end of the register. */
1058 static inline long
1059 neon_reg_offset (int reg, int n)
1060 {
1061 int sreg;
1062 sreg = reg * 2 + n;
1063 return vfp_reg_offset(0, sreg);
1064 }
1065
1066 static TCGv neon_load_reg(int reg, int pass)
1067 {
1068 TCGv tmp = new_tmp();
1069 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1070 return tmp;
1071 }
1072
1073 static void neon_store_reg(int reg, int pass, TCGv var)
1074 {
1075 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1076 dead_tmp(var);
1077 }
1078
1079 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1080 {
1081 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1082 }
1083
1084 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1085 {
1086 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1087 }
1088
1089 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1090 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1091 #define tcg_gen_st_f32 tcg_gen_st_i32
1092 #define tcg_gen_st_f64 tcg_gen_st_i64
1093
1094 static inline void gen_mov_F0_vreg(int dp, int reg)
1095 {
1096 if (dp)
1097 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1098 else
1099 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1100 }
1101
1102 static inline void gen_mov_F1_vreg(int dp, int reg)
1103 {
1104 if (dp)
1105 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1106 else
1107 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1108 }
1109
1110 static inline void gen_mov_vreg_F0(int dp, int reg)
1111 {
1112 if (dp)
1113 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1114 else
1115 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1116 }
1117
1118 #define ARM_CP_RW_BIT (1 << 20)
1119
1120 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1121 {
1122 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1123 }
1124
1125 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1126 {
1127 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1128 }
1129
1130 static inline TCGv iwmmxt_load_creg(int reg)
1131 {
1132 TCGv var = new_tmp();
1133 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1134 return var;
1135 }
1136
1137 static inline void iwmmxt_store_creg(int reg, TCGv var)
1138 {
1139 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1140 dead_tmp(var);
1141 }
1142
1143 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1144 {
1145 iwmmxt_store_reg(cpu_M0, rn);
1146 }
1147
1148 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1149 {
1150 iwmmxt_load_reg(cpu_M0, rn);
1151 }
1152
1153 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1154 {
1155 iwmmxt_load_reg(cpu_V1, rn);
1156 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1157 }
1158
1159 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1160 {
1161 iwmmxt_load_reg(cpu_V1, rn);
1162 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1163 }
1164
1165 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1166 {
1167 iwmmxt_load_reg(cpu_V1, rn);
1168 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1169 }
1170
1171 #define IWMMXT_OP(name) \
1172 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1173 { \
1174 iwmmxt_load_reg(cpu_V1, rn); \
1175 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1176 }
1177
1178 #define IWMMXT_OP_ENV(name) \
1179 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1180 { \
1181 iwmmxt_load_reg(cpu_V1, rn); \
1182 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1183 }
1184
1185 #define IWMMXT_OP_ENV_SIZE(name) \
1186 IWMMXT_OP_ENV(name##b) \
1187 IWMMXT_OP_ENV(name##w) \
1188 IWMMXT_OP_ENV(name##l)
1189
1190 #define IWMMXT_OP_ENV1(name) \
1191 static inline void gen_op_iwmmxt_##name##_M0(void) \
1192 { \
1193 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1194 }
1195
1196 IWMMXT_OP(maddsq)
1197 IWMMXT_OP(madduq)
1198 IWMMXT_OP(sadb)
1199 IWMMXT_OP(sadw)
1200 IWMMXT_OP(mulslw)
1201 IWMMXT_OP(mulshw)
1202 IWMMXT_OP(mululw)
1203 IWMMXT_OP(muluhw)
1204 IWMMXT_OP(macsw)
1205 IWMMXT_OP(macuw)
1206
1207 IWMMXT_OP_ENV_SIZE(unpackl)
1208 IWMMXT_OP_ENV_SIZE(unpackh)
1209
1210 IWMMXT_OP_ENV1(unpacklub)
1211 IWMMXT_OP_ENV1(unpackluw)
1212 IWMMXT_OP_ENV1(unpacklul)
1213 IWMMXT_OP_ENV1(unpackhub)
1214 IWMMXT_OP_ENV1(unpackhuw)
1215 IWMMXT_OP_ENV1(unpackhul)
1216 IWMMXT_OP_ENV1(unpacklsb)
1217 IWMMXT_OP_ENV1(unpacklsw)
1218 IWMMXT_OP_ENV1(unpacklsl)
1219 IWMMXT_OP_ENV1(unpackhsb)
1220 IWMMXT_OP_ENV1(unpackhsw)
1221 IWMMXT_OP_ENV1(unpackhsl)
1222
1223 IWMMXT_OP_ENV_SIZE(cmpeq)
1224 IWMMXT_OP_ENV_SIZE(cmpgtu)
1225 IWMMXT_OP_ENV_SIZE(cmpgts)
1226
1227 IWMMXT_OP_ENV_SIZE(mins)
1228 IWMMXT_OP_ENV_SIZE(minu)
1229 IWMMXT_OP_ENV_SIZE(maxs)
1230 IWMMXT_OP_ENV_SIZE(maxu)
1231
1232 IWMMXT_OP_ENV_SIZE(subn)
1233 IWMMXT_OP_ENV_SIZE(addn)
1234 IWMMXT_OP_ENV_SIZE(subu)
1235 IWMMXT_OP_ENV_SIZE(addu)
1236 IWMMXT_OP_ENV_SIZE(subs)
1237 IWMMXT_OP_ENV_SIZE(adds)
1238
1239 IWMMXT_OP_ENV(avgb0)
1240 IWMMXT_OP_ENV(avgb1)
1241 IWMMXT_OP_ENV(avgw0)
1242 IWMMXT_OP_ENV(avgw1)
1243
1244 IWMMXT_OP(msadb)
1245
1246 IWMMXT_OP_ENV(packuw)
1247 IWMMXT_OP_ENV(packul)
1248 IWMMXT_OP_ENV(packuq)
1249 IWMMXT_OP_ENV(packsw)
1250 IWMMXT_OP_ENV(packsl)
1251 IWMMXT_OP_ENV(packsq)
1252
1253 static void gen_op_iwmmxt_set_mup(void)
1254 {
1255 TCGv tmp;
1256 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1257 tcg_gen_ori_i32(tmp, tmp, 2);
1258 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1259 }
1260
1261 static void gen_op_iwmmxt_set_cup(void)
1262 {
1263 TCGv tmp;
1264 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1265 tcg_gen_ori_i32(tmp, tmp, 1);
1266 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1267 }
1268
1269 static void gen_op_iwmmxt_setpsr_nz(void)
1270 {
1271 TCGv tmp = new_tmp();
1272 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1273 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1274 }
1275
1276 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1277 {
1278 iwmmxt_load_reg(cpu_V1, rn);
1279 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1280 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1281 }
1282
1283 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1284 {
1285 int rd;
1286 uint32_t offset;
1287 TCGv tmp;
1288
1289 rd = (insn >> 16) & 0xf;
1290 tmp = load_reg(s, rd);
1291
1292 offset = (insn & 0xff) << ((insn >> 7) & 2);
1293 if (insn & (1 << 24)) {
1294 /* Pre indexed */
1295 if (insn & (1 << 23))
1296 tcg_gen_addi_i32(tmp, tmp, offset);
1297 else
1298 tcg_gen_addi_i32(tmp, tmp, -offset);
1299 tcg_gen_mov_i32(dest, tmp);
1300 if (insn & (1 << 21))
1301 store_reg(s, rd, tmp);
1302 else
1303 dead_tmp(tmp);
1304 } else if (insn & (1 << 21)) {
1305 /* Post indexed */
1306 tcg_gen_mov_i32(dest, tmp);
1307 if (insn & (1 << 23))
1308 tcg_gen_addi_i32(tmp, tmp, offset);
1309 else
1310 tcg_gen_addi_i32(tmp, tmp, -offset);
1311 store_reg(s, rd, tmp);
1312 } else if (!(insn & (1 << 23)))
1313 return 1;
1314 return 0;
1315 }
1316
1317 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1318 {
1319 int rd = (insn >> 0) & 0xf;
1320 TCGv tmp;
1321
1322 if (insn & (1 << 8)) {
1323 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1324 return 1;
1325 } else {
1326 tmp = iwmmxt_load_creg(rd);
1327 }
1328 } else {
1329 tmp = new_tmp();
1330 iwmmxt_load_reg(cpu_V0, rd);
1331 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1332 }
1333 tcg_gen_andi_i32(tmp, tmp, mask);
1334 tcg_gen_mov_i32(dest, tmp);
1335 dead_tmp(tmp);
1336 return 0;
1337 }
1338
1339 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1340 (ie. an undefined instruction). */
1341 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1342 {
1343 int rd, wrd;
1344 int rdhi, rdlo, rd0, rd1, i;
1345 TCGv addr;
1346 TCGv tmp, tmp2, tmp3;
1347
1348 if ((insn & 0x0e000e00) == 0x0c000000) {
1349 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1350 wrd = insn & 0xf;
1351 rdlo = (insn >> 12) & 0xf;
1352 rdhi = (insn >> 16) & 0xf;
1353 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1354 iwmmxt_load_reg(cpu_V0, wrd);
1355 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1356 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1357 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1358 } else { /* TMCRR */
1359 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1360 iwmmxt_store_reg(cpu_V0, wrd);
1361 gen_op_iwmmxt_set_mup();
1362 }
1363 return 0;
1364 }
1365
1366 wrd = (insn >> 12) & 0xf;
1367 addr = new_tmp();
1368 if (gen_iwmmxt_address(s, insn, addr)) {
1369 dead_tmp(addr);
1370 return 1;
1371 }
1372 if (insn & ARM_CP_RW_BIT) {
1373 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1374 tmp = new_tmp();
1375 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1376 iwmmxt_store_creg(wrd, tmp);
1377 } else {
1378 i = 1;
1379 if (insn & (1 << 8)) {
1380 if (insn & (1 << 22)) { /* WLDRD */
1381 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1382 i = 0;
1383 } else { /* WLDRW wRd */
1384 tmp = gen_ld32(addr, IS_USER(s));
1385 }
1386 } else {
1387 if (insn & (1 << 22)) { /* WLDRH */
1388 tmp = gen_ld16u(addr, IS_USER(s));
1389 } else { /* WLDRB */
1390 tmp = gen_ld8u(addr, IS_USER(s));
1391 }
1392 }
1393 if (i) {
1394 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1395 dead_tmp(tmp);
1396 }
1397 gen_op_iwmmxt_movq_wRn_M0(wrd);
1398 }
1399 } else {
1400 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1401 tmp = iwmmxt_load_creg(wrd);
1402 gen_st32(tmp, addr, IS_USER(s));
1403 } else {
1404 gen_op_iwmmxt_movq_M0_wRn(wrd);
1405 tmp = new_tmp();
1406 if (insn & (1 << 8)) {
1407 if (insn & (1 << 22)) { /* WSTRD */
1408 dead_tmp(tmp);
1409 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1410 } else { /* WSTRW wRd */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st32(tmp, addr, IS_USER(s));
1413 }
1414 } else {
1415 if (insn & (1 << 22)) { /* WSTRH */
1416 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1417 gen_st16(tmp, addr, IS_USER(s));
1418 } else { /* WSTRB */
1419 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1420 gen_st8(tmp, addr, IS_USER(s));
1421 }
1422 }
1423 }
1424 }
1425 dead_tmp(addr);
1426 return 0;
1427 }
1428
1429 if ((insn & 0x0f000000) != 0x0e000000)
1430 return 1;
1431
1432 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1433 case 0x000: /* WOR */
1434 wrd = (insn >> 12) & 0xf;
1435 rd0 = (insn >> 0) & 0xf;
1436 rd1 = (insn >> 16) & 0xf;
1437 gen_op_iwmmxt_movq_M0_wRn(rd0);
1438 gen_op_iwmmxt_orq_M0_wRn(rd1);
1439 gen_op_iwmmxt_setpsr_nz();
1440 gen_op_iwmmxt_movq_wRn_M0(wrd);
1441 gen_op_iwmmxt_set_mup();
1442 gen_op_iwmmxt_set_cup();
1443 break;
1444 case 0x011: /* TMCR */
1445 if (insn & 0xf)
1446 return 1;
1447 rd = (insn >> 12) & 0xf;
1448 wrd = (insn >> 16) & 0xf;
1449 switch (wrd) {
1450 case ARM_IWMMXT_wCID:
1451 case ARM_IWMMXT_wCASF:
1452 break;
1453 case ARM_IWMMXT_wCon:
1454 gen_op_iwmmxt_set_cup();
1455 /* Fall through. */
1456 case ARM_IWMMXT_wCSSF:
1457 tmp = iwmmxt_load_creg(wrd);
1458 tmp2 = load_reg(s, rd);
1459 tcg_gen_andc_i32(tmp, tmp, tmp2);
1460 dead_tmp(tmp2);
1461 iwmmxt_store_creg(wrd, tmp);
1462 break;
1463 case ARM_IWMMXT_wCGR0:
1464 case ARM_IWMMXT_wCGR1:
1465 case ARM_IWMMXT_wCGR2:
1466 case ARM_IWMMXT_wCGR3:
1467 gen_op_iwmmxt_set_cup();
1468 tmp = load_reg(s, rd);
1469 iwmmxt_store_creg(wrd, tmp);
1470 break;
1471 default:
1472 return 1;
1473 }
1474 break;
1475 case 0x100: /* WXOR */
1476 wrd = (insn >> 12) & 0xf;
1477 rd0 = (insn >> 0) & 0xf;
1478 rd1 = (insn >> 16) & 0xf;
1479 gen_op_iwmmxt_movq_M0_wRn(rd0);
1480 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1481 gen_op_iwmmxt_setpsr_nz();
1482 gen_op_iwmmxt_movq_wRn_M0(wrd);
1483 gen_op_iwmmxt_set_mup();
1484 gen_op_iwmmxt_set_cup();
1485 break;
1486 case 0x111: /* TMRC */
1487 if (insn & 0xf)
1488 return 1;
1489 rd = (insn >> 12) & 0xf;
1490 wrd = (insn >> 16) & 0xf;
1491 tmp = iwmmxt_load_creg(wrd);
1492 store_reg(s, rd, tmp);
1493 break;
1494 case 0x300: /* WANDN */
1495 wrd = (insn >> 12) & 0xf;
1496 rd0 = (insn >> 0) & 0xf;
1497 rd1 = (insn >> 16) & 0xf;
1498 gen_op_iwmmxt_movq_M0_wRn(rd0);
1499 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1500 gen_op_iwmmxt_andq_M0_wRn(rd1);
1501 gen_op_iwmmxt_setpsr_nz();
1502 gen_op_iwmmxt_movq_wRn_M0(wrd);
1503 gen_op_iwmmxt_set_mup();
1504 gen_op_iwmmxt_set_cup();
1505 break;
1506 case 0x200: /* WAND */
1507 wrd = (insn >> 12) & 0xf;
1508 rd0 = (insn >> 0) & 0xf;
1509 rd1 = (insn >> 16) & 0xf;
1510 gen_op_iwmmxt_movq_M0_wRn(rd0);
1511 gen_op_iwmmxt_andq_M0_wRn(rd1);
1512 gen_op_iwmmxt_setpsr_nz();
1513 gen_op_iwmmxt_movq_wRn_M0(wrd);
1514 gen_op_iwmmxt_set_mup();
1515 gen_op_iwmmxt_set_cup();
1516 break;
1517 case 0x810: case 0xa10: /* WMADD */
1518 wrd = (insn >> 12) & 0xf;
1519 rd0 = (insn >> 0) & 0xf;
1520 rd1 = (insn >> 16) & 0xf;
1521 gen_op_iwmmxt_movq_M0_wRn(rd0);
1522 if (insn & (1 << 21))
1523 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1524 else
1525 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1526 gen_op_iwmmxt_movq_wRn_M0(wrd);
1527 gen_op_iwmmxt_set_mup();
1528 break;
1529 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1530 wrd = (insn >> 12) & 0xf;
1531 rd0 = (insn >> 16) & 0xf;
1532 rd1 = (insn >> 0) & 0xf;
1533 gen_op_iwmmxt_movq_M0_wRn(rd0);
1534 switch ((insn >> 22) & 3) {
1535 case 0:
1536 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1537 break;
1538 case 1:
1539 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1540 break;
1541 case 2:
1542 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1543 break;
1544 case 3:
1545 return 1;
1546 }
1547 gen_op_iwmmxt_movq_wRn_M0(wrd);
1548 gen_op_iwmmxt_set_mup();
1549 gen_op_iwmmxt_set_cup();
1550 break;
1551 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1552 wrd = (insn >> 12) & 0xf;
1553 rd0 = (insn >> 16) & 0xf;
1554 rd1 = (insn >> 0) & 0xf;
1555 gen_op_iwmmxt_movq_M0_wRn(rd0);
1556 switch ((insn >> 22) & 3) {
1557 case 0:
1558 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1559 break;
1560 case 1:
1561 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1562 break;
1563 case 2:
1564 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1565 break;
1566 case 3:
1567 return 1;
1568 }
1569 gen_op_iwmmxt_movq_wRn_M0(wrd);
1570 gen_op_iwmmxt_set_mup();
1571 gen_op_iwmmxt_set_cup();
1572 break;
1573 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1574 wrd = (insn >> 12) & 0xf;
1575 rd0 = (insn >> 16) & 0xf;
1576 rd1 = (insn >> 0) & 0xf;
1577 gen_op_iwmmxt_movq_M0_wRn(rd0);
1578 if (insn & (1 << 22))
1579 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1580 else
1581 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1582 if (!(insn & (1 << 20)))
1583 gen_op_iwmmxt_addl_M0_wRn(wrd);
1584 gen_op_iwmmxt_movq_wRn_M0(wrd);
1585 gen_op_iwmmxt_set_mup();
1586 break;
1587 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1588 wrd = (insn >> 12) & 0xf;
1589 rd0 = (insn >> 16) & 0xf;
1590 rd1 = (insn >> 0) & 0xf;
1591 gen_op_iwmmxt_movq_M0_wRn(rd0);
1592 if (insn & (1 << 21)) {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1597 } else {
1598 if (insn & (1 << 20))
1599 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1600 else
1601 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1602 }
1603 gen_op_iwmmxt_movq_wRn_M0(wrd);
1604 gen_op_iwmmxt_set_mup();
1605 break;
1606 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1607 wrd = (insn >> 12) & 0xf;
1608 rd0 = (insn >> 16) & 0xf;
1609 rd1 = (insn >> 0) & 0xf;
1610 gen_op_iwmmxt_movq_M0_wRn(rd0);
1611 if (insn & (1 << 21))
1612 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1613 else
1614 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1615 if (!(insn & (1 << 20))) {
1616 iwmmxt_load_reg(cpu_V1, wrd);
1617 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1618 }
1619 gen_op_iwmmxt_movq_wRn_M0(wrd);
1620 gen_op_iwmmxt_set_mup();
1621 break;
1622 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1623 wrd = (insn >> 12) & 0xf;
1624 rd0 = (insn >> 16) & 0xf;
1625 rd1 = (insn >> 0) & 0xf;
1626 gen_op_iwmmxt_movq_M0_wRn(rd0);
1627 switch ((insn >> 22) & 3) {
1628 case 0:
1629 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1630 break;
1631 case 1:
1632 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1633 break;
1634 case 2:
1635 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1636 break;
1637 case 3:
1638 return 1;
1639 }
1640 gen_op_iwmmxt_movq_wRn_M0(wrd);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1643 break;
1644 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1645 wrd = (insn >> 12) & 0xf;
1646 rd0 = (insn >> 16) & 0xf;
1647 rd1 = (insn >> 0) & 0xf;
1648 gen_op_iwmmxt_movq_M0_wRn(rd0);
1649 if (insn & (1 << 22)) {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1654 } else {
1655 if (insn & (1 << 20))
1656 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1657 else
1658 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1659 }
1660 gen_op_iwmmxt_movq_wRn_M0(wrd);
1661 gen_op_iwmmxt_set_mup();
1662 gen_op_iwmmxt_set_cup();
1663 break;
1664 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1665 wrd = (insn >> 12) & 0xf;
1666 rd0 = (insn >> 16) & 0xf;
1667 rd1 = (insn >> 0) & 0xf;
1668 gen_op_iwmmxt_movq_M0_wRn(rd0);
1669 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1670 tcg_gen_andi_i32(tmp, tmp, 7);
1671 iwmmxt_load_reg(cpu_V1, rd1);
1672 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1673 dead_tmp(tmp);
1674 gen_op_iwmmxt_movq_wRn_M0(wrd);
1675 gen_op_iwmmxt_set_mup();
1676 break;
1677 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1678 if (((insn >> 6) & 3) == 3)
1679 return 1;
1680 rd = (insn >> 12) & 0xf;
1681 wrd = (insn >> 16) & 0xf;
1682 tmp = load_reg(s, rd);
1683 gen_op_iwmmxt_movq_M0_wRn(wrd);
1684 switch ((insn >> 6) & 3) {
1685 case 0:
1686 tmp2 = tcg_const_i32(0xff);
1687 tmp3 = tcg_const_i32((insn & 7) << 3);
1688 break;
1689 case 1:
1690 tmp2 = tcg_const_i32(0xffff);
1691 tmp3 = tcg_const_i32((insn & 3) << 4);
1692 break;
1693 case 2:
1694 tmp2 = tcg_const_i32(0xffffffff);
1695 tmp3 = tcg_const_i32((insn & 1) << 5);
1696 break;
1697 default:
1698 TCGV_UNUSED(tmp2);
1699 TCGV_UNUSED(tmp3);
1700 }
1701 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1702 tcg_temp_free(tmp3);
1703 tcg_temp_free(tmp2);
1704 dead_tmp(tmp);
1705 gen_op_iwmmxt_movq_wRn_M0(wrd);
1706 gen_op_iwmmxt_set_mup();
1707 break;
1708 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1709 rd = (insn >> 12) & 0xf;
1710 wrd = (insn >> 16) & 0xf;
1711 if (rd == 15 || ((insn >> 22) & 3) == 3)
1712 return 1;
1713 gen_op_iwmmxt_movq_M0_wRn(wrd);
1714 tmp = new_tmp();
1715 switch ((insn >> 22) & 3) {
1716 case 0:
1717 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1718 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1719 if (insn & 8) {
1720 tcg_gen_ext8s_i32(tmp, tmp);
1721 } else {
1722 tcg_gen_andi_i32(tmp, tmp, 0xff);
1723 }
1724 break;
1725 case 1:
1726 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1727 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1728 if (insn & 8) {
1729 tcg_gen_ext16s_i32(tmp, tmp);
1730 } else {
1731 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1732 }
1733 break;
1734 case 2:
1735 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1736 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1737 break;
1738 }
1739 store_reg(s, rd, tmp);
1740 break;
1741 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1742 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1743 return 1;
1744 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1745 switch ((insn >> 22) & 3) {
1746 case 0:
1747 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1748 break;
1749 case 1:
1750 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1751 break;
1752 case 2:
1753 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1754 break;
1755 }
1756 tcg_gen_shli_i32(tmp, tmp, 28);
1757 gen_set_nzcv(tmp);
1758 dead_tmp(tmp);
1759 break;
1760 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1761 if (((insn >> 6) & 3) == 3)
1762 return 1;
1763 rd = (insn >> 12) & 0xf;
1764 wrd = (insn >> 16) & 0xf;
1765 tmp = load_reg(s, rd);
1766 switch ((insn >> 6) & 3) {
1767 case 0:
1768 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1769 break;
1770 case 1:
1771 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1772 break;
1773 case 2:
1774 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1775 break;
1776 }
1777 dead_tmp(tmp);
1778 gen_op_iwmmxt_movq_wRn_M0(wrd);
1779 gen_op_iwmmxt_set_mup();
1780 break;
1781 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1782 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1783 return 1;
1784 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1785 tmp2 = new_tmp();
1786 tcg_gen_mov_i32(tmp2, tmp);
1787 switch ((insn >> 22) & 3) {
1788 case 0:
1789 for (i = 0; i < 7; i ++) {
1790 tcg_gen_shli_i32(tmp2, tmp2, 4);
1791 tcg_gen_and_i32(tmp, tmp, tmp2);
1792 }
1793 break;
1794 case 1:
1795 for (i = 0; i < 3; i ++) {
1796 tcg_gen_shli_i32(tmp2, tmp2, 8);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 }
1799 break;
1800 case 2:
1801 tcg_gen_shli_i32(tmp2, tmp2, 16);
1802 tcg_gen_and_i32(tmp, tmp, tmp2);
1803 break;
1804 }
1805 gen_set_nzcv(tmp);
1806 dead_tmp(tmp2);
1807 dead_tmp(tmp);
1808 break;
1809 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1810 wrd = (insn >> 12) & 0xf;
1811 rd0 = (insn >> 16) & 0xf;
1812 gen_op_iwmmxt_movq_M0_wRn(rd0);
1813 switch ((insn >> 22) & 3) {
1814 case 0:
1815 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1816 break;
1817 case 1:
1818 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1819 break;
1820 case 2:
1821 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1822 break;
1823 case 3:
1824 return 1;
1825 }
1826 gen_op_iwmmxt_movq_wRn_M0(wrd);
1827 gen_op_iwmmxt_set_mup();
1828 break;
1829 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1830 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1831 return 1;
1832 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1833 tmp2 = new_tmp();
1834 tcg_gen_mov_i32(tmp2, tmp);
1835 switch ((insn >> 22) & 3) {
1836 case 0:
1837 for (i = 0; i < 7; i ++) {
1838 tcg_gen_shli_i32(tmp2, tmp2, 4);
1839 tcg_gen_or_i32(tmp, tmp, tmp2);
1840 }
1841 break;
1842 case 1:
1843 for (i = 0; i < 3; i ++) {
1844 tcg_gen_shli_i32(tmp2, tmp2, 8);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 }
1847 break;
1848 case 2:
1849 tcg_gen_shli_i32(tmp2, tmp2, 16);
1850 tcg_gen_or_i32(tmp, tmp, tmp2);
1851 break;
1852 }
1853 gen_set_nzcv(tmp);
1854 dead_tmp(tmp2);
1855 dead_tmp(tmp);
1856 break;
1857 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1858 rd = (insn >> 12) & 0xf;
1859 rd0 = (insn >> 16) & 0xf;
1860 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1861 return 1;
1862 gen_op_iwmmxt_movq_M0_wRn(rd0);
1863 tmp = new_tmp();
1864 switch ((insn >> 22) & 3) {
1865 case 0:
1866 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1867 break;
1868 case 1:
1869 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1870 break;
1871 case 2:
1872 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1873 break;
1874 }
1875 store_reg(s, rd, tmp);
1876 break;
1877 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1878 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1879 wrd = (insn >> 12) & 0xf;
1880 rd0 = (insn >> 16) & 0xf;
1881 rd1 = (insn >> 0) & 0xf;
1882 gen_op_iwmmxt_movq_M0_wRn(rd0);
1883 switch ((insn >> 22) & 3) {
1884 case 0:
1885 if (insn & (1 << 21))
1886 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1887 else
1888 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1889 break;
1890 case 1:
1891 if (insn & (1 << 21))
1892 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1893 else
1894 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1895 break;
1896 case 2:
1897 if (insn & (1 << 21))
1898 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1899 else
1900 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1901 break;
1902 case 3:
1903 return 1;
1904 }
1905 gen_op_iwmmxt_movq_wRn_M0(wrd);
1906 gen_op_iwmmxt_set_mup();
1907 gen_op_iwmmxt_set_cup();
1908 break;
1909 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1910 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1911 wrd = (insn >> 12) & 0xf;
1912 rd0 = (insn >> 16) & 0xf;
1913 gen_op_iwmmxt_movq_M0_wRn(rd0);
1914 switch ((insn >> 22) & 3) {
1915 case 0:
1916 if (insn & (1 << 21))
1917 gen_op_iwmmxt_unpacklsb_M0();
1918 else
1919 gen_op_iwmmxt_unpacklub_M0();
1920 break;
1921 case 1:
1922 if (insn & (1 << 21))
1923 gen_op_iwmmxt_unpacklsw_M0();
1924 else
1925 gen_op_iwmmxt_unpackluw_M0();
1926 break;
1927 case 2:
1928 if (insn & (1 << 21))
1929 gen_op_iwmmxt_unpacklsl_M0();
1930 else
1931 gen_op_iwmmxt_unpacklul_M0();
1932 break;
1933 case 3:
1934 return 1;
1935 }
1936 gen_op_iwmmxt_movq_wRn_M0(wrd);
1937 gen_op_iwmmxt_set_mup();
1938 gen_op_iwmmxt_set_cup();
1939 break;
1940 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1941 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1942 wrd = (insn >> 12) & 0xf;
1943 rd0 = (insn >> 16) & 0xf;
1944 gen_op_iwmmxt_movq_M0_wRn(rd0);
1945 switch ((insn >> 22) & 3) {
1946 case 0:
1947 if (insn & (1 << 21))
1948 gen_op_iwmmxt_unpackhsb_M0();
1949 else
1950 gen_op_iwmmxt_unpackhub_M0();
1951 break;
1952 case 1:
1953 if (insn & (1 << 21))
1954 gen_op_iwmmxt_unpackhsw_M0();
1955 else
1956 gen_op_iwmmxt_unpackhuw_M0();
1957 break;
1958 case 2:
1959 if (insn & (1 << 21))
1960 gen_op_iwmmxt_unpackhsl_M0();
1961 else
1962 gen_op_iwmmxt_unpackhul_M0();
1963 break;
1964 case 3:
1965 return 1;
1966 }
1967 gen_op_iwmmxt_movq_wRn_M0(wrd);
1968 gen_op_iwmmxt_set_mup();
1969 gen_op_iwmmxt_set_cup();
1970 break;
1971 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1972 case 0x214: case 0x614: case 0xa14: case 0xe14:
1973 if (((insn >> 22) & 3) == 0)
1974 return 1;
1975 wrd = (insn >> 12) & 0xf;
1976 rd0 = (insn >> 16) & 0xf;
1977 gen_op_iwmmxt_movq_M0_wRn(rd0);
1978 tmp = new_tmp();
1979 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1980 dead_tmp(tmp);
1981 return 1;
1982 }
1983 switch ((insn >> 22) & 3) {
1984 case 1:
1985 gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp);
1986 break;
1987 case 2:
1988 gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp);
1989 break;
1990 case 3:
1991 gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp);
1992 break;
1993 }
1994 dead_tmp(tmp);
1995 gen_op_iwmmxt_movq_wRn_M0(wrd);
1996 gen_op_iwmmxt_set_mup();
1997 gen_op_iwmmxt_set_cup();
1998 break;
1999 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2000 case 0x014: case 0x414: case 0x814: case 0xc14:
2001 if (((insn >> 22) & 3) == 0)
2002 return 1;
2003 wrd = (insn >> 12) & 0xf;
2004 rd0 = (insn >> 16) & 0xf;
2005 gen_op_iwmmxt_movq_M0_wRn(rd0);
2006 tmp = new_tmp();
2007 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2008 dead_tmp(tmp);
2009 return 1;
2010 }
2011 switch ((insn >> 22) & 3) {
2012 case 1:
2013 gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp);
2014 break;
2015 case 2:
2016 gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp);
2017 break;
2018 case 3:
2019 gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp);
2020 break;
2021 }
2022 dead_tmp(tmp);
2023 gen_op_iwmmxt_movq_wRn_M0(wrd);
2024 gen_op_iwmmxt_set_mup();
2025 gen_op_iwmmxt_set_cup();
2026 break;
2027 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2028 case 0x114: case 0x514: case 0x914: case 0xd14:
2029 if (((insn >> 22) & 3) == 0)
2030 return 1;
2031 wrd = (insn >> 12) & 0xf;
2032 rd0 = (insn >> 16) & 0xf;
2033 gen_op_iwmmxt_movq_M0_wRn(rd0);
2034 tmp = new_tmp();
2035 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2036 dead_tmp(tmp);
2037 return 1;
2038 }
2039 switch ((insn >> 22) & 3) {
2040 case 1:
2041 gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp);
2042 break;
2043 case 2:
2044 gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp);
2045 break;
2046 case 3:
2047 gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp);
2048 break;
2049 }
2050 dead_tmp(tmp);
2051 gen_op_iwmmxt_movq_wRn_M0(wrd);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2054 break;
2055 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2056 case 0x314: case 0x714: case 0xb14: case 0xf14:
2057 if (((insn >> 22) & 3) == 0)
2058 return 1;
2059 wrd = (insn >> 12) & 0xf;
2060 rd0 = (insn >> 16) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0);
2062 tmp = new_tmp();
2063 switch ((insn >> 22) & 3) {
2064 case 1:
2065 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2066 dead_tmp(tmp);
2067 return 1;
2068 }
2069 gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp);
2070 break;
2071 case 2:
2072 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2073 dead_tmp(tmp);
2074 return 1;
2075 }
2076 gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp);
2077 break;
2078 case 3:
2079 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2080 dead_tmp(tmp);
2081 return 1;
2082 }
2083 gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp);
2084 break;
2085 }
2086 dead_tmp(tmp);
2087 gen_op_iwmmxt_movq_wRn_M0(wrd);
2088 gen_op_iwmmxt_set_mup();
2089 gen_op_iwmmxt_set_cup();
2090 break;
2091 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2092 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2093 wrd = (insn >> 12) & 0xf;
2094 rd0 = (insn >> 16) & 0xf;
2095 rd1 = (insn >> 0) & 0xf;
2096 gen_op_iwmmxt_movq_M0_wRn(rd0);
2097 switch ((insn >> 22) & 3) {
2098 case 0:
2099 if (insn & (1 << 21))
2100 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2101 else
2102 gen_op_iwmmxt_minub_M0_wRn(rd1);
2103 break;
2104 case 1:
2105 if (insn & (1 << 21))
2106 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2107 else
2108 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2109 break;
2110 case 2:
2111 if (insn & (1 << 21))
2112 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2113 else
2114 gen_op_iwmmxt_minul_M0_wRn(rd1);
2115 break;
2116 case 3:
2117 return 1;
2118 }
2119 gen_op_iwmmxt_movq_wRn_M0(wrd);
2120 gen_op_iwmmxt_set_mup();
2121 break;
2122 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2123 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2124 wrd = (insn >> 12) & 0xf;
2125 rd0 = (insn >> 16) & 0xf;
2126 rd1 = (insn >> 0) & 0xf;
2127 gen_op_iwmmxt_movq_M0_wRn(rd0);
2128 switch ((insn >> 22) & 3) {
2129 case 0:
2130 if (insn & (1 << 21))
2131 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2132 else
2133 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2134 break;
2135 case 1:
2136 if (insn & (1 << 21))
2137 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2138 else
2139 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2140 break;
2141 case 2:
2142 if (insn & (1 << 21))
2143 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2144 else
2145 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2146 break;
2147 case 3:
2148 return 1;
2149 }
2150 gen_op_iwmmxt_movq_wRn_M0(wrd);
2151 gen_op_iwmmxt_set_mup();
2152 break;
2153 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2154 case 0x402: case 0x502: case 0x602: case 0x702:
2155 wrd = (insn >> 12) & 0xf;
2156 rd0 = (insn >> 16) & 0xf;
2157 rd1 = (insn >> 0) & 0xf;
2158 gen_op_iwmmxt_movq_M0_wRn(rd0);
2159 tmp = tcg_const_i32((insn >> 20) & 3);
2160 iwmmxt_load_reg(cpu_V1, rd1);
2161 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2162 tcg_temp_free(tmp);
2163 gen_op_iwmmxt_movq_wRn_M0(wrd);
2164 gen_op_iwmmxt_set_mup();
2165 break;
2166 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2167 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2168 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2169 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2170 wrd = (insn >> 12) & 0xf;
2171 rd0 = (insn >> 16) & 0xf;
2172 rd1 = (insn >> 0) & 0xf;
2173 gen_op_iwmmxt_movq_M0_wRn(rd0);
2174 switch ((insn >> 20) & 0xf) {
2175 case 0x0:
2176 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2177 break;
2178 case 0x1:
2179 gen_op_iwmmxt_subub_M0_wRn(rd1);
2180 break;
2181 case 0x3:
2182 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2183 break;
2184 case 0x4:
2185 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2186 break;
2187 case 0x5:
2188 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2189 break;
2190 case 0x7:
2191 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2192 break;
2193 case 0x8:
2194 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2195 break;
2196 case 0x9:
2197 gen_op_iwmmxt_subul_M0_wRn(rd1);
2198 break;
2199 case 0xb:
2200 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2201 break;
2202 default:
2203 return 1;
2204 }
2205 gen_op_iwmmxt_movq_wRn_M0(wrd);
2206 gen_op_iwmmxt_set_mup();
2207 gen_op_iwmmxt_set_cup();
2208 break;
2209 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2210 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2211 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2212 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2213 wrd = (insn >> 12) & 0xf;
2214 rd0 = (insn >> 16) & 0xf;
2215 gen_op_iwmmxt_movq_M0_wRn(rd0);
2216 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2217 gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp);
2218 tcg_temp_free(tmp);
2219 gen_op_iwmmxt_movq_wRn_M0(wrd);
2220 gen_op_iwmmxt_set_mup();
2221 gen_op_iwmmxt_set_cup();
2222 break;
2223 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2224 case 0x418: case 0x518: case 0x618: case 0x718:
2225 case 0x818: case 0x918: case 0xa18: case 0xb18:
2226 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2227 wrd = (insn >> 12) & 0xf;
2228 rd0 = (insn >> 16) & 0xf;
2229 rd1 = (insn >> 0) & 0xf;
2230 gen_op_iwmmxt_movq_M0_wRn(rd0);
2231 switch ((insn >> 20) & 0xf) {
2232 case 0x0:
2233 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2234 break;
2235 case 0x1:
2236 gen_op_iwmmxt_addub_M0_wRn(rd1);
2237 break;
2238 case 0x3:
2239 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2240 break;
2241 case 0x4:
2242 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2243 break;
2244 case 0x5:
2245 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2246 break;
2247 case 0x7:
2248 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2249 break;
2250 case 0x8:
2251 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2252 break;
2253 case 0x9:
2254 gen_op_iwmmxt_addul_M0_wRn(rd1);
2255 break;
2256 case 0xb:
2257 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2258 break;
2259 default:
2260 return 1;
2261 }
2262 gen_op_iwmmxt_movq_wRn_M0(wrd);
2263 gen_op_iwmmxt_set_mup();
2264 gen_op_iwmmxt_set_cup();
2265 break;
2266 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2267 case 0x408: case 0x508: case 0x608: case 0x708:
2268 case 0x808: case 0x908: case 0xa08: case 0xb08:
2269 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2270 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2271 return 1;
2272 wrd = (insn >> 12) & 0xf;
2273 rd0 = (insn >> 16) & 0xf;
2274 rd1 = (insn >> 0) & 0xf;
2275 gen_op_iwmmxt_movq_M0_wRn(rd0);
2276 switch ((insn >> 22) & 3) {
2277 case 1:
2278 if (insn & (1 << 21))
2279 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2280 else
2281 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2282 break;
2283 case 2:
2284 if (insn & (1 << 21))
2285 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2286 else
2287 gen_op_iwmmxt_packul_M0_wRn(rd1);
2288 break;
2289 case 3:
2290 if (insn & (1 << 21))
2291 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2292 else
2293 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2294 break;
2295 }
2296 gen_op_iwmmxt_movq_wRn_M0(wrd);
2297 gen_op_iwmmxt_set_mup();
2298 gen_op_iwmmxt_set_cup();
2299 break;
2300 case 0x201: case 0x203: case 0x205: case 0x207:
2301 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2302 case 0x211: case 0x213: case 0x215: case 0x217:
2303 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2304 wrd = (insn >> 5) & 0xf;
2305 rd0 = (insn >> 12) & 0xf;
2306 rd1 = (insn >> 0) & 0xf;
2307 if (rd0 == 0xf || rd1 == 0xf)
2308 return 1;
2309 gen_op_iwmmxt_movq_M0_wRn(wrd);
2310 tmp = load_reg(s, rd0);
2311 tmp2 = load_reg(s, rd1);
2312 switch ((insn >> 16) & 0xf) {
2313 case 0x0: /* TMIA */
2314 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2315 break;
2316 case 0x8: /* TMIAPH */
2317 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2318 break;
2319 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2320 if (insn & (1 << 16))
2321 tcg_gen_shri_i32(tmp, tmp, 16);
2322 if (insn & (1 << 17))
2323 tcg_gen_shri_i32(tmp2, tmp2, 16);
2324 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2325 break;
2326 default:
2327 dead_tmp(tmp2);
2328 dead_tmp(tmp);
2329 return 1;
2330 }
2331 dead_tmp(tmp2);
2332 dead_tmp(tmp);
2333 gen_op_iwmmxt_movq_wRn_M0(wrd);
2334 gen_op_iwmmxt_set_mup();
2335 break;
2336 default:
2337 return 1;
2338 }
2339
2340 return 0;
2341 }
2342
2343 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2344 (ie. an undefined instruction). */
2345 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2346 {
2347 int acc, rd0, rd1, rdhi, rdlo;
2348 TCGv tmp, tmp2;
2349
2350 if ((insn & 0x0ff00f10) == 0x0e200010) {
2351 /* Multiply with Internal Accumulate Format */
2352 rd0 = (insn >> 12) & 0xf;
2353 rd1 = insn & 0xf;
2354 acc = (insn >> 5) & 7;
2355
2356 if (acc != 0)
2357 return 1;
2358
2359 tmp = load_reg(s, rd0);
2360 tmp2 = load_reg(s, rd1);
2361 switch ((insn >> 16) & 0xf) {
2362 case 0x0: /* MIA */
2363 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2364 break;
2365 case 0x8: /* MIAPH */
2366 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2367 break;
2368 case 0xc: /* MIABB */
2369 case 0xd: /* MIABT */
2370 case 0xe: /* MIATB */
2371 case 0xf: /* MIATT */
2372 if (insn & (1 << 16))
2373 tcg_gen_shri_i32(tmp, tmp, 16);
2374 if (insn & (1 << 17))
2375 tcg_gen_shri_i32(tmp2, tmp2, 16);
2376 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2377 break;
2378 default:
2379 return 1;
2380 }
2381 dead_tmp(tmp2);
2382 dead_tmp(tmp);
2383
2384 gen_op_iwmmxt_movq_wRn_M0(acc);
2385 return 0;
2386 }
2387
2388 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2389 /* Internal Accumulator Access Format */
2390 rdhi = (insn >> 16) & 0xf;
2391 rdlo = (insn >> 12) & 0xf;
2392 acc = insn & 7;
2393
2394 if (acc != 0)
2395 return 1;
2396
2397 if (insn & ARM_CP_RW_BIT) { /* MRA */
2398 iwmmxt_load_reg(cpu_V0, acc);
2399 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2400 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2401 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2402 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2403 } else { /* MAR */
2404 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2405 iwmmxt_store_reg(cpu_V0, acc);
2406 }
2407 return 0;
2408 }
2409
2410 return 1;
2411 }
2412
2413 /* Disassemble system coprocessor instruction. Return nonzero if
2414 instruction is not defined. */
2415 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2416 {
2417 TCGv tmp, tmp2;
2418 uint32_t rd = (insn >> 12) & 0xf;
2419 uint32_t cp = (insn >> 8) & 0xf;
2420 if (IS_USER(s)) {
2421 return 1;
2422 }
2423
2424 if (insn & ARM_CP_RW_BIT) {
2425 if (!env->cp[cp].cp_read)
2426 return 1;
2427 gen_set_pc_im(s->pc);
2428 tmp = new_tmp();
2429 tmp2 = tcg_const_i32(insn);
2430 gen_helper_get_cp(tmp, cpu_env, tmp2);
2431 tcg_temp_free(tmp2);
2432 store_reg(s, rd, tmp);
2433 } else {
2434 if (!env->cp[cp].cp_write)
2435 return 1;
2436 gen_set_pc_im(s->pc);
2437 tmp = load_reg(s, rd);
2438 tmp2 = tcg_const_i32(insn);
2439 gen_helper_set_cp(cpu_env, tmp2, tmp);
2440 tcg_temp_free(tmp2);
2441 dead_tmp(tmp);
2442 }
2443 return 0;
2444 }
2445
2446 static int cp15_user_ok(uint32_t insn)
2447 {
2448 int cpn = (insn >> 16) & 0xf;
2449 int cpm = insn & 0xf;
2450 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2451
2452 if (cpn == 13 && cpm == 0) {
2453 /* TLS register. */
2454 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2455 return 1;
2456 }
2457 if (cpn == 7) {
2458 /* ISB, DSB, DMB. */
2459 if ((cpm == 5 && op == 4)
2460 || (cpm == 10 && (op == 4 || op == 5)))
2461 return 1;
2462 }
2463 return 0;
2464 }
2465
2466 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2467 {
2468 TCGv tmp;
2469 int cpn = (insn >> 16) & 0xf;
2470 int cpm = insn & 0xf;
2471 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2472
2473 if (!arm_feature(env, ARM_FEATURE_V6K))
2474 return 0;
2475
2476 if (!(cpn == 13 && cpm == 0))
2477 return 0;
2478
2479 if (insn & ARM_CP_RW_BIT) {
2480 switch (op) {
2481 case 2:
2482 tmp = load_cpu_field(cp15.c13_tls1);
2483 break;
2484 case 3:
2485 tmp = load_cpu_field(cp15.c13_tls2);
2486 break;
2487 case 4:
2488 tmp = load_cpu_field(cp15.c13_tls3);
2489 break;
2490 default:
2491 return 0;
2492 }
2493 store_reg(s, rd, tmp);
2494
2495 } else {
2496 tmp = load_reg(s, rd);
2497 switch (op) {
2498 case 2:
2499 store_cpu_field(tmp, cp15.c13_tls1);
2500 break;
2501 case 3:
2502 store_cpu_field(tmp, cp15.c13_tls2);
2503 break;
2504 case 4:
2505 store_cpu_field(tmp, cp15.c13_tls3);
2506 break;
2507 default:
2508 dead_tmp(tmp);
2509 return 0;
2510 }
2511 }
2512 return 1;
2513 }
2514
2515 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2516 instruction is not defined. */
2517 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2518 {
2519 uint32_t rd;
2520 TCGv tmp, tmp2;
2521
2522 /* M profile cores use memory mapped registers instead of cp15. */
2523 if (arm_feature(env, ARM_FEATURE_M))
2524 return 1;
2525
2526 if ((insn & (1 << 25)) == 0) {
2527 if (insn & (1 << 20)) {
2528 /* mrrc */
2529 return 1;
2530 }
2531 /* mcrr. Used for block cache operations, so implement as no-op. */
2532 return 0;
2533 }
2534 if ((insn & (1 << 4)) == 0) {
2535 /* cdp */
2536 return 1;
2537 }
2538 if (IS_USER(s) && !cp15_user_ok(insn)) {
2539 return 1;
2540 }
2541 if ((insn & 0x0fff0fff) == 0x0e070f90
2542 || (insn & 0x0fff0fff) == 0x0e070f58) {
2543 /* Wait for interrupt. */
2544 gen_set_pc_im(s->pc);
2545 s->is_jmp = DISAS_WFI;
2546 return 0;
2547 }
2548 rd = (insn >> 12) & 0xf;
2549
2550 if (cp15_tls_load_store(env, s, insn, rd))
2551 return 0;
2552
2553 tmp2 = tcg_const_i32(insn);
2554 if (insn & ARM_CP_RW_BIT) {
2555 tmp = new_tmp();
2556 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2557 /* If the destination register is r15 then sets condition codes. */
2558 if (rd != 15)
2559 store_reg(s, rd, tmp);
2560 else
2561 dead_tmp(tmp);
2562 } else {
2563 tmp = load_reg(s, rd);
2564 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2565 dead_tmp(tmp);
2566 /* Normally we would always end the TB here, but Linux
2567 * arch/arm/mach-pxa/sleep.S expects two instructions following
2568 * an MMU enable to execute from cache. Imitate this behaviour. */
2569 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2570 (insn & 0x0fff0fff) != 0x0e010f10)
2571 gen_lookup_tb(s);
2572 }
2573 tcg_temp_free_i32(tmp2);
2574 return 0;
2575 }
2576
2577 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2578 #define VFP_SREG(insn, bigbit, smallbit) \
2579 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2580 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2581 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2582 reg = (((insn) >> (bigbit)) & 0x0f) \
2583 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2584 } else { \
2585 if (insn & (1 << (smallbit))) \
2586 return 1; \
2587 reg = ((insn) >> (bigbit)) & 0x0f; \
2588 }} while (0)
2589
2590 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2591 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2592 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2593 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2594 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2595 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2596
2597 /* Move between integer and VFP cores. */
2598 static TCGv gen_vfp_mrs(void)
2599 {
2600 TCGv tmp = new_tmp();
2601 tcg_gen_mov_i32(tmp, cpu_F0s);
2602 return tmp;
2603 }
2604
2605 static void gen_vfp_msr(TCGv tmp)
2606 {
2607 tcg_gen_mov_i32(cpu_F0s, tmp);
2608 dead_tmp(tmp);
2609 }
2610
2611 static void gen_neon_dup_u8(TCGv var, int shift)
2612 {
2613 TCGv tmp = new_tmp();
2614 if (shift)
2615 tcg_gen_shri_i32(var, var, shift);
2616 tcg_gen_ext8u_i32(var, var);
2617 tcg_gen_shli_i32(tmp, var, 8);
2618 tcg_gen_or_i32(var, var, tmp);
2619 tcg_gen_shli_i32(tmp, var, 16);
2620 tcg_gen_or_i32(var, var, tmp);
2621 dead_tmp(tmp);
2622 }
2623
2624 static void gen_neon_dup_low16(TCGv var)
2625 {
2626 TCGv tmp = new_tmp();
2627 tcg_gen_ext16u_i32(var, var);
2628 tcg_gen_shli_i32(tmp, var, 16);
2629 tcg_gen_or_i32(var, var, tmp);
2630 dead_tmp(tmp);
2631 }
2632
2633 static void gen_neon_dup_high16(TCGv var)
2634 {
2635 TCGv tmp = new_tmp();
2636 tcg_gen_andi_i32(var, var, 0xffff0000);
2637 tcg_gen_shri_i32(tmp, var, 16);
2638 tcg_gen_or_i32(var, var, tmp);
2639 dead_tmp(tmp);
2640 }
2641
2642 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2643 (ie. an undefined instruction). */
2644 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2645 {
2646 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2647 int dp, veclen;
2648 TCGv addr;
2649 TCGv tmp;
2650 TCGv tmp2;
2651
2652 if (!arm_feature(env, ARM_FEATURE_VFP))
2653 return 1;
2654
2655 if (!s->vfp_enabled) {
2656 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2657 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2658 return 1;
2659 rn = (insn >> 16) & 0xf;
2660 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2661 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2662 return 1;
2663 }
2664 dp = ((insn & 0xf00) == 0xb00);
2665 switch ((insn >> 24) & 0xf) {
2666 case 0xe:
2667 if (insn & (1 << 4)) {
2668 /* single register transfer */
2669 rd = (insn >> 12) & 0xf;
2670 if (dp) {
2671 int size;
2672 int pass;
2673
2674 VFP_DREG_N(rn, insn);
2675 if (insn & 0xf)
2676 return 1;
2677 if (insn & 0x00c00060
2678 && !arm_feature(env, ARM_FEATURE_NEON))
2679 return 1;
2680
2681 pass = (insn >> 21) & 1;
2682 if (insn & (1 << 22)) {
2683 size = 0;
2684 offset = ((insn >> 5) & 3) * 8;
2685 } else if (insn & (1 << 5)) {
2686 size = 1;
2687 offset = (insn & (1 << 6)) ? 16 : 0;
2688 } else {
2689 size = 2;
2690 offset = 0;
2691 }
2692 if (insn & ARM_CP_RW_BIT) {
2693 /* vfp->arm */
2694 tmp = neon_load_reg(rn, pass);
2695 switch (size) {
2696 case 0:
2697 if (offset)
2698 tcg_gen_shri_i32(tmp, tmp, offset);
2699 if (insn & (1 << 23))
2700 gen_uxtb(tmp);
2701 else
2702 gen_sxtb(tmp);
2703 break;
2704 case 1:
2705 if (insn & (1 << 23)) {
2706 if (offset) {
2707 tcg_gen_shri_i32(tmp, tmp, 16);
2708 } else {
2709 gen_uxth(tmp);
2710 }
2711 } else {
2712 if (offset) {
2713 tcg_gen_sari_i32(tmp, tmp, 16);
2714 } else {
2715 gen_sxth(tmp);
2716 }
2717 }
2718 break;
2719 case 2:
2720 break;
2721 }
2722 store_reg(s, rd, tmp);
2723 } else {
2724 /* arm->vfp */
2725 tmp = load_reg(s, rd);
2726 if (insn & (1 << 23)) {
2727 /* VDUP */
2728 if (size == 0) {
2729 gen_neon_dup_u8(tmp, 0);
2730 } else if (size == 1) {
2731 gen_neon_dup_low16(tmp);
2732 }
2733 for (n = 0; n <= pass * 2; n++) {
2734 tmp2 = new_tmp();
2735 tcg_gen_mov_i32(tmp2, tmp);
2736 neon_store_reg(rn, n, tmp2);
2737 }
2738 neon_store_reg(rn, n, tmp);
2739 } else {
2740 /* VMOV */
2741 switch (size) {
2742 case 0:
2743 tmp2 = neon_load_reg(rn, pass);
2744 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2745 dead_tmp(tmp2);
2746 break;
2747 case 1:
2748 tmp2 = neon_load_reg(rn, pass);
2749 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2750 dead_tmp(tmp2);
2751 break;
2752 case 2:
2753 break;
2754 }
2755 neon_store_reg(rn, pass, tmp);
2756 }
2757 }
2758 } else { /* !dp */
2759 if ((insn & 0x6f) != 0x00)
2760 return 1;
2761 rn = VFP_SREG_N(insn);
2762 if (insn & ARM_CP_RW_BIT) {
2763 /* vfp->arm */
2764 if (insn & (1 << 21)) {
2765 /* system register */
2766 rn >>= 1;
2767
2768 switch (rn) {
2769 case ARM_VFP_FPSID:
2770 /* VFP2 allows access to FSID from userspace.
2771 VFP3 restricts all id registers to privileged
2772 accesses. */
2773 if (IS_USER(s)
2774 && arm_feature(env, ARM_FEATURE_VFP3))
2775 return 1;
2776 tmp = load_cpu_field(vfp.xregs[rn]);
2777 break;
2778 case ARM_VFP_FPEXC:
2779 if (IS_USER(s))
2780 return 1;
2781 tmp = load_cpu_field(vfp.xregs[rn]);
2782 break;
2783 case ARM_VFP_FPINST:
2784 case ARM_VFP_FPINST2:
2785 /* Not present in VFP3. */
2786 if (IS_USER(s)
2787 || arm_feature(env, ARM_FEATURE_VFP3))
2788 return 1;
2789 tmp = load_cpu_field(vfp.xregs[rn]);
2790 break;
2791 case ARM_VFP_FPSCR:
2792 if (rd == 15) {
2793 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2794 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2795 } else {
2796 tmp = new_tmp();
2797 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2798 }
2799 break;
2800 case ARM_VFP_MVFR0:
2801 case ARM_VFP_MVFR1:
2802 if (IS_USER(s)
2803 || !arm_feature(env, ARM_FEATURE_VFP3))
2804 return 1;
2805 tmp = load_cpu_field(vfp.xregs[rn]);
2806 break;
2807 default:
2808 return 1;
2809 }
2810 } else {
2811 gen_mov_F0_vreg(0, rn);
2812 tmp = gen_vfp_mrs();
2813 }
2814 if (rd == 15) {
2815 /* Set the 4 flag bits in the CPSR. */
2816 gen_set_nzcv(tmp);
2817 dead_tmp(tmp);
2818 } else {
2819 store_reg(s, rd, tmp);
2820 }
2821 } else {
2822 /* arm->vfp */
2823 tmp = load_reg(s, rd);
2824 if (insn & (1 << 21)) {
2825 rn >>= 1;
2826 /* system register */
2827 switch (rn) {
2828 case ARM_VFP_FPSID:
2829 case ARM_VFP_MVFR0:
2830 case ARM_VFP_MVFR1:
2831 /* Writes are ignored. */
2832 break;
2833 case ARM_VFP_FPSCR:
2834 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2835 dead_tmp(tmp);
2836 gen_lookup_tb(s);
2837 break;
2838 case ARM_VFP_FPEXC:
2839 if (IS_USER(s))
2840 return 1;
2841 /* TODO: VFP subarchitecture support.
2842 * For now, keep the EN bit only */
2843 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2844 store_cpu_field(tmp, vfp.xregs[rn]);
2845 gen_lookup_tb(s);
2846 break;
2847 case ARM_VFP_FPINST:
2848 case ARM_VFP_FPINST2:
2849 store_cpu_field(tmp, vfp.xregs[rn]);
2850 break;
2851 default:
2852 return 1;
2853 }
2854 } else {
2855 gen_vfp_msr(tmp);
2856 gen_mov_vreg_F0(0, rn);
2857 }
2858 }
2859 }
2860 } else {
2861 /* data processing */
2862 /* The opcode is in bits 23, 21, 20 and 6. */
2863 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2864 if (dp) {
2865 if (op == 15) {
2866 /* rn is opcode */
2867 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2868 } else {
2869 /* rn is register number */
2870 VFP_DREG_N(rn, insn);
2871 }
2872
2873 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2874 /* Integer or single precision destination. */
2875 rd = VFP_SREG_D(insn);
2876 } else {
2877 VFP_DREG_D(rd, insn);
2878 }
2879 if (op == 15 &&
2880 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2881 /* VCVT from int is always from S reg regardless of dp bit.
2882 * VCVT with immediate frac_bits has same format as SREG_M
2883 */
2884 rm = VFP_SREG_M(insn);
2885 } else {
2886 VFP_DREG_M(rm, insn);
2887 }
2888 } else {
2889 rn = VFP_SREG_N(insn);
2890 if (op == 15 && rn == 15) {
2891 /* Double precision destination. */
2892 VFP_DREG_D(rd, insn);
2893 } else {
2894 rd = VFP_SREG_D(insn);
2895 }
2896 /* NB that we implicitly rely on the encoding for the frac_bits
2897 * in VCVT of fixed to float being the same as that of an SREG_M
2898 */
2899 rm = VFP_SREG_M(insn);
2900 }
2901
2902 veclen = s->vec_len;
2903 if (op == 15 && rn > 3)
2904 veclen = 0;
2905
2906 /* Shut up compiler warnings. */
2907 delta_m = 0;
2908 delta_d = 0;
2909 bank_mask = 0;
2910
2911 if (veclen > 0) {
2912 if (dp)
2913 bank_mask = 0xc;
2914 else
2915 bank_mask = 0x18;
2916
2917 /* Figure out what type of vector operation this is. */
2918 if ((rd & bank_mask) == 0) {
2919 /* scalar */
2920 veclen = 0;
2921 } else {
2922 if (dp)
2923 delta_d = (s->vec_stride >> 1) + 1;
2924 else
2925 delta_d = s->vec_stride + 1;
2926
2927 if ((rm & bank_mask) == 0) {
2928 /* mixed scalar/vector */
2929 delta_m = 0;
2930 } else {
2931 /* vector */
2932 delta_m = delta_d;
2933 }
2934 }
2935 }
2936
2937 /* Load the initial operands. */
2938 if (op == 15) {
2939 switch (rn) {
2940 case 16:
2941 case 17:
2942 /* Integer source */
2943 gen_mov_F0_vreg(0, rm);
2944 break;
2945 case 8:
2946 case 9:
2947 /* Compare */
2948 gen_mov_F0_vreg(dp, rd);
2949 gen_mov_F1_vreg(dp, rm);
2950 break;
2951 case 10:
2952 case 11:
2953 /* Compare with zero */
2954 gen_mov_F0_vreg(dp, rd);
2955 gen_vfp_F1_ld0(dp);
2956 break;
2957 case 20:
2958 case 21:
2959 case 22:
2960 case 23:
2961 case 28:
2962 case 29:
2963 case 30:
2964 case 31:
2965 /* Source and destination the same. */
2966 gen_mov_F0_vreg(dp, rd);
2967 break;
2968 default:
2969 /* One source operand. */
2970 gen_mov_F0_vreg(dp, rm);
2971 break;
2972 }
2973 } else {
2974 /* Two source operands. */
2975 gen_mov_F0_vreg(dp, rn);
2976 gen_mov_F1_vreg(dp, rm);
2977 }
2978
2979 for (;;) {
2980 /* Perform the calculation. */
2981 switch (op) {
2982 case 0: /* mac: fd + (fn * fm) */
2983 gen_vfp_mul(dp);
2984 gen_mov_F1_vreg(dp, rd);
2985 gen_vfp_add(dp);
2986 break;
2987 case 1: /* nmac: fd - (fn * fm) */
2988 gen_vfp_mul(dp);
2989 gen_vfp_neg(dp);
2990 gen_mov_F1_vreg(dp, rd);
2991 gen_vfp_add(dp);
2992 break;
2993 case 2: /* msc: -fd + (fn * fm) */
2994 gen_vfp_mul(dp);
2995 gen_mov_F1_vreg(dp, rd);
2996 gen_vfp_sub(dp);
2997 break;
2998 case 3: /* nmsc: -fd - (fn * fm) */
2999 gen_vfp_mul(dp);
3000 gen_vfp_neg(dp);
3001 gen_mov_F1_vreg(dp, rd);
3002 gen_vfp_sub(dp);
3003 break;
3004 case 4: /* mul: fn * fm */
3005 gen_vfp_mul(dp);
3006 break;
3007 case 5: /* nmul: -(fn * fm) */
3008 gen_vfp_mul(dp);
3009 gen_vfp_neg(dp);
3010 break;
3011 case 6: /* add: fn + fm */
3012 gen_vfp_add(dp);
3013 break;
3014 case 7: /* sub: fn - fm */
3015 gen_vfp_sub(dp);
3016 break;
3017 case 8: /* div: fn / fm */
3018 gen_vfp_div(dp);
3019 break;
3020 case 14: /* fconst */
3021 if (!arm_feature(env, ARM_FEATURE_VFP3))
3022 return 1;
3023
3024 n = (insn << 12) & 0x80000000;
3025 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3026 if (dp) {
3027 if (i & 0x40)
3028 i |= 0x3f80;
3029 else
3030 i |= 0x4000;
3031 n |= i << 16;
3032 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3033 } else {
3034 if (i & 0x40)
3035 i |= 0x780;
3036 else
3037 i |= 0x800;
3038 n |= i << 19;
3039 tcg_gen_movi_i32(cpu_F0s, n);
3040 }
3041 break;
3042 case 15: /* extension space */
3043 switch (rn) {
3044 case 0: /* cpy */
3045 /* no-op */
3046 break;
3047 case 1: /* abs */
3048 gen_vfp_abs(dp);
3049 break;
3050 case 2: /* neg */
3051 gen_vfp_neg(dp);
3052 break;
3053 case 3: /* sqrt */
3054 gen_vfp_sqrt(dp);
3055 break;
3056 case 4: /* vcvtb.f32.f16 */
3057 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3058 return 1;
3059 tmp = gen_vfp_mrs();
3060 tcg_gen_ext16u_i32(tmp, tmp);
3061 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3062 dead_tmp(tmp);
3063 break;
3064 case 5: /* vcvtt.f32.f16 */
3065 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3066 return 1;
3067 tmp = gen_vfp_mrs();
3068 tcg_gen_shri_i32(tmp, tmp, 16);
3069 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3070 dead_tmp(tmp);
3071 break;
3072 case 6: /* vcvtb.f16.f32 */
3073 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3074 return 1;
3075 tmp = new_tmp();
3076 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3077 gen_mov_F0_vreg(0, rd);
3078 tmp2 = gen_vfp_mrs();
3079 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3080 tcg_gen_or_i32(tmp, tmp, tmp2);
3081 dead_tmp(tmp2);
3082 gen_vfp_msr(tmp);
3083 break;
3084 case 7: /* vcvtt.f16.f32 */
3085 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3086 return 1;
3087 tmp = new_tmp();
3088 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3089 tcg_gen_shli_i32(tmp, tmp, 16);
3090 gen_mov_F0_vreg(0, rd);
3091 tmp2 = gen_vfp_mrs();
3092 tcg_gen_ext16u_i32(tmp2, tmp2);
3093 tcg_gen_or_i32(tmp, tmp, tmp2);
3094 dead_tmp(tmp2);
3095 gen_vfp_msr(tmp);
3096 break;
3097 case 8: /* cmp */
3098 gen_vfp_cmp(dp);
3099 break;
3100 case 9: /* cmpe */
3101 gen_vfp_cmpe(dp);
3102 break;
3103 case 10: /* cmpz */
3104 gen_vfp_cmp(dp);
3105 break;
3106 case 11: /* cmpez */
3107 gen_vfp_F1_ld0(dp);
3108 gen_vfp_cmpe(dp);
3109 break;
3110 case 15: /* single<->double conversion */
3111 if (dp)
3112 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3113 else
3114 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3115 break;
3116 case 16: /* fuito */
3117 gen_vfp_uito(dp);
3118 break;
3119 case 17: /* fsito */
3120 gen_vfp_sito(dp);
3121 break;
3122 case 20: /* fshto */
3123 if (!arm_feature(env, ARM_FEATURE_VFP3))
3124 return 1;
3125 gen_vfp_shto(dp, 16 - rm);
3126 break;
3127 case 21: /* fslto */
3128 if (!arm_feature(env, ARM_FEATURE_VFP3))
3129 return 1;
3130 gen_vfp_slto(dp, 32 - rm);
3131 break;
3132 case 22: /* fuhto */
3133 if (!arm_feature(env, ARM_FEATURE_VFP3))
3134 return 1;
3135 gen_vfp_uhto(dp, 16 - rm);
3136 break;
3137 case 23: /* fulto */
3138 if (!arm_feature(env, ARM_FEATURE_VFP3))
3139 return 1;
3140 gen_vfp_ulto(dp, 32 - rm);
3141 break;
3142 case 24: /* ftoui */
3143 gen_vfp_toui(dp);
3144 break;
3145 case 25: /* ftouiz */
3146 gen_vfp_touiz(dp);
3147 break;
3148 case 26: /* ftosi */
3149 gen_vfp_tosi(dp);
3150 break;
3151 case 27: /* ftosiz */
3152 gen_vfp_tosiz(dp);
3153 break;
3154 case 28: /* ftosh */
3155 if (!arm_feature(env, ARM_FEATURE_VFP3))
3156 return 1;
3157 gen_vfp_tosh(dp, 16 - rm);
3158 break;
3159 case 29: /* ftosl */
3160 if (!arm_feature(env, ARM_FEATURE_VFP3))
3161 return 1;
3162 gen_vfp_tosl(dp, 32 - rm);
3163 break;
3164 case 30: /* ftouh */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_touh(dp, 16 - rm);
3168 break;
3169 case 31: /* ftoul */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_toul(dp, 32 - rm);
3173 break;
3174 default: /* undefined */
3175 printf ("rn:%d\n", rn);
3176 return 1;
3177 }
3178 break;
3179 default: /* undefined */
3180 printf ("op:%d\n", op);
3181 return 1;
3182 }
3183
3184 /* Write back the result. */
3185 if (op == 15 && (rn >= 8 && rn <= 11))
3186 ; /* Comparison, do nothing. */
3187 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3188 /* VCVT double to int: always integer result. */
3189 gen_mov_vreg_F0(0, rd);
3190 else if (op == 15 && rn == 15)
3191 /* conversion */
3192 gen_mov_vreg_F0(!dp, rd);
3193 else
3194 gen_mov_vreg_F0(dp, rd);
3195
3196 /* break out of the loop if we have finished */
3197 if (veclen == 0)
3198 break;
3199
3200 if (op == 15 && delta_m == 0) {
3201 /* single source one-many */
3202 while (veclen--) {
3203 rd = ((rd + delta_d) & (bank_mask - 1))
3204 | (rd & bank_mask);
3205 gen_mov_vreg_F0(dp, rd);
3206 }
3207 break;
3208 }
3209 /* Setup the next operands. */
3210 veclen--;
3211 rd = ((rd + delta_d) & (bank_mask - 1))
3212 | (rd & bank_mask);
3213
3214 if (op == 15) {
3215 /* One source operand. */
3216 rm = ((rm + delta_m) & (bank_mask - 1))
3217 | (rm & bank_mask);
3218 gen_mov_F0_vreg(dp, rm);
3219 } else {
3220 /* Two source operands. */
3221 rn = ((rn + delta_d) & (bank_mask - 1))
3222 | (rn & bank_mask);
3223 gen_mov_F0_vreg(dp, rn);
3224 if (delta_m) {
3225 rm = ((rm + delta_m) & (bank_mask - 1))
3226 | (rm & bank_mask);
3227 gen_mov_F1_vreg(dp, rm);
3228 }
3229 }
3230 }
3231 }
3232 break;
3233 case 0xc:
3234 case 0xd:
3235 if (dp && (insn & 0x03e00000) == 0x00400000) {
3236 /* two-register transfer */
3237 rn = (insn >> 16) & 0xf;
3238 rd = (insn >> 12) & 0xf;
3239 if (dp) {
3240 VFP_DREG_M(rm, insn);
3241 } else {
3242 rm = VFP_SREG_M(insn);
3243 }
3244
3245 if (insn & ARM_CP_RW_BIT) {
3246 /* vfp->arm */
3247 if (dp) {
3248 gen_mov_F0_vreg(0, rm * 2);
3249 tmp = gen_vfp_mrs();
3250 store_reg(s, rd, tmp);
3251 gen_mov_F0_vreg(0, rm * 2 + 1);
3252 tmp = gen_vfp_mrs();
3253 store_reg(s, rn, tmp);
3254 } else {
3255 gen_mov_F0_vreg(0, rm);
3256 tmp = gen_vfp_mrs();
3257 store_reg(s, rn, tmp);
3258 gen_mov_F0_vreg(0, rm + 1);
3259 tmp = gen_vfp_mrs();
3260 store_reg(s, rd, tmp);
3261 }
3262 } else {
3263 /* arm->vfp */
3264 if (dp) {
3265 tmp = load_reg(s, rd);
3266 gen_vfp_msr(tmp);
3267 gen_mov_vreg_F0(0, rm * 2);
3268 tmp = load_reg(s, rn);
3269 gen_vfp_msr(tmp);
3270 gen_mov_vreg_F0(0, rm * 2 + 1);
3271 } else {
3272 tmp = load_reg(s, rn);
3273 gen_vfp_msr(tmp);
3274 gen_mov_vreg_F0(0, rm);
3275 tmp = load_reg(s, rd);
3276 gen_vfp_msr(tmp);
3277 gen_mov_vreg_F0(0, rm + 1);
3278 }
3279 }
3280 } else {
3281 /* Load/store */
3282 rn = (insn >> 16) & 0xf;
3283 if (dp)
3284 VFP_DREG_D(rd, insn);
3285 else
3286 rd = VFP_SREG_D(insn);
3287 if (s->thumb && rn == 15) {
3288 addr = new_tmp();
3289 tcg_gen_movi_i32(addr, s->pc & ~2);
3290 } else {
3291 addr = load_reg(s, rn);
3292 }
3293 if ((insn & 0x01200000) == 0x01000000) {
3294 /* Single load/store */
3295 offset = (insn & 0xff) << 2;
3296 if ((insn & (1 << 23)) == 0)
3297 offset = -offset;
3298 tcg_gen_addi_i32(addr, addr, offset);
3299 if (insn & (1 << 20)) {
3300 gen_vfp_ld(s, dp, addr);
3301 gen_mov_vreg_F0(dp, rd);
3302 } else {
3303 gen_mov_F0_vreg(dp, rd);
3304 gen_vfp_st(s, dp, addr);
3305 }
3306 dead_tmp(addr);
3307 } else {
3308 /* load/store multiple */
3309 if (dp)
3310 n = (insn >> 1) & 0x7f;
3311 else
3312 n = insn & 0xff;
3313
3314 if (insn & (1 << 24)) /* pre-decrement */
3315 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3316
3317 if (dp)
3318 offset = 8;
3319 else
3320 offset = 4;
3321 for (i = 0; i < n; i++) {
3322 if (insn & ARM_CP_RW_BIT) {
3323 /* load */
3324 gen_vfp_ld(s, dp, addr);
3325 gen_mov_vreg_F0(dp, rd + i);
3326 } else {
3327 /* store */
3328 gen_mov_F0_vreg(dp, rd + i);
3329 gen_vfp_st(s, dp, addr);
3330 }
3331 tcg_gen_addi_i32(addr, addr, offset);
3332 }
3333 if (insn & (1 << 21)) {
3334 /* writeback */
3335 if (insn & (1 << 24))
3336 offset = -offset * n;
3337 else if (dp && (insn & 1))
3338 offset = 4;
3339 else
3340 offset = 0;
3341
3342 if (offset != 0)
3343 tcg_gen_addi_i32(addr, addr, offset);
3344 store_reg(s, rn, addr);
3345 } else {
3346 dead_tmp(addr);
3347 }
3348 }
3349 }
3350 break;
3351 default:
3352 /* Should never happen. */
3353 return 1;
3354 }
3355 return 0;
3356 }
3357
3358 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3359 {
3360 TranslationBlock *tb;
3361
3362 tb = s->tb;
3363 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3364 tcg_gen_goto_tb(n);
3365 gen_set_pc_im(dest);
3366 tcg_gen_exit_tb((long)tb + n);
3367 } else {
3368 gen_set_pc_im(dest);
3369 tcg_gen_exit_tb(0);
3370 }
3371 }
3372
3373 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3374 {
3375 if (unlikely(s->singlestep_enabled)) {
3376 /* An indirect jump so that we still trigger the debug exception. */
3377 if (s->thumb)
3378 dest |= 1;
3379 gen_bx_im(s, dest);
3380 } else {
3381 gen_goto_tb(s, 0, dest);
3382 s->is_jmp = DISAS_TB_JUMP;
3383 }
3384 }
3385
3386 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3387 {
3388 if (x)
3389 tcg_gen_sari_i32(t0, t0, 16);
3390 else
3391 gen_sxth(t0);
3392 if (y)
3393 tcg_gen_sari_i32(t1, t1, 16);
3394 else
3395 gen_sxth(t1);
3396 tcg_gen_mul_i32(t0, t0, t1);
3397 }
3398
3399 /* Return the mask of PSR bits set by a MSR instruction. */
3400 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3401 uint32_t mask;
3402
3403 mask = 0;
3404 if (flags & (1 << 0))
3405 mask |= 0xff;
3406 if (flags & (1 << 1))
3407 mask |= 0xff00;
3408 if (flags & (1 << 2))
3409 mask |= 0xff0000;
3410 if (flags & (1 << 3))
3411 mask |= 0xff000000;
3412
3413 /* Mask out undefined bits. */
3414 mask &= ~CPSR_RESERVED;
3415 if (!arm_feature(env, ARM_FEATURE_V6))
3416 mask &= ~(CPSR_E | CPSR_GE);
3417 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3418 mask &= ~CPSR_IT;
3419 /* Mask out execution state bits. */
3420 if (!spsr)
3421 mask &= ~CPSR_EXEC;
3422 /* Mask out privileged bits. */
3423 if (IS_USER(s))
3424 mask &= CPSR_USER;
3425 return mask;
3426 }
3427
3428 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3429 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3430 {
3431 TCGv tmp;
3432 if (spsr) {
3433 /* ??? This is also undefined in system mode. */
3434 if (IS_USER(s))
3435 return 1;
3436
3437 tmp = load_cpu_field(spsr);
3438 tcg_gen_andi_i32(tmp, tmp, ~mask);
3439 tcg_gen_andi_i32(t0, t0, mask);
3440 tcg_gen_or_i32(tmp, tmp, t0);
3441 store_cpu_field(tmp, spsr);
3442 } else {
3443 gen_set_cpsr(t0, mask);
3444 }
3445 dead_tmp(t0);
3446 gen_lookup_tb(s);
3447 return 0;
3448 }
3449
3450 /* Returns nonzero if access to the PSR is not permitted. */
3451 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3452 {
3453 TCGv tmp;
3454 tmp = new_tmp();
3455 tcg_gen_movi_i32(tmp, val);
3456 return gen_set_psr(s, mask, spsr, tmp);
3457 }
3458
3459 /* Generate an old-style exception return. Marks pc as dead. */
3460 static void gen_exception_return(DisasContext *s, TCGv pc)
3461 {
3462 TCGv tmp;
3463 store_reg(s, 15, pc);
3464 tmp = load_cpu_field(spsr);
3465 gen_set_cpsr(tmp, 0xffffffff);
3466 dead_tmp(tmp);
3467 s->is_jmp = DISAS_UPDATE;
3468 }
3469
3470 /* Generate a v6 exception return. Marks both values as dead. */
3471 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3472 {
3473 gen_set_cpsr(cpsr, 0xffffffff);
3474 dead_tmp(cpsr);
3475 store_reg(s, 15, pc);
3476 s->is_jmp = DISAS_UPDATE;
3477 }
3478
3479 static inline void
3480 gen_set_condexec (DisasContext *s)
3481 {
3482 if (s->condexec_mask) {
3483 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3484 TCGv tmp = new_tmp();
3485 tcg_gen_movi_i32(tmp, val);
3486 store_cpu_field(tmp, condexec_bits);
3487 }
3488 }
3489
3490 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3491 {
3492 gen_set_condexec(s);
3493 gen_set_pc_im(s->pc - offset);
3494 gen_exception(excp);
3495 s->is_jmp = DISAS_JUMP;
3496 }
3497
3498 static void gen_nop_hint(DisasContext *s, int val)
3499 {
3500 switch (val) {
3501 case 3: /* wfi */
3502 gen_set_pc_im(s->pc);
3503 s->is_jmp = DISAS_WFI;
3504 break;
3505 case 2: /* wfe */
3506 case 4: /* sev */
3507 /* TODO: Implement SEV and WFE. May help SMP performance. */
3508 default: /* nop */
3509 break;
3510 }
3511 }
3512
3513 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3514
3515 static inline int gen_neon_add(int size, TCGv t0, TCGv t1)
3516 {
3517 switch (size) {
3518 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3519 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3520 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3521 default: return 1;
3522 }
3523 return 0;
3524 }
3525
3526 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3527 {
3528 switch (size) {
3529 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3530 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3531 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3532 default: return;
3533 }
3534 }
3535
3536 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3537 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3538 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3539 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3540 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3541
3542 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3543 switch ((size << 1) | u) { \
3544 case 0: \
3545 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3546 break; \
3547 case 1: \
3548 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3549 break; \
3550 case 2: \
3551 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3552 break; \
3553 case 3: \
3554 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3555 break; \
3556 case 4: \
3557 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3558 break; \
3559 case 5: \
3560 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3561 break; \
3562 default: return 1; \
3563 }} while (0)
3564
3565 #define GEN_NEON_INTEGER_OP(name) do { \
3566 switch ((size << 1) | u) { \
3567 case 0: \
3568 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3569 break; \
3570 case 1: \
3571 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3572 break; \
3573 case 2: \
3574 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3575 break; \
3576 case 3: \
3577 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3578 break; \
3579 case 4: \
3580 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3581 break; \
3582 case 5: \
3583 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3584 break; \
3585 default: return 1; \
3586 }} while (0)
3587
3588 static TCGv neon_load_scratch(int scratch)
3589 {
3590 TCGv tmp = new_tmp();
3591 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3592 return tmp;
3593 }
3594
3595 static void neon_store_scratch(int scratch, TCGv var)
3596 {
3597 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3598 dead_tmp(var);
3599 }
3600
3601 static inline TCGv neon_get_scalar(int size, int reg)
3602 {
3603 TCGv tmp;
3604 if (size == 1) {
3605 tmp = neon_load_reg(reg & 7, reg >> 4);
3606 if (reg & 8) {
3607 gen_neon_dup_high16(tmp);
3608 } else {
3609 gen_neon_dup_low16(tmp);
3610 }
3611 } else {
3612 tmp = neon_load_reg(reg & 15, reg >> 4);
3613 }
3614 return tmp;
3615 }
3616
3617 static void gen_neon_unzip_u8(TCGv t0, TCGv t1)
3618 {
3619 TCGv rd, rm, tmp;
3620
3621 rd = new_tmp();
3622 rm = new_tmp();
3623 tmp = new_tmp();
3624
3625 tcg_gen_andi_i32(rd, t0, 0xff);
3626 tcg_gen_shri_i32(tmp, t0, 8);
3627 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3628 tcg_gen_or_i32(rd, rd, tmp);
3629 tcg_gen_shli_i32(tmp, t1, 16);
3630 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3631 tcg_gen_or_i32(rd, rd, tmp);
3632 tcg_gen_shli_i32(tmp, t1, 8);
3633 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3634 tcg_gen_or_i32(rd, rd, tmp);
3635
3636 tcg_gen_shri_i32(rm, t0, 8);
3637 tcg_gen_andi_i32(rm, rm, 0xff);
3638 tcg_gen_shri_i32(tmp, t0, 16);
3639 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3640 tcg_gen_or_i32(rm, rm, tmp);
3641 tcg_gen_shli_i32(tmp, t1, 8);
3642 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3643 tcg_gen_or_i32(rm, rm, tmp);
3644 tcg_gen_andi_i32(tmp, t1, 0xff000000);
3645 tcg_gen_or_i32(t1, rm, tmp);
3646 tcg_gen_mov_i32(t0, rd);
3647
3648 dead_tmp(tmp);
3649 dead_tmp(rm);
3650 dead_tmp(rd);
3651 }
3652
3653 static void gen_neon_zip_u8(TCGv t0, TCGv t1)
3654 {
3655 TCGv rd, rm, tmp;
3656
3657 rd = new_tmp();
3658 rm = new_tmp();
3659 tmp = new_tmp();
3660
3661 tcg_gen_andi_i32(rd, t0, 0xff);
3662 tcg_gen_shli_i32(tmp, t1, 8);
3663 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3664 tcg_gen_or_i32(rd, rd, tmp);
3665 tcg_gen_shli_i32(tmp, t0, 16);
3666 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3667 tcg_gen_or_i32(rd, rd, tmp);
3668 tcg_gen_shli_i32(tmp, t1, 24);
3669 tcg_gen_andi_i32(tmp, tmp, 0xff000000);
3670 tcg_gen_or_i32(rd, rd, tmp);
3671
3672 tcg_gen_andi_i32(rm, t1, 0xff000000);
3673 tcg_gen_shri_i32(tmp, t0, 8);
3674 tcg_gen_andi_i32(tmp, tmp, 0xff0000);
3675 tcg_gen_or_i32(rm, rm, tmp);
3676 tcg_gen_shri_i32(tmp, t1, 8);
3677 tcg_gen_andi_i32(tmp, tmp, 0xff00);
3678 tcg_gen_or_i32(rm, rm, tmp);
3679 tcg_gen_shri_i32(tmp, t0, 16);
3680 tcg_gen_andi_i32(tmp, tmp, 0xff);
3681 tcg_gen_or_i32(t1, rm, tmp);
3682 tcg_gen_mov_i32(t0, rd);
3683
3684 dead_tmp(tmp);
3685 dead_tmp(rm);
3686 dead_tmp(rd);
3687 }
3688
3689 static void gen_neon_zip_u16(TCGv t0, TCGv t1)
3690 {
3691 TCGv tmp, tmp2;
3692
3693 tmp = new_tmp();
3694 tmp2 = new_tmp();
3695
3696 tcg_gen_andi_i32(tmp, t0, 0xffff);
3697 tcg_gen_shli_i32(tmp2, t1, 16);
3698 tcg_gen_or_i32(tmp, tmp, tmp2);
3699 tcg_gen_andi_i32(t1, t1, 0xffff0000);
3700 tcg_gen_shri_i32(tmp2, t0, 16);
3701 tcg_gen_or_i32(t1, t1, tmp2);
3702 tcg_gen_mov_i32(t0, tmp);
3703
3704 dead_tmp(tmp2);
3705 dead_tmp(tmp);
3706 }
3707
3708 static void gen_neon_unzip(int reg, int q, int tmp, int size)
3709 {
3710 int n;
3711 TCGv t0, t1;
3712
3713 for (n = 0; n < q + 1; n += 2) {
3714 t0 = neon_load_reg(reg, n);
3715 t1 = neon_load_reg(reg, n + 1);
3716 switch (size) {
3717 case 0: gen_neon_unzip_u8(t0, t1); break;
3718 case 1: gen_neon_zip_u16(t0, t1); break; /* zip and unzip are the same. */
3719 case 2: /* no-op */; break;
3720 default: abort();
3721 }
3722 neon_store_scratch(tmp + n, t0);
3723 neon_store_scratch(tmp + n + 1, t1);
3724 }
3725 }
3726
3727 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3728 {
3729 TCGv rd, tmp;
3730
3731 rd = new_tmp();
3732 tmp = new_tmp();
3733
3734 tcg_gen_shli_i32(rd, t0, 8);
3735 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3736 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3737 tcg_gen_or_i32(rd, rd, tmp);
3738
3739 tcg_gen_shri_i32(t1, t1, 8);
3740 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3741 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3742 tcg_gen_or_i32(t1, t1, tmp);
3743 tcg_gen_mov_i32(t0, rd);
3744
3745 dead_tmp(tmp);
3746 dead_tmp(rd);
3747 }
3748
3749 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3750 {
3751 TCGv rd, tmp;
3752
3753 rd = new_tmp();
3754 tmp = new_tmp();
3755
3756 tcg_gen_shli_i32(rd, t0, 16);
3757 tcg_gen_andi_i32(tmp, t1, 0xffff);
3758 tcg_gen_or_i32(rd, rd, tmp);
3759 tcg_gen_shri_i32(t1, t1, 16);
3760 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3761 tcg_gen_or_i32(t1, t1, tmp);
3762 tcg_gen_mov_i32(t0, rd);
3763
3764 dead_tmp(tmp);
3765 dead_tmp(rd);
3766 }
3767
3768
3769 static struct {
3770 int nregs;
3771 int interleave;
3772 int spacing;
3773 } neon_ls_element_type[11] = {
3774 {4, 4, 1},
3775 {4, 4, 2},
3776 {4, 1, 1},
3777 {4, 2, 1},
3778 {3, 3, 1},
3779 {3, 3, 2},
3780 {3, 1, 1},
3781 {1, 1, 1},
3782 {2, 2, 1},
3783 {2, 2, 2},
3784 {2, 1, 1}
3785 };
3786
3787 /* Translate a NEON load/store element instruction. Return nonzero if the
3788 instruction is invalid. */
3789 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3790 {
3791 int rd, rn, rm;
3792 int op;
3793 int nregs;
3794 int interleave;
3795 int spacing;
3796 int stride;
3797 int size;
3798 int reg;
3799 int pass;
3800 int load;
3801 int shift;
3802 int n;
3803 TCGv addr;
3804 TCGv tmp;
3805 TCGv tmp2;
3806 TCGv_i64 tmp64;
3807
3808 if (!s->vfp_enabled)
3809 return 1;
3810 VFP_DREG_D(rd, insn);
3811 rn = (insn >> 16) & 0xf;
3812 rm = insn & 0xf;
3813 load = (insn & (1 << 21)) != 0;
3814 addr = new_tmp();
3815 if ((insn & (1 << 23)) == 0) {
3816 /* Load store all elements. */
3817 op = (insn >> 8) & 0xf;
3818 size = (insn >> 6) & 3;
3819 if (op > 10)
3820 return 1;
3821 nregs = neon_ls_element_type[op].nregs;
3822 interleave = neon_ls_element_type[op].interleave;
3823 spacing = neon_ls_element_type[op].spacing;
3824 if (size == 3 && (interleave | spacing) != 1)
3825 return 1;
3826 load_reg_var(s, addr, rn);
3827 stride = (1 << size) * interleave;
3828 for (reg = 0; reg < nregs; reg++) {
3829 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3830 load_reg_var(s, addr, rn);
3831 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3832 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3833 load_reg_var(s, addr, rn);
3834 tcg_gen_addi_i32(addr, addr, 1 << size);
3835 }
3836 if (size == 3) {
3837 if (load) {
3838 tmp64 = gen_ld64(addr, IS_USER(s));
3839 neon_store_reg64(tmp64, rd);
3840 tcg_temp_free_i64(tmp64);
3841 } else {
3842 tmp64 = tcg_temp_new_i64();
3843 neon_load_reg64(tmp64, rd);
3844 gen_st64(tmp64, addr, IS_USER(s));
3845 }
3846 tcg_gen_addi_i32(addr, addr, stride);
3847 } else {
3848 for (pass = 0; pass < 2; pass++) {
3849 if (size == 2) {
3850 if (load) {
3851 tmp = gen_ld32(addr, IS_USER(s));
3852 neon_store_reg(rd, pass, tmp);
3853 } else {
3854 tmp = neon_load_reg(rd, pass);
3855 gen_st32(tmp, addr, IS_USER(s));
3856 }
3857 tcg_gen_addi_i32(addr, addr, stride);
3858 } else if (size == 1) {
3859 if (load) {
3860 tmp = gen_ld16u(addr, IS_USER(s));
3861 tcg_gen_addi_i32(addr, addr, stride);
3862 tmp2 = gen_ld16u(addr, IS_USER(s));
3863 tcg_gen_addi_i32(addr, addr, stride);
3864 tcg_gen_shli_i32(tmp2, tmp2, 16);
3865 tcg_gen_or_i32(tmp, tmp, tmp2);
3866 dead_tmp(tmp2);
3867 neon_store_reg(rd, pass, tmp);
3868 } else {
3869 tmp = neon_load_reg(rd, pass);
3870 tmp2 = new_tmp();
3871 tcg_gen_shri_i32(tmp2, tmp, 16);
3872 gen_st16(tmp, addr, IS_USER(s));
3873 tcg_gen_addi_i32(addr, addr, stride);
3874 gen_st16(tmp2, addr, IS_USER(s));
3875 tcg_gen_addi_i32(addr, addr, stride);
3876 }
3877 } else /* size == 0 */ {
3878 if (load) {
3879 TCGV_UNUSED(tmp2);
3880 for (n = 0; n < 4; n++) {
3881 tmp = gen_ld8u(addr, IS_USER(s));
3882 tcg_gen_addi_i32(addr, addr, stride);
3883 if (n == 0) {
3884 tmp2 = tmp;
3885 } else {
3886 tcg_gen_shli_i32(tmp, tmp, n * 8);
3887 tcg_gen_or_i32(tmp2, tmp2, tmp);
3888 dead_tmp(tmp);
3889 }
3890 }
3891 neon_store_reg(rd, pass, tmp2);
3892 } else {
3893 tmp2 = neon_load_reg(rd, pass);
3894 for (n = 0; n < 4; n++) {
3895 tmp = new_tmp();
3896 if (n == 0) {
3897 tcg_gen_mov_i32(tmp, tmp2);
3898 } else {
3899 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3900 }
3901 gen_st8(tmp, addr, IS_USER(s));
3902 tcg_gen_addi_i32(addr, addr, stride);
3903 }
3904 dead_tmp(tmp2);
3905 }
3906 }
3907 }
3908 }
3909 rd += spacing;
3910 }
3911 stride = nregs * 8;
3912 } else {
3913 size = (insn >> 10) & 3;
3914 if (size == 3) {
3915 /* Load single element to all lanes. */
3916 if (!load)
3917 return 1;
3918 size = (insn >> 6) & 3;
3919 nregs = ((insn >> 8) & 3) + 1;
3920 stride = (insn & (1 << 5)) ? 2 : 1;
3921 load_reg_var(s, addr, rn);
3922 for (reg = 0; reg < nregs; reg++) {
3923 switch (size) {
3924 case 0:
3925 tmp = gen_ld8u(addr, IS_USER(s));
3926 gen_neon_dup_u8(tmp, 0);
3927 break;
3928 case 1:
3929 tmp = gen_ld16u(addr, IS_USER(s));
3930 gen_neon_dup_low16(tmp);
3931 break;
3932 case 2:
3933 tmp = gen_ld32(addr, IS_USER(s));
3934 break;
3935 case 3:
3936 return 1;
3937 default: /* Avoid compiler warnings. */
3938 abort();
3939 }
3940 tcg_gen_addi_i32(addr, addr, 1 << size);
3941 tmp2 = new_tmp();
3942 tcg_gen_mov_i32(tmp2, tmp);
3943 neon_store_reg(rd, 0, tmp2);
3944 neon_store_reg(rd, 1, tmp);
3945 rd += stride;
3946 }
3947 stride = (1 << size) * nregs;
3948 } else {
3949 /* Single element. */
3950 pass = (insn >> 7) & 1;
3951 switch (size) {
3952 case 0:
3953 shift = ((insn >> 5) & 3) * 8;
3954 stride = 1;
3955 break;
3956 case 1:
3957 shift = ((insn >> 6) & 1) * 16;
3958 stride = (insn & (1 << 5)) ? 2 : 1;
3959 break;
3960 case 2:
3961 shift = 0;
3962 stride = (insn & (1 << 6)) ? 2 : 1;
3963 break;
3964 default:
3965 abort();
3966 }
3967 nregs = ((insn >> 8) & 3) + 1;
3968 load_reg_var(s, addr, rn);
3969 for (reg = 0; reg < nregs; reg++) {
3970 if (load) {
3971 switch (size) {
3972 case 0:
3973 tmp = gen_ld8u(addr, IS_USER(s));
3974 break;
3975 case 1:
3976 tmp = gen_ld16u(addr, IS_USER(s));
3977 break;
3978 case 2:
3979 tmp = gen_ld32(addr, IS_USER(s));
3980 break;
3981 default: /* Avoid compiler warnings. */
3982 abort();
3983 }
3984 if (size != 2) {
3985 tmp2 = neon_load_reg(rd, pass);
3986 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
3987 dead_tmp(tmp2);
3988 }
3989 neon_store_reg(rd, pass, tmp);
3990 } else { /* Store */
3991 tmp = neon_load_reg(rd, pass);
3992 if (shift)
3993 tcg_gen_shri_i32(tmp, tmp, shift);
3994 switch (size) {
3995 case 0:
3996 gen_st8(tmp, addr, IS_USER(s));
3997 break;
3998 case 1:
3999 gen_st16(tmp, addr, IS_USER(s));
4000 break;
4001 case 2:
4002 gen_st32(tmp, addr, IS_USER(s));
4003 break;
4004 }
4005 }
4006 rd += stride;
4007 tcg_gen_addi_i32(addr, addr, 1 << size);
4008 }
4009 stride = nregs * (1 << size);
4010 }
4011 }
4012 dead_tmp(addr);
4013 if (rm != 15) {
4014 TCGv base;
4015
4016 base = load_reg(s, rn);
4017 if (rm == 13) {
4018 tcg_gen_addi_i32(base, base, stride);
4019 } else {
4020 TCGv index;
4021 index = load_reg(s, rm);
4022 tcg_gen_add_i32(base, base, index);
4023 dead_tmp(index);
4024 }
4025 store_reg(s, rn, base);
4026 }
4027 return 0;
4028 }
4029
4030 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4031 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4032 {
4033 tcg_gen_and_i32(t, t, c);
4034 tcg_gen_andc_i32(f, f, c);
4035 tcg_gen_or_i32(dest, t, f);
4036 }
4037
4038 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4039 {
4040 switch (size) {
4041 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4042 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4043 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4044 default: abort();
4045 }
4046 }
4047
4048 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4049 {
4050 switch (size) {
4051 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
4052 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
4053 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
4054 default: abort();
4055 }
4056 }
4057
4058 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4059 {
4060 switch (size) {
4061 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
4062 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
4063 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
4064 default: abort();
4065 }
4066 }
4067
4068 static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4069 {
4070 switch (size) {
4071 case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break;
4072 case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break;
4073 case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break;
4074 default: abort();
4075 }
4076 }
4077
4078 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4079 int q, int u)
4080 {
4081 if (q) {
4082 if (u) {
4083 switch (size) {
4084 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4085 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4086 default: abort();
4087 }
4088 } else {
4089 switch (size) {
4090 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4091 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4092 default: abort();
4093 }
4094 }
4095 } else {
4096 if (u) {
4097 switch (size) {
4098 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4099 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4100 default: abort();
4101 }
4102 } else {
4103 switch (size) {
4104 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4105 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4106 default: abort();
4107 }
4108 }
4109 }
4110 }
4111
4112 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4113 {
4114 if (u) {
4115 switch (size) {
4116 case 0: gen_helper_neon_widen_u8(dest, src); break;
4117 case 1: gen_helper_neon_widen_u16(dest, src); break;
4118 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4119 default: abort();
4120 }
4121 } else {
4122 switch (size) {
4123 case 0: gen_helper_neon_widen_s8(dest, src); break;
4124 case 1: gen_helper_neon_widen_s16(dest, src); break;
4125 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4126 default: abort();
4127 }
4128 }
4129 dead_tmp(src);
4130 }
4131
4132 static inline void gen_neon_addl(int size)
4133 {
4134 switch (size) {
4135 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4136 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4137 case 2: tcg_gen_add_i64(CPU_V001); break;
4138 default: abort();
4139 }
4140 }
4141
4142 static inline void gen_neon_subl(int size)
4143 {
4144 switch (size) {
4145 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4146 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4147 case 2: tcg_gen_sub_i64(CPU_V001); break;
4148 default: abort();
4149 }
4150 }
4151
4152 static inline void gen_neon_negl(TCGv_i64 var, int size)
4153 {
4154 switch (size) {
4155 case 0: gen_helper_neon_negl_u16(var, var); break;
4156 case 1: gen_helper_neon_negl_u32(var, var); break;
4157 case 2: gen_helper_neon_negl_u64(var, var); break;
4158 default: abort();
4159 }
4160 }
4161
4162 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4163 {
4164 switch (size) {
4165 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4166 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4167 default: abort();
4168 }
4169 }
4170
4171 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4172 {
4173 TCGv_i64 tmp;
4174
4175 switch ((size << 1) | u) {
4176 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4177 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4178 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4179 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4180 case 4:
4181 tmp = gen_muls_i64_i32(a, b);
4182 tcg_gen_mov_i64(dest, tmp);
4183 break;
4184 case 5:
4185 tmp = gen_mulu_i64_i32(a, b);
4186 tcg_gen_mov_i64(dest, tmp);
4187 break;
4188 default: abort();
4189 }
4190
4191 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4192 Don't forget to clean them now. */
4193 if (size < 2) {
4194 dead_tmp(a);
4195 dead_tmp(b);
4196 }
4197 }
4198
4199 /* Translate a NEON data processing instruction. Return nonzero if the
4200 instruction is invalid.
4201 We process data in a mixture of 32-bit and 64-bit chunks.
4202 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4203
4204 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4205 {
4206 int op;
4207 int q;
4208 int rd, rn, rm;
4209 int size;
4210 int shift;
4211 int pass;
4212 int count;
4213 int pairwise;
4214 int u;
4215 int n;
4216 uint32_t imm, mask;
4217 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4218 TCGv_i64 tmp64;
4219
4220 if (!s->vfp_enabled)
4221 return 1;
4222 q = (insn & (1 << 6)) != 0;
4223 u = (insn >> 24) & 1;
4224 VFP_DREG_D(rd, insn);
4225 VFP_DREG_N(rn, insn);
4226 VFP_DREG_M(rm, insn);
4227 size = (insn >> 20) & 3;
4228 if ((insn & (1 << 23)) == 0) {
4229 /* Three register same length. */
4230 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4231 if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9
4232 || op == 10 || op == 11 || op == 16)) {
4233 /* 64-bit element instructions. */
4234 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4235 neon_load_reg64(cpu_V0, rn + pass);
4236 neon_load_reg64(cpu_V1, rm + pass);
4237 switch (op) {
4238 case 1: /* VQADD */
4239 if (u) {
4240 gen_helper_neon_qadd_u64(cpu_V0, cpu_env,
4241 cpu_V0, cpu_V1);
4242 } else {
4243 gen_helper_neon_qadd_s64(cpu_V0, cpu_env,
4244 cpu_V0, cpu_V1);
4245 }
4246 break;
4247 case 5: /* VQSUB */
4248 if (u) {
4249 gen_helper_neon_qsub_u64(cpu_V0, cpu_env,
4250 cpu_V0, cpu_V1);
4251 } else {
4252 gen_helper_neon_qsub_s64(cpu_V0, cpu_env,
4253 cpu_V0, cpu_V1);
4254 }
4255 break;
4256 case 8: /* VSHL */
4257 if (u) {
4258 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4259 } else {
4260 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4261 }
4262 break;
4263 case 9: /* VQSHL */
4264 if (u) {
4265 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4266 cpu_V1, cpu_V0);
4267 } else {
4268 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4269 cpu_V1, cpu_V0);
4270 }
4271 break;
4272 case 10: /* VRSHL */
4273 if (u) {
4274 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4275 } else {
4276 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4277 }
4278 break;
4279 case 11: /* VQRSHL */
4280 if (u) {
4281 gen_helper_neon_qrshl_u64(cpu_V0, cpu_env,
4282 cpu_V1, cpu_V0);
4283 } else {
4284 gen_helper_neon_qrshl_s64(cpu_V0, cpu_env,
4285 cpu_V1, cpu_V0);
4286 }
4287 break;
4288 case 16:
4289 if (u) {
4290 tcg_gen_sub_i64(CPU_V001);
4291 } else {
4292 tcg_gen_add_i64(CPU_V001);
4293 }
4294 break;
4295 default:
4296 abort();
4297 }
4298 neon_store_reg64(cpu_V0, rd + pass);
4299 }
4300 return 0;
4301 }
4302 switch (op) {
4303 case 8: /* VSHL */
4304 case 9: /* VQSHL */
4305 case 10: /* VRSHL */
4306 case 11: /* VQRSHL */
4307 {
4308 int rtmp;
4309 /* Shift instruction operands are reversed. */
4310 rtmp = rn;
4311 rn = rm;
4312 rm = rtmp;
4313 pairwise = 0;
4314 }
4315 break;
4316 case 20: /* VPMAX */
4317 case 21: /* VPMIN */
4318 case 23: /* VPADD */
4319 pairwise = 1;
4320 break;
4321 case 26: /* VPADD (float) */
4322 pairwise = (u && size < 2);
4323 break;
4324 case 30: /* VPMIN/VPMAX (float) */
4325 pairwise = u;
4326 break;
4327 default:
4328 pairwise = 0;
4329 break;
4330 }
4331
4332 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4333
4334 if (pairwise) {
4335 /* Pairwise. */
4336 if (q)
4337 n = (pass & 1) * 2;
4338 else
4339 n = 0;
4340 if (pass < q + 1) {
4341 tmp = neon_load_reg(rn, n);
4342 tmp2 = neon_load_reg(rn, n + 1);
4343 } else {
4344 tmp = neon_load_reg(rm, n);
4345 tmp2 = neon_load_reg(rm, n + 1);
4346 }
4347 } else {
4348 /* Elementwise. */
4349 tmp = neon_load_reg(rn, pass);
4350 tmp2 = neon_load_reg(rm, pass);
4351 }
4352 switch (op) {
4353 case 0: /* VHADD */
4354 GEN_NEON_INTEGER_OP(hadd);
4355 break;
4356 case 1: /* VQADD */
4357 GEN_NEON_INTEGER_OP_ENV(qadd);
4358 break;
4359 case 2: /* VRHADD */
4360 GEN_NEON_INTEGER_OP(rhadd);
4361 break;
4362 case 3: /* Logic ops. */
4363 switch ((u << 2) | size) {
4364 case 0: /* VAND */
4365 tcg_gen_and_i32(tmp, tmp, tmp2);
4366 break;
4367 case 1: /* BIC */
4368 tcg_gen_andc_i32(tmp, tmp, tmp2);
4369 break;
4370 case 2: /* VORR */
4371 tcg_gen_or_i32(tmp, tmp, tmp2);
4372 break;
4373 case 3: /* VORN */
4374 tcg_gen_orc_i32(tmp, tmp, tmp2);
4375 break;
4376 case 4: /* VEOR */
4377 tcg_gen_xor_i32(tmp, tmp, tmp2);
4378 break;
4379 case 5: /* VBSL */
4380 tmp3 = neon_load_reg(rd, pass);
4381 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4382 dead_tmp(tmp3);
4383 break;
4384 case 6: /* VBIT */
4385 tmp3 = neon_load_reg(rd, pass);
4386 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4387 dead_tmp(tmp3);
4388 break;
4389 case 7: /* VBIF */
4390 tmp3 = neon_load_reg(rd, pass);
4391 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4392 dead_tmp(tmp3);
4393 break;
4394 }
4395 break;
4396 case 4: /* VHSUB */
4397 GEN_NEON_INTEGER_OP(hsub);
4398 break;
4399 case 5: /* VQSUB */
4400 GEN_NEON_INTEGER_OP_ENV(qsub);
4401 break;
4402 case 6: /* VCGT */
4403 GEN_NEON_INTEGER_OP(cgt);
4404 break;
4405 case 7: /* VCGE */
4406 GEN_NEON_INTEGER_OP(cge);
4407 break;
4408 case 8: /* VSHL */
4409 GEN_NEON_INTEGER_OP(shl);
4410 break;
4411 case 9: /* VQSHL */
4412 GEN_NEON_INTEGER_OP_ENV(qshl);
4413 break;
4414 case 10: /* VRSHL */
4415 GEN_NEON_INTEGER_OP(rshl);
4416 break;
4417 case 11: /* VQRSHL */
4418 GEN_NEON_INTEGER_OP_ENV(qrshl);
4419 break;
4420 case 12: /* VMAX */
4421 GEN_NEON_INTEGER_OP(max);
4422 break;
4423 case 13: /* VMIN */
4424 GEN_NEON_INTEGER_OP(min);
4425 break;
4426 case 14: /* VABD */
4427 GEN_NEON_INTEGER_OP(abd);
4428 break;
4429 case 15: /* VABA */
4430 GEN_NEON_INTEGER_OP(abd);
4431 dead_tmp(tmp2);
4432 tmp2 = neon_load_reg(rd, pass);
4433 gen_neon_add(size, tmp, tmp2);
4434 break;
4435 case 16:
4436 if (!u) { /* VADD */
4437 if (gen_neon_add(size, tmp, tmp2))
4438 return 1;
4439 } else { /* VSUB */
4440 switch (size) {
4441 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4442 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4443 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4444 default: return 1;
4445 }
4446 }
4447 break;
4448 case 17:
4449 if (!u) { /* VTST */
4450 switch (size) {
4451 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4452 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4453 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4454 default: return 1;
4455 }
4456 } else { /* VCEQ */
4457 switch (size) {
4458 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4459 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4460 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4461 default: return 1;
4462 }
4463 }
4464 break;
4465 case 18: /* Multiply. */
4466 switch (size) {
4467 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4468 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4469 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4470 default: return 1;
4471 }
4472 dead_tmp(tmp2);
4473 tmp2 = neon_load_reg(rd, pass);
4474 if (u) { /* VMLS */
4475 gen_neon_rsb(size, tmp, tmp2);
4476 } else { /* VMLA */
4477 gen_neon_add(size, tmp, tmp2);
4478 }
4479 break;
4480 case 19: /* VMUL */
4481 if (u) { /* polynomial */
4482 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4483 } else { /* Integer */
4484 switch (size) {
4485 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4486 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4487 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4488 default: return 1;
4489 }
4490 }
4491 break;
4492 case 20: /* VPMAX */
4493 GEN_NEON_INTEGER_OP(pmax);
4494 break;
4495 case 21: /* VPMIN */
4496 GEN_NEON_INTEGER_OP(pmin);
4497 break;
4498 case 22: /* Hultiply high. */
4499 if (!u) { /* VQDMULH */
4500 switch (size) {
4501 case 1: gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4502 case 2: gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4503 default: return 1;
4504 }
4505 } else { /* VQRDHMUL */
4506 switch (size) {
4507 case 1: gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2); break;
4508 case 2: gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2); break;
4509 default: return 1;
4510 }
4511 }
4512 break;
4513 case 23: /* VPADD */
4514 if (u)
4515 return 1;
4516 switch (size) {
4517 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4518 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4519 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4520 default: return 1;
4521 }
4522 break;
4523 case 26: /* Floating point arithnetic. */
4524 switch ((u << 2) | size) {
4525 case 0: /* VADD */
4526 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4527 break;
4528 case 2: /* VSUB */
4529 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4530 break;
4531 case 4: /* VPADD */
4532 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4533 break;
4534 case 6: /* VABD */
4535 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4536 break;
4537 default:
4538 return 1;
4539 }
4540 break;
4541 case 27: /* Float multiply. */
4542 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4543 if (!u) {
4544 dead_tmp(tmp2);
4545 tmp2 = neon_load_reg(rd, pass);
4546 if (size == 0) {
4547 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4548 } else {
4549 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4550 }
4551 }
4552 break;
4553 case 28: /* Float compare. */
4554 if (!u) {
4555 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4556 } else {
4557 if (size == 0)
4558 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4559 else
4560 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4561 }
4562 break;
4563 case 29: /* Float compare absolute. */
4564 if (!u)
4565 return 1;
4566 if (size == 0)
4567 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4568 else
4569 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4570 break;
4571 case 30: /* Float min/max. */
4572 if (size == 0)
4573 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4574 else
4575 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4576 break;
4577 case 31:
4578 if (size == 0)
4579 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4580 else
4581 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4582 break;
4583 default:
4584 abort();
4585 }
4586 dead_tmp(tmp2);
4587
4588 /* Save the result. For elementwise operations we can put it
4589 straight into the destination register. For pairwise operations
4590 we have to be careful to avoid clobbering the source operands. */
4591 if (pairwise && rd == rm) {
4592 neon_store_scratch(pass, tmp);
4593 } else {
4594 neon_store_reg(rd, pass, tmp);
4595 }
4596
4597 } /* for pass */
4598 if (pairwise && rd == rm) {
4599 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4600 tmp = neon_load_scratch(pass);
4601 neon_store_reg(rd, pass, tmp);
4602 }
4603 }
4604 /* End of 3 register same size operations. */
4605 } else if (insn & (1 << 4)) {
4606 if ((insn & 0x00380080) != 0) {
4607 /* Two registers and shift. */
4608 op = (insn >> 8) & 0xf;
4609 if (insn & (1 << 7)) {
4610 /* 64-bit shift. */
4611 size = 3;
4612 } else {
4613 size = 2;
4614 while ((insn & (1 << (size + 19))) == 0)
4615 size--;
4616 }
4617 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4618 /* To avoid excessive dumplication of ops we implement shift
4619 by immediate using the variable shift operations. */
4620 if (op < 8) {
4621 /* Shift by immediate:
4622 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4623 /* Right shifts are encoded as N - shift, where N is the
4624 element size in bits. */
4625 if (op <= 4)
4626 shift = shift - (1 << (size + 3));
4627 if (size == 3) {
4628 count = q + 1;
4629 } else {
4630 count = q ? 4: 2;
4631 }
4632 switch (size) {
4633 case 0:
4634 imm = (uint8_t) shift;
4635 imm |= imm << 8;
4636 imm |= imm << 16;
4637 break;
4638 case 1:
4639 imm = (uint16_t) shift;
4640 imm |= imm << 16;
4641 break;
4642 case 2:
4643 case 3:
4644 imm = shift;
4645 break;
4646 default:
4647 abort();
4648 }
4649
4650 for (pass = 0; pass < count; pass++) {
4651 if (size == 3) {
4652 neon_load_reg64(cpu_V0, rm + pass);
4653 tcg_gen_movi_i64(cpu_V1, imm);
4654 switch (op) {
4655 case 0: /* VSHR */
4656 case 1: /* VSRA */
4657 if (u)
4658 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4659 else
4660 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4661 break;
4662 case 2: /* VRSHR */
4663 case 3: /* VRSRA */
4664 if (u)
4665 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4666 else
4667 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4668 break;
4669 case 4: /* VSRI */
4670 if (!u)
4671 return 1;
4672 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4673 break;
4674 case 5: /* VSHL, VSLI */
4675 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4676 break;
4677 case 6: /* VQSHLU */
4678 if (u) {
4679 gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
4680 cpu_V0, cpu_V1);
4681 } else {
4682 return 1;
4683 }
4684 break;
4685 case 7: /* VQSHL */
4686 if (u) {
4687 gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
4688 cpu_V0, cpu_V1);
4689 } else {
4690 gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
4691 cpu_V0, cpu_V1);
4692 }
4693 break;
4694 }
4695 if (op == 1 || op == 3) {
4696 /* Accumulate. */
4697 neon_load_reg64(cpu_V1, rd + pass);
4698 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4699 } else if (op == 4 || (op == 5 && u)) {
4700 /* Insert */
4701 neon_load_reg64(cpu_V1, rd + pass);
4702 uint64_t mask;
4703 if (shift < -63 || shift > 63) {
4704 mask = 0;
4705 } else {
4706 if (op == 4) {
4707 mask = 0xffffffffffffffffull >> -shift;
4708 } else {
4709 mask = 0xffffffffffffffffull << shift;
4710 }
4711 }
4712 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4713 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
4714 }
4715 neon_store_reg64(cpu_V0, rd + pass);
4716 } else { /* size < 3 */
4717 /* Operands in T0 and T1. */
4718 tmp = neon_load_reg(rm, pass);
4719 tmp2 = new_tmp();
4720 tcg_gen_movi_i32(tmp2, imm);
4721 switch (op) {
4722 case 0: /* VSHR */
4723 case 1: /* VSRA */
4724 GEN_NEON_INTEGER_OP(shl);
4725 break;
4726 case 2: /* VRSHR */
4727 case 3: /* VRSRA */
4728 GEN_NEON_INTEGER_OP(rshl);
4729 break;
4730 case 4: /* VSRI */
4731 if (!u)
4732 return 1;
4733 GEN_NEON_INTEGER_OP(shl);
4734 break;
4735 case 5: /* VSHL, VSLI */
4736 switch (size) {
4737 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4738 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4739 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4740 default: return 1;
4741 }
4742 break;
4743 case 6: /* VQSHLU */
4744 if (!u) {
4745 return 1;
4746 }
4747 switch (size) {
4748 case 0:
4749 gen_helper_neon_qshlu_s8(tmp, cpu_env,
4750 tmp, tmp2);
4751 break;
4752 case 1:
4753 gen_helper_neon_qshlu_s16(tmp, cpu_env,
4754 tmp, tmp2);
4755 break;
4756 case 2:
4757 gen_helper_neon_qshlu_s32(tmp, cpu_env,
4758 tmp, tmp2);
4759 break;
4760 default:
4761 return 1;
4762 }
4763 break;
4764 case 7: /* VQSHL */
4765 GEN_NEON_INTEGER_OP_ENV(qshl);
4766 break;
4767 }
4768 dead_tmp(tmp2);
4769
4770 if (op == 1 || op == 3) {
4771 /* Accumulate. */
4772 tmp2 = neon_load_reg(rd, pass);
4773 gen_neon_add(size, tmp, tmp2);
4774 dead_tmp(tmp2);
4775 } else if (op == 4 || (op == 5 && u)) {
4776 /* Insert */
4777 switch (size) {
4778 case 0:
4779 if (op == 4)
4780 mask = 0xff >> -shift;
4781 else
4782 mask = (uint8_t)(0xff << shift);
4783 mask |= mask << 8;
4784 mask |= mask << 16;
4785 break;
4786 case 1:
4787 if (op == 4)
4788 mask = 0xffff >> -shift;
4789 else
4790 mask = (uint16_t)(0xffff << shift);
4791 mask |= mask << 16;
4792 break;
4793 case 2:
4794 if (shift < -31 || shift > 31) {
4795 mask = 0;
4796 } else {
4797 if (op == 4)
4798 mask = 0xffffffffu >> -shift;
4799 else
4800 mask = 0xffffffffu << shift;
4801 }
4802 break;
4803 default:
4804 abort();
4805 }
4806 tmp2 = neon_load_reg(rd, pass);
4807 tcg_gen_andi_i32(tmp, tmp, mask);
4808 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
4809 tcg_gen_or_i32(tmp, tmp, tmp2);
4810 dead_tmp(tmp2);
4811 }
4812 neon_store_reg(rd, pass, tmp);
4813 }
4814 } /* for pass */
4815 } else if (op < 10) {
4816 /* Shift by immediate and narrow:
4817 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
4818 shift = shift - (1 << (size + 3));
4819 size++;
4820 switch (size) {
4821 case 1:
4822 imm = (uint16_t)shift;
4823 imm |= imm << 16;
4824 tmp2 = tcg_const_i32(imm);
4825 TCGV_UNUSED_I64(tmp64);
4826 break;
4827 case 2:
4828 imm = (uint32_t)shift;
4829 tmp2 = tcg_const_i32(imm);
4830 TCGV_UNUSED_I64(tmp64);
4831 break;
4832 case 3:
4833 tmp64 = tcg_const_i64(shift);
4834 TCGV_UNUSED(tmp2);
4835 break;
4836 default:
4837 abort();
4838 }
4839
4840 for (pass = 0; pass < 2; pass++) {
4841 if (size == 3) {
4842 neon_load_reg64(cpu_V0, rm + pass);
4843 if (q) {
4844 if (u)
4845 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64);
4846 else
4847 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64);
4848 } else {
4849 if (u)
4850 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64);
4851 else
4852 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64);
4853 }
4854 } else {
4855 tmp = neon_load_reg(rm + pass, 0);
4856 gen_neon_shift_narrow(size, tmp, tmp2, q, u);
4857 tmp3 = neon_load_reg(rm + pass, 1);
4858 gen_neon_shift_narrow(size, tmp3, tmp2, q, u);
4859 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
4860 dead_tmp(tmp);
4861 dead_tmp(tmp3);
4862 }
4863 tmp = new_tmp();
4864 if (op == 8 && !u) {
4865 gen_neon_narrow(size - 1, tmp, cpu_V0);
4866 } else {
4867 if (op == 8)
4868 gen_neon_narrow_sats(size - 1, tmp, cpu_V0);
4869 else
4870 gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
4871 }
4872 neon_store_reg(rd, pass, tmp);
4873 } /* for pass */
4874 if (size == 3) {
4875 tcg_temp_free_i64(tmp64);
4876 } else {
4877 tcg_temp_free_i32(tmp2);
4878 }
4879 } else if (op == 10) {
4880 /* VSHLL */
4881 if (q || size == 3)
4882 return 1;
4883 tmp = neon_load_reg(rm, 0);
4884 tmp2 = neon_load_reg(rm, 1);
4885 for (pass = 0; pass < 2; pass++) {
4886 if (pass == 1)
4887 tmp = tmp2;
4888
4889 gen_neon_widen(cpu_V0, tmp, size, u);
4890
4891 if (shift != 0) {
4892 /* The shift is less than the width of the source
4893 type, so we can just shift the whole register. */
4894 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
4895 /* Widen the result of shift: we need to clear
4896 * the potential overflow bits resulting from
4897 * left bits of the narrow input appearing as
4898 * right bits of left the neighbour narrow
4899 * input. */
4900 if (size < 2 || !u) {
4901 uint64_t imm64;
4902 if (size == 0) {
4903 imm = (0xffu >> (8 - shift));
4904 imm |= imm << 16;
4905 } else if (size == 1) {
4906 imm = 0xffff >> (16 - shift);
4907 } else {
4908 /* size == 2 */
4909 imm = 0xffffffff >> (32 - shift);
4910 }
4911 if (size < 2) {
4912 imm64 = imm | (((uint64_t)imm) << 32);
4913 } else {
4914 imm64 = imm;
4915 }
4916 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
4917 }
4918 }
4919 neon_store_reg64(cpu_V0, rd + pass);
4920 }
4921 } else if (op >= 14) {
4922 /* VCVT fixed-point. */
4923 /* We have already masked out the must-be-1 top bit of imm6,
4924 * hence this 32-shift where the ARM ARM has 64-imm6.
4925 */
4926 shift = 32 - shift;
4927 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4928 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
4929 if (!(op & 1)) {
4930 if (u)
4931 gen_vfp_ulto(0, shift);
4932 else
4933 gen_vfp_slto(0, shift);
4934 } else {
4935 if (u)
4936 gen_vfp_toul(0, shift);
4937 else
4938 gen_vfp_tosl(0, shift);
4939 }
4940 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
4941 }
4942 } else {
4943 return 1;
4944 }
4945 } else { /* (insn & 0x00380080) == 0 */
4946 int invert;
4947
4948 op = (insn >> 8) & 0xf;
4949 /* One register and immediate. */
4950 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4951 invert = (insn & (1 << 5)) != 0;
4952 switch (op) {
4953 case 0: case 1:
4954 /* no-op */
4955 break;
4956 case 2: case 3:
4957 imm <<= 8;
4958 break;
4959 case 4: case 5:
4960 imm <<= 16;
4961 break;
4962 case 6: case 7:
4963 imm <<= 24;
4964 break;
4965 case 8: case 9:
4966 imm |= imm << 16;
4967 break;
4968 case 10: case 11:
4969 imm = (imm << 8) | (imm << 24);
4970 break;
4971 case 12:
4972 imm = (imm << 8) | 0xff;
4973 break;
4974 case 13:
4975 imm = (imm << 16) | 0xffff;
4976 break;
4977 case 14:
4978 imm |= (imm << 8) | (imm << 16) | (imm << 24);
4979 if (invert)
4980 imm = ~imm;
4981 break;
4982 case 15:
4983 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
4984 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
4985 break;
4986 }
4987 if (invert)
4988 imm = ~imm;
4989
4990 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4991 if (op & 1 && op < 12) {
4992 tmp = neon_load_reg(rd, pass);
4993 if (invert) {
4994 /* The immediate value has already been inverted, so
4995 BIC becomes AND. */
4996 tcg_gen_andi_i32(tmp, tmp, imm);
4997 } else {
4998 tcg_gen_ori_i32(tmp, tmp, imm);
4999 }
5000 } else {
5001 /* VMOV, VMVN. */
5002 tmp = new_tmp();
5003 if (op == 14 && invert) {
5004 uint32_t val;
5005 val = 0;
5006 for (n = 0; n < 4; n++) {
5007 if (imm & (1 << (n + (pass & 1) * 4)))
5008 val |= 0xff << (n * 8);
5009 }
5010 tcg_gen_movi_i32(tmp, val);
5011 } else {
5012 tcg_gen_movi_i32(tmp, imm);
5013 }
5014 }
5015 neon_store_reg(rd, pass, tmp);
5016 }
5017 }
5018 } else { /* (insn & 0x00800010 == 0x00800000) */
5019 if (size != 3) {
5020 op = (insn >> 8) & 0xf;
5021 if ((insn & (1 << 6)) == 0) {
5022 /* Three registers of different lengths. */
5023 int src1_wide;
5024 int src2_wide;
5025 int prewiden;
5026 /* prewiden, src1_wide, src2_wide */
5027 static const int neon_3reg_wide[16][3] = {
5028 {1, 0, 0}, /* VADDL */
5029 {1, 1, 0}, /* VADDW */
5030 {1, 0, 0}, /* VSUBL */
5031 {1, 1, 0}, /* VSUBW */
5032 {0, 1, 1}, /* VADDHN */
5033 {0, 0, 0}, /* VABAL */
5034 {0, 1, 1}, /* VSUBHN */
5035 {0, 0, 0}, /* VABDL */
5036 {0, 0, 0}, /* VMLAL */
5037 {0, 0, 0}, /* VQDMLAL */
5038 {0, 0, 0}, /* VMLSL */
5039 {0, 0, 0}, /* VQDMLSL */
5040 {0, 0, 0}, /* Integer VMULL */
5041 {0, 0, 0}, /* VQDMULL */
5042 {0, 0, 0} /* Polynomial VMULL */
5043 };
5044
5045 prewiden = neon_3reg_wide[op][0];
5046 src1_wide = neon_3reg_wide[op][1];
5047 src2_wide = neon_3reg_wide[op][2];
5048
5049 if (size == 0 && (op == 9 || op == 11 || op == 13))
5050 return 1;
5051
5052 /* Avoid overlapping operands. Wide source operands are
5053 always aligned so will never overlap with wide
5054 destinations in problematic ways. */
5055 if (rd == rm && !src2_wide) {
5056 tmp = neon_load_reg(rm, 1);
5057 neon_store_scratch(2, tmp);
5058 } else if (rd == rn && !src1_wide) {
5059 tmp = neon_load_reg(rn, 1);
5060 neon_store_scratch(2, tmp);
5061 }
5062 TCGV_UNUSED(tmp3);
5063 for (pass = 0; pass < 2; pass++) {
5064 if (src1_wide) {
5065 neon_load_reg64(cpu_V0, rn + pass);
5066 TCGV_UNUSED(tmp);
5067 } else {
5068 if (pass == 1 && rd == rn) {
5069 tmp = neon_load_scratch(2);
5070 } else {
5071 tmp = neon_load_reg(rn, pass);
5072 }
5073 if (prewiden) {
5074 gen_neon_widen(cpu_V0, tmp, size, u);
5075 }
5076 }
5077 if (src2_wide) {
5078 neon_load_reg64(cpu_V1, rm + pass);
5079 TCGV_UNUSED(tmp2);
5080 } else {
5081 if (pass == 1 && rd == rm) {
5082 tmp2 = neon_load_scratch(2);
5083 } else {
5084 tmp2 = neon_load_reg(rm, pass);
5085 }
5086 if (prewiden) {
5087 gen_neon_widen(cpu_V1, tmp2, size, u);
5088 }
5089 }
5090 switch (op) {
5091 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5092 gen_neon_addl(size);
5093 break;
5094 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5095 gen_neon_subl(size);
5096 break;
5097 case 5: case 7: /* VABAL, VABDL */
5098 switch ((size << 1) | u) {
5099 case 0:
5100 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5101 break;
5102 case 1:
5103 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5104 break;
5105 case 2:
5106 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5107 break;
5108 case 3:
5109 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5110 break;
5111 case 4:
5112 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5113 break;
5114 case 5:
5115 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5116 break;
5117 default: abort();
5118 }
5119 dead_tmp(tmp2);
5120 dead_tmp(tmp);
5121 break;
5122 case 8: case 9: case 10: case 11: case 12: case 13:
5123 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5124 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5125 break;
5126 case 14: /* Polynomial VMULL */
5127 cpu_abort(env, "Polynomial VMULL not implemented");
5128
5129 default: /* 15 is RESERVED. */
5130 return 1;
5131 }
5132 if (op == 5 || op == 13 || (op >= 8 && op <= 11)) {
5133 /* Accumulate. */
5134 if (op == 10 || op == 11) {
5135 gen_neon_negl(cpu_V0, size);
5136 }
5137
5138 if (op != 13) {
5139 neon_load_reg64(cpu_V1, rd + pass);
5140 }
5141
5142 switch (op) {
5143 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
5144 gen_neon_addl(size);
5145 break;
5146 case 9: case 11: /* VQDMLAL, VQDMLSL */
5147 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5148 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5149 break;
5150 /* Fall through. */
5151 case 13: /* VQDMULL */
5152 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5153 break;
5154 default:
5155 abort();
5156 }
5157 neon_store_reg64(cpu_V0, rd + pass);
5158 } else if (op == 4 || op == 6) {
5159 /* Narrowing operation. */
5160 tmp = new_tmp();
5161 if (!u) {
5162 switch (size) {
5163 case 0:
5164 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5165 break;
5166 case 1:
5167 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5168 break;
5169 case 2:
5170 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5171 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5172 break;
5173 default: abort();
5174 }
5175 } else {
5176 switch (size) {
5177 case 0:
5178 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5179 break;
5180 case 1:
5181 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5182 break;
5183 case 2:
5184 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5185 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5186 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5187 break;
5188 default: abort();
5189 }
5190 }
5191 if (pass == 0) {
5192 tmp3 = tmp;
5193 } else {
5194 neon_store_reg(rd, 0, tmp3);
5195 neon_store_reg(rd, 1, tmp);
5196 }
5197 } else {
5198 /* Write back the result. */
5199 neon_store_reg64(cpu_V0, rd + pass);
5200 }
5201 }
5202 } else {
5203 /* Two registers and a scalar. */
5204 switch (op) {
5205 case 0: /* Integer VMLA scalar */
5206 case 1: /* Float VMLA scalar */
5207 case 4: /* Integer VMLS scalar */
5208 case 5: /* Floating point VMLS scalar */
5209 case 8: /* Integer VMUL scalar */
5210 case 9: /* Floating point VMUL scalar */
5211 case 12: /* VQDMULH scalar */
5212 case 13: /* VQRDMULH scalar */
5213 tmp = neon_get_scalar(size, rm);
5214 neon_store_scratch(0, tmp);
5215 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5216 tmp = neon_load_scratch(0);
5217 tmp2 = neon_load_reg(rn, pass);
5218 if (op == 12) {
5219 if (size == 1) {
5220 gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
5221 } else {
5222 gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
5223 }
5224 } else if (op == 13) {
5225 if (size == 1) {
5226 gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
5227 } else {
5228 gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
5229 }
5230 } else if (op & 1) {
5231 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5232 } else {
5233 switch (size) {
5234 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5235 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5236 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5237 default: return 1;
5238 }
5239 }
5240 dead_tmp(tmp2);
5241 if (op < 8) {
5242 /* Accumulate. */
5243 tmp2 = neon_load_reg(rd, pass);
5244 switch (op) {
5245 case 0:
5246 gen_neon_add(size, tmp, tmp2);
5247 break;
5248 case 1:
5249 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5250 break;
5251 case 4:
5252 gen_neon_rsb(size, tmp, tmp2);
5253 break;
5254 case 5:
5255 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5256 break;
5257 default:
5258 abort();
5259 }
5260 dead_tmp(tmp2);
5261 }
5262 neon_store_reg(rd, pass, tmp);
5263 }
5264 break;
5265 case 2: /* VMLAL sclar */
5266 case 3: /* VQDMLAL scalar */
5267 case 6: /* VMLSL scalar */
5268 case 7: /* VQDMLSL scalar */
5269 case 10: /* VMULL scalar */
5270 case 11: /* VQDMULL scalar */
5271 if (size == 0 && (op == 3 || op == 7 || op == 11))
5272 return 1;
5273
5274 tmp2 = neon_get_scalar(size, rm);
5275 /* We need a copy of tmp2 because gen_neon_mull
5276 * deletes it during pass 0. */
5277 tmp4 = new_tmp();
5278 tcg_gen_mov_i32(tmp4, tmp2);
5279 tmp3 = neon_load_reg(rn, 1);
5280
5281 for (pass = 0; pass < 2; pass++) {
5282 if (pass == 0) {
5283 tmp = neon_load_reg(rn, 0);
5284 } else {
5285 tmp = tmp3;
5286 tmp2 = tmp4;
5287 }
5288 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5289 if (op == 6 || op == 7) {
5290 gen_neon_negl(cpu_V0, size);
5291 }
5292 if (op != 11) {
5293 neon_load_reg64(cpu_V1, rd + pass);
5294 }
5295 switch (op) {
5296 case 2: case 6:
5297 gen_neon_addl(size);
5298 break;
5299 case 3: case 7:
5300 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5301 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5302 break;
5303 case 10:
5304 /* no-op */
5305 break;
5306 case 11:
5307 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5308 break;
5309 default:
5310 abort();
5311 }
5312 neon_store_reg64(cpu_V0, rd + pass);
5313 }
5314
5315
5316 break;
5317 default: /* 14 and 15 are RESERVED */
5318 return 1;
5319 }
5320 }
5321 } else { /* size == 3 */
5322 if (!u) {
5323 /* Extract. */
5324 imm = (insn >> 8) & 0xf;
5325
5326 if (imm > 7 && !q)
5327 return 1;
5328
5329 if (imm == 0) {
5330 neon_load_reg64(cpu_V0, rn);
5331 if (q) {
5332 neon_load_reg64(cpu_V1, rn + 1);
5333 }
5334 } else if (imm == 8) {
5335 neon_load_reg64(cpu_V0, rn + 1);
5336 if (q) {
5337 neon_load_reg64(cpu_V1, rm);
5338 }
5339 } else if (q) {
5340 tmp64 = tcg_temp_new_i64();
5341 if (imm < 8) {
5342 neon_load_reg64(cpu_V0, rn);
5343 neon_load_reg64(tmp64, rn + 1);
5344 } else {
5345 neon_load_reg64(cpu_V0, rn + 1);
5346 neon_load_reg64(tmp64, rm);
5347 }
5348 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5349 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5350 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5351 if (imm < 8) {
5352 neon_load_reg64(cpu_V1, rm);
5353 } else {
5354 neon_load_reg64(cpu_V1, rm + 1);
5355 imm -= 8;
5356 }
5357 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5358 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5359 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5360 tcg_temp_free_i64(tmp64);
5361 } else {
5362 /* BUGFIX */
5363 neon_load_reg64(cpu_V0, rn);
5364 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5365 neon_load_reg64(cpu_V1, rm);
5366 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5367 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5368 }
5369 neon_store_reg64(cpu_V0, rd);
5370 if (q) {
5371 neon_store_reg64(cpu_V1, rd + 1);
5372 }
5373 } else if ((insn & (1 << 11)) == 0) {
5374 /* Two register misc. */
5375 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5376 size = (insn >> 18) & 3;
5377 switch (op) {
5378 case 0: /* VREV64 */
5379 if (size == 3)
5380 return 1;
5381 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5382 tmp = neon_load_reg(rm, pass * 2);
5383 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5384 switch (size) {
5385 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5386 case 1: gen_swap_half(tmp); break;
5387 case 2: /* no-op */ break;
5388 default: abort();
5389 }
5390 neon_store_reg(rd, pass * 2 + 1, tmp);
5391 if (size == 2) {
5392 neon_store_reg(rd, pass * 2, tmp2);
5393 } else {
5394 switch (size) {
5395 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5396 case 1: gen_swap_half(tmp2); break;
5397 default: abort();
5398 }
5399 neon_store_reg(rd, pass * 2, tmp2);
5400 }
5401 }
5402 break;
5403 case 4: case 5: /* VPADDL */
5404 case 12: case 13: /* VPADAL */
5405 if (size == 3)
5406 return 1;
5407 for (pass = 0; pass < q + 1; pass++) {
5408 tmp = neon_load_reg(rm, pass * 2);
5409 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5410 tmp = neon_load_reg(rm, pass * 2 + 1);
5411 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5412 switch (size) {
5413 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5414 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5415 case 2: tcg_gen_add_i64(CPU_V001); break;
5416 default: abort();
5417 }
5418 if (op >= 12) {
5419 /* Accumulate. */
5420 neon_load_reg64(cpu_V1, rd + pass);
5421 gen_neon_addl(size);
5422 }
5423 neon_store_reg64(cpu_V0, rd + pass);
5424 }
5425 break;
5426 case 33: /* VTRN */
5427 if (size == 2) {
5428 for (n = 0; n < (q ? 4 : 2); n += 2) {
5429 tmp = neon_load_reg(rm, n);
5430 tmp2 = neon_load_reg(rd, n + 1);
5431 neon_store_reg(rm, n, tmp2);
5432 neon_store_reg(rd, n + 1, tmp);
5433 }
5434 } else {
5435 goto elementwise;
5436 }
5437 break;
5438 case 34: /* VUZP */
5439 /* Reg Before After
5440 Rd A3 A2 A1 A0 B2 B0 A2 A0
5441 Rm B3 B2 B1 B0 B3 B1 A3 A1
5442 */
5443 if (size == 3)
5444 return 1;
5445 gen_neon_unzip(rd, q, 0, size);
5446 gen_neon_unzip(rm, q, 4, size);
5447 if (q) {
5448 static int unzip_order_q[8] =
5449 {0, 2, 4, 6, 1, 3, 5, 7};
5450 for (n = 0; n < 8; n++) {
5451 int reg = (n < 4) ? rd : rm;
5452 tmp = neon_load_scratch(unzip_order_q[n]);
5453 neon_store_reg(reg, n % 4, tmp);
5454 }
5455 } else {
5456 static int unzip_order[4] =
5457 {0, 4, 1, 5};
5458 for (n = 0; n < 4; n++) {
5459 int reg = (n < 2) ? rd : rm;
5460 tmp = neon_load_scratch(unzip_order[n]);
5461 neon_store_reg(reg, n % 2, tmp);
5462 }
5463 }
5464 break;
5465 case 35: /* VZIP */
5466 /* Reg Before After
5467 Rd A3 A2 A1 A0 B1 A1 B0 A0
5468 Rm B3 B2 B1 B0 B3 A3 B2 A2
5469 */
5470 if (size == 3)
5471 return 1;
5472 count = (q ? 4 : 2);
5473 for (n = 0; n < count; n++) {
5474 tmp = neon_load_reg(rd, n);
5475 tmp2 = neon_load_reg(rd, n);
5476 switch (size) {
5477 case 0: gen_neon_zip_u8(tmp, tmp2); break;
5478 case 1: gen_neon_zip_u16(tmp, tmp2); break;
5479 case 2: /* no-op */; break;
5480 default: abort();
5481 }
5482 neon_store_scratch(n * 2, tmp);
5483 neon_store_scratch(n * 2 + 1, tmp2);
5484 }
5485 for (n = 0; n < count * 2; n++) {
5486 int reg = (n < count) ? rd : rm;
5487 tmp = neon_load_scratch(n);
5488 neon_store_reg(reg, n % count, tmp);
5489 }
5490 break;
5491 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5492 if (size == 3)
5493 return 1;
5494 TCGV_UNUSED(tmp2);
5495 for (pass = 0; pass < 2; pass++) {
5496 neon_load_reg64(cpu_V0, rm + pass);
5497 tmp = new_tmp();
5498 if (op == 36) {
5499 if (q) { /* VQMOVUN */
5500 gen_neon_unarrow_sats(size, tmp, cpu_V0);
5501 } else { /* VMOVN */
5502 gen_neon_narrow(size, tmp, cpu_V0);
5503 }
5504 } else { /* VQMOVN */
5505 if (q) {
5506 gen_neon_narrow_satu(size, tmp, cpu_V0);
5507 } else {
5508 gen_neon_narrow_sats(size, tmp, cpu_V0);
5509 }
5510 }
5511 if (pass == 0) {
5512 tmp2 = tmp;
5513 } else {
5514 neon_store_reg(rd, 0, tmp2);
5515 neon_store_reg(rd, 1, tmp);
5516 }
5517 }
5518 break;
5519 case 38: /* VSHLL */
5520 if (q || size == 3)
5521 return 1;
5522 tmp = neon_load_reg(rm, 0);
5523 tmp2 = neon_load_reg(rm, 1);
5524 for (pass = 0; pass < 2; pass++) {
5525 if (pass == 1)
5526 tmp = tmp2;
5527 gen_neon_widen(cpu_V0, tmp, size, 1);
5528 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5529 neon_store_reg64(cpu_V0, rd + pass);
5530 }
5531 break;
5532 case 44: /* VCVT.F16.F32 */
5533 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5534 return 1;
5535 tmp = new_tmp();
5536 tmp2 = new_tmp();
5537 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5538 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5539 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5540 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5541 tcg_gen_shli_i32(tmp2, tmp2, 16);
5542 tcg_gen_or_i32(tmp2, tmp2, tmp);
5543 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5544 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5545 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5546 neon_store_reg(rd, 0, tmp2);
5547 tmp2 = new_tmp();
5548 gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5549 tcg_gen_shli_i32(tmp2, tmp2, 16);
5550 tcg_gen_or_i32(tmp2, tmp2, tmp);
5551 neon_store_reg(rd, 1, tmp2);
5552 dead_tmp(tmp);
5553 break;
5554 case 46: /* VCVT.F32.F16 */
5555 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
5556 return 1;
5557 tmp3 = new_tmp();
5558 tmp = neon_load_reg(rm, 0);
5559 tmp2 = neon_load_reg(rm, 1);
5560 tcg_gen_ext16u_i32(tmp3, tmp);
5561 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5562 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5563 tcg_gen_shri_i32(tmp3, tmp, 16);
5564 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5565 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5566 dead_tmp(tmp);
5567 tcg_gen_ext16u_i32(tmp3, tmp2);
5568 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5569 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5570 tcg_gen_shri_i32(tmp3, tmp2, 16);
5571 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5572 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5573 dead_tmp(tmp2);
5574 dead_tmp(tmp3);
5575 break;
5576 default:
5577 elementwise:
5578 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5579 if (op == 30 || op == 31 || op >= 58) {
5580 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5581 neon_reg_offset(rm, pass));
5582 TCGV_UNUSED(tmp);
5583 } else {
5584 tmp = neon_load_reg(rm, pass);
5585 }
5586 switch (op) {
5587 case 1: /* VREV32 */
5588 switch (size) {
5589 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5590 case 1: gen_swap_half(tmp); break;
5591 default: return 1;
5592 }
5593 break;
5594 case 2: /* VREV16 */
5595 if (size != 0)
5596 return 1;
5597 gen_rev16(tmp);
5598 break;
5599 case 8: /* CLS */
5600 switch (size) {
5601 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5602 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5603 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5604 default: return 1;
5605 }
5606 break;
5607 case 9: /* CLZ */
5608 switch (size) {
5609 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5610 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5611 case 2: gen_helper_clz(tmp, tmp); break;
5612 default: return 1;
5613 }
5614 break;
5615 case 10: /* CNT */
5616 if (size != 0)
5617 return 1;
5618 gen_helper_neon_cnt_u8(tmp, tmp);
5619 break;
5620 case 11: /* VNOT */
5621 if (size != 0)
5622 return 1;
5623 tcg_gen_not_i32(tmp, tmp);
5624 break;
5625 case 14: /* VQABS */
5626 switch (size) {
5627 case 0: gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); break;
5628 case 1: gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); break;
5629 case 2: gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); break;
5630 default: return 1;
5631 }
5632 break;
5633 case 15: /* VQNEG */
5634 switch (size) {
5635 case 0: gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); break;
5636 case 1: gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); break;
5637 case 2: gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); break;
5638 default: return 1;
5639 }
5640 break;
5641 case 16: case 19: /* VCGT #0, VCLE #0 */
5642 tmp2 = tcg_const_i32(0);
5643 switch(size) {
5644 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5645 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5646 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5647 default: return 1;
5648 }
5649 tcg_temp_free(tmp2);
5650 if (op == 19)
5651 tcg_gen_not_i32(tmp, tmp);
5652 break;
5653 case 17: case 20: /* VCGE #0, VCLT #0 */
5654 tmp2 = tcg_const_i32(0);
5655 switch(size) {
5656 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5657 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5658 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5659 default: return 1;
5660 }
5661 tcg_temp_free(tmp2);
5662 if (op == 20)
5663 tcg_gen_not_i32(tmp, tmp);
5664 break;
5665 case 18: /* VCEQ #0 */
5666 tmp2 = tcg_const_i32(0);
5667 switch(size) {
5668 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5669 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5670 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5671 default: return 1;
5672 }
5673 tcg_temp_free(tmp2);
5674 break;
5675 case 22: /* VABS */
5676 switch(size) {
5677 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5678 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5679 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5680 default: return 1;
5681 }
5682 break;
5683 case 23: /* VNEG */
5684 if (size == 3)
5685 return 1;
5686 tmp2 = tcg_const_i32(0);
5687 gen_neon_rsb(size, tmp, tmp2);
5688 tcg_temp_free(tmp2);
5689 break;
5690 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5691 tmp2 = tcg_const_i32(0);
5692 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5693 tcg_temp_free(tmp2);
5694 if (op == 27)
5695 tcg_gen_not_i32(tmp, tmp);
5696 break;
5697 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5698 tmp2 = tcg_const_i32(0);
5699 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5700 tcg_temp_free(tmp2);
5701 if (op == 28)
5702 tcg_gen_not_i32(tmp, tmp);
5703 break;
5704 case 26: /* Float VCEQ #0 */
5705 tmp2 = tcg_const_i32(0);
5706 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5707 tcg_temp_free(tmp2);
5708 break;
5709 case 30: /* Float VABS */
5710 gen_vfp_abs(0);
5711 break;
5712 case 31: /* Float VNEG */
5713 gen_vfp_neg(0);
5714 break;
5715 case 32: /* VSWP */
5716 tmp2 = neon_load_reg(rd, pass);
5717 neon_store_reg(rm, pass, tmp2);
5718 break;
5719 case 33: /* VTRN */
5720 tmp2 = neon_load_reg(rd, pass);
5721 switch (size) {
5722 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5723 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5724 case 2: abort();
5725 default: return 1;
5726 }
5727 neon_store_reg(rm, pass, tmp2);
5728 break;
5729 case 56: /* Integer VRECPE */
5730 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5731 break;
5732 case 57: /* Integer VRSQRTE */
5733 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5734 break;
5735 case 58: /* Float VRECPE */
5736 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5737 break;
5738 case 59: /* Float VRSQRTE */
5739 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5740 break;
5741 case 60: /* VCVT.F32.S32 */
5742 gen_vfp_sito(0);
5743 break;
5744 case 61: /* VCVT.F32.U32 */
5745 gen_vfp_uito(0);
5746 break;
5747 case 62: /* VCVT.S32.F32 */
5748 gen_vfp_tosiz(0);
5749 break;
5750 case 63: /* VCVT.U32.F32 */
5751 gen_vfp_touiz(0);
5752 break;
5753 default:
5754 /* Reserved: 21, 29, 39-56 */
5755 return 1;
5756 }
5757 if (op == 30 || op == 31 || op >= 58) {
5758 tcg_gen_st_f32(cpu_F0s, cpu_env,
5759 neon_reg_offset(rd, pass));
5760 } else {
5761 neon_store_reg(rd, pass, tmp);
5762 }
5763 }
5764 break;
5765 }
5766 } else if ((insn & (1 << 10)) == 0) {
5767 /* VTBL, VTBX. */
5768 n = ((insn >> 5) & 0x18) + 8;
5769 if (insn & (1 << 6)) {
5770 tmp = neon_load_reg(rd, 0);
5771 } else {
5772 tmp = new_tmp();
5773 tcg_gen_movi_i32(tmp, 0);
5774 }
5775 tmp2 = neon_load_reg(rm, 0);
5776 tmp4 = tcg_const_i32(rn);
5777 tmp5 = tcg_const_i32(n);
5778 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
5779 dead_tmp(tmp);
5780 if (insn & (1 << 6)) {
5781 tmp = neon_load_reg(rd, 1);
5782 } else {
5783 tmp = new_tmp();
5784 tcg_gen_movi_i32(tmp, 0);
5785 }
5786 tmp3 = neon_load_reg(rm, 1);
5787 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
5788 tcg_temp_free_i32(tmp5);
5789 tcg_temp_free_i32(tmp4);
5790 neon_store_reg(rd, 0, tmp2);
5791 neon_store_reg(rd, 1, tmp3);
5792 dead_tmp(tmp);
5793 } else if ((insn & 0x380) == 0) {
5794 /* VDUP */
5795 if (insn & (1 << 19)) {
5796 tmp = neon_load_reg(rm, 1);
5797 } else {
5798 tmp = neon_load_reg(rm, 0);
5799 }
5800 if (insn & (1 << 16)) {
5801 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
5802 } else if (insn & (1 << 17)) {
5803 if ((insn >> 18) & 1)
5804 gen_neon_dup_high16(tmp);
5805 else
5806 gen_neon_dup_low16(tmp);
5807 }
5808 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5809 tmp2 = new_tmp();
5810 tcg_gen_mov_i32(tmp2, tmp);
5811 neon_store_reg(rd, pass, tmp2);
5812 }
5813 dead_tmp(tmp);
5814 } else {
5815 return 1;
5816 }
5817 }
5818 }
5819 return 0;
5820 }
5821
5822 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5823 {
5824 int crn = (insn >> 16) & 0xf;
5825 int crm = insn & 0xf;
5826 int op1 = (insn >> 21) & 7;
5827 int op2 = (insn >> 5) & 7;
5828 int rt = (insn >> 12) & 0xf;
5829 TCGv tmp;
5830
5831 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5832 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5833 /* TEECR */
5834 if (IS_USER(s))
5835 return 1;
5836 tmp = load_cpu_field(teecr);
5837 store_reg(s, rt, tmp);
5838 return 0;
5839 }
5840 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5841 /* TEEHBR */
5842 if (IS_USER(s) && (env->teecr & 1))
5843 return 1;
5844 tmp = load_cpu_field(teehbr);
5845 store_reg(s, rt, tmp);
5846 return 0;
5847 }
5848 }
5849 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5850 op1, crn, crm, op2);
5851 return 1;
5852 }
5853
5854 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5855 {
5856 int crn = (insn >> 16) & 0xf;
5857 int crm = insn & 0xf;
5858 int op1 = (insn >> 21) & 7;
5859 int op2 = (insn >> 5) & 7;
5860 int rt = (insn >> 12) & 0xf;
5861 TCGv tmp;
5862
5863 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
5864 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5865 /* TEECR */
5866 if (IS_USER(s))
5867 return 1;
5868 tmp = load_reg(s, rt);
5869 gen_helper_set_teecr(cpu_env, tmp);
5870 dead_tmp(tmp);
5871 return 0;
5872 }
5873 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5874 /* TEEHBR */
5875 if (IS_USER(s) && (env->teecr & 1))
5876 return 1;
5877 tmp = load_reg(s, rt);
5878 store_cpu_field(tmp, teehbr);
5879 return 0;
5880 }
5881 }
5882 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5883 op1, crn, crm, op2);
5884 return 1;
5885 }
5886
5887 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5888 {
5889 int cpnum;
5890
5891 cpnum = (insn >> 8) & 0xf;
5892 if (arm_feature(env, ARM_FEATURE_XSCALE)
5893 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
5894 return 1;
5895
5896 switch (cpnum) {
5897 case 0:
5898 case 1:
5899 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
5900 return disas_iwmmxt_insn(env, s, insn);
5901 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
5902 return disas_dsp_insn(env, s, insn);
5903 }
5904 return 1;
5905 case 10:
5906 case 11:
5907 return disas_vfp_insn (env, s, insn);
5908 case 14:
5909 /* Coprocessors 7-15 are architecturally reserved by ARM.
5910 Unfortunately Intel decided to ignore this. */
5911 if (arm_feature(env, ARM_FEATURE_XSCALE))
5912 goto board;
5913 if (insn & (1 << 20))
5914 return disas_cp14_read(env, s, insn);
5915 else
5916 return disas_cp14_write(env, s, insn);
5917 case 15:
5918 return disas_cp15_insn (env, s, insn);
5919 default:
5920 board:
5921 /* Unknown coprocessor. See if the board has hooked it. */
5922 return disas_cp_insn (env, s, insn);
5923 }
5924 }
5925
5926
5927 /* Store a 64-bit value to a register pair. Clobbers val. */
5928 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5929 {
5930 TCGv tmp;
5931 tmp = new_tmp();
5932 tcg_gen_trunc_i64_i32(tmp, val);
5933 store_reg(s, rlow, tmp);
5934 tmp = new_tmp();
5935 tcg_gen_shri_i64(val, val, 32);
5936 tcg_gen_trunc_i64_i32(tmp, val);
5937 store_reg(s, rhigh, tmp);
5938 }
5939
5940 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
5941 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5942 {
5943 TCGv_i64 tmp;
5944 TCGv tmp2;
5945
5946 /* Load value and extend to 64 bits. */
5947 tmp = tcg_temp_new_i64();
5948 tmp2 = load_reg(s, rlow);
5949 tcg_gen_extu_i32_i64(tmp, tmp2);
5950 dead_tmp(tmp2);
5951 tcg_gen_add_i64(val, val, tmp);
5952 tcg_temp_free_i64(tmp);
5953 }
5954
5955 /* load and add a 64-bit value from a register pair. */
5956 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5957 {
5958 TCGv_i64 tmp;
5959 TCGv tmpl;
5960 TCGv tmph;
5961
5962 /* Load 64-bit value rd:rn. */
5963 tmpl = load_reg(s, rlow);
5964 tmph = load_reg(s, rhigh);
5965 tmp = tcg_temp_new_i64();
5966 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
5967 dead_tmp(tmpl);
5968 dead_tmp(tmph);
5969 tcg_gen_add_i64(val, val, tmp);
5970 tcg_temp_free_i64(tmp);
5971 }
5972
5973 /* Set N and Z flags from a 64-bit value. */
5974 static void gen_logicq_cc(TCGv_i64 val)
5975 {
5976 TCGv tmp = new_tmp();
5977 gen_helper_logicq_cc(tmp, val);
5978 gen_logic_CC(tmp);
5979 dead_tmp(tmp);
5980 }
5981
5982 /* Load/Store exclusive instructions are implemented by remembering
5983 the value/address loaded, and seeing if these are the same
5984 when the store is performed. This should be is sufficient to implement
5985 the architecturally mandated semantics, and avoids having to monitor
5986 regular stores.
5987
5988 In system emulation mode only one CPU will be running at once, so
5989 this sequence is effectively atomic. In user emulation mode we
5990 throw an exception and handle the atomic operation elsewhere. */
5991 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
5992 TCGv addr, int size)
5993 {
5994 TCGv tmp;
5995
5996 switch (size) {
5997 case 0:
5998 tmp = gen_ld8u(addr, IS_USER(s));
5999 break;
6000 case 1:
6001 tmp = gen_ld16u(addr, IS_USER(s));
6002 break;
6003 case 2:
6004 case 3:
6005 tmp = gen_ld32(addr, IS_USER(s));
6006 break;
6007 default:
6008 abort();
6009 }
6010 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6011 store_reg(s, rt, tmp);
6012 if (size == 3) {
6013 TCGv tmp2 = new_tmp();
6014 tcg_gen_addi_i32(tmp2, addr, 4);
6015 tmp = gen_ld32(tmp2, IS_USER(s));
6016 dead_tmp(tmp2);
6017 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6018 store_reg(s, rt2, tmp);
6019 }
6020 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6021 }
6022
6023 static void gen_clrex(DisasContext *s)
6024 {
6025 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6026 }
6027
6028 #ifdef CONFIG_USER_ONLY
6029 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6030 TCGv addr, int size)
6031 {
6032 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6033 tcg_gen_movi_i32(cpu_exclusive_info,
6034 size | (rd << 4) | (rt << 8) | (rt2 << 12));
6035 gen_exception_insn(s, 4, EXCP_STREX);
6036 }
6037 #else
6038 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6039 TCGv addr, int size)
6040 {
6041 TCGv tmp;
6042 int done_label;
6043 int fail_label;
6044
6045 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6046 [addr] = {Rt};
6047 {Rd} = 0;
6048 } else {
6049 {Rd} = 1;
6050 } */
6051 fail_label = gen_new_label();
6052 done_label = gen_new_label();
6053 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6054 switch (size) {
6055 case 0:
6056 tmp = gen_ld8u(addr, IS_USER(s));
6057 break;
6058 case 1:
6059 tmp = gen_ld16u(addr, IS_USER(s));
6060 break;
6061 case 2:
6062 case 3:
6063 tmp = gen_ld32(addr, IS_USER(s));
6064 break;
6065 default:
6066 abort();
6067 }
6068 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6069 dead_tmp(tmp);
6070 if (size == 3) {
6071 TCGv tmp2 = new_tmp();
6072 tcg_gen_addi_i32(tmp2, addr, 4);
6073 tmp = gen_ld32(tmp2, IS_USER(s));
6074 dead_tmp(tmp2);
6075 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6076 dead_tmp(tmp);
6077 }
6078 tmp = load_reg(s, rt);
6079 switch (size) {
6080 case 0:
6081 gen_st8(tmp, addr, IS_USER(s));
6082 break;
6083 case 1:
6084 gen_st16(tmp, addr, IS_USER(s));
6085 break;
6086 case 2:
6087 case 3:
6088 gen_st32(tmp, addr, IS_USER(s));
6089 break;
6090 default:
6091 abort();
6092 }
6093 if (size == 3) {
6094 tcg_gen_addi_i32(addr, addr, 4);
6095 tmp = load_reg(s, rt2);
6096 gen_st32(tmp, addr, IS_USER(s));
6097 }
6098 tcg_gen_movi_i32(cpu_R[rd], 0);
6099 tcg_gen_br(done_label);
6100 gen_set_label(fail_label);
6101 tcg_gen_movi_i32(cpu_R[rd], 1);
6102 gen_set_label(done_label);
6103 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6104 }
6105 #endif
6106
6107 static void disas_arm_insn(CPUState * env, DisasContext *s)
6108 {
6109 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6110 TCGv tmp;
6111 TCGv tmp2;
6112 TCGv tmp3;
6113 TCGv addr;
6114 TCGv_i64 tmp64;
6115
6116 insn = ldl_code(s->pc);
6117 s->pc += 4;
6118
6119 /* M variants do not implement ARM mode. */
6120 if (IS_M(env))
6121 goto illegal_op;
6122 cond = insn >> 28;
6123 if (cond == 0xf){
6124 /* Unconditional instructions. */
6125 if (((insn >> 25) & 7) == 1) {
6126 /* NEON Data processing. */
6127 if (!arm_feature(env, ARM_FEATURE_NEON))
6128 goto illegal_op;
6129
6130 if (disas_neon_data_insn(env, s, insn))
6131 goto illegal_op;
6132 return;
6133 }
6134 if ((insn & 0x0f100000) == 0x04000000) {
6135 /* NEON load/store. */
6136 if (!arm_feature(env, ARM_FEATURE_NEON))
6137 goto illegal_op;
6138
6139 if (disas_neon_ls_insn(env, s, insn))
6140 goto illegal_op;
6141 return;
6142 }
6143 if (((insn & 0x0f30f000) == 0x0510f000) ||
6144 ((insn & 0x0f30f010) == 0x0710f000)) {
6145 if ((insn & (1 << 22)) == 0) {
6146 /* PLDW; v7MP */
6147 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6148 goto illegal_op;
6149 }
6150 }
6151 /* Otherwise PLD; v5TE+ */
6152 return;
6153 }
6154 if (((insn & 0x0f70f000) == 0x0450f000) ||
6155 ((insn & 0x0f70f010) == 0x0650f000)) {
6156 ARCH(7);
6157 return; /* PLI; V7 */
6158 }
6159 if (((insn & 0x0f700000) == 0x04100000) ||
6160 ((insn & 0x0f700010) == 0x06100000)) {
6161 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6162 goto illegal_op;
6163 }
6164 return; /* v7MP: Unallocated memory hint: must NOP */
6165 }
6166
6167 if ((insn & 0x0ffffdff) == 0x01010000) {
6168 ARCH(6);
6169 /* setend */
6170 if (insn & (1 << 9)) {
6171 /* BE8 mode not implemented. */
6172 goto illegal_op;
6173 }
6174 return;
6175 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6176 switch ((insn >> 4) & 0xf) {
6177 case 1: /* clrex */
6178 ARCH(6K);
6179 gen_clrex(s);
6180 return;
6181 case 4: /* dsb */
6182 case 5: /* dmb */
6183 case 6: /* isb */
6184 ARCH(7);
6185 /* We don't emulate caches so these are a no-op. */
6186 return;
6187 default:
6188 goto illegal_op;
6189 }
6190 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6191 /* srs */
6192 int32_t offset;
6193 if (IS_USER(s))
6194 goto illegal_op;
6195 ARCH(6);
6196 op1 = (insn & 0x1f);
6197 addr = new_tmp();
6198 tmp = tcg_const_i32(op1);
6199 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6200 tcg_temp_free_i32(tmp);
6201 i = (insn >> 23) & 3;
6202 switch (i) {
6203 case 0: offset = -4; break; /* DA */
6204 case 1: offset = 0; break; /* IA */
6205 case 2: offset = -8; break; /* DB */
6206 case 3: offset = 4; break; /* IB */
6207 default: abort();
6208 }
6209 if (offset)
6210 tcg_gen_addi_i32(addr, addr, offset);
6211 tmp = load_reg(s, 14);
6212 gen_st32(tmp, addr, 0);
6213 tmp = load_cpu_field(spsr);
6214 tcg_gen_addi_i32(addr, addr, 4);
6215 gen_st32(tmp, addr, 0);
6216 if (insn & (1 << 21)) {
6217 /* Base writeback. */
6218 switch (i) {
6219 case 0: offset = -8; break;
6220 case 1: offset = 4; break;
6221 case 2: offset = -4; break;
6222 case 3: offset = 0; break;
6223 default: abort();
6224 }
6225 if (offset)
6226 tcg_gen_addi_i32(addr, addr, offset);
6227 tmp = tcg_const_i32(op1);
6228 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6229 tcg_temp_free_i32(tmp);
6230 dead_tmp(addr);
6231 } else {
6232 dead_tmp(addr);
6233 }
6234 return;
6235 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6236 /* rfe */
6237 int32_t offset;
6238 if (IS_USER(s))
6239 goto illegal_op;
6240 ARCH(6);
6241 rn = (insn >> 16) & 0xf;
6242 addr = load_reg(s, rn);
6243 i = (insn >> 23) & 3;
6244 switch (i) {
6245 case 0: offset = -4; break; /* DA */
6246 case 1: offset = 0; break; /* IA */
6247 case 2: offset = -8; break; /* DB */
6248 case 3: offset = 4; break; /* IB */
6249 default: abort();
6250 }
6251 if (offset)
6252 tcg_gen_addi_i32(addr, addr, offset);
6253 /* Load PC into tmp and CPSR into tmp2. */
6254 tmp = gen_ld32(addr, 0);
6255 tcg_gen_addi_i32(addr, addr, 4);
6256 tmp2 = gen_ld32(addr, 0);
6257 if (insn & (1 << 21)) {
6258 /* Base writeback. */
6259 switch (i) {
6260 case 0: offset = -8; break;
6261 case 1: offset = 4; break;
6262 case 2: offset = -4; break;
6263 case 3: offset = 0; break;
6264 default: abort();
6265 }
6266 if (offset)
6267 tcg_gen_addi_i32(addr, addr, offset);
6268 store_reg(s, rn, addr);
6269 } else {
6270 dead_tmp(addr);
6271 }
6272 gen_rfe(s, tmp, tmp2);
6273 return;
6274 } else if ((insn & 0x0e000000) == 0x0a000000) {
6275 /* branch link and change to thumb (blx <offset>) */
6276 int32_t offset;
6277
6278 val = (uint32_t)s->pc;
6279 tmp = new_tmp();
6280 tcg_gen_movi_i32(tmp, val);
6281 store_reg(s, 14, tmp);
6282 /* Sign-extend the 24-bit offset */
6283 offset = (((int32_t)insn) << 8) >> 8;
6284 /* offset * 4 + bit24 * 2 + (thumb bit) */
6285 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6286 /* pipeline offset */
6287 val += 4;
6288 gen_bx_im(s, val);
6289 return;
6290 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6291 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6292 /* iWMMXt register transfer. */
6293 if (env->cp15.c15_cpar & (1 << 1))
6294 if (!disas_iwmmxt_insn(env, s, insn))
6295 return;
6296 }
6297 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6298 /* Coprocessor double register transfer. */
6299 } else if ((insn & 0x0f000010) == 0x0e000010) {
6300 /* Additional coprocessor register transfer. */
6301 } else if ((insn & 0x0ff10020) == 0x01000000) {
6302 uint32_t mask;
6303 uint32_t val;
6304 /* cps (privileged) */
6305 if (IS_USER(s))
6306 return;
6307 mask = val = 0;
6308 if (insn & (1 << 19)) {
6309 if (insn & (1 << 8))
6310 mask |= CPSR_A;
6311 if (insn & (1 << 7))
6312 mask |= CPSR_I;
6313 if (insn & (1 << 6))
6314 mask |= CPSR_F;
6315 if (insn & (1 << 18))
6316 val |= mask;
6317 }
6318 if (insn & (1 << 17)) {
6319 mask |= CPSR_M;
6320 val |= (insn & 0x1f);
6321 }
6322 if (mask) {
6323 gen_set_psr_im(s, mask, 0, val);
6324 }
6325 return;
6326 }
6327 goto illegal_op;
6328 }
6329 if (cond != 0xe) {
6330 /* if not always execute, we generate a conditional jump to
6331 next instruction */
6332 s->condlabel = gen_new_label();
6333 gen_test_cc(cond ^ 1, s->condlabel);
6334 s->condjmp = 1;
6335 }
6336 if ((insn & 0x0f900000) == 0x03000000) {
6337 if ((insn & (1 << 21)) == 0) {
6338 ARCH(6T2);
6339 rd = (insn >> 12) & 0xf;
6340 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6341 if ((insn & (1 << 22)) == 0) {
6342 /* MOVW */
6343 tmp = new_tmp();
6344 tcg_gen_movi_i32(tmp, val);
6345 } else {
6346 /* MOVT */
6347 tmp = load_reg(s, rd);
6348 tcg_gen_ext16u_i32(tmp, tmp);
6349 tcg_gen_ori_i32(tmp, tmp, val << 16);
6350 }
6351 store_reg(s, rd, tmp);
6352 } else {
6353 if (((insn >> 12) & 0xf) != 0xf)
6354 goto illegal_op;
6355 if (((insn >> 16) & 0xf) == 0) {
6356 gen_nop_hint(s, insn & 0xff);
6357 } else {
6358 /* CPSR = immediate */
6359 val = insn & 0xff;
6360 shift = ((insn >> 8) & 0xf) * 2;
6361 if (shift)
6362 val = (val >> shift) | (val << (32 - shift));
6363 i = ((insn & (1 << 22)) != 0);
6364 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6365 goto illegal_op;
6366 }
6367 }
6368 } else if ((insn & 0x0f900000) == 0x01000000
6369 && (insn & 0x00000090) != 0x00000090) {
6370 /* miscellaneous instructions */
6371 op1 = (insn >> 21) & 3;
6372 sh = (insn >> 4) & 0xf;
6373 rm = insn & 0xf;
6374 switch (sh) {
6375 case 0x0: /* move program status register */
6376 if (op1 & 1) {
6377 /* PSR = reg */
6378 tmp = load_reg(s, rm);
6379 i = ((op1 & 2) != 0);
6380 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6381 goto illegal_op;
6382 } else {
6383 /* reg = PSR */
6384 rd = (insn >> 12) & 0xf;
6385 if (op1 & 2) {
6386 if (IS_USER(s))
6387 goto illegal_op;
6388 tmp = load_cpu_field(spsr);
6389 } else {
6390 tmp = new_tmp();
6391 gen_helper_cpsr_read(tmp);
6392 }
6393 store_reg(s, rd, tmp);
6394 }
6395 break;
6396 case 0x1:
6397 if (op1 == 1) {
6398 /* branch/exchange thumb (bx). */
6399 tmp = load_reg(s, rm);
6400 gen_bx(s, tmp);
6401 } else if (op1 == 3) {
6402 /* clz */
6403 rd = (insn >> 12) & 0xf;
6404 tmp = load_reg(s, rm);
6405 gen_helper_clz(tmp, tmp);
6406 store_reg(s, rd, tmp);
6407 } else {
6408 goto illegal_op;
6409 }
6410 break;
6411 case 0x2:
6412 if (op1 == 1) {
6413 ARCH(5J); /* bxj */
6414 /* Trivial implementation equivalent to bx. */
6415 tmp = load_reg(s, rm);
6416 gen_bx(s, tmp);
6417 } else {
6418 goto illegal_op;
6419 }
6420 break;
6421 case 0x3:
6422 if (op1 != 1)
6423 goto illegal_op;
6424
6425 /* branch link/exchange thumb (blx) */
6426 tmp = load_reg(s, rm);
6427 tmp2 = new_tmp();
6428 tcg_gen_movi_i32(tmp2, s->pc);
6429 store_reg(s, 14, tmp2);
6430 gen_bx(s, tmp);
6431 break;
6432 case 0x5: /* saturating add/subtract */
6433 rd = (insn >> 12) & 0xf;
6434 rn = (insn >> 16) & 0xf;
6435 tmp = load_reg(s, rm);
6436 tmp2 = load_reg(s, rn);
6437 if (op1 & 2)
6438 gen_helper_double_saturate(tmp2, tmp2);
6439 if (op1 & 1)
6440 gen_helper_sub_saturate(tmp, tmp, tmp2);
6441 else
6442 gen_helper_add_saturate(tmp, tmp, tmp2);
6443 dead_tmp(tmp2);
6444 store_reg(s, rd, tmp);
6445 break;
6446 case 7:
6447 /* SMC instruction (op1 == 3)
6448 and undefined instructions (op1 == 0 || op1 == 2)
6449 will trap */
6450 if (op1 != 1) {
6451 goto illegal_op;
6452 }
6453 /* bkpt */
6454 gen_exception_insn(s, 4, EXCP_BKPT);
6455 break;
6456 case 0x8: /* signed multiply */
6457 case 0xa:
6458 case 0xc:
6459 case 0xe:
6460 rs = (insn >> 8) & 0xf;
6461 rn = (insn >> 12) & 0xf;
6462 rd = (insn >> 16) & 0xf;
6463 if (op1 == 1) {
6464 /* (32 * 16) >> 16 */
6465 tmp = load_reg(s, rm);
6466 tmp2 = load_reg(s, rs);
6467 if (sh & 4)
6468 tcg_gen_sari_i32(tmp2, tmp2, 16);
6469 else
6470 gen_sxth(tmp2);
6471 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6472 tcg_gen_shri_i64(tmp64, tmp64, 16);
6473 tmp = new_tmp();
6474 tcg_gen_trunc_i64_i32(tmp, tmp64);
6475 tcg_temp_free_i64(tmp64);
6476 if ((sh & 2) == 0) {
6477 tmp2 = load_reg(s, rn);
6478 gen_helper_add_setq(tmp, tmp, tmp2);
6479 dead_tmp(tmp2);
6480 }
6481 store_reg(s, rd, tmp);
6482 } else {
6483 /* 16 * 16 */
6484 tmp = load_reg(s, rm);
6485 tmp2 = load_reg(s, rs);
6486 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6487 dead_tmp(tmp2);
6488 if (op1 == 2) {
6489 tmp64 = tcg_temp_new_i64();
6490 tcg_gen_ext_i32_i64(tmp64, tmp);
6491 dead_tmp(tmp);
6492 gen_addq(s, tmp64, rn, rd);
6493 gen_storeq_reg(s, rn, rd, tmp64);
6494 tcg_temp_free_i64(tmp64);
6495 } else {
6496 if (op1 == 0) {
6497 tmp2 = load_reg(s, rn);
6498 gen_helper_add_setq(tmp, tmp, tmp2);
6499 dead_tmp(tmp2);
6500 }
6501 store_reg(s, rd, tmp);
6502 }
6503 }
6504 break;
6505 default:
6506 goto illegal_op;
6507 }
6508 } else if (((insn & 0x0e000000) == 0 &&
6509 (insn & 0x00000090) != 0x90) ||
6510 ((insn & 0x0e000000) == (1 << 25))) {
6511 int set_cc, logic_cc, shiftop;
6512
6513 op1 = (insn >> 21) & 0xf;
6514 set_cc = (insn >> 20) & 1;
6515 logic_cc = table_logic_cc[op1] & set_cc;
6516
6517 /* data processing instruction */
6518 if (insn & (1 << 25)) {
6519 /* immediate operand */
6520 val = insn & 0xff;
6521 shift = ((insn >> 8) & 0xf) * 2;
6522 if (shift) {
6523 val = (val >> shift) | (val << (32 - shift));
6524 }
6525 tmp2 = new_tmp();
6526 tcg_gen_movi_i32(tmp2, val);
6527 if (logic_cc && shift) {
6528 gen_set_CF_bit31(tmp2);
6529 }
6530 } else {
6531 /* register */
6532 rm = (insn) & 0xf;
6533 tmp2 = load_reg(s, rm);
6534 shiftop = (insn >> 5) & 3;
6535 if (!(insn & (1 << 4))) {
6536 shift = (insn >> 7) & 0x1f;
6537 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6538 } else {
6539 rs = (insn >> 8) & 0xf;
6540 tmp = load_reg(s, rs);
6541 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6542 }
6543 }
6544 if (op1 != 0x0f && op1 != 0x0d) {
6545 rn = (insn >> 16) & 0xf;
6546 tmp = load_reg(s, rn);
6547 } else {
6548 TCGV_UNUSED(tmp);
6549 }
6550 rd = (insn >> 12) & 0xf;
6551 switch(op1) {
6552 case 0x00:
6553 tcg_gen_and_i32(tmp, tmp, tmp2);
6554 if (logic_cc) {
6555 gen_logic_CC(tmp);
6556 }
6557 store_reg_bx(env, s, rd, tmp);
6558 break;
6559 case 0x01:
6560 tcg_gen_xor_i32(tmp, tmp, tmp2);
6561 if (logic_cc) {
6562 gen_logic_CC(tmp);
6563 }
6564 store_reg_bx(env, s, rd, tmp);
6565 break;
6566 case 0x02:
6567 if (set_cc && rd == 15) {
6568 /* SUBS r15, ... is used for exception return. */
6569 if (IS_USER(s)) {
6570 goto illegal_op;
6571 }
6572 gen_helper_sub_cc(tmp, tmp, tmp2);
6573 gen_exception_return(s, tmp);
6574 } else {
6575 if (set_cc) {
6576 gen_helper_sub_cc(tmp, tmp, tmp2);
6577 } else {
6578 tcg_gen_sub_i32(tmp, tmp, tmp2);
6579 }
6580 store_reg_bx(env, s, rd, tmp);
6581 }
6582 break;
6583 case 0x03:
6584 if (set_cc) {
6585 gen_helper_sub_cc(tmp, tmp2, tmp);
6586 } else {
6587 tcg_gen_sub_i32(tmp, tmp2, tmp);
6588 }
6589 store_reg_bx(env, s, rd, tmp);
6590 break;
6591 case 0x04:
6592 if (set_cc) {
6593 gen_helper_add_cc(tmp, tmp, tmp2);
6594 } else {
6595 tcg_gen_add_i32(tmp, tmp, tmp2);
6596 }
6597 store_reg_bx(env, s, rd, tmp);
6598 break;
6599 case 0x05:
6600 if (set_cc) {
6601 gen_helper_adc_cc(tmp, tmp, tmp2);
6602 } else {
6603 gen_add_carry(tmp, tmp, tmp2);
6604 }
6605 store_reg_bx(env, s, rd, tmp);
6606 break;
6607 case 0x06:
6608 if (set_cc) {
6609 gen_helper_sbc_cc(tmp, tmp, tmp2);
6610 } else {
6611 gen_sub_carry(tmp, tmp, tmp2);
6612 }
6613 store_reg_bx(env, s, rd, tmp);
6614 break;
6615 case 0x07:
6616 if (set_cc) {
6617 gen_helper_sbc_cc(tmp, tmp2, tmp);
6618 } else {
6619 gen_sub_carry(tmp, tmp2, tmp);
6620 }
6621 store_reg_bx(env, s, rd, tmp);
6622 break;
6623 case 0x08:
6624 if (set_cc) {
6625 tcg_gen_and_i32(tmp, tmp, tmp2);
6626 gen_logic_CC(tmp);
6627 }
6628 dead_tmp(tmp);
6629 break;
6630 case 0x09:
6631 if (set_cc) {
6632 tcg_gen_xor_i32(tmp, tmp, tmp2);
6633 gen_logic_CC(tmp);
6634 }
6635 dead_tmp(tmp);
6636 break;
6637 case 0x0a:
6638 if (set_cc) {
6639 gen_helper_sub_cc(tmp, tmp, tmp2);
6640 }
6641 dead_tmp(tmp);
6642 break;
6643 case 0x0b:
6644 if (set_cc) {
6645 gen_helper_add_cc(tmp, tmp, tmp2);
6646 }
6647 dead_tmp(tmp);
6648 break;
6649 case 0x0c:
6650 tcg_gen_or_i32(tmp, tmp, tmp2);
6651 if (logic_cc) {
6652 gen_logic_CC(tmp);
6653 }
6654 store_reg_bx(env, s, rd, tmp);
6655 break;
6656 case 0x0d:
6657 if (logic_cc && rd == 15) {
6658 /* MOVS r15, ... is used for exception return. */
6659 if (IS_USER(s)) {
6660 goto illegal_op;
6661 }
6662 gen_exception_return(s, tmp2);
6663 } else {
6664 if (logic_cc) {
6665 gen_logic_CC(tmp2);
6666 }
6667 store_reg_bx(env, s, rd, tmp2);
6668 }
6669 break;
6670 case 0x0e:
6671 tcg_gen_andc_i32(tmp, tmp, tmp2);
6672 if (logic_cc) {
6673 gen_logic_CC(tmp);
6674 }
6675 store_reg_bx(env, s, rd, tmp);
6676 break;
6677 default:
6678 case 0x0f:
6679 tcg_gen_not_i32(tmp2, tmp2);
6680 if (logic_cc) {
6681 gen_logic_CC(tmp2);
6682 }
6683 store_reg_bx(env, s, rd, tmp2);
6684 break;
6685 }
6686 if (op1 != 0x0f && op1 != 0x0d) {
6687 dead_tmp(tmp2);
6688 }
6689 } else {
6690 /* other instructions */
6691 op1 = (insn >> 24) & 0xf;
6692 switch(op1) {
6693 case 0x0:
6694 case 0x1:
6695 /* multiplies, extra load/stores */
6696 sh = (insn >> 5) & 3;
6697 if (sh == 0) {
6698 if (op1 == 0x0) {
6699 rd = (insn >> 16) & 0xf;
6700 rn = (insn >> 12) & 0xf;
6701 rs = (insn >> 8) & 0xf;
6702 rm = (insn) & 0xf;
6703 op1 = (insn >> 20) & 0xf;
6704 switch (op1) {
6705 case 0: case 1: case 2: case 3: case 6:
6706 /* 32 bit mul */
6707 tmp = load_reg(s, rs);
6708 tmp2 = load_reg(s, rm);
6709 tcg_gen_mul_i32(tmp, tmp, tmp2);
6710 dead_tmp(tmp2);
6711 if (insn & (1 << 22)) {
6712 /* Subtract (mls) */
6713 ARCH(6T2);
6714 tmp2 = load_reg(s, rn);
6715 tcg_gen_sub_i32(tmp, tmp2, tmp);
6716 dead_tmp(tmp2);
6717 } else if (insn & (1 << 21)) {
6718 /* Add */
6719 tmp2 = load_reg(s, rn);
6720 tcg_gen_add_i32(tmp, tmp, tmp2);
6721 dead_tmp(tmp2);
6722 }
6723 if (insn & (1 << 20))
6724 gen_logic_CC(tmp);
6725 store_reg(s, rd, tmp);
6726 break;
6727 case 4:
6728 /* 64 bit mul double accumulate (UMAAL) */
6729 ARCH(6);
6730 tmp = load_reg(s, rs);
6731 tmp2 = load_reg(s, rm);
6732 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6733 gen_addq_lo(s, tmp64, rn);
6734 gen_addq_lo(s, tmp64, rd);
6735 gen_storeq_reg(s, rn, rd, tmp64);
6736 tcg_temp_free_i64(tmp64);
6737 break;
6738 case 8: case 9: case 10: case 11:
6739 case 12: case 13: case 14: case 15:
6740 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
6741 tmp = load_reg(s, rs);
6742 tmp2 = load_reg(s, rm);
6743 if (insn & (1 << 22)) {
6744 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6745 } else {
6746 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
6747 }
6748 if (insn & (1 << 21)) { /* mult accumulate */
6749 gen_addq(s, tmp64, rn, rd);
6750 }
6751 if (insn & (1 << 20)) {
6752 gen_logicq_cc(tmp64);
6753 }
6754 gen_storeq_reg(s, rn, rd, tmp64);
6755 tcg_temp_free_i64(tmp64);
6756 break;
6757 default:
6758 goto illegal_op;
6759 }
6760 } else {
6761 rn = (insn >> 16) & 0xf;
6762 rd = (insn >> 12) & 0xf;
6763 if (insn & (1 << 23)) {
6764 /* load/store exclusive */
6765 op1 = (insn >> 21) & 0x3;
6766 if (op1)
6767 ARCH(6K);
6768 else
6769 ARCH(6);
6770 addr = tcg_temp_local_new_i32();
6771 load_reg_var(s, addr, rn);
6772 if (insn & (1 << 20)) {
6773 switch (op1) {
6774 case 0: /* ldrex */
6775 gen_load_exclusive(s, rd, 15, addr, 2);
6776 break;
6777 case 1: /* ldrexd */
6778 gen_load_exclusive(s, rd, rd + 1, addr, 3);
6779 break;
6780 case 2: /* ldrexb */
6781 gen_load_exclusive(s, rd, 15, addr, 0);
6782 break;
6783 case 3: /* ldrexh */
6784 gen_load_exclusive(s, rd, 15, addr, 1);
6785 break;
6786 default:
6787 abort();
6788 }
6789 } else {
6790 rm = insn & 0xf;
6791 switch (op1) {
6792 case 0: /* strex */
6793 gen_store_exclusive(s, rd, rm, 15, addr, 2);
6794 break;
6795 case 1: /* strexd */
6796 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
6797 break;
6798 case 2: /* strexb */
6799 gen_store_exclusive(s, rd, rm, 15, addr, 0);
6800 break;
6801 case 3: /* strexh */
6802 gen_store_exclusive(s, rd, rm, 15, addr, 1);
6803 break;
6804 default:
6805 abort();
6806 }
6807 }
6808 tcg_temp_free(addr);
6809 } else {
6810 /* SWP instruction */
6811 rm = (insn) & 0xf;
6812
6813 /* ??? This is not really atomic. However we know
6814 we never have multiple CPUs running in parallel,
6815 so it is good enough. */
6816 addr = load_reg(s, rn);
6817 tmp = load_reg(s, rm);
6818 if (insn & (1 << 22)) {
6819 tmp2 = gen_ld8u(addr, IS_USER(s));
6820 gen_st8(tmp, addr, IS_USER(s));
6821 } else {
6822 tmp2 = gen_ld32(addr, IS_USER(s));
6823 gen_st32(tmp, addr, IS_USER(s));
6824 }
6825 dead_tmp(addr);
6826 store_reg(s, rd, tmp2);
6827 }
6828 }
6829 } else {
6830 int address_offset;
6831 int load;
6832 /* Misc load/store */
6833 rn = (insn >> 16) & 0xf;
6834 rd = (insn >> 12) & 0xf;
6835 addr = load_reg(s, rn);
6836 if (insn & (1 << 24))
6837 gen_add_datah_offset(s, insn, 0, addr);
6838 address_offset = 0;
6839 if (insn & (1 << 20)) {
6840 /* load */
6841 switch(sh) {
6842 case 1:
6843 tmp = gen_ld16u(addr, IS_USER(s));
6844 break;
6845 case 2:
6846 tmp = gen_ld8s(addr, IS_USER(s));
6847 break;
6848 default:
6849 case 3:
6850 tmp = gen_ld16s(addr, IS_USER(s));
6851 break;
6852 }
6853 load = 1;
6854 } else if (sh & 2) {
6855 /* doubleword */
6856 if (sh & 1) {
6857 /* store */
6858 tmp = load_reg(s, rd);
6859 gen_st32(tmp, addr, IS_USER(s));
6860 tcg_gen_addi_i32(addr, addr, 4);
6861 tmp = load_reg(s, rd + 1);
6862 gen_st32(tmp, addr, IS_USER(s));
6863 load = 0;
6864 } else {
6865 /* load */
6866 tmp = gen_ld32(addr, IS_USER(s));
6867 store_reg(s, rd, tmp);
6868 tcg_gen_addi_i32(addr, addr, 4);
6869 tmp = gen_ld32(addr, IS_USER(s));
6870 rd++;
6871 load = 1;
6872 }
6873 address_offset = -4;
6874 } else {
6875 /* store */
6876 tmp = load_reg(s, rd);
6877 gen_st16(tmp, addr, IS_USER(s));
6878 load = 0;
6879 }
6880 /* Perform base writeback before the loaded value to
6881 ensure correct behavior with overlapping index registers.
6882 ldrd with base writeback is is undefined if the
6883 destination and index registers overlap. */
6884 if (!(insn & (1 << 24))) {
6885 gen_add_datah_offset(s, insn, address_offset, addr);
6886 store_reg(s, rn, addr);
6887 } else if (insn & (1 << 21)) {
6888 if (address_offset)
6889 tcg_gen_addi_i32(addr, addr, address_offset);
6890 store_reg(s, rn, addr);
6891 } else {
6892 dead_tmp(addr);
6893 }
6894 if (load) {
6895 /* Complete the load. */
6896 store_reg(s, rd, tmp);
6897 }
6898 }
6899 break;
6900 case 0x4:
6901 case 0x5:
6902 goto do_ldst;
6903 case 0x6:
6904 case 0x7:
6905 if (insn & (1 << 4)) {
6906 ARCH(6);
6907 /* Armv6 Media instructions. */
6908 rm = insn & 0xf;
6909 rn = (insn >> 16) & 0xf;
6910 rd = (insn >> 12) & 0xf;
6911 rs = (insn >> 8) & 0xf;
6912 switch ((insn >> 23) & 3) {
6913 case 0: /* Parallel add/subtract. */
6914 op1 = (insn >> 20) & 7;
6915 tmp = load_reg(s, rn);
6916 tmp2 = load_reg(s, rm);
6917 sh = (insn >> 5) & 7;
6918 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6919 goto illegal_op;
6920 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6921 dead_tmp(tmp2);
6922 store_reg(s, rd, tmp);
6923 break;
6924 case 1:
6925 if ((insn & 0x00700020) == 0) {
6926 /* Halfword pack. */
6927 tmp = load_reg(s, rn);
6928 tmp2 = load_reg(s, rm);
6929 shift = (insn >> 7) & 0x1f;
6930 if (insn & (1 << 6)) {
6931 /* pkhtb */
6932 if (shift == 0)
6933 shift = 31;
6934 tcg_gen_sari_i32(tmp2, tmp2, shift);
6935 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
6936 tcg_gen_ext16u_i32(tmp2, tmp2);
6937 } else {
6938 /* pkhbt */
6939 if (shift)
6940 tcg_gen_shli_i32(tmp2, tmp2, shift);
6941 tcg_gen_ext16u_i32(tmp, tmp);
6942 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
6943 }
6944 tcg_gen_or_i32(tmp, tmp, tmp2);
6945 dead_tmp(tmp2);
6946 store_reg(s, rd, tmp);
6947 } else if ((insn & 0x00200020) == 0x00200000) {
6948 /* [us]sat */
6949 tmp = load_reg(s, rm);
6950 shift = (insn >> 7) & 0x1f;
6951 if (insn & (1 << 6)) {
6952 if (shift == 0)
6953 shift = 31;
6954 tcg_gen_sari_i32(tmp, tmp, shift);
6955 } else {
6956 tcg_gen_shli_i32(tmp, tmp, shift);
6957 }
6958 sh = (insn >> 16) & 0x1f;
6959 tmp2 = tcg_const_i32(sh);
6960 if (insn & (1 << 22))
6961 gen_helper_usat(tmp, tmp, tmp2);
6962 else
6963 gen_helper_ssat(tmp, tmp, tmp2);
6964 tcg_temp_free_i32(tmp2);
6965 store_reg(s, rd, tmp);
6966 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6967 /* [us]sat16 */
6968 tmp = load_reg(s, rm);
6969 sh = (insn >> 16) & 0x1f;
6970 tmp2 = tcg_const_i32(sh);
6971 if (insn & (1 << 22))
6972 gen_helper_usat16(tmp, tmp, tmp2);
6973 else
6974 gen_helper_ssat16(tmp, tmp, tmp2);
6975 tcg_temp_free_i32(tmp2);
6976 store_reg(s, rd, tmp);
6977 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6978 /* Select bytes. */
6979 tmp = load_reg(s, rn);
6980 tmp2 = load_reg(s, rm);
6981 tmp3 = new_tmp();
6982 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
6983 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
6984 dead_tmp(tmp3);
6985 dead_tmp(tmp2);
6986 store_reg(s, rd, tmp);
6987 } else if ((insn & 0x000003e0) == 0x00000060) {
6988 tmp = load_reg(s, rm);
6989 shift = (insn >> 10) & 3;
6990 /* ??? In many cases it's not neccessary to do a
6991 rotate, a shift is sufficient. */
6992 if (shift != 0)
6993 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
6994 op1 = (insn >> 20) & 7;
6995 switch (op1) {
6996 case 0: gen_sxtb16(tmp); break;
6997 case 2: gen_sxtb(tmp); break;
6998 case 3: gen_sxth(tmp); break;
6999 case 4: gen_uxtb16(tmp); break;
7000 case 6: gen_uxtb(tmp); break;
7001 case 7: gen_uxth(tmp); break;
7002 default: goto illegal_op;
7003 }
7004 if (rn != 15) {
7005 tmp2 = load_reg(s, rn);
7006 if ((op1 & 3) == 0) {
7007 gen_add16(tmp, tmp2);
7008 } else {
7009 tcg_gen_add_i32(tmp, tmp, tmp2);
7010 dead_tmp(tmp2);
7011 }
7012 }
7013 store_reg(s, rd, tmp);
7014 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7015 /* rev */
7016 tmp = load_reg(s, rm);
7017 if (insn & (1 << 22)) {
7018 if (insn & (1 << 7)) {
7019 gen_revsh(tmp);
7020 } else {
7021 ARCH(6T2);
7022 gen_helper_rbit(tmp, tmp);
7023 }
7024 } else {
7025 if (insn & (1 << 7))
7026 gen_rev16(tmp);
7027 else
7028 tcg_gen_bswap32_i32(tmp, tmp);
7029 }
7030 store_reg(s, rd, tmp);
7031 } else {
7032 goto illegal_op;
7033 }
7034 break;
7035 case 2: /* Multiplies (Type 3). */
7036 tmp = load_reg(s, rm);
7037 tmp2 = load_reg(s, rs);
7038 if (insn & (1 << 20)) {
7039 /* Signed multiply most significant [accumulate].
7040 (SMMUL, SMMLA, SMMLS) */
7041 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7042
7043 if (rd != 15) {
7044 tmp = load_reg(s, rd);
7045 if (insn & (1 << 6)) {
7046 tmp64 = gen_subq_msw(tmp64, tmp);
7047 } else {
7048 tmp64 = gen_addq_msw(tmp64, tmp);
7049 }
7050 }
7051 if (insn & (1 << 5)) {
7052 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7053 }
7054 tcg_gen_shri_i64(tmp64, tmp64, 32);
7055 tmp = new_tmp();
7056 tcg_gen_trunc_i64_i32(tmp, tmp64);
7057 tcg_temp_free_i64(tmp64);
7058 store_reg(s, rn, tmp);
7059 } else {
7060 if (insn & (1 << 5))
7061 gen_swap_half(tmp2);
7062 gen_smul_dual(tmp, tmp2);
7063 /* This addition cannot overflow. */
7064 if (insn & (1 << 6)) {
7065 tcg_gen_sub_i32(tmp, tmp, tmp2);
7066 } else {
7067 tcg_gen_add_i32(tmp, tmp, tmp2);
7068 }
7069 dead_tmp(tmp2);
7070 if (insn & (1 << 22)) {
7071 /* smlald, smlsld */
7072 tmp64 = tcg_temp_new_i64();
7073 tcg_gen_ext_i32_i64(tmp64, tmp);
7074 dead_tmp(tmp);
7075 gen_addq(s, tmp64, rd, rn);
7076 gen_storeq_reg(s, rd, rn, tmp64);
7077 tcg_temp_free_i64(tmp64);
7078 } else {
7079 /* smuad, smusd, smlad, smlsd */
7080 if (rd != 15)
7081 {
7082 tmp2 = load_reg(s, rd);
7083 gen_helper_add_setq(tmp, tmp, tmp2);
7084 dead_tmp(tmp2);
7085 }
7086 store_reg(s, rn, tmp);
7087 }
7088 }
7089 break;
7090 case 3:
7091 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7092 switch (op1) {
7093 case 0: /* Unsigned sum of absolute differences. */
7094 ARCH(6);
7095 tmp = load_reg(s, rm);
7096 tmp2 = load_reg(s, rs);
7097 gen_helper_usad8(tmp, tmp, tmp2);
7098 dead_tmp(tmp2);
7099 if (rd != 15) {
7100 tmp2 = load_reg(s, rd);
7101 tcg_gen_add_i32(tmp, tmp, tmp2);
7102 dead_tmp(tmp2);
7103 }
7104 store_reg(s, rn, tmp);
7105 break;
7106 case 0x20: case 0x24: case 0x28: case 0x2c:
7107 /* Bitfield insert/clear. */
7108 ARCH(6T2);
7109 shift = (insn >> 7) & 0x1f;
7110 i = (insn >> 16) & 0x1f;
7111 i = i + 1 - shift;
7112 if (rm == 15) {
7113 tmp = new_tmp();
7114 tcg_gen_movi_i32(tmp, 0);
7115 } else {
7116 tmp = load_reg(s, rm);
7117 }
7118 if (i != 32) {
7119 tmp2 = load_reg(s, rd);
7120 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7121 dead_tmp(tmp2);
7122 }
7123 store_reg(s, rd, tmp);
7124 break;
7125 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7126 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7127 ARCH(6T2);
7128 tmp = load_reg(s, rm);
7129 shift = (insn >> 7) & 0x1f;
7130 i = ((insn >> 16) & 0x1f) + 1;
7131 if (shift + i > 32)
7132 goto illegal_op;
7133 if (i < 32) {
7134 if (op1 & 0x20) {
7135 gen_ubfx(tmp, shift, (1u << i) - 1);
7136 } else {
7137 gen_sbfx(tmp, shift, i);
7138 }
7139 }
7140 store_reg(s, rd, tmp);
7141 break;
7142 default:
7143 goto illegal_op;
7144 }
7145 break;
7146 }
7147 break;
7148 }
7149 do_ldst:
7150 /* Check for undefined extension instructions
7151 * per the ARM Bible IE:
7152 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7153 */
7154 sh = (0xf << 20) | (0xf << 4);
7155 if (op1 == 0x7 && ((insn & sh) == sh))
7156 {
7157 goto illegal_op;
7158 }
7159 /* load/store byte/word */
7160 rn = (insn >> 16) & 0xf;
7161 rd = (insn >> 12) & 0xf;
7162 tmp2 = load_reg(s, rn);
7163 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7164 if (insn & (1 << 24))
7165 gen_add_data_offset(s, insn, tmp2);
7166 if (insn & (1 << 20)) {
7167 /* load */
7168 if (insn & (1 << 22)) {
7169 tmp = gen_ld8u(tmp2, i);
7170 } else {
7171 tmp = gen_ld32(tmp2, i);
7172 }
7173 } else {
7174 /* store */
7175 tmp = load_reg(s, rd);
7176 if (insn & (1 << 22))
7177 gen_st8(tmp, tmp2, i);
7178 else
7179 gen_st32(tmp, tmp2, i);
7180 }
7181 if (!(insn & (1 << 24))) {
7182 gen_add_data_offset(s, insn, tmp2);
7183 store_reg(s, rn, tmp2);
7184 } else if (insn & (1 << 21)) {
7185 store_reg(s, rn, tmp2);
7186 } else {
7187 dead_tmp(tmp2);
7188 }
7189 if (insn & (1 << 20)) {
7190 /* Complete the load. */
7191 if (rd == 15)
7192 gen_bx(s, tmp);
7193 else
7194 store_reg(s, rd, tmp);
7195 }
7196 break;
7197 case 0x08:
7198 case 0x09:
7199 {
7200 int j, n, user, loaded_base;
7201 TCGv loaded_var;
7202 /* load/store multiple words */
7203 /* XXX: store correct base if write back */
7204 user = 0;
7205 if (insn & (1 << 22)) {
7206 if (IS_USER(s))
7207 goto illegal_op; /* only usable in supervisor mode */
7208
7209 if ((insn & (1 << 15)) == 0)
7210 user = 1;
7211 }
7212 rn = (insn >> 16) & 0xf;
7213 addr = load_reg(s, rn);
7214
7215 /* compute total size */
7216 loaded_base = 0;
7217 TCGV_UNUSED(loaded_var);
7218 n = 0;
7219 for(i=0;i<16;i++) {
7220 if (insn & (1 << i))
7221 n++;
7222 }
7223 /* XXX: test invalid n == 0 case ? */
7224 if (insn & (1 << 23)) {
7225 if (insn & (1 << 24)) {
7226 /* pre increment */
7227 tcg_gen_addi_i32(addr, addr, 4);
7228 } else {
7229 /* post increment */
7230 }
7231 } else {
7232 if (insn & (1 << 24)) {
7233 /* pre decrement */
7234 tcg_gen_addi_i32(addr, addr, -(n * 4));
7235 } else {
7236 /* post decrement */
7237 if (n != 1)
7238 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7239 }
7240 }
7241 j = 0;
7242 for(i=0;i<16;i++) {
7243 if (insn & (1 << i)) {
7244 if (insn & (1 << 20)) {
7245 /* load */
7246 tmp = gen_ld32(addr, IS_USER(s));
7247 if (i == 15) {
7248 gen_bx(s, tmp);
7249 } else if (user) {
7250 tmp2 = tcg_const_i32(i);
7251 gen_helper_set_user_reg(tmp2, tmp);
7252 tcg_temp_free_i32(tmp2);
7253 dead_tmp(tmp);
7254 } else if (i == rn) {
7255 loaded_var = tmp;
7256 loaded_base = 1;
7257 } else {
7258 store_reg(s, i, tmp);
7259 }
7260 } else {
7261 /* store */
7262 if (i == 15) {
7263 /* special case: r15 = PC + 8 */
7264 val = (long)s->pc + 4;
7265 tmp = new_tmp();
7266 tcg_gen_movi_i32(tmp, val);
7267 } else if (user) {
7268 tmp = new_tmp();
7269 tmp2 = tcg_const_i32(i);
7270 gen_helper_get_user_reg(tmp, tmp2);
7271 tcg_temp_free_i32(tmp2);
7272 } else {
7273 tmp = load_reg(s, i);
7274 }
7275 gen_st32(tmp, addr, IS_USER(s));
7276 }
7277 j++;
7278 /* no need to add after the last transfer */
7279 if (j != n)
7280 tcg_gen_addi_i32(addr, addr, 4);
7281 }
7282 }
7283 if (insn & (1 << 21)) {
7284 /* write back */
7285 if (insn & (1 << 23)) {
7286 if (insn & (1 << 24)) {
7287 /* pre increment */
7288 } else {
7289 /* post increment */
7290 tcg_gen_addi_i32(addr, addr, 4);
7291 }
7292 } else {
7293 if (insn & (1 << 24)) {
7294 /* pre decrement */
7295 if (n != 1)
7296 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7297 } else {
7298 /* post decrement */
7299 tcg_gen_addi_i32(addr, addr, -(n * 4));
7300 }
7301 }
7302 store_reg(s, rn, addr);
7303 } else {
7304 dead_tmp(addr);
7305 }
7306 if (loaded_base) {
7307 store_reg(s, rn, loaded_var);
7308 }
7309 if ((insn & (1 << 22)) && !user) {
7310 /* Restore CPSR from SPSR. */
7311 tmp = load_cpu_field(spsr);
7312 gen_set_cpsr(tmp, 0xffffffff);
7313 dead_tmp(tmp);
7314 s->is_jmp = DISAS_UPDATE;
7315 }
7316 }
7317 break;
7318 case 0xa:
7319 case 0xb:
7320 {
7321 int32_t offset;
7322
7323 /* branch (and link) */
7324 val = (int32_t)s->pc;
7325 if (insn & (1 << 24)) {
7326 tmp = new_tmp();
7327 tcg_gen_movi_i32(tmp, val);
7328 store_reg(s, 14, tmp);
7329 }
7330 offset = (((int32_t)insn << 8) >> 8);
7331 val += (offset << 2) + 4;
7332 gen_jmp(s, val);
7333 }
7334 break;
7335 case 0xc:
7336 case 0xd:
7337 case 0xe:
7338 /* Coprocessor. */
7339 if (disas_coproc_insn(env, s, insn))
7340 goto illegal_op;
7341 break;
7342 case 0xf:
7343 /* swi */
7344 gen_set_pc_im(s->pc);
7345 s->is_jmp = DISAS_SWI;
7346 break;
7347 default:
7348 illegal_op:
7349 gen_exception_insn(s, 4, EXCP_UDEF);
7350 break;
7351 }
7352 }
7353 }
7354
7355 /* Return true if this is a Thumb-2 logical op. */
7356 static int
7357 thumb2_logic_op(int op)
7358 {
7359 return (op < 8);
7360 }
7361
7362 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7363 then set condition code flags based on the result of the operation.
7364 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7365 to the high bit of T1.
7366 Returns zero if the opcode is valid. */
7367
7368 static int
7369 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7370 {
7371 int logic_cc;
7372
7373 logic_cc = 0;
7374 switch (op) {
7375 case 0: /* and */
7376 tcg_gen_and_i32(t0, t0, t1);
7377 logic_cc = conds;
7378 break;
7379 case 1: /* bic */
7380 tcg_gen_andc_i32(t0, t0, t1);
7381 logic_cc = conds;
7382 break;
7383 case 2: /* orr */
7384 tcg_gen_or_i32(t0, t0, t1);
7385 logic_cc = conds;
7386 break;
7387 case 3: /* orn */
7388 tcg_gen_not_i32(t1, t1);
7389 tcg_gen_or_i32(t0, t0, t1);
7390 logic_cc = conds;
7391 break;
7392 case 4: /* eor */
7393 tcg_gen_xor_i32(t0, t0, t1);
7394 logic_cc = conds;
7395 break;
7396 case 8: /* add */
7397 if (conds)
7398 gen_helper_add_cc(t0, t0, t1);
7399 else
7400 tcg_gen_add_i32(t0, t0, t1);
7401 break;
7402 case 10: /* adc */
7403 if (conds)
7404 gen_helper_adc_cc(t0, t0, t1);
7405 else
7406 gen_adc(t0, t1);
7407 break;
7408 case 11: /* sbc */
7409 if (conds)
7410 gen_helper_sbc_cc(t0, t0, t1);
7411 else
7412 gen_sub_carry(t0, t0, t1);
7413 break;
7414 case 13: /* sub */
7415 if (conds)
7416 gen_helper_sub_cc(t0, t0, t1);
7417 else
7418 tcg_gen_sub_i32(t0, t0, t1);
7419 break;
7420 case 14: /* rsb */
7421 if (conds)
7422 gen_helper_sub_cc(t0, t1, t0);
7423 else
7424 tcg_gen_sub_i32(t0, t1, t0);
7425 break;
7426 default: /* 5, 6, 7, 9, 12, 15. */
7427 return 1;
7428 }
7429 if (logic_cc) {
7430 gen_logic_CC(t0);
7431 if (shifter_out)
7432 gen_set_CF_bit31(t1);
7433 }
7434 return 0;
7435 }
7436
7437 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7438 is not legal. */
7439 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7440 {
7441 uint32_t insn, imm, shift, offset;
7442 uint32_t rd, rn, rm, rs;
7443 TCGv tmp;
7444 TCGv tmp2;
7445 TCGv tmp3;
7446 TCGv addr;
7447 TCGv_i64 tmp64;
7448 int op;
7449 int shiftop;
7450 int conds;
7451 int logic_cc;
7452
7453 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7454 || arm_feature (env, ARM_FEATURE_M))) {
7455 /* Thumb-1 cores may need to treat bl and blx as a pair of
7456 16-bit instructions to get correct prefetch abort behavior. */
7457 insn = insn_hw1;
7458 if ((insn & (1 << 12)) == 0) {
7459 /* Second half of blx. */
7460 offset = ((insn & 0x7ff) << 1);
7461 tmp = load_reg(s, 14);
7462 tcg_gen_addi_i32(tmp, tmp, offset);
7463 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7464
7465 tmp2 = new_tmp();
7466 tcg_gen_movi_i32(tmp2, s->pc | 1);
7467 store_reg(s, 14, tmp2);
7468 gen_bx(s, tmp);
7469 return 0;
7470 }
7471 if (insn & (1 << 11)) {
7472 /* Second half of bl. */
7473 offset = ((insn & 0x7ff) << 1) | 1;
7474 tmp = load_reg(s, 14);
7475 tcg_gen_addi_i32(tmp, tmp, offset);
7476
7477 tmp2 = new_tmp();
7478 tcg_gen_movi_i32(tmp2, s->pc | 1);
7479 store_reg(s, 14, tmp2);
7480 gen_bx(s, tmp);
7481 return 0;
7482 }
7483 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7484 /* Instruction spans a page boundary. Implement it as two
7485 16-bit instructions in case the second half causes an
7486 prefetch abort. */
7487 offset = ((int32_t)insn << 21) >> 9;
7488 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7489 return 0;
7490 }
7491 /* Fall through to 32-bit decode. */
7492 }
7493
7494 insn = lduw_code(s->pc);
7495 s->pc += 2;
7496 insn |= (uint32_t)insn_hw1 << 16;
7497
7498 if ((insn & 0xf800e800) != 0xf000e800) {
7499 ARCH(6T2);
7500 }
7501
7502 rn = (insn >> 16) & 0xf;
7503 rs = (insn >> 12) & 0xf;
7504 rd = (insn >> 8) & 0xf;
7505 rm = insn & 0xf;
7506 switch ((insn >> 25) & 0xf) {
7507 case 0: case 1: case 2: case 3:
7508 /* 16-bit instructions. Should never happen. */
7509 abort();
7510 case 4:
7511 if (insn & (1 << 22)) {
7512 /* Other load/store, table branch. */
7513 if (insn & 0x01200000) {
7514 /* Load/store doubleword. */
7515 if (rn == 15) {
7516 addr = new_tmp();
7517 tcg_gen_movi_i32(addr, s->pc & ~3);
7518 } else {
7519 addr = load_reg(s, rn);
7520 }
7521 offset = (insn & 0xff) * 4;
7522 if ((insn & (1 << 23)) == 0)
7523 offset = -offset;
7524 if (insn & (1 << 24)) {
7525 tcg_gen_addi_i32(addr, addr, offset);
7526 offset = 0;
7527 }
7528 if (insn & (1 << 20)) {
7529 /* ldrd */
7530 tmp = gen_ld32(addr, IS_USER(s));
7531 store_reg(s, rs, tmp);
7532 tcg_gen_addi_i32(addr, addr, 4);
7533 tmp = gen_ld32(addr, IS_USER(s));
7534 store_reg(s, rd, tmp);
7535 } else {
7536 /* strd */
7537 tmp = load_reg(s, rs);
7538 gen_st32(tmp, addr, IS_USER(s));
7539 tcg_gen_addi_i32(addr, addr, 4);
7540 tmp = load_reg(s, rd);
7541 gen_st32(tmp, addr, IS_USER(s));
7542 }
7543 if (insn & (1 << 21)) {
7544 /* Base writeback. */
7545 if (rn == 15)
7546 goto illegal_op;
7547 tcg_gen_addi_i32(addr, addr, offset - 4);
7548 store_reg(s, rn, addr);
7549 } else {
7550 dead_tmp(addr);
7551 }
7552 } else if ((insn & (1 << 23)) == 0) {
7553 /* Load/store exclusive word. */
7554 addr = tcg_temp_local_new();
7555 load_reg_var(s, addr, rn);
7556 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7557 if (insn & (1 << 20)) {
7558 gen_load_exclusive(s, rs, 15, addr, 2);
7559 } else {
7560 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7561 }
7562 tcg_temp_free(addr);
7563 } else if ((insn & (1 << 6)) == 0) {
7564 /* Table Branch. */
7565 if (rn == 15) {
7566 addr = new_tmp();
7567 tcg_gen_movi_i32(addr, s->pc);
7568 } else {
7569 addr = load_reg(s, rn);
7570 }
7571 tmp = load_reg(s, rm);
7572 tcg_gen_add_i32(addr, addr, tmp);
7573 if (insn & (1 << 4)) {
7574 /* tbh */
7575 tcg_gen_add_i32(addr, addr, tmp);
7576 dead_tmp(tmp);
7577 tmp = gen_ld16u(addr, IS_USER(s));
7578 } else { /* tbb */
7579 dead_tmp(tmp);
7580 tmp = gen_ld8u(addr, IS_USER(s));
7581 }
7582 dead_tmp(addr);
7583 tcg_gen_shli_i32(tmp, tmp, 1);
7584 tcg_gen_addi_i32(tmp, tmp, s->pc);
7585 store_reg(s, 15, tmp);
7586 } else {
7587 /* Load/store exclusive byte/halfword/doubleword. */
7588 ARCH(7);
7589 op = (insn >> 4) & 0x3;
7590 if (op == 2) {
7591 goto illegal_op;
7592 }
7593 addr = tcg_temp_local_new();
7594 load_reg_var(s, addr, rn);
7595 if (insn & (1 << 20)) {
7596 gen_load_exclusive(s, rs, rd, addr, op);
7597 } else {
7598 gen_store_exclusive(s, rm, rs, rd, addr, op);
7599 }
7600 tcg_temp_free(addr);
7601 }
7602 } else {
7603 /* Load/store multiple, RFE, SRS. */
7604 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7605 /* Not available in user mode. */
7606 if (IS_USER(s))
7607 goto illegal_op;
7608 if (insn & (1 << 20)) {
7609 /* rfe */
7610 addr = load_reg(s, rn);
7611 if ((insn & (1 << 24)) == 0)
7612 tcg_gen_addi_i32(addr, addr, -8);
7613 /* Load PC into tmp and CPSR into tmp2. */
7614 tmp = gen_ld32(addr, 0);
7615 tcg_gen_addi_i32(addr, addr, 4);
7616 tmp2 = gen_ld32(addr, 0);
7617 if (insn & (1 << 21)) {
7618 /* Base writeback. */
7619 if (insn & (1 << 24)) {
7620 tcg_gen_addi_i32(addr, addr, 4);
7621 } else {
7622 tcg_gen_addi_i32(addr, addr, -4);
7623 }
7624 store_reg(s, rn, addr);
7625 } else {
7626 dead_tmp(addr);
7627 }
7628 gen_rfe(s, tmp, tmp2);
7629 } else {
7630 /* srs */
7631 op = (insn & 0x1f);
7632 addr = new_tmp();
7633 tmp = tcg_const_i32(op);
7634 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7635 tcg_temp_free_i32(tmp);
7636 if ((insn & (1 << 24)) == 0) {
7637 tcg_gen_addi_i32(addr, addr, -8);
7638 }
7639 tmp = load_reg(s, 14);
7640 gen_st32(tmp, addr, 0);
7641 tcg_gen_addi_i32(addr, addr, 4);
7642 tmp = new_tmp();
7643 gen_helper_cpsr_read(tmp);
7644 gen_st32(tmp, addr, 0);
7645 if (insn & (1 << 21)) {
7646 if ((insn & (1 << 24)) == 0) {
7647 tcg_gen_addi_i32(addr, addr, -4);
7648 } else {
7649 tcg_gen_addi_i32(addr, addr, 4);
7650 }
7651 tmp = tcg_const_i32(op);
7652 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7653 tcg_temp_free_i32(tmp);
7654 } else {
7655 dead_tmp(addr);
7656 }
7657 }
7658 } else {
7659 int i;
7660 /* Load/store multiple. */
7661 addr = load_reg(s, rn);
7662 offset = 0;
7663 for (i = 0; i < 16; i++) {
7664 if (insn & (1 << i))
7665 offset += 4;
7666 }
7667 if (insn & (1 << 24)) {
7668 tcg_gen_addi_i32(addr, addr, -offset);
7669 }
7670
7671 for (i = 0; i < 16; i++) {
7672 if ((insn & (1 << i)) == 0)
7673 continue;
7674 if (insn & (1 << 20)) {
7675 /* Load. */
7676 tmp = gen_ld32(addr, IS_USER(s));
7677 if (i == 15) {
7678 gen_bx(s, tmp);
7679 } else {
7680 store_reg(s, i, tmp);
7681 }
7682 } else {
7683 /* Store. */
7684 tmp = load_reg(s, i);
7685 gen_st32(tmp, addr, IS_USER(s));
7686 }
7687 tcg_gen_addi_i32(addr, addr, 4);
7688 }
7689 if (insn & (1 << 21)) {
7690 /* Base register writeback. */
7691 if (insn & (1 << 24)) {
7692 tcg_gen_addi_i32(addr, addr, -offset);
7693 }
7694 /* Fault if writeback register is in register list. */
7695 if (insn & (1 << rn))
7696 goto illegal_op;
7697 store_reg(s, rn, addr);
7698 } else {
7699 dead_tmp(addr);
7700 }
7701 }
7702 }
7703 break;
7704 case 5:
7705
7706 op = (insn >> 21) & 0xf;
7707 if (op == 6) {
7708 /* Halfword pack. */
7709 tmp = load_reg(s, rn);
7710 tmp2 = load_reg(s, rm);
7711 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
7712 if (insn & (1 << 5)) {
7713 /* pkhtb */
7714 if (shift == 0)
7715 shift = 31;
7716 tcg_gen_sari_i32(tmp2, tmp2, shift);
7717 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7718 tcg_gen_ext16u_i32(tmp2, tmp2);
7719 } else {
7720 /* pkhbt */
7721 if (shift)
7722 tcg_gen_shli_i32(tmp2, tmp2, shift);
7723 tcg_gen_ext16u_i32(tmp, tmp);
7724 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7725 }
7726 tcg_gen_or_i32(tmp, tmp, tmp2);
7727 dead_tmp(tmp2);
7728 store_reg(s, rd, tmp);
7729 } else {
7730 /* Data processing register constant shift. */
7731 if (rn == 15) {
7732 tmp = new_tmp();
7733 tcg_gen_movi_i32(tmp, 0);
7734 } else {
7735 tmp = load_reg(s, rn);
7736 }
7737 tmp2 = load_reg(s, rm);
7738
7739 shiftop = (insn >> 4) & 3;
7740 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7741 conds = (insn & (1 << 20)) != 0;
7742 logic_cc = (conds && thumb2_logic_op(op));
7743 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
7744 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
7745 goto illegal_op;
7746 dead_tmp(tmp2);
7747 if (rd != 15) {
7748 store_reg(s, rd, tmp);
7749 } else {
7750 dead_tmp(tmp);
7751 }
7752 }
7753 break;
7754 case 13: /* Misc data processing. */
7755 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7756 if (op < 4 && (insn & 0xf000) != 0xf000)
7757 goto illegal_op;
7758 switch (op) {
7759 case 0: /* Register controlled shift. */
7760 tmp = load_reg(s, rn);
7761 tmp2 = load_reg(s, rm);
7762 if ((insn & 0x70) != 0)
7763 goto illegal_op;
7764 op = (insn >> 21) & 3;
7765 logic_cc = (insn & (1 << 20)) != 0;
7766 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
7767 if (logic_cc)
7768 gen_logic_CC(tmp);
7769 store_reg_bx(env, s, rd, tmp);
7770 break;
7771 case 1: /* Sign/zero extend. */
7772 tmp = load_reg(s, rm);
7773 shift = (insn >> 4) & 3;
7774 /* ??? In many cases it's not neccessary to do a
7775 rotate, a shift is sufficient. */
7776 if (shift != 0)
7777 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7778 op = (insn >> 20) & 7;
7779 switch (op) {
7780 case 0: gen_sxth(tmp); break;
7781 case 1: gen_uxth(tmp); break;
7782 case 2: gen_sxtb16(tmp); break;
7783 case 3: gen_uxtb16(tmp); break;
7784 case 4: gen_sxtb(tmp); break;
7785 case 5: gen_uxtb(tmp); break;
7786 default: goto illegal_op;
7787 }
7788 if (rn != 15) {
7789 tmp2 = load_reg(s, rn);
7790 if ((op >> 1) == 1) {
7791 gen_add16(tmp, tmp2);
7792 } else {
7793 tcg_gen_add_i32(tmp, tmp, tmp2);
7794 dead_tmp(tmp2);
7795 }
7796 }
7797 store_reg(s, rd, tmp);
7798 break;
7799 case 2: /* SIMD add/subtract. */
7800 op = (insn >> 20) & 7;
7801 shift = (insn >> 4) & 7;
7802 if ((op & 3) == 3 || (shift & 3) == 3)
7803 goto illegal_op;
7804 tmp = load_reg(s, rn);
7805 tmp2 = load_reg(s, rm);
7806 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
7807 dead_tmp(tmp2);
7808 store_reg(s, rd, tmp);
7809 break;
7810 case 3: /* Other data processing. */
7811 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7812 if (op < 4) {
7813 /* Saturating add/subtract. */
7814 tmp = load_reg(s, rn);
7815 tmp2 = load_reg(s, rm);
7816 if (op & 1)
7817 gen_helper_double_saturate(tmp, tmp);
7818 if (op & 2)
7819 gen_helper_sub_saturate(tmp, tmp2, tmp);
7820 else
7821 gen_helper_add_saturate(tmp, tmp, tmp2);
7822 dead_tmp(tmp2);
7823 } else {
7824 tmp = load_reg(s, rn);
7825 switch (op) {
7826 case 0x0a: /* rbit */
7827 gen_helper_rbit(tmp, tmp);
7828 break;
7829 case 0x08: /* rev */
7830 tcg_gen_bswap32_i32(tmp, tmp);
7831 break;
7832 case 0x09: /* rev16 */
7833 gen_rev16(tmp);
7834 break;
7835 case 0x0b: /* revsh */
7836 gen_revsh(tmp);
7837 break;
7838 case 0x10: /* sel */
7839 tmp2 = load_reg(s, rm);
7840 tmp3 = new_tmp();
7841 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7842 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7843 dead_tmp(tmp3);
7844 dead_tmp(tmp2);
7845 break;
7846 case 0x18: /* clz */
7847 gen_helper_clz(tmp, tmp);
7848 break;
7849 default:
7850 goto illegal_op;
7851 }
7852 }
7853 store_reg(s, rd, tmp);
7854 break;
7855 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7856 op = (insn >> 4) & 0xf;
7857 tmp = load_reg(s, rn);
7858 tmp2 = load_reg(s, rm);
7859 switch ((insn >> 20) & 7) {
7860 case 0: /* 32 x 32 -> 32 */
7861 tcg_gen_mul_i32(tmp, tmp, tmp2);
7862 dead_tmp(tmp2);
7863 if (rs != 15) {
7864 tmp2 = load_reg(s, rs);
7865 if (op)
7866 tcg_gen_sub_i32(tmp, tmp2, tmp);
7867 else
7868 tcg_gen_add_i32(tmp, tmp, tmp2);
7869 dead_tmp(tmp2);
7870 }
7871 break;
7872 case 1: /* 16 x 16 -> 32 */
7873 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7874 dead_tmp(tmp2);
7875 if (rs != 15) {
7876 tmp2 = load_reg(s, rs);
7877 gen_helper_add_setq(tmp, tmp, tmp2);
7878 dead_tmp(tmp2);
7879 }
7880 break;
7881 case 2: /* Dual multiply add. */
7882 case 4: /* Dual multiply subtract. */
7883 if (op)
7884 gen_swap_half(tmp2);
7885 gen_smul_dual(tmp, tmp2);
7886 /* This addition cannot overflow. */
7887 if (insn & (1 << 22)) {
7888 tcg_gen_sub_i32(tmp, tmp, tmp2);
7889 } else {
7890 tcg_gen_add_i32(tmp, tmp, tmp2);
7891 }
7892 dead_tmp(tmp2);
7893 if (rs != 15)
7894 {
7895 tmp2 = load_reg(s, rs);
7896 gen_helper_add_setq(tmp, tmp, tmp2);
7897 dead_tmp(tmp2);
7898 }
7899 break;
7900 case 3: /* 32 * 16 -> 32msb */
7901 if (op)
7902 tcg_gen_sari_i32(tmp2, tmp2, 16);
7903 else
7904 gen_sxth(tmp2);
7905 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7906 tcg_gen_shri_i64(tmp64, tmp64, 16);
7907 tmp = new_tmp();
7908 tcg_gen_trunc_i64_i32(tmp, tmp64);
7909 tcg_temp_free_i64(tmp64);
7910 if (rs != 15)
7911 {
7912 tmp2 = load_reg(s, rs);
7913 gen_helper_add_setq(tmp, tmp, tmp2);
7914 dead_tmp(tmp2);
7915 }
7916 break;
7917 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
7918 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7919 if (rs != 15) {
7920 tmp = load_reg(s, rs);
7921 if (insn & (1 << 20)) {
7922 tmp64 = gen_addq_msw(tmp64, tmp);
7923 } else {
7924 tmp64 = gen_subq_msw(tmp64, tmp);
7925 }
7926 }
7927 if (insn & (1 << 4)) {
7928 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7929 }
7930 tcg_gen_shri_i64(tmp64, tmp64, 32);
7931 tmp = new_tmp();
7932 tcg_gen_trunc_i64_i32(tmp, tmp64);
7933 tcg_temp_free_i64(tmp64);
7934 break;
7935 case 7: /* Unsigned sum of absolute differences. */
7936 gen_helper_usad8(tmp, tmp, tmp2);
7937 dead_tmp(tmp2);
7938 if (rs != 15) {
7939 tmp2 = load_reg(s, rs);
7940 tcg_gen_add_i32(tmp, tmp, tmp2);
7941 dead_tmp(tmp2);
7942 }
7943 break;
7944 }
7945 store_reg(s, rd, tmp);
7946 break;
7947 case 6: case 7: /* 64-bit multiply, Divide. */
7948 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7949 tmp = load_reg(s, rn);
7950 tmp2 = load_reg(s, rm);
7951 if ((op & 0x50) == 0x10) {
7952 /* sdiv, udiv */
7953 if (!arm_feature(env, ARM_FEATURE_DIV))
7954 goto illegal_op;
7955 if (op & 0x20)
7956 gen_helper_udiv(tmp, tmp, tmp2);
7957 else
7958 gen_helper_sdiv(tmp, tmp, tmp2);
7959 dead_tmp(tmp2);
7960 store_reg(s, rd, tmp);
7961 } else if ((op & 0xe) == 0xc) {
7962 /* Dual multiply accumulate long. */
7963 if (op & 1)
7964 gen_swap_half(tmp2);
7965 gen_smul_dual(tmp, tmp2);
7966 if (op & 0x10) {
7967 tcg_gen_sub_i32(tmp, tmp, tmp2);
7968 } else {
7969 tcg_gen_add_i32(tmp, tmp, tmp2);
7970 }
7971 dead_tmp(tmp2);
7972 /* BUGFIX */
7973 tmp64 = tcg_temp_new_i64();
7974 tcg_gen_ext_i32_i64(tmp64, tmp);
7975 dead_tmp(tmp);
7976 gen_addq(s, tmp64, rs, rd);
7977 gen_storeq_reg(s, rs, rd, tmp64);
7978 tcg_temp_free_i64(tmp64);
7979 } else {
7980 if (op & 0x20) {
7981 /* Unsigned 64-bit multiply */
7982 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7983 } else {
7984 if (op & 8) {
7985 /* smlalxy */
7986 gen_mulxy(tmp, tmp2, op & 2, op & 1);
7987 dead_tmp(tmp2);
7988 tmp64 = tcg_temp_new_i64();
7989 tcg_gen_ext_i32_i64(tmp64, tmp);
7990 dead_tmp(tmp);
7991 } else {
7992 /* Signed 64-bit multiply */
7993 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7994 }
7995 }
7996 if (op & 4) {
7997 /* umaal */
7998 gen_addq_lo(s, tmp64, rs);
7999 gen_addq_lo(s, tmp64, rd);
8000 } else if (op & 0x40) {
8001 /* 64-bit accumulate. */
8002 gen_addq(s, tmp64, rs, rd);
8003 }
8004 gen_storeq_reg(s, rs, rd, tmp64);
8005 tcg_temp_free_i64(tmp64);
8006 }
8007 break;
8008 }
8009 break;
8010 case 6: case 7: case 14: case 15:
8011 /* Coprocessor. */
8012 if (((insn >> 24) & 3) == 3) {
8013 /* Translate into the equivalent ARM encoding. */
8014 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
8015 if (disas_neon_data_insn(env, s, insn))
8016 goto illegal_op;
8017 } else {
8018 if (insn & (1 << 28))
8019 goto illegal_op;
8020 if (disas_coproc_insn (env, s, insn))
8021 goto illegal_op;
8022 }
8023 break;
8024 case 8: case 9: case 10: case 11:
8025 if (insn & (1 << 15)) {
8026 /* Branches, misc control. */
8027 if (insn & 0x5000) {
8028 /* Unconditional branch. */
8029 /* signextend(hw1[10:0]) -> offset[:12]. */
8030 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8031 /* hw1[10:0] -> offset[11:1]. */
8032 offset |= (insn & 0x7ff) << 1;
8033 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8034 offset[24:22] already have the same value because of the
8035 sign extension above. */
8036 offset ^= ((~insn) & (1 << 13)) << 10;
8037 offset ^= ((~insn) & (1 << 11)) << 11;
8038
8039 if (insn & (1 << 14)) {
8040 /* Branch and link. */
8041 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
8042 }
8043
8044 offset += s->pc;
8045 if (insn & (1 << 12)) {
8046 /* b/bl */
8047 gen_jmp(s, offset);
8048 } else {
8049 /* blx */
8050 offset &= ~(uint32_t)2;
8051 gen_bx_im(s, offset);
8052 }
8053 } else if (((insn >> 23) & 7) == 7) {
8054 /* Misc control */
8055 if (insn & (1 << 13))
8056 goto illegal_op;
8057
8058 if (insn & (1 << 26)) {
8059 /* Secure monitor call (v6Z) */
8060 goto illegal_op; /* not implemented. */
8061 } else {
8062 op = (insn >> 20) & 7;
8063 switch (op) {
8064 case 0: /* msr cpsr. */
8065 if (IS_M(env)) {
8066 tmp = load_reg(s, rn);
8067 addr = tcg_const_i32(insn & 0xff);
8068 gen_helper_v7m_msr(cpu_env, addr, tmp);
8069 tcg_temp_free_i32(addr);
8070 dead_tmp(tmp);
8071 gen_lookup_tb(s);
8072 break;
8073 }
8074 /* fall through */
8075 case 1: /* msr spsr. */
8076 if (IS_M(env))
8077 goto illegal_op;
8078 tmp = load_reg(s, rn);
8079 if (gen_set_psr(s,
8080 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8081 op == 1, tmp))
8082 goto illegal_op;
8083 break;
8084 case 2: /* cps, nop-hint. */
8085 if (((insn >> 8) & 7) == 0) {
8086 gen_nop_hint(s, insn & 0xff);
8087 }
8088 /* Implemented as NOP in user mode. */
8089 if (IS_USER(s))
8090 break;
8091 offset = 0;
8092 imm = 0;
8093 if (insn & (1 << 10)) {
8094 if (insn & (1 << 7))
8095 offset |= CPSR_A;
8096 if (insn & (1 << 6))
8097 offset |= CPSR_I;
8098 if (insn & (1 << 5))
8099 offset |= CPSR_F;
8100 if (insn & (1 << 9))
8101 imm = CPSR_A | CPSR_I | CPSR_F;
8102 }
8103 if (insn & (1 << 8)) {
8104 offset |= 0x1f;
8105 imm |= (insn & 0x1f);
8106 }
8107 if (offset) {
8108 gen_set_psr_im(s, offset, 0, imm);
8109 }
8110 break;
8111 case 3: /* Special control operations. */
8112 ARCH(7);
8113 op = (insn >> 4) & 0xf;
8114 switch (op) {
8115 case 2: /* clrex */
8116 gen_clrex(s);
8117 break;
8118 case 4: /* dsb */
8119 case 5: /* dmb */
8120 case 6: /* isb */
8121 /* These execute as NOPs. */
8122 break;
8123 default:
8124 goto illegal_op;
8125 }
8126 break;
8127 case 4: /* bxj */
8128 /* Trivial implementation equivalent to bx. */
8129 tmp = load_reg(s, rn);
8130 gen_bx(s, tmp);
8131 break;
8132 case 5: /* Exception return. */
8133 if (IS_USER(s)) {
8134 goto illegal_op;
8135 }
8136 if (rn != 14 || rd != 15) {
8137 goto illegal_op;
8138 }
8139 tmp = load_reg(s, rn);
8140 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8141 gen_exception_return(s, tmp);
8142 break;
8143 case 6: /* mrs cpsr. */
8144 tmp = new_tmp();
8145 if (IS_M(env)) {
8146 addr = tcg_const_i32(insn & 0xff);
8147 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8148 tcg_temp_free_i32(addr);
8149 } else {
8150 gen_helper_cpsr_read(tmp);
8151 }
8152 store_reg(s, rd, tmp);
8153 break;
8154 case 7: /* mrs spsr. */
8155 /* Not accessible in user mode. */
8156 if (IS_USER(s) || IS_M(env))
8157 goto illegal_op;
8158 tmp = load_cpu_field(spsr);
8159 store_reg(s, rd, tmp);
8160 break;
8161 }
8162 }
8163 } else {
8164 /* Conditional branch. */
8165 op = (insn >> 22) & 0xf;
8166 /* Generate a conditional jump to next instruction. */
8167 s->condlabel = gen_new_label();
8168 gen_test_cc(op ^ 1, s->condlabel);
8169 s->condjmp = 1;
8170
8171 /* offset[11:1] = insn[10:0] */
8172 offset = (insn & 0x7ff) << 1;
8173 /* offset[17:12] = insn[21:16]. */
8174 offset |= (insn & 0x003f0000) >> 4;
8175 /* offset[31:20] = insn[26]. */
8176 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8177 /* offset[18] = insn[13]. */
8178 offset |= (insn & (1 << 13)) << 5;
8179 /* offset[19] = insn[11]. */
8180 offset |= (insn & (1 << 11)) << 8;
8181
8182 /* jump to the offset */
8183 gen_jmp(s, s->pc + offset);
8184 }
8185 } else {
8186 /* Data processing immediate. */
8187 if (insn & (1 << 25)) {
8188 if (insn & (1 << 24)) {
8189 if (insn & (1 << 20))
8190 goto illegal_op;
8191 /* Bitfield/Saturate. */
8192 op = (insn >> 21) & 7;
8193 imm = insn & 0x1f;
8194 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8195 if (rn == 15) {
8196 tmp = new_tmp();
8197 tcg_gen_movi_i32(tmp, 0);
8198 } else {
8199 tmp = load_reg(s, rn);
8200 }
8201 switch (op) {
8202 case 2: /* Signed bitfield extract. */
8203 imm++;
8204 if (shift + imm > 32)
8205 goto illegal_op;
8206 if (imm < 32)
8207 gen_sbfx(tmp, shift, imm);
8208 break;
8209 case 6: /* Unsigned bitfield extract. */
8210 imm++;
8211 if (shift + imm > 32)
8212 goto illegal_op;
8213 if (imm < 32)
8214 gen_ubfx(tmp, shift, (1u << imm) - 1);
8215 break;
8216 case 3: /* Bitfield insert/clear. */
8217 if (imm < shift)
8218 goto illegal_op;
8219 imm = imm + 1 - shift;
8220 if (imm != 32) {
8221 tmp2 = load_reg(s, rd);
8222 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8223 dead_tmp(tmp2);
8224 }
8225 break;
8226 case 7:
8227 goto illegal_op;
8228 default: /* Saturate. */
8229 if (shift) {
8230 if (op & 1)
8231 tcg_gen_sari_i32(tmp, tmp, shift);
8232 else
8233 tcg_gen_shli_i32(tmp, tmp, shift);
8234 }
8235 tmp2 = tcg_const_i32(imm);
8236 if (op & 4) {
8237 /* Unsigned. */
8238 if ((op & 1) && shift == 0)
8239 gen_helper_usat16(tmp, tmp, tmp2);
8240 else
8241 gen_helper_usat(tmp, tmp, tmp2);
8242 } else {
8243 /* Signed. */
8244 if ((op & 1) && shift == 0)
8245 gen_helper_ssat16(tmp, tmp, tmp2);
8246 else
8247 gen_helper_ssat(tmp, tmp, tmp2);
8248 }
8249 tcg_temp_free_i32(tmp2);
8250 break;
8251 }
8252 store_reg(s, rd, tmp);
8253 } else {
8254 imm = ((insn & 0x04000000) >> 15)
8255 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8256 if (insn & (1 << 22)) {
8257 /* 16-bit immediate. */
8258 imm |= (insn >> 4) & 0xf000;
8259 if (insn & (1 << 23)) {
8260 /* movt */
8261 tmp = load_reg(s, rd);
8262 tcg_gen_ext16u_i32(tmp, tmp);
8263 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8264 } else {
8265 /* movw */
8266 tmp = new_tmp();
8267 tcg_gen_movi_i32(tmp, imm);
8268 }
8269 } else {
8270 /* Add/sub 12-bit immediate. */
8271 if (rn == 15) {
8272 offset = s->pc & ~(uint32_t)3;
8273 if (insn & (1 << 23))
8274 offset -= imm;
8275 else
8276 offset += imm;
8277 tmp = new_tmp();
8278 tcg_gen_movi_i32(tmp, offset);
8279 } else {
8280 tmp = load_reg(s, rn);
8281 if (insn & (1 << 23))
8282 tcg_gen_subi_i32(tmp, tmp, imm);
8283 else
8284 tcg_gen_addi_i32(tmp, tmp, imm);
8285 }
8286 }
8287 store_reg(s, rd, tmp);
8288 }
8289 } else {
8290 int shifter_out = 0;
8291 /* modified 12-bit immediate. */
8292 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8293 imm = (insn & 0xff);
8294 switch (shift) {
8295 case 0: /* XY */
8296 /* Nothing to do. */
8297 break;
8298 case 1: /* 00XY00XY */
8299 imm |= imm << 16;
8300 break;
8301 case 2: /* XY00XY00 */
8302 imm |= imm << 16;
8303 imm <<= 8;
8304 break;
8305 case 3: /* XYXYXYXY */
8306 imm |= imm << 16;
8307 imm |= imm << 8;
8308 break;
8309 default: /* Rotated constant. */
8310 shift = (shift << 1) | (imm >> 7);
8311 imm |= 0x80;
8312 imm = imm << (32 - shift);
8313 shifter_out = 1;
8314 break;
8315 }
8316 tmp2 = new_tmp();
8317 tcg_gen_movi_i32(tmp2, imm);
8318 rn = (insn >> 16) & 0xf;
8319 if (rn == 15) {
8320 tmp = new_tmp();
8321 tcg_gen_movi_i32(tmp, 0);
8322 } else {
8323 tmp = load_reg(s, rn);
8324 }
8325 op = (insn >> 21) & 0xf;
8326 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8327 shifter_out, tmp, tmp2))
8328 goto illegal_op;
8329 dead_tmp(tmp2);
8330 rd = (insn >> 8) & 0xf;
8331 if (rd != 15) {
8332 store_reg(s, rd, tmp);
8333 } else {
8334 dead_tmp(tmp);
8335 }
8336 }
8337 }
8338 break;
8339 case 12: /* Load/store single data item. */
8340 {
8341 int postinc = 0;
8342 int writeback = 0;
8343 int user;
8344 if ((insn & 0x01100000) == 0x01000000) {
8345 if (disas_neon_ls_insn(env, s, insn))
8346 goto illegal_op;
8347 break;
8348 }
8349 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8350 if (rs == 15) {
8351 if (!(insn & (1 << 20))) {
8352 goto illegal_op;
8353 }
8354 if (op != 2) {
8355 /* Byte or halfword load space with dest == r15 : memory hints.
8356 * Catch them early so we don't emit pointless addressing code.
8357 * This space is a mix of:
8358 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8359 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8360 * cores)
8361 * unallocated hints, which must be treated as NOPs
8362 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8363 * which is easiest for the decoding logic
8364 * Some space which must UNDEF
8365 */
8366 int op1 = (insn >> 23) & 3;
8367 int op2 = (insn >> 6) & 0x3f;
8368 if (op & 2) {
8369 goto illegal_op;
8370 }
8371 if (rn == 15) {
8372 /* UNPREDICTABLE or unallocated hint */
8373 return 0;
8374 }
8375 if (op1 & 1) {
8376 return 0; /* PLD* or unallocated hint */
8377 }
8378 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8379 return 0; /* PLD* or unallocated hint */
8380 }
8381 /* UNDEF space, or an UNPREDICTABLE */
8382 return 1;
8383 }
8384 }
8385 user = IS_USER(s);
8386 if (rn == 15) {
8387 addr = new_tmp();
8388 /* PC relative. */
8389 /* s->pc has already been incremented by 4. */
8390 imm = s->pc & 0xfffffffc;
8391 if (insn & (1 << 23))
8392 imm += insn & 0xfff;
8393 else
8394 imm -= insn & 0xfff;
8395 tcg_gen_movi_i32(addr, imm);
8396 } else {
8397 addr = load_reg(s, rn);
8398 if (insn & (1 << 23)) {
8399 /* Positive offset. */
8400 imm = insn & 0xfff;
8401 tcg_gen_addi_i32(addr, addr, imm);
8402 } else {
8403 imm = insn & 0xff;
8404 switch ((insn >> 8) & 7) {
8405 case 0: case 8: /* Shifted Register. */
8406 shift = (insn >> 4) & 0xf;
8407 if (shift > 3)
8408 goto illegal_op;
8409 tmp = load_reg(s, rm);
8410 if (shift)
8411 tcg_gen_shli_i32(tmp, tmp, shift);
8412 tcg_gen_add_i32(addr, addr, tmp);
8413 dead_tmp(tmp);
8414 break;
8415 case 4: /* Negative offset. */
8416 tcg_gen_addi_i32(addr, addr, -imm);
8417 break;
8418 case 6: /* User privilege. */
8419 tcg_gen_addi_i32(addr, addr, imm);
8420 user = 1;
8421 break;
8422 case 1: /* Post-decrement. */
8423 imm = -imm;
8424 /* Fall through. */
8425 case 3: /* Post-increment. */
8426 postinc = 1;
8427 writeback = 1;
8428 break;
8429 case 5: /* Pre-decrement. */
8430 imm = -imm;
8431 /* Fall through. */
8432 case 7: /* Pre-increment. */
8433 tcg_gen_addi_i32(addr, addr, imm);
8434 writeback = 1;
8435 break;
8436 default:
8437 goto illegal_op;
8438 }
8439 }
8440 }
8441 if (insn & (1 << 20)) {
8442 /* Load. */
8443 switch (op) {
8444 case 0: tmp = gen_ld8u(addr, user); break;
8445 case 4: tmp = gen_ld8s(addr, user); break;
8446 case 1: tmp = gen_ld16u(addr, user); break;
8447 case 5: tmp = gen_ld16s(addr, user); break;
8448 case 2: tmp = gen_ld32(addr, user); break;
8449 default: goto illegal_op;
8450 }
8451 if (rs == 15) {
8452 gen_bx(s, tmp);
8453 } else {
8454 store_reg(s, rs, tmp);
8455 }
8456 } else {
8457 /* Store. */
8458 tmp = load_reg(s, rs);
8459 switch (op) {
8460 case 0: gen_st8(tmp, addr, user); break;
8461 case 1: gen_st16(tmp, addr, user); break;
8462 case 2: gen_st32(tmp, addr, user); break;
8463 default: goto illegal_op;
8464 }
8465 }
8466 if (postinc)
8467 tcg_gen_addi_i32(addr, addr, imm);
8468 if (writeback) {
8469 store_reg(s, rn, addr);
8470 } else {
8471 dead_tmp(addr);
8472 }
8473 }
8474 break;
8475 default:
8476 goto illegal_op;
8477 }
8478 return 0;
8479 illegal_op:
8480 return 1;
8481 }
8482
8483 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8484 {
8485 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8486 int32_t offset;
8487 int i;
8488 TCGv tmp;
8489 TCGv tmp2;
8490 TCGv addr;
8491
8492 if (s->condexec_mask) {
8493 cond = s->condexec_cond;
8494 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8495 s->condlabel = gen_new_label();
8496 gen_test_cc(cond ^ 1, s->condlabel);
8497 s->condjmp = 1;
8498 }
8499 }
8500
8501 insn = lduw_code(s->pc);
8502 s->pc += 2;
8503
8504 switch (insn >> 12) {
8505 case 0: case 1:
8506
8507 rd = insn & 7;
8508 op = (insn >> 11) & 3;
8509 if (op == 3) {
8510 /* add/subtract */
8511 rn = (insn >> 3) & 7;
8512 tmp = load_reg(s, rn);
8513 if (insn & (1 << 10)) {
8514 /* immediate */
8515 tmp2 = new_tmp();
8516 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8517 } else {
8518 /* reg */
8519 rm = (insn >> 6) & 7;
8520 tmp2 = load_reg(s, rm);
8521 }
8522 if (insn & (1 << 9)) {
8523 if (s->condexec_mask)
8524 tcg_gen_sub_i32(tmp, tmp, tmp2);
8525 else
8526 gen_helper_sub_cc(tmp, tmp, tmp2);
8527 } else {
8528 if (s->condexec_mask)
8529 tcg_gen_add_i32(tmp, tmp, tmp2);
8530 else
8531 gen_helper_add_cc(tmp, tmp, tmp2);
8532 }
8533 dead_tmp(tmp2);
8534 store_reg(s, rd, tmp);
8535 } else {
8536 /* shift immediate */
8537 rm = (insn >> 3) & 7;
8538 shift = (insn >> 6) & 0x1f;
8539 tmp = load_reg(s, rm);
8540 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8541 if (!s->condexec_mask)
8542 gen_logic_CC(tmp);
8543 store_reg(s, rd, tmp);
8544 }
8545 break;
8546 case 2: case 3:
8547 /* arithmetic large immediate */
8548 op = (insn >> 11) & 3;
8549 rd = (insn >> 8) & 0x7;
8550 if (op == 0) { /* mov */
8551 tmp = new_tmp();
8552 tcg_gen_movi_i32(tmp, insn & 0xff);
8553 if (!s->condexec_mask)
8554 gen_logic_CC(tmp);
8555 store_reg(s, rd, tmp);
8556 } else {
8557 tmp = load_reg(s, rd);
8558 tmp2 = new_tmp();
8559 tcg_gen_movi_i32(tmp2, insn & 0xff);
8560 switch (op) {
8561 case 1: /* cmp */
8562 gen_helper_sub_cc(tmp, tmp, tmp2);
8563 dead_tmp(tmp);
8564 dead_tmp(tmp2);
8565 break;
8566 case 2: /* add */
8567 if (s->condexec_mask)
8568 tcg_gen_add_i32(tmp, tmp, tmp2);
8569 else
8570 gen_helper_add_cc(tmp, tmp, tmp2);
8571 dead_tmp(tmp2);
8572 store_reg(s, rd, tmp);
8573 break;
8574 case 3: /* sub */
8575 if (s->condexec_mask)
8576 tcg_gen_sub_i32(tmp, tmp, tmp2);
8577 else
8578 gen_helper_sub_cc(tmp, tmp, tmp2);
8579 dead_tmp(tmp2);
8580 store_reg(s, rd, tmp);
8581 break;
8582 }
8583 }
8584 break;
8585 case 4:
8586 if (insn & (1 << 11)) {
8587 rd = (insn >> 8) & 7;
8588 /* load pc-relative. Bit 1 of PC is ignored. */
8589 val = s->pc + 2 + ((insn & 0xff) * 4);
8590 val &= ~(uint32_t)2;
8591 addr = new_tmp();
8592 tcg_gen_movi_i32(addr, val);
8593 tmp = gen_ld32(addr, IS_USER(s));
8594 dead_tmp(addr);
8595 store_reg(s, rd, tmp);
8596 break;
8597 }
8598 if (insn & (1 << 10)) {
8599 /* data processing extended or blx */
8600 rd = (insn & 7) | ((insn >> 4) & 8);
8601 rm = (insn >> 3) & 0xf;
8602 op = (insn >> 8) & 3;
8603 switch (op) {
8604 case 0: /* add */
8605 tmp = load_reg(s, rd);
8606 tmp2 = load_reg(s, rm);
8607 tcg_gen_add_i32(tmp, tmp, tmp2);
8608 dead_tmp(tmp2);
8609 store_reg(s, rd, tmp);
8610 break;
8611 case 1: /* cmp */
8612 tmp = load_reg(s, rd);
8613 tmp2 = load_reg(s, rm);
8614 gen_helper_sub_cc(tmp, tmp, tmp2);
8615 dead_tmp(tmp2);
8616 dead_tmp(tmp);
8617 break;
8618 case 2: /* mov/cpy */
8619 tmp = load_reg(s, rm);
8620 store_reg(s, rd, tmp);
8621 break;
8622 case 3:/* branch [and link] exchange thumb register */
8623 tmp = load_reg(s, rm);
8624 if (insn & (1 << 7)) {
8625 val = (uint32_t)s->pc | 1;
8626 tmp2 = new_tmp();
8627 tcg_gen_movi_i32(tmp2, val);
8628 store_reg(s, 14, tmp2);
8629 }
8630 gen_bx(s, tmp);
8631 break;
8632 }
8633 break;
8634 }
8635
8636 /* data processing register */
8637 rd = insn & 7;
8638 rm = (insn >> 3) & 7;
8639 op = (insn >> 6) & 0xf;
8640 if (op == 2 || op == 3 || op == 4 || op == 7) {
8641 /* the shift/rotate ops want the operands backwards */
8642 val = rm;
8643 rm = rd;
8644 rd = val;
8645 val = 1;
8646 } else {
8647 val = 0;
8648 }
8649
8650 if (op == 9) { /* neg */
8651 tmp = new_tmp();
8652 tcg_gen_movi_i32(tmp, 0);
8653 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8654 tmp = load_reg(s, rd);
8655 } else {
8656 TCGV_UNUSED(tmp);
8657 }
8658
8659 tmp2 = load_reg(s, rm);
8660 switch (op) {
8661 case 0x0: /* and */
8662 tcg_gen_and_i32(tmp, tmp, tmp2);
8663 if (!s->condexec_mask)
8664 gen_logic_CC(tmp);
8665 break;
8666 case 0x1: /* eor */
8667 tcg_gen_xor_i32(tmp, tmp, tmp2);
8668 if (!s->condexec_mask)
8669 gen_logic_CC(tmp);
8670 break;
8671 case 0x2: /* lsl */
8672 if (s->condexec_mask) {
8673 gen_helper_shl(tmp2, tmp2, tmp);
8674 } else {
8675 gen_helper_shl_cc(tmp2, tmp2, tmp);
8676 gen_logic_CC(tmp2);
8677 }
8678 break;
8679 case 0x3: /* lsr */
8680 if (s->condexec_mask) {
8681 gen_helper_shr(tmp2, tmp2, tmp);
8682 } else {
8683 gen_helper_shr_cc(tmp2, tmp2, tmp);
8684 gen_logic_CC(tmp2);
8685 }
8686 break;
8687 case 0x4: /* asr */
8688 if (s->condexec_mask) {
8689 gen_helper_sar(tmp2, tmp2, tmp);
8690 } else {
8691 gen_helper_sar_cc(tmp2, tmp2, tmp);
8692 gen_logic_CC(tmp2);
8693 }
8694 break;
8695 case 0x5: /* adc */
8696 if (s->condexec_mask)
8697 gen_adc(tmp, tmp2);
8698 else
8699 gen_helper_adc_cc(tmp, tmp, tmp2);
8700 break;
8701 case 0x6: /* sbc */
8702 if (s->condexec_mask)
8703 gen_sub_carry(tmp, tmp, tmp2);
8704 else
8705 gen_helper_sbc_cc(tmp, tmp, tmp2);
8706 break;
8707 case 0x7: /* ror */
8708 if (s->condexec_mask) {
8709 tcg_gen_andi_i32(tmp, tmp, 0x1f);
8710 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
8711 } else {
8712 gen_helper_ror_cc(tmp2, tmp2, tmp);
8713 gen_logic_CC(tmp2);
8714 }
8715 break;
8716 case 0x8: /* tst */
8717 tcg_gen_and_i32(tmp, tmp, tmp2);
8718 gen_logic_CC(tmp);
8719 rd = 16;
8720 break;
8721 case 0x9: /* neg */
8722 if (s->condexec_mask)
8723 tcg_gen_neg_i32(tmp, tmp2);
8724 else
8725 gen_helper_sub_cc(tmp, tmp, tmp2);
8726 break;
8727 case 0xa: /* cmp */
8728 gen_helper_sub_cc(tmp, tmp, tmp2);
8729 rd = 16;
8730 break;
8731 case 0xb: /* cmn */
8732 gen_helper_add_cc(tmp, tmp, tmp2);
8733 rd = 16;
8734 break;
8735 case 0xc: /* orr */
8736 tcg_gen_or_i32(tmp, tmp, tmp2);
8737 if (!s->condexec_mask)
8738 gen_logic_CC(tmp);
8739 break;
8740 case 0xd: /* mul */
8741 tcg_gen_mul_i32(tmp, tmp, tmp2);
8742 if (!s->condexec_mask)
8743 gen_logic_CC(tmp);
8744 break;
8745 case 0xe: /* bic */
8746 tcg_gen_andc_i32(tmp, tmp, tmp2);
8747 if (!s->condexec_mask)
8748 gen_logic_CC(tmp);
8749 break;
8750 case 0xf: /* mvn */
8751 tcg_gen_not_i32(tmp2, tmp2);
8752 if (!s->condexec_mask)
8753 gen_logic_CC(tmp2);
8754 val = 1;
8755 rm = rd;
8756 break;
8757 }
8758 if (rd != 16) {
8759 if (val) {
8760 store_reg(s, rm, tmp2);
8761 if (op != 0xf)
8762 dead_tmp(tmp);
8763 } else {
8764 store_reg(s, rd, tmp);
8765 dead_tmp(tmp2);
8766 }
8767 } else {
8768 dead_tmp(tmp);
8769 dead_tmp(tmp2);
8770 }
8771 break;
8772
8773 case 5:
8774 /* load/store register offset. */
8775 rd = insn & 7;
8776 rn = (insn >> 3) & 7;
8777 rm = (insn >> 6) & 7;
8778 op = (insn >> 9) & 7;
8779 addr = load_reg(s, rn);
8780 tmp = load_reg(s, rm);
8781 tcg_gen_add_i32(addr, addr, tmp);
8782 dead_tmp(tmp);
8783
8784 if (op < 3) /* store */
8785 tmp = load_reg(s, rd);
8786
8787 switch (op) {
8788 case 0: /* str */
8789 gen_st32(tmp, addr, IS_USER(s));
8790 break;
8791 case 1: /* strh */
8792 gen_st16(tmp, addr, IS_USER(s));
8793 break;
8794 case 2: /* strb */
8795 gen_st8(tmp, addr, IS_USER(s));
8796 break;
8797 case 3: /* ldrsb */
8798 tmp = gen_ld8s(addr, IS_USER(s));
8799 break;
8800 case 4: /* ldr */
8801 tmp = gen_ld32(addr, IS_USER(s));
8802 break;
8803 case 5: /* ldrh */
8804 tmp = gen_ld16u(addr, IS_USER(s));
8805 break;
8806 case 6: /* ldrb */
8807 tmp = gen_ld8u(addr, IS_USER(s));
8808 break;
8809 case 7: /* ldrsh */
8810 tmp = gen_ld16s(addr, IS_USER(s));
8811 break;
8812 }
8813 if (op >= 3) /* load */
8814 store_reg(s, rd, tmp);
8815 dead_tmp(addr);
8816 break;
8817
8818 case 6:
8819 /* load/store word immediate offset */
8820 rd = insn & 7;
8821 rn = (insn >> 3) & 7;
8822 addr = load_reg(s, rn);
8823 val = (insn >> 4) & 0x7c;
8824 tcg_gen_addi_i32(addr, addr, val);
8825
8826 if (insn & (1 << 11)) {
8827 /* load */
8828 tmp = gen_ld32(addr, IS_USER(s));
8829 store_reg(s, rd, tmp);
8830 } else {
8831 /* store */
8832 tmp = load_reg(s, rd);
8833 gen_st32(tmp, addr, IS_USER(s));
8834 }
8835 dead_tmp(addr);
8836 break;
8837
8838 case 7:
8839 /* load/store byte immediate offset */
8840 rd = insn & 7;
8841 rn = (insn >> 3) & 7;
8842 addr = load_reg(s, rn);
8843 val = (insn >> 6) & 0x1f;
8844 tcg_gen_addi_i32(addr, addr, val);
8845
8846 if (insn & (1 << 11)) {
8847 /* load */
8848 tmp = gen_ld8u(addr, IS_USER(s));
8849 store_reg(s, rd, tmp);
8850 } else {
8851 /* store */
8852 tmp = load_reg(s, rd);
8853 gen_st8(tmp, addr, IS_USER(s));
8854 }
8855 dead_tmp(addr);
8856 break;
8857
8858 case 8:
8859 /* load/store halfword immediate offset */
8860 rd = insn & 7;
8861 rn = (insn >> 3) & 7;
8862 addr = load_reg(s, rn);
8863 val = (insn >> 5) & 0x3e;
8864 tcg_gen_addi_i32(addr, addr, val);
8865
8866 if (insn & (1 << 11)) {
8867 /* load */
8868 tmp = gen_ld16u(addr, IS_USER(s));
8869 store_reg(s, rd, tmp);
8870 } else {
8871 /* store */
8872 tmp = load_reg(s, rd);
8873 gen_st16(tmp, addr, IS_USER(s));
8874 }
8875 dead_tmp(addr);
8876 break;
8877
8878 case 9:
8879 /* load/store from stack */
8880 rd = (insn >> 8) & 7;
8881 addr = load_reg(s, 13);
8882 val = (insn & 0xff) * 4;
8883 tcg_gen_addi_i32(addr, addr, val);
8884
8885 if (insn & (1 << 11)) {
8886 /* load */
8887 tmp = gen_ld32(addr, IS_USER(s));
8888 store_reg(s, rd, tmp);
8889 } else {
8890 /* store */
8891 tmp = load_reg(s, rd);
8892 gen_st32(tmp, addr, IS_USER(s));
8893 }
8894 dead_tmp(addr);
8895 break;
8896
8897 case 10:
8898 /* add to high reg */
8899 rd = (insn >> 8) & 7;
8900 if (insn & (1 << 11)) {
8901 /* SP */
8902 tmp = load_reg(s, 13);
8903 } else {
8904 /* PC. bit 1 is ignored. */
8905 tmp = new_tmp();
8906 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
8907 }
8908 val = (insn & 0xff) * 4;
8909 tcg_gen_addi_i32(tmp, tmp, val);
8910 store_reg(s, rd, tmp);
8911 break;
8912
8913 case 11:
8914 /* misc */
8915 op = (insn >> 8) & 0xf;
8916 switch (op) {
8917 case 0:
8918 /* adjust stack pointer */
8919 tmp = load_reg(s, 13);
8920 val = (insn & 0x7f) * 4;
8921 if (insn & (1 << 7))
8922 val = -(int32_t)val;
8923 tcg_gen_addi_i32(tmp, tmp, val);
8924 store_reg(s, 13, tmp);
8925 break;
8926
8927 case 2: /* sign/zero extend. */
8928 ARCH(6);
8929 rd = insn & 7;
8930 rm = (insn >> 3) & 7;
8931 tmp = load_reg(s, rm);
8932 switch ((insn >> 6) & 3) {
8933 case 0: gen_sxth(tmp); break;
8934 case 1: gen_sxtb(tmp); break;
8935 case 2: gen_uxth(tmp); break;
8936 case 3: gen_uxtb(tmp); break;
8937 }
8938 store_reg(s, rd, tmp);
8939 break;
8940 case 4: case 5: case 0xc: case 0xd:
8941 /* push/pop */
8942 addr = load_reg(s, 13);
8943 if (insn & (1 << 8))
8944 offset = 4;
8945 else
8946 offset = 0;
8947 for (i = 0; i < 8; i++) {
8948 if (insn & (1 << i))
8949 offset += 4;
8950 }
8951 if ((insn & (1 << 11)) == 0) {
8952 tcg_gen_addi_i32(addr, addr, -offset);
8953 }
8954 for (i = 0; i < 8; i++) {
8955 if (insn & (1 << i)) {
8956 if (insn & (1 << 11)) {
8957 /* pop */
8958 tmp = gen_ld32(addr, IS_USER(s));
8959 store_reg(s, i, tmp);
8960 } else {
8961 /* push */
8962 tmp = load_reg(s, i);
8963 gen_st32(tmp, addr, IS_USER(s));
8964 }
8965 /* advance to the next address. */
8966 tcg_gen_addi_i32(addr, addr, 4);
8967 }
8968 }
8969 TCGV_UNUSED(tmp);
8970 if (insn & (1 << 8)) {
8971 if (insn & (1 << 11)) {
8972 /* pop pc */
8973 tmp = gen_ld32(addr, IS_USER(s));
8974 /* don't set the pc until the rest of the instruction
8975 has completed */
8976 } else {
8977 /* push lr */
8978 tmp = load_reg(s, 14);
8979 gen_st32(tmp, addr, IS_USER(s));
8980 }
8981 tcg_gen_addi_i32(addr, addr, 4);
8982 }
8983 if ((insn & (1 << 11)) == 0) {
8984 tcg_gen_addi_i32(addr, addr, -offset);
8985 }
8986 /* write back the new stack pointer */
8987 store_reg(s, 13, addr);
8988 /* set the new PC value */
8989 if ((insn & 0x0900) == 0x0900)
8990 gen_bx(s, tmp);
8991 break;
8992
8993 case 1: case 3: case 9: case 11: /* czb */
8994 rm = insn & 7;
8995 tmp = load_reg(s, rm);
8996 s->condlabel = gen_new_label();
8997 s->condjmp = 1;
8998 if (insn & (1 << 11))
8999 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9000 else
9001 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
9002 dead_tmp(tmp);
9003 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9004 val = (uint32_t)s->pc + 2;
9005 val += offset;
9006 gen_jmp(s, val);
9007 break;
9008
9009 case 15: /* IT, nop-hint. */
9010 if ((insn & 0xf) == 0) {
9011 gen_nop_hint(s, (insn >> 4) & 0xf);
9012 break;
9013 }
9014 /* If Then. */
9015 s->condexec_cond = (insn >> 4) & 0xe;
9016 s->condexec_mask = insn & 0x1f;
9017 /* No actual code generated for this insn, just setup state. */
9018 break;
9019
9020 case 0xe: /* bkpt */
9021 gen_exception_insn(s, 2, EXCP_BKPT);
9022 break;
9023
9024 case 0xa: /* rev */
9025 ARCH(6);
9026 rn = (insn >> 3) & 0x7;
9027 rd = insn & 0x7;
9028 tmp = load_reg(s, rn);
9029 switch ((insn >> 6) & 3) {
9030 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
9031 case 1: gen_rev16(tmp); break;
9032 case 3: gen_revsh(tmp); break;
9033 default: goto illegal_op;
9034 }
9035 store_reg(s, rd, tmp);
9036 break;
9037
9038 case 6: /* cps */
9039 ARCH(6);
9040 if (IS_USER(s))
9041 break;
9042 if (IS_M(env)) {
9043 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9044 /* PRIMASK */
9045 if (insn & 1) {
9046 addr = tcg_const_i32(16);
9047 gen_helper_v7m_msr(cpu_env, addr, tmp);
9048 tcg_temp_free_i32(addr);
9049 }
9050 /* FAULTMASK */
9051 if (insn & 2) {
9052 addr = tcg_const_i32(17);
9053 gen_helper_v7m_msr(cpu_env, addr, tmp);
9054 tcg_temp_free_i32(addr);
9055 }
9056 tcg_temp_free_i32(tmp);
9057 gen_lookup_tb(s);
9058 } else {
9059 if (insn & (1 << 4))
9060 shift = CPSR_A | CPSR_I | CPSR_F;
9061 else
9062 shift = 0;
9063 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9064 }
9065 break;
9066
9067 default:
9068 goto undef;
9069 }
9070 break;
9071
9072 case 12:
9073 /* load/store multiple */
9074 rn = (insn >> 8) & 0x7;
9075 addr = load_reg(s, rn);
9076 for (i = 0; i < 8; i++) {
9077 if (insn & (1 << i)) {
9078 if (insn & (1 << 11)) {
9079 /* load */
9080 tmp = gen_ld32(addr, IS_USER(s));
9081 store_reg(s, i, tmp);
9082 } else {
9083 /* store */
9084 tmp = load_reg(s, i);
9085 gen_st32(tmp, addr, IS_USER(s));
9086 }
9087 /* advance to the next address */
9088 tcg_gen_addi_i32(addr, addr, 4);
9089 }
9090 }
9091 /* Base register writeback. */
9092 if ((insn & (1 << rn)) == 0) {
9093 store_reg(s, rn, addr);
9094 } else {
9095 dead_tmp(addr);
9096 }
9097 break;
9098
9099 case 13:
9100 /* conditional branch or swi */
9101 cond = (insn >> 8) & 0xf;
9102 if (cond == 0xe)
9103 goto undef;
9104
9105 if (cond == 0xf) {
9106 /* swi */
9107 gen_set_pc_im(s->pc);
9108 s->is_jmp = DISAS_SWI;
9109 break;
9110 }
9111 /* generate a conditional jump to next instruction */
9112 s->condlabel = gen_new_label();
9113 gen_test_cc(cond ^ 1, s->condlabel);
9114 s->condjmp = 1;
9115
9116 /* jump to the offset */
9117 val = (uint32_t)s->pc + 2;
9118 offset = ((int32_t)insn << 24) >> 24;
9119 val += offset << 1;
9120 gen_jmp(s, val);
9121 break;
9122
9123 case 14:
9124 if (insn & (1 << 11)) {
9125 if (disas_thumb2_insn(env, s, insn))
9126 goto undef32;
9127 break;
9128 }
9129 /* unconditional branch */
9130 val = (uint32_t)s->pc;
9131 offset = ((int32_t)insn << 21) >> 21;
9132 val += (offset << 1) + 2;
9133 gen_jmp(s, val);
9134 break;
9135
9136 case 15:
9137 if (disas_thumb2_insn(env, s, insn))
9138 goto undef32;
9139 break;
9140 }
9141 return;
9142 undef32:
9143 gen_exception_insn(s, 4, EXCP_UDEF);
9144 return;
9145 illegal_op:
9146 undef:
9147 gen_exception_insn(s, 2, EXCP_UDEF);
9148 }
9149
9150 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9151 basic block 'tb'. If search_pc is TRUE, also generate PC
9152 information for each intermediate instruction. */
9153 static inline void gen_intermediate_code_internal(CPUState *env,
9154 TranslationBlock *tb,
9155 int search_pc)
9156 {
9157 DisasContext dc1, *dc = &dc1;
9158 CPUBreakpoint *bp;
9159 uint16_t *gen_opc_end;
9160 int j, lj;
9161 target_ulong pc_start;
9162 uint32_t next_page_start;
9163 int num_insns;
9164 int max_insns;
9165
9166 /* generate intermediate code */
9167 num_temps = 0;
9168
9169 pc_start = tb->pc;
9170
9171 dc->tb = tb;
9172
9173 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9174
9175 dc->is_jmp = DISAS_NEXT;
9176 dc->pc = pc_start;
9177 dc->singlestep_enabled = env->singlestep_enabled;
9178 dc->condjmp = 0;
9179 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9180 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9181 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9182 #if !defined(CONFIG_USER_ONLY)
9183 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9184 #endif
9185 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9186 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9187 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9188 cpu_F0s = tcg_temp_new_i32();
9189 cpu_F1s = tcg_temp_new_i32();
9190 cpu_F0d = tcg_temp_new_i64();
9191 cpu_F1d = tcg_temp_new_i64();
9192 cpu_V0 = cpu_F0d;
9193 cpu_V1 = cpu_F1d;
9194 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9195 cpu_M0 = tcg_temp_new_i64();
9196 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9197 lj = -1;
9198 num_insns = 0;
9199 max_insns = tb->cflags & CF_COUNT_MASK;
9200 if (max_insns == 0)
9201 max_insns = CF_COUNT_MASK;
9202
9203 gen_icount_start();
9204
9205 /* A note on handling of the condexec (IT) bits:
9206 *
9207 * We want to avoid the overhead of having to write the updated condexec
9208 * bits back to the CPUState for every instruction in an IT block. So:
9209 * (1) if the condexec bits are not already zero then we write
9210 * zero back into the CPUState now. This avoids complications trying
9211 * to do it at the end of the block. (For example if we don't do this
9212 * it's hard to identify whether we can safely skip writing condexec
9213 * at the end of the TB, which we definitely want to do for the case
9214 * where a TB doesn't do anything with the IT state at all.)
9215 * (2) if we are going to leave the TB then we call gen_set_condexec()
9216 * which will write the correct value into CPUState if zero is wrong.
9217 * This is done both for leaving the TB at the end, and for leaving
9218 * it because of an exception we know will happen, which is done in
9219 * gen_exception_insn(). The latter is necessary because we need to
9220 * leave the TB with the PC/IT state just prior to execution of the
9221 * instruction which caused the exception.
9222 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9223 * then the CPUState will be wrong and we need to reset it.
9224 * This is handled in the same way as restoration of the
9225 * PC in these situations: we will be called again with search_pc=1
9226 * and generate a mapping of the condexec bits for each PC in
9227 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9228 * the condexec bits.
9229 *
9230 * Note that there are no instructions which can read the condexec
9231 * bits, and none which can write non-static values to them, so
9232 * we don't need to care about whether CPUState is correct in the
9233 * middle of a TB.
9234 */
9235
9236 /* Reset the conditional execution bits immediately. This avoids
9237 complications trying to do it at the end of the block. */
9238 if (dc->condexec_mask || dc->condexec_cond)
9239 {
9240 TCGv tmp = new_tmp();
9241 tcg_gen_movi_i32(tmp, 0);
9242 store_cpu_field(tmp, condexec_bits);
9243 }
9244 do {
9245 #ifdef CONFIG_USER_ONLY
9246 /* Intercept jump to the magic kernel page. */
9247 if (dc->pc >= 0xffff0000) {
9248 /* We always get here via a jump, so know we are not in a
9249 conditional execution block. */
9250 gen_exception(EXCP_KERNEL_TRAP);
9251 dc->is_jmp = DISAS_UPDATE;
9252 break;
9253 }
9254 #else
9255 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9256 /* We always get here via a jump, so know we are not in a
9257 conditional execution block. */
9258 gen_exception(EXCP_EXCEPTION_EXIT);
9259 dc->is_jmp = DISAS_UPDATE;
9260 break;
9261 }
9262 #endif
9263
9264 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9265 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9266 if (bp->pc == dc->pc) {
9267 gen_exception_insn(dc, 0, EXCP_DEBUG);
9268 /* Advance PC so that clearing the breakpoint will
9269 invalidate this TB. */
9270 dc->pc += 2;
9271 goto done_generating;
9272 break;
9273 }
9274 }
9275 }
9276 if (search_pc) {
9277 j = gen_opc_ptr - gen_opc_buf;
9278 if (lj < j) {
9279 lj++;
9280 while (lj < j)
9281 gen_opc_instr_start[lj++] = 0;
9282 }
9283 gen_opc_pc[lj] = dc->pc;
9284 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9285 gen_opc_instr_start[lj] = 1;
9286 gen_opc_icount[lj] = num_insns;
9287 }
9288
9289 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9290 gen_io_start();
9291
9292 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9293 tcg_gen_debug_insn_start(dc->pc);
9294 }
9295
9296 if (dc->thumb) {
9297 disas_thumb_insn(env, dc);
9298 if (dc->condexec_mask) {
9299 dc->condexec_cond = (dc->condexec_cond & 0xe)
9300 | ((dc->condexec_mask >> 4) & 1);
9301 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9302 if (dc->condexec_mask == 0) {
9303 dc->condexec_cond = 0;
9304 }
9305 }
9306 } else {
9307 disas_arm_insn(env, dc);
9308 }
9309 if (num_temps) {
9310 fprintf(stderr, "Internal resource leak before %08x\n", dc->pc);
9311 num_temps = 0;
9312 }
9313
9314 if (dc->condjmp && !dc->is_jmp) {
9315 gen_set_label(dc->condlabel);
9316 dc->condjmp = 0;
9317 }
9318 /* Translation stops when a conditional branch is encountered.
9319 * Otherwise the subsequent code could get translated several times.
9320 * Also stop translation when a page boundary is reached. This
9321 * ensures prefetch aborts occur at the right place. */
9322 num_insns ++;
9323 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9324 !env->singlestep_enabled &&
9325 !singlestep &&
9326 dc->pc < next_page_start &&
9327 num_insns < max_insns);
9328
9329 if (tb->cflags & CF_LAST_IO) {
9330 if (dc->condjmp) {
9331 /* FIXME: This can theoretically happen with self-modifying
9332 code. */
9333 cpu_abort(env, "IO on conditional branch instruction");
9334 }
9335 gen_io_end();
9336 }
9337
9338 /* At this stage dc->condjmp will only be set when the skipped
9339 instruction was a conditional branch or trap, and the PC has
9340 already been written. */
9341 if (unlikely(env->singlestep_enabled)) {
9342 /* Make sure the pc is updated, and raise a debug exception. */
9343 if (dc->condjmp) {
9344 gen_set_condexec(dc);
9345 if (dc->is_jmp == DISAS_SWI) {
9346 gen_exception(EXCP_SWI);
9347 } else {
9348 gen_exception(EXCP_DEBUG);
9349 }
9350 gen_set_label(dc->condlabel);
9351 }
9352 if (dc->condjmp || !dc->is_jmp) {
9353 gen_set_pc_im(dc->pc);
9354 dc->condjmp = 0;
9355 }
9356 gen_set_condexec(dc);
9357 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9358 gen_exception(EXCP_SWI);
9359 } else {
9360 /* FIXME: Single stepping a WFI insn will not halt
9361 the CPU. */
9362 gen_exception(EXCP_DEBUG);
9363 }
9364 } else {
9365 /* While branches must always occur at the end of an IT block,
9366 there are a few other things that can cause us to terminate
9367 the TB in the middel of an IT block:
9368 - Exception generating instructions (bkpt, swi, undefined).
9369 - Page boundaries.
9370 - Hardware watchpoints.
9371 Hardware breakpoints have already been handled and skip this code.
9372 */
9373 gen_set_condexec(dc);
9374 switch(dc->is_jmp) {
9375 case DISAS_NEXT:
9376 gen_goto_tb(dc, 1, dc->pc);
9377 break;
9378 default:
9379 case DISAS_JUMP:
9380 case DISAS_UPDATE:
9381 /* indicate that the hash table must be used to find the next TB */
9382 tcg_gen_exit_tb(0);
9383 break;
9384 case DISAS_TB_JUMP:
9385 /* nothing more to generate */
9386 break;
9387 case DISAS_WFI:
9388 gen_helper_wfi();
9389 break;
9390 case DISAS_SWI:
9391 gen_exception(EXCP_SWI);
9392 break;
9393 }
9394 if (dc->condjmp) {
9395 gen_set_label(dc->condlabel);
9396 gen_set_condexec(dc);
9397 gen_goto_tb(dc, 1, dc->pc);
9398 dc->condjmp = 0;
9399 }
9400 }
9401
9402 done_generating:
9403 gen_icount_end(tb, num_insns);
9404 *gen_opc_ptr = INDEX_op_end;
9405
9406 #ifdef DEBUG_DISAS
9407 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9408 qemu_log("----------------\n");
9409 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9410 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9411 qemu_log("\n");
9412 }
9413 #endif
9414 if (search_pc) {
9415 j = gen_opc_ptr - gen_opc_buf;
9416 lj++;
9417 while (lj <= j)
9418 gen_opc_instr_start[lj++] = 0;
9419 } else {
9420 tb->size = dc->pc - pc_start;
9421 tb->icount = num_insns;
9422 }
9423 }
9424
9425 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9426 {
9427 gen_intermediate_code_internal(env, tb, 0);
9428 }
9429
9430 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9431 {
9432 gen_intermediate_code_internal(env, tb, 1);
9433 }
9434
9435 static const char *cpu_mode_names[16] = {
9436 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9437 "???", "???", "???", "und", "???", "???", "???", "sys"
9438 };
9439
9440 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9441 int flags)
9442 {
9443 int i;
9444 #if 0
9445 union {
9446 uint32_t i;
9447 float s;
9448 } s0, s1;
9449 CPU_DoubleU d;
9450 /* ??? This assumes float64 and double have the same layout.
9451 Oh well, it's only debug dumps. */
9452 union {
9453 float64 f64;
9454 double d;
9455 } d0;
9456 #endif
9457 uint32_t psr;
9458
9459 for(i=0;i<16;i++) {
9460 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9461 if ((i % 4) == 3)
9462 cpu_fprintf(f, "\n");
9463 else
9464 cpu_fprintf(f, " ");
9465 }
9466 psr = cpsr_read(env);
9467 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9468 psr,
9469 psr & (1 << 31) ? 'N' : '-',
9470 psr & (1 << 30) ? 'Z' : '-',
9471 psr & (1 << 29) ? 'C' : '-',
9472 psr & (1 << 28) ? 'V' : '-',
9473 psr & CPSR_T ? 'T' : 'A',
9474 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9475
9476 #if 0
9477 for (i = 0; i < 16; i++) {
9478 d.d = env->vfp.regs[i];
9479 s0.i = d.l.lower;
9480 s1.i = d.l.upper;
9481 d0.f64 = d.d;
9482 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9483 i * 2, (int)s0.i, s0.s,
9484 i * 2 + 1, (int)s1.i, s1.s,
9485 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9486 d0.d);
9487 }
9488 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9489 #endif
9490 }
9491
9492 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9493 unsigned long searched_pc, int pc_pos, void *puc)
9494 {
9495 env->regs[15] = gen_opc_pc[pc_pos];
9496 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9497 }
QEmu