9 #include "qemu-common.h"
10 #include "host-utils.h"
11 #if !defined(CONFIG_USER_ONLY)
12 #include "hw/loader.h"
15 static uint32_t cortexa9_cp15_c0_c1
[8] =
16 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
18 static uint32_t cortexa9_cp15_c0_c2
[8] =
19 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
21 static uint32_t cortexa8_cp15_c0_c1
[8] =
22 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
24 static uint32_t cortexa8_cp15_c0_c2
[8] =
25 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
27 static uint32_t mpcore_cp15_c0_c1
[8] =
28 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
30 static uint32_t mpcore_cp15_c0_c2
[8] =
31 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
33 static uint32_t arm1136_cp15_c0_c1
[8] =
34 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
36 static uint32_t arm1136_cp15_c0_c2
[8] =
37 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
39 static uint32_t cpu_arm_find_by_name(const char *name
);
41 static inline void set_feature(CPUARMState
*env
, int feature
)
43 env
->features
|= 1u << feature
;
46 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
48 env
->cp15
.c0_cpuid
= id
;
50 case ARM_CPUID_ARM926
:
51 set_feature(env
, ARM_FEATURE_VFP
);
52 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
53 env
->cp15
.c0_cachetype
= 0x1dd20d2;
54 env
->cp15
.c1_sys
= 0x00090078;
56 case ARM_CPUID_ARM946
:
57 set_feature(env
, ARM_FEATURE_MPU
);
58 env
->cp15
.c0_cachetype
= 0x0f004006;
59 env
->cp15
.c1_sys
= 0x00000078;
61 case ARM_CPUID_ARM1026
:
62 set_feature(env
, ARM_FEATURE_VFP
);
63 set_feature(env
, ARM_FEATURE_AUXCR
);
64 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
65 env
->cp15
.c0_cachetype
= 0x1dd20d2;
66 env
->cp15
.c1_sys
= 0x00090078;
68 case ARM_CPUID_ARM1136_R2
:
69 case ARM_CPUID_ARM1136
:
70 set_feature(env
, ARM_FEATURE_V6
);
71 set_feature(env
, ARM_FEATURE_VFP
);
72 set_feature(env
, ARM_FEATURE_AUXCR
);
73 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
74 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
75 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
76 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
77 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
78 env
->cp15
.c0_cachetype
= 0x1dd20d2;
79 env
->cp15
.c1_sys
= 0x00050078;
81 case ARM_CPUID_ARM11MPCORE
:
82 set_feature(env
, ARM_FEATURE_V6
);
83 set_feature(env
, ARM_FEATURE_V6K
);
84 set_feature(env
, ARM_FEATURE_VFP
);
85 set_feature(env
, ARM_FEATURE_AUXCR
);
86 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
87 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
88 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
89 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
90 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
91 env
->cp15
.c0_cachetype
= 0x1dd20d2;
93 case ARM_CPUID_CORTEXA8
:
94 set_feature(env
, ARM_FEATURE_V6
);
95 set_feature(env
, ARM_FEATURE_V6K
);
96 set_feature(env
, ARM_FEATURE_V7
);
97 set_feature(env
, ARM_FEATURE_AUXCR
);
98 set_feature(env
, ARM_FEATURE_THUMB2
);
99 set_feature(env
, ARM_FEATURE_VFP
);
100 set_feature(env
, ARM_FEATURE_VFP3
);
101 set_feature(env
, ARM_FEATURE_NEON
);
102 set_feature(env
, ARM_FEATURE_THUMB2EE
);
103 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
104 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
105 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
106 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
107 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
108 env
->cp15
.c0_cachetype
= 0x82048004;
109 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
110 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
111 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
112 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
113 env
->cp15
.c1_sys
= 0x00c50078;
115 case ARM_CPUID_CORTEXA9
:
116 set_feature(env
, ARM_FEATURE_V6
);
117 set_feature(env
, ARM_FEATURE_V6K
);
118 set_feature(env
, ARM_FEATURE_V7
);
119 set_feature(env
, ARM_FEATURE_AUXCR
);
120 set_feature(env
, ARM_FEATURE_THUMB2
);
121 set_feature(env
, ARM_FEATURE_VFP
);
122 set_feature(env
, ARM_FEATURE_VFP3
);
123 set_feature(env
, ARM_FEATURE_VFP_FP16
);
124 set_feature(env
, ARM_FEATURE_NEON
);
125 set_feature(env
, ARM_FEATURE_THUMB2EE
);
126 /* Note that A9 supports the MP extensions even for
127 * A9UP and single-core A9MP (which are both different
128 * and valid configurations; we don't model A9UP).
130 set_feature(env
, ARM_FEATURE_V7MP
);
131 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41034000; /* Guess */
132 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
133 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
134 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
135 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
136 env
->cp15
.c0_cachetype
= 0x80038003;
137 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
138 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
139 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
140 env
->cp15
.c1_sys
= 0x00c50078;
142 case ARM_CPUID_CORTEXM3
:
143 set_feature(env
, ARM_FEATURE_V6
);
144 set_feature(env
, ARM_FEATURE_THUMB2
);
145 set_feature(env
, ARM_FEATURE_V7
);
146 set_feature(env
, ARM_FEATURE_M
);
147 set_feature(env
, ARM_FEATURE_DIV
);
149 case ARM_CPUID_ANY
: /* For userspace emulation. */
150 set_feature(env
, ARM_FEATURE_V6
);
151 set_feature(env
, ARM_FEATURE_V6K
);
152 set_feature(env
, ARM_FEATURE_V7
);
153 set_feature(env
, ARM_FEATURE_THUMB2
);
154 set_feature(env
, ARM_FEATURE_VFP
);
155 set_feature(env
, ARM_FEATURE_VFP3
);
156 set_feature(env
, ARM_FEATURE_VFP_FP16
);
157 set_feature(env
, ARM_FEATURE_NEON
);
158 set_feature(env
, ARM_FEATURE_THUMB2EE
);
159 set_feature(env
, ARM_FEATURE_DIV
);
160 set_feature(env
, ARM_FEATURE_V7MP
);
162 case ARM_CPUID_TI915T
:
163 case ARM_CPUID_TI925T
:
164 set_feature(env
, ARM_FEATURE_OMAPCP
);
165 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
166 env
->cp15
.c0_cachetype
= 0x5109149;
167 env
->cp15
.c1_sys
= 0x00000070;
168 env
->cp15
.c15_i_max
= 0x000;
169 env
->cp15
.c15_i_min
= 0xff0;
171 case ARM_CPUID_PXA250
:
172 case ARM_CPUID_PXA255
:
173 case ARM_CPUID_PXA260
:
174 case ARM_CPUID_PXA261
:
175 case ARM_CPUID_PXA262
:
176 set_feature(env
, ARM_FEATURE_XSCALE
);
177 /* JTAG_ID is ((id << 28) | 0x09265013) */
178 env
->cp15
.c0_cachetype
= 0xd172172;
179 env
->cp15
.c1_sys
= 0x00000078;
181 case ARM_CPUID_PXA270_A0
:
182 case ARM_CPUID_PXA270_A1
:
183 case ARM_CPUID_PXA270_B0
:
184 case ARM_CPUID_PXA270_B1
:
185 case ARM_CPUID_PXA270_C0
:
186 case ARM_CPUID_PXA270_C5
:
187 set_feature(env
, ARM_FEATURE_XSCALE
);
188 /* JTAG_ID is ((id << 28) | 0x09265013) */
189 set_feature(env
, ARM_FEATURE_IWMMXT
);
190 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
191 env
->cp15
.c0_cachetype
= 0xd172172;
192 env
->cp15
.c1_sys
= 0x00000078;
195 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
200 void cpu_reset(CPUARMState
*env
)
204 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
205 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
206 log_cpu_state(env
, 0);
209 id
= env
->cp15
.c0_cpuid
;
210 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
212 cpu_reset_model_id(env
, id
);
213 #if defined (CONFIG_USER_ONLY)
214 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
215 /* For user mode we must enable access to coprocessors */
216 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
217 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
218 env
->cp15
.c15_cpar
= 3;
219 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
220 env
->cp15
.c15_cpar
= 1;
223 /* SVC mode with interrupts disabled. */
224 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
225 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
226 clear at reset. Initial SP and PC are loaded from ROM. */
230 env
->uncached_cpsr
&= ~CPSR_I
;
233 /* We should really use ldl_phys here, in case the guest
234 modified flash and reset itself. However images
235 loaded via -kenrel have not been copied yet, so load the
236 values directly from there. */
237 env
->regs
[13] = ldl_p(rom
);
240 env
->regs
[15] = pc
& ~1;
243 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
244 env
->cp15
.c2_base_mask
= 0xffffc000u
;
246 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
247 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
248 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
252 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
256 /* VFP data registers are always little-endian. */
257 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
259 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
262 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
263 /* Aliases for Q regs. */
266 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
267 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
271 switch (reg
- nregs
) {
272 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
273 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
274 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
279 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
283 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
285 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
288 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
291 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
292 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
296 switch (reg
- nregs
) {
297 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
298 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
299 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
304 CPUARMState
*cpu_arm_init(const char *cpu_model
)
308 static int inited
= 0;
310 id
= cpu_arm_find_by_name(cpu_model
);
313 env
= qemu_mallocz(sizeof(CPUARMState
));
317 arm_translate_init();
320 env
->cpu_model_str
= cpu_model
;
321 env
->cp15
.c0_cpuid
= id
;
323 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
324 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
325 51, "arm-neon.xml", 0);
326 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
327 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
328 35, "arm-vfp3.xml", 0);
329 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
330 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
331 19, "arm-vfp.xml", 0);
342 static const struct arm_cpu_t arm_cpu_names
[] = {
343 { ARM_CPUID_ARM926
, "arm926"},
344 { ARM_CPUID_ARM946
, "arm946"},
345 { ARM_CPUID_ARM1026
, "arm1026"},
346 { ARM_CPUID_ARM1136
, "arm1136"},
347 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
348 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
349 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
350 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
351 { ARM_CPUID_CORTEXA9
, "cortex-a9"},
352 { ARM_CPUID_TI925T
, "ti925t" },
353 { ARM_CPUID_PXA250
, "pxa250" },
354 { ARM_CPUID_PXA255
, "pxa255" },
355 { ARM_CPUID_PXA260
, "pxa260" },
356 { ARM_CPUID_PXA261
, "pxa261" },
357 { ARM_CPUID_PXA262
, "pxa262" },
358 { ARM_CPUID_PXA270
, "pxa270" },
359 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
360 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
361 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
362 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
363 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
364 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
365 { ARM_CPUID_ANY
, "any"},
369 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
373 (*cpu_fprintf
)(f
, "Available CPUs:\n");
374 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
375 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
379 /* return 0 if not found */
380 static uint32_t cpu_arm_find_by_name(const char *name
)
386 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
387 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
388 id
= arm_cpu_names
[i
].id
;
395 void cpu_arm_close(CPUARMState
*env
)
400 uint32_t cpsr_read(CPUARMState
*env
)
404 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
405 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
406 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
407 | ((env
->condexec_bits
& 0xfc) << 8)
411 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
413 if (mask
& CPSR_NZCV
) {
414 env
->ZF
= (~val
) & CPSR_Z
;
416 env
->CF
= (val
>> 29) & 1;
417 env
->VF
= (val
<< 3) & 0x80000000;
420 env
->QF
= ((val
& CPSR_Q
) != 0);
422 env
->thumb
= ((val
& CPSR_T
) != 0);
423 if (mask
& CPSR_IT_0_1
) {
424 env
->condexec_bits
&= ~3;
425 env
->condexec_bits
|= (val
>> 25) & 3;
427 if (mask
& CPSR_IT_2_7
) {
428 env
->condexec_bits
&= 3;
429 env
->condexec_bits
|= (val
>> 8) & 0xfc;
431 if (mask
& CPSR_GE
) {
432 env
->GE
= (val
>> 16) & 0xf;
435 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
436 switch_mode(env
, val
& CPSR_M
);
438 mask
&= ~CACHED_CPSR_BITS
;
439 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
442 /* Sign/zero extend */
443 uint32_t HELPER(sxtb16
)(uint32_t x
)
446 res
= (uint16_t)(int8_t)x
;
447 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
451 uint32_t HELPER(uxtb16
)(uint32_t x
)
454 res
= (uint16_t)(uint8_t)x
;
455 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
459 uint32_t HELPER(clz
)(uint32_t x
)
464 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
468 if (num
== INT_MIN
&& den
== -1)
473 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
480 uint32_t HELPER(rbit
)(uint32_t x
)
482 x
= ((x
& 0xff000000) >> 24)
483 | ((x
& 0x00ff0000) >> 8)
484 | ((x
& 0x0000ff00) << 8)
485 | ((x
& 0x000000ff) << 24);
486 x
= ((x
& 0xf0f0f0f0) >> 4)
487 | ((x
& 0x0f0f0f0f) << 4);
488 x
= ((x
& 0x88888888) >> 3)
489 | ((x
& 0x44444444) >> 1)
490 | ((x
& 0x22222222) << 1)
491 | ((x
& 0x11111111) << 3);
495 uint32_t HELPER(abs
)(uint32_t x
)
497 return ((int32_t)x
< 0) ? -x
: x
;
500 #if defined(CONFIG_USER_ONLY)
502 void do_interrupt (CPUState
*env
)
504 env
->exception_index
= -1;
507 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
508 int mmu_idx
, int is_softmmu
)
511 env
->exception_index
= EXCP_PREFETCH_ABORT
;
512 env
->cp15
.c6_insn
= address
;
514 env
->exception_index
= EXCP_DATA_ABORT
;
515 env
->cp15
.c6_data
= address
;
520 /* These should probably raise undefined insn exceptions. */
521 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
523 int op1
= (insn
>> 8) & 0xf;
524 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
528 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
530 int op1
= (insn
>> 8) & 0xf;
531 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
535 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
537 cpu_abort(env
, "cp15 insn %08x\n", insn
);
540 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
542 cpu_abort(env
, "cp15 insn %08x\n", insn
);
545 /* These should probably raise undefined insn exceptions. */
546 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
548 cpu_abort(env
, "v7m_mrs %d\n", reg
);
551 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
553 cpu_abort(env
, "v7m_mrs %d\n", reg
);
557 void switch_mode(CPUState
*env
, int mode
)
559 if (mode
!= ARM_CPU_MODE_USR
)
560 cpu_abort(env
, "Tried to switch out of user mode\n");
563 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
565 cpu_abort(env
, "banked r13 write\n");
568 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
570 cpu_abort(env
, "banked r13 read\n");
576 extern int semihosting_enabled
;
578 /* Map CPU modes onto saved register banks. */
579 static inline int bank_number (int mode
)
582 case ARM_CPU_MODE_USR
:
583 case ARM_CPU_MODE_SYS
:
585 case ARM_CPU_MODE_SVC
:
587 case ARM_CPU_MODE_ABT
:
589 case ARM_CPU_MODE_UND
:
591 case ARM_CPU_MODE_IRQ
:
593 case ARM_CPU_MODE_FIQ
:
596 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
600 void switch_mode(CPUState
*env
, int mode
)
605 old_mode
= env
->uncached_cpsr
& CPSR_M
;
606 if (mode
== old_mode
)
609 if (old_mode
== ARM_CPU_MODE_FIQ
) {
610 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
611 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
612 } else if (mode
== ARM_CPU_MODE_FIQ
) {
613 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
614 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
617 i
= bank_number(old_mode
);
618 env
->banked_r13
[i
] = env
->regs
[13];
619 env
->banked_r14
[i
] = env
->regs
[14];
620 env
->banked_spsr
[i
] = env
->spsr
;
622 i
= bank_number(mode
);
623 env
->regs
[13] = env
->banked_r13
[i
];
624 env
->regs
[14] = env
->banked_r14
[i
];
625 env
->spsr
= env
->banked_spsr
[i
];
628 static void v7m_push(CPUARMState
*env
, uint32_t val
)
631 stl_phys(env
->regs
[13], val
);
634 static uint32_t v7m_pop(CPUARMState
*env
)
637 val
= ldl_phys(env
->regs
[13]);
642 /* Switch to V7M main or process stack pointer. */
643 static void switch_v7m_sp(CPUARMState
*env
, int process
)
646 if (env
->v7m
.current_sp
!= process
) {
647 tmp
= env
->v7m
.other_sp
;
648 env
->v7m
.other_sp
= env
->regs
[13];
650 env
->v7m
.current_sp
= process
;
654 static void do_v7m_exception_exit(CPUARMState
*env
)
659 type
= env
->regs
[15];
660 if (env
->v7m
.exception
!= 0)
661 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
663 /* Switch to the target stack. */
664 switch_v7m_sp(env
, (type
& 4) != 0);
666 env
->regs
[0] = v7m_pop(env
);
667 env
->regs
[1] = v7m_pop(env
);
668 env
->regs
[2] = v7m_pop(env
);
669 env
->regs
[3] = v7m_pop(env
);
670 env
->regs
[12] = v7m_pop(env
);
671 env
->regs
[14] = v7m_pop(env
);
672 env
->regs
[15] = v7m_pop(env
);
674 xpsr_write(env
, xpsr
, 0xfffffdff);
675 /* Undo stack alignment. */
678 /* ??? The exception return type specifies Thread/Handler mode. However
679 this is also implied by the xPSR value. Not sure what to do
680 if there is a mismatch. */
681 /* ??? Likewise for mismatches between the CONTROL register and the stack
685 static void do_interrupt_v7m(CPUARMState
*env
)
687 uint32_t xpsr
= xpsr_read(env
);
692 if (env
->v7m
.current_sp
)
694 if (env
->v7m
.exception
== 0)
697 /* For exceptions we just mark as pending on the NVIC, and let that
699 /* TODO: Need to escalate if the current priority is higher than the
700 one we're raising. */
701 switch (env
->exception_index
) {
703 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
707 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
709 case EXCP_PREFETCH_ABORT
:
710 case EXCP_DATA_ABORT
:
711 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
714 if (semihosting_enabled
) {
716 nr
= lduw_code(env
->regs
[15]) & 0xff;
719 env
->regs
[0] = do_arm_semihosting(env
);
723 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
726 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
728 case EXCP_EXCEPTION_EXIT
:
729 do_v7m_exception_exit(env
);
732 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
733 return; /* Never happens. Keep compiler happy. */
736 /* Align stack pointer. */
737 /* ??? Should only do this if Configuration Control Register
738 STACKALIGN bit is set. */
739 if (env
->regs
[13] & 4) {
743 /* Switch to the handler mode. */
745 v7m_push(env
, env
->regs
[15]);
746 v7m_push(env
, env
->regs
[14]);
747 v7m_push(env
, env
->regs
[12]);
748 v7m_push(env
, env
->regs
[3]);
749 v7m_push(env
, env
->regs
[2]);
750 v7m_push(env
, env
->regs
[1]);
751 v7m_push(env
, env
->regs
[0]);
752 switch_v7m_sp(env
, 0);
753 env
->uncached_cpsr
&= ~CPSR_IT
;
755 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
756 env
->regs
[15] = addr
& 0xfffffffe;
757 env
->thumb
= addr
& 1;
760 /* Handle a CPU exception. */
761 void do_interrupt(CPUARMState
*env
)
769 do_interrupt_v7m(env
);
772 /* TODO: Vectored interrupt controller. */
773 switch (env
->exception_index
) {
775 new_mode
= ARM_CPU_MODE_UND
;
784 if (semihosting_enabled
) {
785 /* Check for semihosting interrupt. */
787 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
789 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
791 /* Only intercept calls from privileged modes, to provide some
792 semblance of security. */
793 if (((mask
== 0x123456 && !env
->thumb
)
794 || (mask
== 0xab && env
->thumb
))
795 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
796 env
->regs
[0] = do_arm_semihosting(env
);
800 new_mode
= ARM_CPU_MODE_SVC
;
803 /* The PC already points to the next instruction. */
807 /* See if this is a semihosting syscall. */
808 if (env
->thumb
&& semihosting_enabled
) {
809 mask
= lduw_code(env
->regs
[15]) & 0xff;
811 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
813 env
->regs
[0] = do_arm_semihosting(env
);
817 /* Fall through to prefetch abort. */
818 case EXCP_PREFETCH_ABORT
:
819 new_mode
= ARM_CPU_MODE_ABT
;
821 mask
= CPSR_A
| CPSR_I
;
824 case EXCP_DATA_ABORT
:
825 new_mode
= ARM_CPU_MODE_ABT
;
827 mask
= CPSR_A
| CPSR_I
;
831 new_mode
= ARM_CPU_MODE_IRQ
;
833 /* Disable IRQ and imprecise data aborts. */
834 mask
= CPSR_A
| CPSR_I
;
838 new_mode
= ARM_CPU_MODE_FIQ
;
840 /* Disable FIQ, IRQ and imprecise data aborts. */
841 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
845 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
846 return; /* Never happens. Keep compiler happy. */
849 if (env
->cp15
.c1_sys
& (1 << 13)) {
852 switch_mode (env
, new_mode
);
853 env
->spsr
= cpsr_read(env
);
855 env
->condexec_bits
= 0;
856 /* Switch to the new mode, and to the correct instruction set. */
857 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
858 env
->uncached_cpsr
|= mask
;
859 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
860 env
->regs
[14] = env
->regs
[15] + offset
;
861 env
->regs
[15] = addr
;
862 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
865 /* Check section/page access permissions.
866 Returns the page protection flags, or zero if the access is not
868 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
874 return PAGE_READ
| PAGE_WRITE
;
876 if (access_type
== 1)
883 if (access_type
== 1)
885 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
887 return is_user
? 0 : PAGE_READ
;
894 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
899 return PAGE_READ
| PAGE_WRITE
;
901 return PAGE_READ
| PAGE_WRITE
;
902 case 4: /* Reserved. */
905 return is_user
? 0 : prot_ro
;
909 if (!arm_feature (env
, ARM_FEATURE_V7
))
917 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
921 if (address
& env
->cp15
.c2_mask
)
922 table
= env
->cp15
.c2_base1
& 0xffffc000;
924 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
926 table
|= (address
>> 18) & 0x3ffc;
930 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
931 int is_user
, uint32_t *phys_ptr
, int *prot
,
932 target_ulong
*page_size
)
942 /* Pagetable walk. */
943 /* Lookup l1 descriptor. */
944 table
= get_level1_table_address(env
, address
);
945 desc
= ldl_phys(table
);
947 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
949 /* Section translation fault. */
953 if (domain
== 0 || domain
== 2) {
955 code
= 9; /* Section domain fault. */
957 code
= 11; /* Page domain fault. */
962 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
963 ap
= (desc
>> 10) & 3;
965 *page_size
= 1024 * 1024;
967 /* Lookup l2 entry. */
969 /* Coarse pagetable. */
970 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
972 /* Fine pagetable. */
973 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
975 desc
= ldl_phys(table
);
977 case 0: /* Page translation fault. */
980 case 1: /* 64k page. */
981 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
982 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
983 *page_size
= 0x10000;
985 case 2: /* 4k page. */
986 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
987 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
990 case 3: /* 1k page. */
992 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
993 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
995 /* Page translation fault. */
1000 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1002 ap
= (desc
>> 4) & 3;
1006 /* Never happens, but compiler isn't smart enough to tell. */
1011 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1013 /* Access permission fault. */
1017 *phys_ptr
= phys_addr
;
1020 return code
| (domain
<< 4);
1023 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1024 int is_user
, uint32_t *phys_ptr
, int *prot
,
1025 target_ulong
*page_size
)
1036 /* Pagetable walk. */
1037 /* Lookup l1 descriptor. */
1038 table
= get_level1_table_address(env
, address
);
1039 desc
= ldl_phys(table
);
1042 /* Section translation fault. */
1046 } else if (type
== 2 && (desc
& (1 << 18))) {
1050 /* Section or page. */
1051 domain
= (desc
>> 4) & 0x1e;
1053 domain
= (env
->cp15
.c3
>> domain
) & 3;
1054 if (domain
== 0 || domain
== 2) {
1056 code
= 9; /* Section domain fault. */
1058 code
= 11; /* Page domain fault. */
1062 if (desc
& (1 << 18)) {
1064 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1065 *page_size
= 0x1000000;
1068 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1069 *page_size
= 0x100000;
1071 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1072 xn
= desc
& (1 << 4);
1075 /* Lookup l2 entry. */
1076 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1077 desc
= ldl_phys(table
);
1078 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1080 case 0: /* Page translation fault. */
1083 case 1: /* 64k page. */
1084 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1085 xn
= desc
& (1 << 15);
1086 *page_size
= 0x10000;
1088 case 2: case 3: /* 4k page. */
1089 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1091 *page_size
= 0x1000;
1094 /* Never happens, but compiler isn't smart enough to tell. */
1100 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1102 if (xn
&& access_type
== 2)
1105 /* The simplified model uses AP[0] as an access control bit. */
1106 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1107 /* Access flag fault. */
1108 code
= (code
== 15) ? 6 : 3;
1111 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1113 /* Access permission fault. */
1120 *phys_ptr
= phys_addr
;
1123 return code
| (domain
<< 4);
1126 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1127 int is_user
, uint32_t *phys_ptr
, int *prot
)
1133 *phys_ptr
= address
;
1134 for (n
= 7; n
>= 0; n
--) {
1135 base
= env
->cp15
.c6_region
[n
];
1136 if ((base
& 1) == 0)
1138 mask
= 1 << ((base
>> 1) & 0x1f);
1139 /* Keep this shift separate from the above to avoid an
1140 (undefined) << 32. */
1141 mask
= (mask
<< 1) - 1;
1142 if (((base
^ address
) & ~mask
) == 0)
1148 if (access_type
== 2) {
1149 mask
= env
->cp15
.c5_insn
;
1151 mask
= env
->cp15
.c5_data
;
1153 mask
= (mask
>> (n
* 4)) & 0xf;
1160 *prot
= PAGE_READ
| PAGE_WRITE
;
1165 *prot
|= PAGE_WRITE
;
1168 *prot
= PAGE_READ
| PAGE_WRITE
;
1179 /* Bad permission. */
1186 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1187 int access_type
, int is_user
,
1188 uint32_t *phys_ptr
, int *prot
,
1189 target_ulong
*page_size
)
1191 /* Fast Context Switch Extension. */
1192 if (address
< 0x02000000)
1193 address
+= env
->cp15
.c13_fcse
;
1195 if ((env
->cp15
.c1_sys
& 1) == 0) {
1196 /* MMU/MPU disabled. */
1197 *phys_ptr
= address
;
1198 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1199 *page_size
= TARGET_PAGE_SIZE
;
1201 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1202 *page_size
= TARGET_PAGE_SIZE
;
1203 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1205 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1206 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1209 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1214 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1215 int access_type
, int mmu_idx
, int is_softmmu
)
1218 target_ulong page_size
;
1222 is_user
= mmu_idx
== MMU_USER_IDX
;
1223 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1226 /* Map a single [sub]page. */
1227 phys_addr
&= ~(uint32_t)0x3ff;
1228 address
&= ~(uint32_t)0x3ff;
1229 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1233 if (access_type
== 2) {
1234 env
->cp15
.c5_insn
= ret
;
1235 env
->cp15
.c6_insn
= address
;
1236 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1238 env
->cp15
.c5_data
= ret
;
1239 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1240 env
->cp15
.c5_data
|= (1 << 11);
1241 env
->cp15
.c6_data
= address
;
1242 env
->exception_index
= EXCP_DATA_ABORT
;
1247 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1250 target_ulong page_size
;
1254 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1262 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1264 int cp_num
= (insn
>> 8) & 0xf;
1265 int cp_info
= (insn
>> 5) & 7;
1266 int src
= (insn
>> 16) & 0xf;
1267 int operand
= insn
& 0xf;
1269 if (env
->cp
[cp_num
].cp_write
)
1270 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1271 cp_info
, src
, operand
, val
);
1274 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1276 int cp_num
= (insn
>> 8) & 0xf;
1277 int cp_info
= (insn
>> 5) & 7;
1278 int dest
= (insn
>> 16) & 0xf;
1279 int operand
= insn
& 0xf;
1281 if (env
->cp
[cp_num
].cp_read
)
1282 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1283 cp_info
, dest
, operand
);
1287 /* Return basic MPU access permission bits. */
1288 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1295 for (i
= 0; i
< 16; i
+= 2) {
1296 ret
|= (val
>> i
) & mask
;
1302 /* Pad basic MPU access permission bits to extended format. */
1303 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1310 for (i
= 0; i
< 16; i
+= 2) {
1311 ret
|= (val
& mask
) << i
;
1317 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1323 op1
= (insn
>> 21) & 7;
1324 op2
= (insn
>> 5) & 7;
1326 switch ((insn
>> 16) & 0xf) {
1329 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1331 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1333 if (arm_feature(env
, ARM_FEATURE_V7
)
1334 && op1
== 2 && crm
== 0 && op2
== 0) {
1335 env
->cp15
.c0_cssel
= val
& 0xf;
1339 case 1: /* System configuration. */
1340 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1344 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1345 env
->cp15
.c1_sys
= val
;
1346 /* ??? Lots of these bits are not implemented. */
1347 /* This may enable/disable the MMU, so do a TLB flush. */
1350 case 1: /* Auxiliary cotrol register. */
1351 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1352 env
->cp15
.c1_xscaleauxcr
= val
;
1355 /* Not implemented. */
1358 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1360 if (env
->cp15
.c1_coproc
!= val
) {
1361 env
->cp15
.c1_coproc
= val
;
1362 /* ??? Is this safe when called from within a TB? */
1370 case 2: /* MMU Page table control / MPU cache control. */
1371 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1374 env
->cp15
.c2_data
= val
;
1377 env
->cp15
.c2_insn
= val
;
1385 env
->cp15
.c2_base0
= val
;
1388 env
->cp15
.c2_base1
= val
;
1392 env
->cp15
.c2_control
= val
;
1393 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1394 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1401 case 3: /* MMU Domain access control / MPU write buffer control. */
1403 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1405 case 4: /* Reserved. */
1407 case 5: /* MMU Fault status / MPU access permission. */
1408 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1412 if (arm_feature(env
, ARM_FEATURE_MPU
))
1413 val
= extended_mpu_ap_bits(val
);
1414 env
->cp15
.c5_data
= val
;
1417 if (arm_feature(env
, ARM_FEATURE_MPU
))
1418 val
= extended_mpu_ap_bits(val
);
1419 env
->cp15
.c5_insn
= val
;
1422 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1424 env
->cp15
.c5_data
= val
;
1427 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1429 env
->cp15
.c5_insn
= val
;
1435 case 6: /* MMU Fault address / MPU base/size. */
1436 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1439 env
->cp15
.c6_region
[crm
] = val
;
1441 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1445 env
->cp15
.c6_data
= val
;
1447 case 1: /* ??? This is WFAR on armv6 */
1449 env
->cp15
.c6_insn
= val
;
1456 case 7: /* Cache control. */
1457 env
->cp15
.c15_i_max
= 0x000;
1458 env
->cp15
.c15_i_min
= 0xff0;
1459 /* No cache, so nothing to do. */
1460 /* ??? MPCore has VA to PA translation functions. */
1462 case 8: /* MMU TLB control. */
1464 case 0: /* Invalidate all. */
1467 case 1: /* Invalidate single TLB entry. */
1468 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1470 case 2: /* Invalidate on ASID. */
1471 tlb_flush(env
, val
== 0);
1473 case 3: /* Invalidate single entry on MVA. */
1474 /* ??? This is like case 1, but ignores ASID. */
1482 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1485 case 0: /* Cache lockdown. */
1487 case 0: /* L1 cache. */
1490 env
->cp15
.c9_data
= val
;
1493 env
->cp15
.c9_insn
= val
;
1499 case 1: /* L2 cache. */
1500 /* Ignore writes to L2 lockdown/auxiliary registers. */
1506 case 1: /* TCM memory region registers. */
1507 /* Not implemented. */
1513 case 10: /* MMU TLB lockdown. */
1514 /* ??? TLB lockdown not implemented. */
1516 case 12: /* Reserved. */
1518 case 13: /* Process ID. */
1521 /* Unlike real hardware the qemu TLB uses virtual addresses,
1522 not modified virtual addresses, so this causes a TLB flush.
1524 if (env
->cp15
.c13_fcse
!= val
)
1526 env
->cp15
.c13_fcse
= val
;
1529 /* This changes the ASID, so do a TLB flush. */
1530 if (env
->cp15
.c13_context
!= val
1531 && !arm_feature(env
, ARM_FEATURE_MPU
))
1533 env
->cp15
.c13_context
= val
;
1539 case 14: /* Reserved. */
1541 case 15: /* Implementation specific. */
1542 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1543 if (op2
== 0 && crm
== 1) {
1544 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1545 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1547 env
->cp15
.c15_cpar
= val
& 0x3fff;
1553 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1557 case 1: /* Set TI925T configuration. */
1558 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1559 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1560 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1562 case 2: /* Set I_max. */
1563 env
->cp15
.c15_i_max
= val
;
1565 case 3: /* Set I_min. */
1566 env
->cp15
.c15_i_min
= val
;
1568 case 4: /* Set thread-ID. */
1569 env
->cp15
.c15_threadid
= val
& 0xffff;
1571 case 8: /* Wait-for-interrupt (deprecated). */
1572 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1582 /* ??? For debugging only. Should raise illegal instruction exception. */
1583 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1584 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1587 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1593 op1
= (insn
>> 21) & 7;
1594 op2
= (insn
>> 5) & 7;
1596 switch ((insn
>> 16) & 0xf) {
1597 case 0: /* ID codes. */
1603 case 0: /* Device ID. */
1604 return env
->cp15
.c0_cpuid
;
1605 case 1: /* Cache Type. */
1606 return env
->cp15
.c0_cachetype
;
1607 case 2: /* TCM status. */
1609 case 3: /* TLB type register. */
1610 return 0; /* No lockable TLB entries. */
1612 /* The MPIDR was standardised in v7; prior to
1613 * this it was implemented only in the 11MPCore.
1614 * For all other pre-v7 cores it does not exist.
1616 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1617 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1618 int mpidr
= env
->cpu_index
;
1619 /* We don't support setting cluster ID ([8..11])
1620 * so these bits always RAZ.
1622 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1624 /* Cores which are uniprocessor (non-coherent)
1625 * but still implement the MP extensions set
1626 * bit 30. (For instance, A9UP.) However we do
1627 * not currently model any of those cores.
1632 /* otherwise fall through to the unimplemented-reg case */
1637 if (!arm_feature(env
, ARM_FEATURE_V6
))
1639 return env
->cp15
.c0_c1
[op2
];
1641 if (!arm_feature(env
, ARM_FEATURE_V6
))
1643 return env
->cp15
.c0_c2
[op2
];
1644 case 3: case 4: case 5: case 6: case 7:
1650 /* These registers aren't documented on arm11 cores. However
1651 Linux looks at them anyway. */
1652 if (!arm_feature(env
, ARM_FEATURE_V6
))
1656 if (!arm_feature(env
, ARM_FEATURE_V7
))
1661 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1663 return env
->cp15
.c0_clid
;
1669 if (op2
!= 0 || crm
!= 0)
1671 return env
->cp15
.c0_cssel
;
1675 case 1: /* System configuration. */
1676 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1679 case 0: /* Control register. */
1680 return env
->cp15
.c1_sys
;
1681 case 1: /* Auxiliary control register. */
1682 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1683 return env
->cp15
.c1_xscaleauxcr
;
1684 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1686 switch (ARM_CPUID(env
)) {
1687 case ARM_CPUID_ARM1026
:
1689 case ARM_CPUID_ARM1136
:
1690 case ARM_CPUID_ARM1136_R2
:
1692 case ARM_CPUID_ARM11MPCORE
:
1694 case ARM_CPUID_CORTEXA8
:
1696 case ARM_CPUID_CORTEXA9
:
1701 case 2: /* Coprocessor access register. */
1702 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1704 return env
->cp15
.c1_coproc
;
1708 case 2: /* MMU Page table control / MPU cache control. */
1709 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1712 return env
->cp15
.c2_data
;
1715 return env
->cp15
.c2_insn
;
1723 return env
->cp15
.c2_base0
;
1725 return env
->cp15
.c2_base1
;
1727 return env
->cp15
.c2_control
;
1732 case 3: /* MMU Domain access control / MPU write buffer control. */
1733 return env
->cp15
.c3
;
1734 case 4: /* Reserved. */
1736 case 5: /* MMU Fault status / MPU access permission. */
1737 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1741 if (arm_feature(env
, ARM_FEATURE_MPU
))
1742 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1743 return env
->cp15
.c5_data
;
1745 if (arm_feature(env
, ARM_FEATURE_MPU
))
1746 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1747 return env
->cp15
.c5_insn
;
1749 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1751 return env
->cp15
.c5_data
;
1753 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1755 return env
->cp15
.c5_insn
;
1759 case 6: /* MMU Fault address. */
1760 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1763 return env
->cp15
.c6_region
[crm
];
1765 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1769 return env
->cp15
.c6_data
;
1771 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1772 /* Watchpoint Fault Adrress. */
1773 return 0; /* Not implemented. */
1775 /* Instruction Fault Adrress. */
1776 /* Arm9 doesn't have an IFAR, but implementing it anyway
1777 shouldn't do any harm. */
1778 return env
->cp15
.c6_insn
;
1781 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1782 /* Instruction Fault Adrress. */
1783 return env
->cp15
.c6_insn
;
1791 case 7: /* Cache control. */
1792 /* FIXME: Should only clear Z flag if destination is r15. */
1795 case 8: /* MMU TLB control. */
1797 case 9: /* Cache lockdown. */
1799 case 0: /* L1 cache. */
1800 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1804 return env
->cp15
.c9_data
;
1806 return env
->cp15
.c9_insn
;
1810 case 1: /* L2 cache */
1813 /* L2 Lockdown and Auxiliary control. */
1818 case 10: /* MMU TLB lockdown. */
1819 /* ??? TLB lockdown not implemented. */
1821 case 11: /* TCM DMA control. */
1822 case 12: /* Reserved. */
1824 case 13: /* Process ID. */
1827 return env
->cp15
.c13_fcse
;
1829 return env
->cp15
.c13_context
;
1833 case 14: /* Reserved. */
1835 case 15: /* Implementation specific. */
1836 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1837 if (op2
== 0 && crm
== 1)
1838 return env
->cp15
.c15_cpar
;
1842 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1846 case 1: /* Read TI925T configuration. */
1847 return env
->cp15
.c15_ticonfig
;
1848 case 2: /* Read I_max. */
1849 return env
->cp15
.c15_i_max
;
1850 case 3: /* Read I_min. */
1851 return env
->cp15
.c15_i_min
;
1852 case 4: /* Read thread-ID. */
1853 return env
->cp15
.c15_threadid
;
1854 case 8: /* TI925T_status */
1857 /* TODO: Peripheral port remap register:
1858 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1859 * controller base address at $rn & ~0xfff and map size of
1860 * 0x200 << ($rn & 0xfff), when MMU is off. */
1866 /* ??? For debugging only. Should raise illegal instruction exception. */
1867 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1868 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1872 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1874 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
1875 env
->regs
[13] = val
;
1877 env
->banked_r13
[bank_number(mode
)] = val
;
1881 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1883 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
1884 return env
->regs
[13];
1886 return env
->banked_r13
[bank_number(mode
)];
1890 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1894 return xpsr_read(env
) & 0xf8000000;
1896 return xpsr_read(env
) & 0xf80001ff;
1898 return xpsr_read(env
) & 0xff00fc00;
1900 return xpsr_read(env
) & 0xff00fdff;
1902 return xpsr_read(env
) & 0x000001ff;
1904 return xpsr_read(env
) & 0x0700fc00;
1906 return xpsr_read(env
) & 0x0700edff;
1908 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1910 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1911 case 16: /* PRIMASK */
1912 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1913 case 17: /* FAULTMASK */
1914 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1915 case 18: /* BASEPRI */
1916 case 19: /* BASEPRI_MAX */
1917 return env
->v7m
.basepri
;
1918 case 20: /* CONTROL */
1919 return env
->v7m
.control
;
1921 /* ??? For debugging only. */
1922 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1927 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1931 xpsr_write(env
, val
, 0xf8000000);
1934 xpsr_write(env
, val
, 0xf8000000);
1937 xpsr_write(env
, val
, 0xfe00fc00);
1940 xpsr_write(env
, val
, 0xfe00fc00);
1943 /* IPSR bits are readonly. */
1946 xpsr_write(env
, val
, 0x0600fc00);
1949 xpsr_write(env
, val
, 0x0600fc00);
1952 if (env
->v7m
.current_sp
)
1953 env
->v7m
.other_sp
= val
;
1955 env
->regs
[13] = val
;
1958 if (env
->v7m
.current_sp
)
1959 env
->regs
[13] = val
;
1961 env
->v7m
.other_sp
= val
;
1963 case 16: /* PRIMASK */
1965 env
->uncached_cpsr
|= CPSR_I
;
1967 env
->uncached_cpsr
&= ~CPSR_I
;
1969 case 17: /* FAULTMASK */
1971 env
->uncached_cpsr
|= CPSR_F
;
1973 env
->uncached_cpsr
&= ~CPSR_F
;
1975 case 18: /* BASEPRI */
1976 env
->v7m
.basepri
= val
& 0xff;
1978 case 19: /* BASEPRI_MAX */
1980 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1981 env
->v7m
.basepri
= val
;
1983 case 20: /* CONTROL */
1984 env
->v7m
.control
= val
& 3;
1985 switch_v7m_sp(env
, (val
& 2) != 0);
1988 /* ??? For debugging only. */
1989 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1994 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1995 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1998 if (cpnum
< 0 || cpnum
> 14) {
1999 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2003 env
->cp
[cpnum
].cp_read
= cp_read
;
2004 env
->cp
[cpnum
].cp_write
= cp_write
;
2005 env
->cp
[cpnum
].opaque
= opaque
;
2010 /* Note that signed overflow is undefined in C. The following routines are
2011 careful to use unsigned types where modulo arithmetic is required.
2012 Failure to do so _will_ break on newer gcc. */
2014 /* Signed saturating arithmetic. */
2016 /* Perform 16-bit signed saturating addition. */
2017 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2022 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2031 /* Perform 8-bit signed saturating addition. */
2032 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2037 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2046 /* Perform 16-bit signed saturating subtraction. */
2047 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2052 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2061 /* Perform 8-bit signed saturating subtraction. */
2062 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2067 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2076 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2077 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2078 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2079 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2082 #include "op_addsub.h"
2084 /* Unsigned saturating arithmetic. */
2085 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2094 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2102 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2111 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2119 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2120 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2121 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2122 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2125 #include "op_addsub.h"
2127 /* Signed modulo arithmetic. */
2128 #define SARITH16(a, b, n, op) do { \
2130 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2131 RESULT(sum, n, 16); \
2133 ge |= 3 << (n * 2); \
2136 #define SARITH8(a, b, n, op) do { \
2138 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2139 RESULT(sum, n, 8); \
2145 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2146 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2147 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2148 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2152 #include "op_addsub.h"
2154 /* Unsigned modulo arithmetic. */
2155 #define ADD16(a, b, n) do { \
2157 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2158 RESULT(sum, n, 16); \
2159 if ((sum >> 16) == 1) \
2160 ge |= 3 << (n * 2); \
2163 #define ADD8(a, b, n) do { \
2165 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2166 RESULT(sum, n, 8); \
2167 if ((sum >> 8) == 1) \
2171 #define SUB16(a, b, n) do { \
2173 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2174 RESULT(sum, n, 16); \
2175 if ((sum >> 16) == 0) \
2176 ge |= 3 << (n * 2); \
2179 #define SUB8(a, b, n) do { \
2181 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2182 RESULT(sum, n, 8); \
2183 if ((sum >> 8) == 0) \
2190 #include "op_addsub.h"
2192 /* Halved signed arithmetic. */
2193 #define ADD16(a, b, n) \
2194 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2195 #define SUB16(a, b, n) \
2196 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2197 #define ADD8(a, b, n) \
2198 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2199 #define SUB8(a, b, n) \
2200 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2203 #include "op_addsub.h"
2205 /* Halved unsigned arithmetic. */
2206 #define ADD16(a, b, n) \
2207 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2208 #define SUB16(a, b, n) \
2209 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2210 #define ADD8(a, b, n) \
2211 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2212 #define SUB8(a, b, n) \
2213 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2216 #include "op_addsub.h"
2218 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2226 /* Unsigned sum of absolute byte differences. */
2227 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2230 sum
= do_usad(a
, b
);
2231 sum
+= do_usad(a
>> 8, b
>> 8);
2232 sum
+= do_usad(a
>> 16, b
>>16);
2233 sum
+= do_usad(a
>> 24, b
>> 24);
2237 /* For ARMv6 SEL instruction. */
2238 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2251 return (a
& mask
) | (b
& ~mask
);
2254 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2256 return (val
>> 32) | (val
!= 0);
2259 /* VFP support. We follow the convention used for VFP instrunctions:
2260 Single precition routines have a "s" suffix, double precision a
2263 /* Convert host exception flags to vfp form. */
2264 static inline int vfp_exceptbits_from_host(int host_bits
)
2266 int target_bits
= 0;
2268 if (host_bits
& float_flag_invalid
)
2270 if (host_bits
& float_flag_divbyzero
)
2272 if (host_bits
& float_flag_overflow
)
2274 if (host_bits
& float_flag_underflow
)
2276 if (host_bits
& float_flag_inexact
)
2277 target_bits
|= 0x10;
2278 if (host_bits
& float_flag_input_denormal
)
2279 target_bits
|= 0x80;
2283 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2288 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2289 | (env
->vfp
.vec_len
<< 16)
2290 | (env
->vfp
.vec_stride
<< 20);
2291 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2292 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2293 fpscr
|= vfp_exceptbits_from_host(i
);
2297 uint32_t vfp_get_fpscr(CPUState
*env
)
2299 return HELPER(vfp_get_fpscr
)(env
);
2302 /* Convert vfp exception flags to target form. */
2303 static inline int vfp_exceptbits_to_host(int target_bits
)
2307 if (target_bits
& 1)
2308 host_bits
|= float_flag_invalid
;
2309 if (target_bits
& 2)
2310 host_bits
|= float_flag_divbyzero
;
2311 if (target_bits
& 4)
2312 host_bits
|= float_flag_overflow
;
2313 if (target_bits
& 8)
2314 host_bits
|= float_flag_underflow
;
2315 if (target_bits
& 0x10)
2316 host_bits
|= float_flag_inexact
;
2317 if (target_bits
& 0x80)
2318 host_bits
|= float_flag_input_denormal
;
2322 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2327 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2328 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2329 env
->vfp
.vec_len
= (val
>> 16) & 7;
2330 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2333 if (changed
& (3 << 22)) {
2334 i
= (val
>> 22) & 3;
2337 i
= float_round_nearest_even
;
2343 i
= float_round_down
;
2346 i
= float_round_to_zero
;
2349 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2351 if (changed
& (1 << 24)) {
2352 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2353 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2355 if (changed
& (1 << 25))
2356 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2358 i
= vfp_exceptbits_to_host(val
);
2359 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2360 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2363 void vfp_set_fpscr(CPUState
*env
, uint32_t val
)
2365 HELPER(vfp_set_fpscr
)(env
, val
);
2368 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2370 #define VFP_BINOP(name) \
2371 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2373 return float32_ ## name (a, b, &env->vfp.fp_status); \
2375 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2377 return float64_ ## name (a, b, &env->vfp.fp_status); \
2385 float32
VFP_HELPER(neg
, s
)(float32 a
)
2387 return float32_chs(a
);
2390 float64
VFP_HELPER(neg
, d
)(float64 a
)
2392 return float64_chs(a
);
2395 float32
VFP_HELPER(abs
, s
)(float32 a
)
2397 return float32_abs(a
);
2400 float64
VFP_HELPER(abs
, d
)(float64 a
)
2402 return float64_abs(a
);
2405 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2407 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2410 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2412 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2415 /* XXX: check quiet/signaling case */
2416 #define DO_VFP_cmp(p, type) \
2417 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2420 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2421 case 0: flags = 0x6; break; \
2422 case -1: flags = 0x8; break; \
2423 case 1: flags = 0x2; break; \
2424 default: case 2: flags = 0x3; break; \
2426 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2427 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2429 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2432 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2433 case 0: flags = 0x6; break; \
2434 case -1: flags = 0x8; break; \
2435 case 1: flags = 0x2; break; \
2436 default: case 2: flags = 0x3; break; \
2438 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2439 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2441 DO_VFP_cmp(s
, float32
)
2442 DO_VFP_cmp(d
, float64
)
2445 /* Helper routines to perform bitwise copies between float and int. */
2446 static inline float32
vfp_itos(uint32_t i
)
2457 static inline uint32_t vfp_stoi(float32 s
)
2468 static inline float64
vfp_itod(uint64_t i
)
2479 static inline uint64_t vfp_dtoi(float64 d
)
2490 /* Integer to float conversion. */
2491 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2493 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2496 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2498 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2501 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2503 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2506 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2508 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2511 /* Float to integer conversion. */
2512 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2514 if (float32_is_any_nan(x
)) {
2515 return float32_zero
;
2517 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2520 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2522 if (float64_is_any_nan(x
)) {
2523 return float32_zero
;
2525 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2528 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2530 if (float32_is_any_nan(x
)) {
2531 return float32_zero
;
2533 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2536 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2538 if (float64_is_any_nan(x
)) {
2539 return float32_zero
;
2541 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2544 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2546 if (float32_is_any_nan(x
)) {
2547 return float32_zero
;
2549 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2552 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2554 if (float64_is_any_nan(x
)) {
2555 return float32_zero
;
2557 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2560 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2562 if (float32_is_any_nan(x
)) {
2563 return float32_zero
;
2565 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2568 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2570 if (float64_is_any_nan(x
)) {
2571 return float32_zero
;
2573 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2576 /* floating point conversion */
2577 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2579 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2580 /* ARM requires that S<->D conversion of any kind of NaN generates
2581 * a quiet NaN by forcing the most significant frac bit to 1.
2583 return float64_maybe_silence_nan(r
);
2586 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2588 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2589 /* ARM requires that S<->D conversion of any kind of NaN generates
2590 * a quiet NaN by forcing the most significant frac bit to 1.
2592 return float32_maybe_silence_nan(r
);
2595 /* VFP3 fixed point conversion. */
2596 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2597 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2600 tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \
2601 &env->vfp.fp_status); \
2602 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2604 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2607 if (ftype##_is_any_nan(x)) { \
2608 return ftype##_zero; \
2610 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2611 return vfp_ito##p(ftype##_to_##itype##_round_to_zero(tmp, \
2612 &env->vfp.fp_status)); \
2615 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2616 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2617 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2618 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2619 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2620 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2621 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2622 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2625 /* Half precision conversions. */
2626 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2628 float_status
*s
= &env
->vfp
.fp_status
;
2629 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2630 return float16_to_float32(a
, ieee
, s
);
2633 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2635 float_status
*s
= &env
->vfp
.fp_status
;
2636 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2637 return float32_to_float16(a
, ieee
, s
);
2640 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2642 float_status
*s
= &env
->vfp
.fp_status
;
2643 float32 two
= int32_to_float32(2, s
);
2644 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2647 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2649 float_status
*s
= &env
->vfp
.standard_fp_status
;
2650 float32 two
= int32_to_float32(2, s
);
2651 float32 three
= int32_to_float32(3, s
);
2653 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2654 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2655 product
= float32_zero
;
2657 product
= float32_mul(a
, b
, s
);
2659 return float32_div(float32_sub(three
, product
, s
), two
, s
);
2664 /* TODO: The architecture specifies the value that the estimate functions
2665 should return. We return the exact reciprocal/root instead. */
2666 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2668 float_status
*s
= &env
->vfp
.fp_status
;
2669 float32 one
= int32_to_float32(1, s
);
2670 return float32_div(one
, a
, s
);
2673 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2675 float_status
*s
= &env
->vfp
.fp_status
;
2676 float32 one
= int32_to_float32(1, s
);
2677 return float32_div(one
, float32_sqrt(a
, s
), s
);
2680 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2682 float_status
*s
= &env
->vfp
.fp_status
;
2684 tmp
= int32_to_float32(a
, s
);
2685 tmp
= float32_scalbn(tmp
, -32, s
);
2686 tmp
= helper_recpe_f32(tmp
, env
);
2687 tmp
= float32_scalbn(tmp
, 31, s
);
2688 return float32_to_int32(tmp
, s
);
2691 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2693 float_status
*s
= &env
->vfp
.fp_status
;
2695 tmp
= int32_to_float32(a
, s
);
2696 tmp
= float32_scalbn(tmp
, -32, s
);
2697 tmp
= helper_rsqrte_f32(tmp
, env
);
2698 tmp
= float32_scalbn(tmp
, 31, s
);
2699 return float32_to_int32(tmp
, s
);
2702 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2705 if (env
->teecr
!= val
) {