usb-ehci: drop EXECUTING checks.
[qemu.git] / hw / usb-ehci.c
blob7471a2f685ef422189b769916ff3dfd5afdd7a69
1 /*
2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
24 * TODO:
25 * o Downstream port handoff
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
35 #define EHCI_DEBUG 0
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
46 #define MMIO_SIZE 0x1000
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
100 #define CONFIGFLAG OPREGBASE + 0x0040
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
141 /* Internal periodic / asynchronous schedule state machine states
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
173 /* EHCI spec version 1.0 Section 3.3
175 typedef struct EHCIitd {
176 uint32_t next;
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 } EHCIitd;
203 /* EHCI spec version 1.0 Section 3.4
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
247 /* EHCI spec version 1.0 Section 3.5
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 } EHCIqtd;
276 /* EHCI spec version 1.0 Section 3.6
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
330 /* EHCI spec version 1.0 Section 3.7
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
337 typedef struct EHCIQueue EHCIQueue;
338 typedef struct EHCIState EHCIState;
340 enum async_state {
341 EHCI_ASYNC_NONE = 0,
342 EHCI_ASYNC_INFLIGHT,
343 EHCI_ASYNC_FINISHED,
346 struct EHCIQueue {
347 EHCIState *ehci;
348 QTAILQ_ENTRY(EHCIQueue) next;
349 bool async_schedule;
350 uint32_t seen, ts;
352 /* cached data from guest - needs to be flushed
353 * when guest removes an entry (doorbell, handshake sequence)
355 EHCIqh qh; // copy of current QH (being worked on)
356 uint32_t qhaddr; // address QH read from
357 EHCIqtd qtd; // copy of current QTD (being worked on)
358 uint32_t qtdaddr; // address QTD read from
360 USBPacket packet;
361 uint8_t buffer[BUFF_SIZE];
362 int pid;
363 uint32_t tbytes;
364 enum async_state async;
365 int usb_status;
368 struct EHCIState {
369 PCIDevice dev;
370 USBBus bus;
371 qemu_irq irq;
372 target_phys_addr_t mem_base;
373 int mem;
374 int num_ports;
376 * EHCI spec version 1.0 Section 2.3
377 * Host Controller Operational Registers
379 union {
380 uint8_t mmio[MMIO_SIZE];
381 struct {
382 uint8_t cap[OPREGBASE];
383 uint32_t usbcmd;
384 uint32_t usbsts;
385 uint32_t usbintr;
386 uint32_t frindex;
387 uint32_t ctrldssegment;
388 uint32_t periodiclistbase;
389 uint32_t asynclistaddr;
390 uint32_t notused[9];
391 uint32_t configflag;
392 uint32_t portsc[NB_PORTS];
397 * Internal states, shadow registers, etc
399 uint32_t sofv;
400 QEMUTimer *frame_timer;
401 int attach_poll_counter;
402 int astate; // Current state in asynchronous schedule
403 int pstate; // Current state in periodic schedule
404 USBPort ports[NB_PORTS];
405 uint32_t usbsts_pending;
406 QTAILQ_HEAD(, EHCIQueue) queues;
408 uint32_t a_fetch_addr; // which address to look at next
409 uint32_t p_fetch_addr; // which address to look at next
411 USBPacket ipacket;
412 uint8_t ibuffer[BUFF_SIZE];
413 int isoch_pause;
415 uint32_t last_run_usec;
416 uint32_t frame_end_usec;
419 #define SET_LAST_RUN_CLOCK(s) \
420 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
422 /* nifty macros from Arnon's EHCI version */
423 #define get_field(data, field) \
424 (((data) & field##_MASK) >> field##_SH)
426 #define set_field(data, newval, field) do { \
427 uint32_t val = *data; \
428 val &= ~ field##_MASK; \
429 val |= ((newval) << field##_SH) & field##_MASK; \
430 *data = val; \
431 } while(0)
433 static const char *ehci_state_names[] = {
434 [ EST_INACTIVE ] = "INACTIVE",
435 [ EST_ACTIVE ] = "ACTIVE",
436 [ EST_EXECUTING ] = "EXECUTING",
437 [ EST_SLEEPING ] = "SLEEPING",
438 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
439 [ EST_FETCHENTRY ] = "FETCH ENTRY",
440 [ EST_FETCHQH ] = "FETCH QH",
441 [ EST_FETCHITD ] = "FETCH ITD",
442 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
443 [ EST_FETCHQTD ] = "FETCH QTD",
444 [ EST_EXECUTE ] = "EXECUTE",
445 [ EST_WRITEBACK ] = "WRITEBACK",
446 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
449 static const char *ehci_mmio_names[] = {
450 [ CAPLENGTH ] = "CAPLENGTH",
451 [ HCIVERSION ] = "HCIVERSION",
452 [ HCSPARAMS ] = "HCSPARAMS",
453 [ HCCPARAMS ] = "HCCPARAMS",
454 [ USBCMD ] = "USBCMD",
455 [ USBSTS ] = "USBSTS",
456 [ USBINTR ] = "USBINTR",
457 [ FRINDEX ] = "FRINDEX",
458 [ PERIODICLISTBASE ] = "P-LIST BASE",
459 [ ASYNCLISTADDR ] = "A-LIST ADDR",
460 [ PORTSC_BEGIN ] = "PORTSC #0",
461 [ PORTSC_BEGIN + 4] = "PORTSC #1",
462 [ PORTSC_BEGIN + 8] = "PORTSC #2",
463 [ PORTSC_BEGIN + 12] = "PORTSC #3",
464 [ CONFIGFLAG ] = "CONFIGFLAG",
467 static const char *nr2str(const char **n, size_t len, uint32_t nr)
469 if (nr < len && n[nr] != NULL) {
470 return n[nr];
471 } else {
472 return "unknown";
476 static const char *state2str(uint32_t state)
478 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
481 static const char *addr2str(target_phys_addr_t addr)
483 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
486 static void ehci_trace_usbsts(uint32_t mask, int state)
488 /* interrupts */
489 if (mask & USBSTS_INT) {
490 trace_usb_ehci_usbsts("INT", state);
492 if (mask & USBSTS_ERRINT) {
493 trace_usb_ehci_usbsts("ERRINT", state);
495 if (mask & USBSTS_PCD) {
496 trace_usb_ehci_usbsts("PCD", state);
498 if (mask & USBSTS_FLR) {
499 trace_usb_ehci_usbsts("FLR", state);
501 if (mask & USBSTS_HSE) {
502 trace_usb_ehci_usbsts("HSE", state);
504 if (mask & USBSTS_IAA) {
505 trace_usb_ehci_usbsts("IAA", state);
508 /* status */
509 if (mask & USBSTS_HALT) {
510 trace_usb_ehci_usbsts("HALT", state);
512 if (mask & USBSTS_REC) {
513 trace_usb_ehci_usbsts("REC", state);
515 if (mask & USBSTS_PSS) {
516 trace_usb_ehci_usbsts("PSS", state);
518 if (mask & USBSTS_ASS) {
519 trace_usb_ehci_usbsts("ASS", state);
523 static inline void ehci_set_usbsts(EHCIState *s, int mask)
525 if ((s->usbsts & mask) == mask) {
526 return;
528 ehci_trace_usbsts(mask, 1);
529 s->usbsts |= mask;
532 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
534 if ((s->usbsts & mask) == 0) {
535 return;
537 ehci_trace_usbsts(mask, 0);
538 s->usbsts &= ~mask;
541 static inline void ehci_set_interrupt(EHCIState *s, int intr)
543 int level = 0;
545 // TODO honour interrupt threshold requests
547 ehci_set_usbsts(s, intr);
549 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
550 level = 1;
553 qemu_set_irq(s->irq, level);
556 static inline void ehci_record_interrupt(EHCIState *s, int intr)
558 s->usbsts_pending |= intr;
561 static inline void ehci_commit_interrupt(EHCIState *s)
563 if (!s->usbsts_pending) {
564 return;
566 ehci_set_interrupt(s, s->usbsts_pending);
567 s->usbsts_pending = 0;
570 static void ehci_set_state(EHCIState *s, int async, int state)
572 if (async) {
573 trace_usb_ehci_state("async", state2str(state));
574 s->astate = state;
575 } else {
576 trace_usb_ehci_state("periodic", state2str(state));
577 s->pstate = state;
581 static int ehci_get_state(EHCIState *s, int async)
583 return async ? s->astate : s->pstate;
586 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
588 if (async) {
589 s->a_fetch_addr = addr;
590 } else {
591 s->p_fetch_addr = addr;
595 static int ehci_get_fetch_addr(EHCIState *s, int async)
597 return async ? s->a_fetch_addr : s->p_fetch_addr;
600 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
602 trace_usb_ehci_qh(q, addr, qh->next,
603 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
604 get_field(qh->epchar, QH_EPCHAR_RL),
605 get_field(qh->epchar, QH_EPCHAR_MPLEN),
606 get_field(qh->epchar, QH_EPCHAR_EPS),
607 get_field(qh->epchar, QH_EPCHAR_EP),
608 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
609 (bool)(qh->epchar & QH_EPCHAR_C),
610 (bool)(qh->epchar & QH_EPCHAR_H),
611 (bool)(qh->epchar & QH_EPCHAR_DTC),
612 (bool)(qh->epchar & QH_EPCHAR_I));
615 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
617 trace_usb_ehci_qtd(q, addr, qtd->next, qtd->altnext,
618 get_field(qtd->token, QTD_TOKEN_TBYTES),
619 get_field(qtd->token, QTD_TOKEN_CPAGE),
620 get_field(qtd->token, QTD_TOKEN_CERR),
621 get_field(qtd->token, QTD_TOKEN_PID),
622 (bool)(qtd->token & QTD_TOKEN_IOC),
623 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
624 (bool)(qtd->token & QTD_TOKEN_HALT),
625 (bool)(qtd->token & QTD_TOKEN_BABBLE),
626 (bool)(qtd->token & QTD_TOKEN_XACTERR));
629 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
631 trace_usb_ehci_itd(addr, itd->next);
634 /* queue management */
636 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
638 EHCIQueue *q;
640 q = qemu_mallocz(sizeof(*q));
641 q->ehci = ehci;
642 q->async_schedule = async;
643 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
644 trace_usb_ehci_queue_action(q, "alloc");
645 return q;
648 static void ehci_free_queue(EHCIQueue *q)
650 trace_usb_ehci_queue_action(q, "free");
651 if (q->async == EHCI_ASYNC_INFLIGHT) {
652 usb_cancel_packet(&q->packet);
654 QTAILQ_REMOVE(&q->ehci->queues, q, next);
655 qemu_free(q);
658 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
660 EHCIQueue *q;
662 QTAILQ_FOREACH(q, &ehci->queues, next) {
663 if (addr == q->qhaddr) {
664 return q;
667 return NULL;
670 static void ehci_queues_rip_unused(EHCIState *ehci)
672 EHCIQueue *q, *tmp;
674 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
675 if (q->seen) {
676 q->seen = 0;
677 q->ts = ehci->last_run_usec;
678 continue;
680 if (ehci->last_run_usec < q->ts + 250000) {
681 /* allow 0.25 sec idle */
682 continue;
684 ehci_free_queue(q);
688 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
690 EHCIQueue *q, *tmp;
692 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
693 if (q->packet.owner != dev) {
694 continue;
696 ehci_free_queue(q);
700 static void ehci_queues_rip_all(EHCIState *ehci)
702 EHCIQueue *q, *tmp;
704 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
705 ehci_free_queue(q);
709 /* Attach or detach a device on root hub */
711 static void ehci_attach(USBPort *port)
713 EHCIState *s = port->opaque;
714 uint32_t *portsc = &s->portsc[port->index];
716 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
718 *portsc |= PORTSC_CONNECT;
719 *portsc |= PORTSC_CSC;
722 * If a high speed device is attached then we own this port(indicated
723 * by zero in the PORTSC_POWNER bit field) so set the status bit
724 * and set an interrupt if enabled.
726 if ( !(*portsc & PORTSC_POWNER)) {
727 ehci_set_interrupt(s, USBSTS_PCD);
731 static void ehci_detach(USBPort *port)
733 EHCIState *s = port->opaque;
734 uint32_t *portsc = &s->portsc[port->index];
736 trace_usb_ehci_port_detach(port->index);
738 *portsc &= ~PORTSC_CONNECT;
739 *portsc |= PORTSC_CSC;
742 * If a high speed device is attached then we own this port(indicated
743 * by zero in the PORTSC_POWNER bit field) so set the status bit
744 * and set an interrupt if enabled.
746 if ( !(*portsc & PORTSC_POWNER)) {
747 ehci_set_interrupt(s, USBSTS_PCD);
751 /* 4.1 host controller initialization */
752 static void ehci_reset(void *opaque)
754 EHCIState *s = opaque;
755 int i;
757 trace_usb_ehci_reset();
759 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
761 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
762 s->usbsts = USBSTS_HALT;
764 s->astate = EST_INACTIVE;
765 s->pstate = EST_INACTIVE;
766 s->isoch_pause = -1;
767 s->attach_poll_counter = 0;
769 for(i = 0; i < NB_PORTS; i++) {
770 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
772 if (s->ports[i].dev) {
773 usb_attach(&s->ports[i], s->ports[i].dev);
776 ehci_queues_rip_all(s);
779 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
781 EHCIState *s = ptr;
782 uint32_t val;
784 val = s->mmio[addr];
786 return val;
789 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
791 EHCIState *s = ptr;
792 uint32_t val;
794 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
796 return val;
799 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
801 EHCIState *s = ptr;
802 uint32_t val;
804 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
805 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
807 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
808 return val;
811 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
813 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
814 exit(1);
817 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
819 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
820 exit(1);
823 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
825 uint32_t *portsc = &s->portsc[port];
826 int rwc;
827 USBDevice *dev = s->ports[port].dev;
829 rwc = val & PORTSC_RWC_MASK;
830 val &= PORTSC_RO_MASK;
832 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
834 *portsc &= ~rwc;
836 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
837 trace_usb_ehci_port_reset(port, 1);
840 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
841 trace_usb_ehci_port_reset(port, 0);
842 usb_attach(&s->ports[port], dev);
844 // TODO how to handle reset of ports with no device
845 if (dev) {
846 usb_send_msg(dev, USB_MSG_RESET);
849 if (s->ports[port].dev) {
850 *portsc &= ~PORTSC_CSC;
853 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
854 * to SW that this port has a high speed device attached
856 * TODO - when to disable?
858 val |= PORTSC_PED;
859 val |= PORTSC_PEDC;
862 *portsc &= ~PORTSC_RO_MASK;
863 *portsc |= val;
866 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
868 EHCIState *s = ptr;
869 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
870 uint32_t old = *mmio;
871 int i;
873 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
875 /* Only aligned reads are allowed on OHCI */
876 if (addr & 3) {
877 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
878 TARGET_FMT_plx "\n", addr);
879 return;
882 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
883 handle_port_status_write(s, (addr-PORTSC)/4, val);
884 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
885 return;
888 if (addr < OPREGBASE) {
889 fprintf(stderr, "usb-ehci: write attempt to read-only register"
890 TARGET_FMT_plx "\n", addr);
891 return;
895 /* Do any register specific pre-write processing here. */
896 switch(addr) {
897 case USBCMD:
898 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
899 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
900 SET_LAST_RUN_CLOCK(s);
901 ehci_clear_usbsts(s, USBSTS_HALT);
904 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
905 qemu_del_timer(s->frame_timer);
906 // TODO - should finish out some stuff before setting halt
907 ehci_set_usbsts(s, USBSTS_HALT);
910 if (val & USBCMD_HCRESET) {
911 ehci_reset(s);
912 val &= ~USBCMD_HCRESET;
915 /* not supporting dynamic frame list size at the moment */
916 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
917 fprintf(stderr, "attempt to set frame list size -- value %d\n",
918 val & USBCMD_FLS);
919 val &= ~USBCMD_FLS;
921 break;
923 case USBSTS:
924 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
925 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
926 val = s->usbsts;
927 ehci_set_interrupt(s, 0);
928 break;
930 case USBINTR:
931 val &= USBINTR_MASK;
932 break;
934 case FRINDEX:
935 s->sofv = val >> 3;
936 break;
938 case CONFIGFLAG:
939 val &= 0x1;
940 if (val) {
941 for(i = 0; i < NB_PORTS; i++)
942 s->portsc[i] &= ~PORTSC_POWNER;
944 break;
946 case PERIODICLISTBASE:
947 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
948 fprintf(stderr,
949 "ehci: PERIODIC list base register set while periodic schedule\n"
950 " is enabled and HC is enabled\n");
952 break;
954 case ASYNCLISTADDR:
955 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
956 fprintf(stderr,
957 "ehci: ASYNC list address register set while async schedule\n"
958 " is enabled and HC is enabled\n");
960 break;
963 *mmio = val;
964 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
968 // TODO : Put in common header file, duplication from usb-ohci.c
970 /* Get an array of dwords from main memory */
971 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
973 int i;
975 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
976 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
977 *buf = le32_to_cpu(*buf);
980 return 1;
983 /* Put an array of dwords in to main memory */
984 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
986 int i;
988 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
989 uint32_t tmp = cpu_to_le32(*buf);
990 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
993 return 1;
996 // 4.10.2
998 static int ehci_qh_do_overlay(EHCIQueue *q)
1000 int i;
1001 int dtoggle;
1002 int ping;
1003 int eps;
1004 int reload;
1006 // remember values in fields to preserve in qh after overlay
1008 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1009 ping = q->qh.token & QTD_TOKEN_PING;
1011 q->qh.current_qtd = q->qtdaddr;
1012 q->qh.next_qtd = q->qtd.next;
1013 q->qh.altnext_qtd = q->qtd.altnext;
1014 q->qh.token = q->qtd.token;
1017 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1018 if (eps == EHCI_QH_EPS_HIGH) {
1019 q->qh.token &= ~QTD_TOKEN_PING;
1020 q->qh.token |= ping;
1023 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1024 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1026 for (i = 0; i < 5; i++) {
1027 q->qh.bufptr[i] = q->qtd.bufptr[i];
1030 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1031 // preserve QH DT bit
1032 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1033 q->qh.token |= dtoggle;
1036 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1037 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1039 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1041 return 0;
1044 static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw)
1046 int bufpos = 0;
1047 int cpage, offset;
1048 uint32_t head;
1049 uint32_t tail;
1052 if (!bytes) {
1053 return 0;
1056 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1057 if (cpage > 4) {
1058 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1059 return USB_RET_PROCERR;
1062 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1064 do {
1065 /* start and end of this page */
1066 head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1067 tail = head + ~QTD_BUFPTR_MASK + 1;
1068 /* add offset into page */
1069 head |= offset;
1071 if (bytes <= (tail - head)) {
1072 tail = head + bytes;
1075 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
1076 cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw);
1078 bufpos += (tail - head);
1079 offset += (tail - head);
1080 bytes -= (tail - head);
1082 if (bytes > 0) {
1083 cpage++;
1084 offset = 0;
1086 } while (bytes > 0);
1088 /* save cpage */
1089 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1091 /* save offset into cpage */
1092 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1093 q->qh.bufptr[0] |= offset;
1095 return 0;
1098 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1100 EHCIQueue *q = container_of(packet, EHCIQueue, packet);
1102 trace_usb_ehci_queue_action(q, "wakeup");
1103 assert(q->async == EHCI_ASYNC_INFLIGHT);
1104 q->async = EHCI_ASYNC_FINISHED;
1105 q->usb_status = packet->len;
1108 static void ehci_execute_complete(EHCIQueue *q)
1110 int c_err, reload;
1112 assert(q->async != EHCI_ASYNC_INFLIGHT);
1113 q->async = EHCI_ASYNC_NONE;
1115 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1116 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1118 if (q->usb_status < 0) {
1119 err:
1120 /* TO-DO: put this is in a function that can be invoked below as well */
1121 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1122 c_err--;
1123 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1125 switch(q->usb_status) {
1126 case USB_RET_NODEV:
1127 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1128 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1129 break;
1130 case USB_RET_STALL:
1131 q->qh.token |= QTD_TOKEN_HALT;
1132 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1133 break;
1134 case USB_RET_NAK:
1135 /* 4.10.3 */
1136 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1137 if ((q->pid == USB_TOKEN_IN) && reload) {
1138 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1139 nakcnt--;
1140 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1141 } else if (!reload) {
1142 return;
1144 break;
1145 case USB_RET_BABBLE:
1146 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1147 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1148 break;
1149 default:
1150 /* should not be triggerable */
1151 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1152 assert(0);
1153 break;
1155 } else {
1156 // DPRINTF("Short packet condition\n");
1157 // TODO check 4.12 for splits
1159 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1160 q->usb_status = USB_RET_BABBLE;
1161 goto err;
1164 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1165 if (ehci_buffer_rw(q, q->usb_status, 1) != 0) {
1166 q->usb_status = USB_RET_PROCERR;
1167 return;
1169 q->tbytes -= q->usb_status;
1170 } else {
1171 q->tbytes = 0;
1174 DPRINTF("updating tbytes to %d\n", q->tbytes);
1175 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1178 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1179 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1181 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1182 ehci_record_interrupt(q->ehci, USBSTS_INT);
1186 // 4.10.3
1188 static int ehci_execute(EHCIQueue *q)
1190 USBPort *port;
1191 USBDevice *dev;
1192 int ret;
1193 int i;
1194 int endp;
1195 int devadr;
1197 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1198 fprintf(stderr, "Attempting to execute inactive QH\n");
1199 return USB_RET_PROCERR;
1202 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1203 if (q->tbytes > BUFF_SIZE) {
1204 fprintf(stderr, "Request for more bytes than allowed\n");
1205 return USB_RET_PROCERR;
1208 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1209 switch(q->pid) {
1210 case 0: q->pid = USB_TOKEN_OUT; break;
1211 case 1: q->pid = USB_TOKEN_IN; break;
1212 case 2: q->pid = USB_TOKEN_SETUP; break;
1213 default: fprintf(stderr, "bad token\n"); break;
1216 if ((q->tbytes && q->pid != USB_TOKEN_IN) &&
1217 (ehci_buffer_rw(q, q->tbytes, 0) != 0)) {
1218 return USB_RET_PROCERR;
1221 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1222 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1224 ret = USB_RET_NODEV;
1226 // TO-DO: associating device with ehci port
1227 for(i = 0; i < NB_PORTS; i++) {
1228 port = &q->ehci->ports[i];
1229 dev = port->dev;
1231 // TODO sometime we will also need to check if we are the port owner
1233 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1234 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1235 i, q->ehci->portsc[i]);
1236 continue;
1239 q->packet.pid = q->pid;
1240 q->packet.devaddr = devadr;
1241 q->packet.devep = endp;
1242 q->packet.data = q->buffer;
1243 q->packet.len = q->tbytes;
1245 ret = usb_handle_packet(dev, &q->packet);
1247 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1248 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1249 q->packet.len, q->tbytes, endp, ret);
1251 if (ret != USB_RET_NODEV) {
1252 break;
1256 if (ret > BUFF_SIZE) {
1257 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1258 return USB_RET_PROCERR;
1261 return ret;
1264 /* 4.7.2
1267 static int ehci_process_itd(EHCIState *ehci,
1268 EHCIitd *itd)
1270 USBPort *port;
1271 USBDevice *dev;
1272 int ret;
1273 int i, j;
1274 int ptr;
1275 int pid;
1276 int pg;
1277 int len;
1278 int dir;
1279 int devadr;
1280 int endp;
1282 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1283 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1284 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1285 /* maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); */
1287 for(i = 0; i < 8; i++) {
1288 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1289 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1290 ehci->frindex >> 3, i);
1292 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1293 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1294 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1295 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1297 if (len > BUFF_SIZE) {
1298 return USB_RET_PROCERR;
1301 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1303 if (!dir) {
1304 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 0);
1305 pid = USB_TOKEN_OUT;
1306 } else
1307 pid = USB_TOKEN_IN;
1309 ret = USB_RET_NODEV;
1311 for (j = 0; j < NB_PORTS; j++) {
1312 port = &ehci->ports[j];
1313 dev = port->dev;
1315 // TODO sometime we will also need to check if we are the port owner
1317 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1318 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1319 j, ehci->portsc[j]);
1320 continue;
1323 ehci->ipacket.pid = pid;
1324 ehci->ipacket.devaddr = devadr;
1325 ehci->ipacket.devep = endp;
1326 ehci->ipacket.data = ehci->ibuffer;
1327 ehci->ipacket.len = len;
1329 DPRINTF("calling usb_handle_packet\n");
1330 ret = usb_handle_packet(dev, &ehci->ipacket);
1332 if (ret != USB_RET_NODEV) {
1333 break;
1337 /* In isoch, there is no facility to indicate a NAK so let's
1338 * instead just complete a zero-byte transaction. Setting
1339 * DBERR seems too draconian.
1342 if (ret == USB_RET_NAK) {
1343 if (ehci->isoch_pause > 0) {
1344 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1345 ehci->isoch_pause--;
1346 return 0;
1347 } else if (ehci->isoch_pause == -1) {
1348 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1349 // Pause frindex for up to 50 msec waiting for data from
1350 // remote
1351 ehci->isoch_pause = 50;
1352 return 0;
1353 } else {
1354 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1355 ret = 0;
1357 } else {
1358 DPRINTF("ISOCH: received ACK, clearing pause\n");
1359 ehci->isoch_pause = -1;
1362 if (ret >= 0) {
1363 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1365 if (itd->transact[i] & ITD_XACT_IOC) {
1366 ehci_record_interrupt(ehci, USBSTS_INT);
1370 if (ret >= 0 && dir) {
1371 cpu_physical_memory_rw(ptr, &ehci->ibuffer[0], len, 1);
1373 if (ret != len) {
1374 DPRINTF("ISOCH IN expected %d, got %d\n",
1375 len, ret);
1376 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1381 return 0;
1384 /* This state is the entry point for asynchronous schedule
1385 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1387 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1389 EHCIqh qh;
1390 int i = 0;
1391 int again = 0;
1392 uint32_t entry = ehci->asynclistaddr;
1394 /* set reclamation flag at start event (4.8.6) */
1395 if (async) {
1396 ehci_set_usbsts(ehci, USBSTS_REC);
1399 ehci_queues_rip_unused(ehci);
1401 /* Find the head of the list (4.9.1.1) */
1402 for(i = 0; i < MAX_QH; i++) {
1403 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1404 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1406 if (qh.epchar & QH_EPCHAR_H) {
1407 if (async) {
1408 entry |= (NLPTR_TYPE_QH << 1);
1411 ehci_set_fetch_addr(ehci, async, entry);
1412 ehci_set_state(ehci, async, EST_FETCHENTRY);
1413 again = 1;
1414 goto out;
1417 entry = qh.next;
1418 if (entry == ehci->asynclistaddr) {
1419 break;
1423 /* no head found for list. */
1425 ehci_set_state(ehci, async, EST_ACTIVE);
1427 out:
1428 return again;
1432 /* This state is the entry point for periodic schedule processing as
1433 * well as being a continuation state for async processing.
1435 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1437 int again = 0;
1438 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1440 if (entry < 0x1000) {
1441 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1442 ehci_set_state(ehci, async, EST_ACTIVE);
1443 goto out;
1446 /* section 4.8, only QH in async schedule */
1447 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1448 fprintf(stderr, "non queue head request in async schedule\n");
1449 return -1;
1452 switch (NLPTR_TYPE_GET(entry)) {
1453 case NLPTR_TYPE_QH:
1454 ehci_set_state(ehci, async, EST_FETCHQH);
1455 again = 1;
1456 break;
1458 case NLPTR_TYPE_ITD:
1459 ehci_set_state(ehci, async, EST_FETCHITD);
1460 again = 1;
1461 break;
1463 default:
1464 // TODO: handle siTD and FSTN types
1465 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1466 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1467 return -1;
1470 out:
1471 return again;
1474 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1476 uint32_t entry;
1477 EHCIQueue *q;
1478 int reload;
1480 entry = ehci_get_fetch_addr(ehci, async);
1481 q = ehci_find_queue_by_qh(ehci, entry);
1482 if (NULL == q) {
1483 q = ehci_alloc_queue(ehci, async);
1485 q->qhaddr = entry;
1486 q->seen++;
1488 if (q->seen > 1) {
1489 /* we are going in circles -- stop processing */
1490 ehci_set_state(ehci, async, EST_ACTIVE);
1491 q = NULL;
1492 goto out;
1495 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1496 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1498 if (q->async == EHCI_ASYNC_INFLIGHT) {
1499 /* I/O still in progress -- skip queue */
1500 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1501 goto out;
1503 if (q->async == EHCI_ASYNC_FINISHED) {
1504 /* I/O finished -- continue processing queue */
1505 trace_usb_ehci_queue_action(q, "resume");
1506 ehci_set_state(ehci, async, EST_EXECUTING);
1507 goto out;
1510 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1512 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1513 if (ehci->usbsts & USBSTS_REC) {
1514 ehci_clear_usbsts(ehci, USBSTS_REC);
1515 } else {
1516 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1517 " - done processing\n", q->qhaddr);
1518 ehci_set_state(ehci, async, EST_ACTIVE);
1519 q = NULL;
1520 goto out;
1524 #if EHCI_DEBUG
1525 if (q->qhaddr != q->qh.next) {
1526 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1527 q->qhaddr,
1528 q->qh.epchar & QH_EPCHAR_H,
1529 q->qh.token & QTD_TOKEN_HALT,
1530 q->qh.token & QTD_TOKEN_ACTIVE,
1531 q->qh.next);
1533 #endif
1535 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1536 if (reload) {
1537 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1540 if (q->qh.token & QTD_TOKEN_HALT) {
1541 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1543 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1544 q->qtdaddr = q->qh.current_qtd;
1545 ehci_set_state(ehci, async, EST_FETCHQTD);
1547 } else {
1548 /* EHCI spec version 1.0 Section 4.10.2 */
1549 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1552 out:
1553 return q;
1556 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1558 uint32_t entry;
1559 EHCIitd itd;
1561 assert(!async);
1562 entry = ehci_get_fetch_addr(ehci, async);
1564 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1565 sizeof(EHCIitd) >> 2);
1566 ehci_trace_itd(ehci, entry, &itd);
1568 if (ehci_process_itd(ehci, &itd) != 0) {
1569 return -1;
1572 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1573 sizeof(EHCIitd) >> 2);
1574 ehci_set_fetch_addr(ehci, async, itd.next);
1575 ehci_set_state(ehci, async, EST_FETCHENTRY);
1577 return 1;
1580 /* Section 4.10.2 - paragraph 3 */
1581 static int ehci_state_advqueue(EHCIQueue *q, int async)
1583 #if 0
1584 /* TO-DO: 4.10.2 - paragraph 2
1585 * if I-bit is set to 1 and QH is not active
1586 * go to horizontal QH
1588 if (I-bit set) {
1589 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1590 goto out;
1592 #endif
1595 * want data and alt-next qTD is valid
1597 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1598 (q->qh.altnext_qtd > 0x1000) &&
1599 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1600 q->qtdaddr = q->qh.altnext_qtd;
1601 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1604 * next qTD is valid
1606 } else if ((q->qh.next_qtd > 0x1000) &&
1607 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1608 q->qtdaddr = q->qh.next_qtd;
1609 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1612 * no valid qTD, try next QH
1614 } else {
1615 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1618 return 1;
1621 /* Section 4.10.2 - paragraph 4 */
1622 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1624 int again = 0;
1626 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1627 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1629 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1630 ehci_set_state(q->ehci, async, EST_EXECUTE);
1631 again = 1;
1632 } else {
1633 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1634 again = 1;
1637 return again;
1640 static int ehci_state_horizqh(EHCIQueue *q, int async)
1642 int again = 0;
1644 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1645 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1646 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1647 again = 1;
1648 } else {
1649 ehci_set_state(q->ehci, async, EST_ACTIVE);
1652 return again;
1656 * Write the qh back to guest physical memory. This step isn't
1657 * in the EHCI spec but we need to do it since we don't share
1658 * physical memory with our guest VM.
1660 * The first three dwords are read-only for the EHCI, so skip them
1661 * when writing back the qh.
1663 static void ehci_flush_qh(EHCIQueue *q)
1665 uint32_t *qh = (uint32_t *) &q->qh;
1666 uint32_t dwords = sizeof(EHCIqh) >> 2;
1667 uint32_t addr = NLPTR_GET(q->qhaddr);
1669 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1672 static int ehci_state_execute(EHCIQueue *q, int async)
1674 int again = 0;
1675 int reload, nakcnt;
1676 int smask;
1678 if (ehci_qh_do_overlay(q) != 0) {
1679 return -1;
1682 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1684 if (!smask) {
1685 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1686 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1687 if (reload && !nakcnt) {
1688 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1689 again = 1;
1690 goto out;
1694 // TODO verify enough time remains in the uframe as in 4.4.1.1
1695 // TODO write back ptr to async list when done or out of time
1696 // TODO Windows does not seem to ever set the MULT field
1698 if (!async) {
1699 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1700 if (!transactCtr) {
1701 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1702 again = 1;
1703 goto out;
1707 if (async) {
1708 ehci_set_usbsts(q->ehci, USBSTS_REC);
1711 q->usb_status = ehci_execute(q);
1712 if (q->usb_status == USB_RET_PROCERR) {
1713 again = -1;
1714 goto out;
1716 if (q->usb_status == USB_RET_ASYNC) {
1717 ehci_flush_qh(q);
1718 trace_usb_ehci_queue_action(q, "suspend");
1719 q->async = EHCI_ASYNC_INFLIGHT;
1720 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1721 again = 1;
1722 goto out;
1725 ehci_set_state(q->ehci, async, EST_EXECUTING);
1726 again = 1;
1728 out:
1729 return again;
1732 static int ehci_state_executing(EHCIQueue *q, int async)
1734 int again = 0;
1735 int reload, nakcnt;
1737 ehci_execute_complete(q);
1738 if (q->usb_status == USB_RET_ASYNC) {
1739 goto out;
1741 if (q->usb_status == USB_RET_PROCERR) {
1742 again = -1;
1743 goto out;
1746 // 4.10.3
1747 if (!async) {
1748 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1749 transactCtr--;
1750 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1751 // 4.10.3, bottom of page 82, should exit this state when transaction
1752 // counter decrements to 0
1755 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1756 if (reload) {
1757 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1758 if (q->usb_status == USB_RET_NAK) {
1759 if (nakcnt) {
1760 nakcnt--;
1762 } else {
1763 nakcnt = reload;
1765 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1768 /* 4.10.5 */
1769 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1770 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1771 } else {
1772 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1775 again = 1;
1777 out:
1778 ehci_flush_qh(q);
1779 return again;
1783 static int ehci_state_writeback(EHCIQueue *q, int async)
1785 int again = 0;
1787 /* Write back the QTD from the QH area */
1788 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1789 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1790 sizeof(EHCIqtd) >> 2);
1793 * EHCI specs say go horizontal here.
1795 * We can also advance the queue here for performance reasons. We
1796 * need to take care to only take that shortcut in case we've
1797 * processed the qtd just written back without errors, i.e. halt
1798 * bit is clear.
1800 if (q->qh.token & QTD_TOKEN_HALT) {
1801 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1802 again = 1;
1803 } else {
1804 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1805 again = 1;
1807 return again;
1811 * This is the state machine that is common to both async and periodic
1814 static void ehci_advance_state(EHCIState *ehci,
1815 int async)
1817 EHCIQueue *q = NULL;
1818 int again;
1819 int iter = 0;
1821 do {
1822 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1823 iter++;
1824 /* if we are roaming a lot of QH without executing a qTD
1825 * something is wrong with the linked list. TO-DO: why is
1826 * this hack needed?
1828 assert(iter < MAX_ITERATIONS);
1829 #if 0
1830 if (iter > MAX_ITERATIONS) {
1831 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1832 ehci_set_state(ehci, async, EST_ACTIVE);
1833 break;
1835 #endif
1837 switch(ehci_get_state(ehci, async)) {
1838 case EST_WAITLISTHEAD:
1839 again = ehci_state_waitlisthead(ehci, async);
1840 break;
1842 case EST_FETCHENTRY:
1843 again = ehci_state_fetchentry(ehci, async);
1844 break;
1846 case EST_FETCHQH:
1847 q = ehci_state_fetchqh(ehci, async);
1848 again = q ? 1 : 0;
1849 break;
1851 case EST_FETCHITD:
1852 again = ehci_state_fetchitd(ehci, async);
1853 break;
1855 case EST_ADVANCEQUEUE:
1856 again = ehci_state_advqueue(q, async);
1857 break;
1859 case EST_FETCHQTD:
1860 again = ehci_state_fetchqtd(q, async);
1861 break;
1863 case EST_HORIZONTALQH:
1864 again = ehci_state_horizqh(q, async);
1865 break;
1867 case EST_EXECUTE:
1868 iter = 0;
1869 again = ehci_state_execute(q, async);
1870 break;
1872 case EST_EXECUTING:
1873 assert(q != NULL);
1874 again = ehci_state_executing(q, async);
1875 break;
1877 case EST_WRITEBACK:
1878 again = ehci_state_writeback(q, async);
1879 break;
1881 default:
1882 fprintf(stderr, "Bad state!\n");
1883 again = -1;
1884 assert(0);
1885 break;
1888 if (again < 0) {
1889 fprintf(stderr, "processing error - resetting ehci HC\n");
1890 ehci_reset(ehci);
1891 again = 0;
1892 assert(0);
1895 while (again);
1897 ehci_commit_interrupt(ehci);
1900 static void ehci_advance_async_state(EHCIState *ehci)
1902 int async = 1;
1904 switch(ehci_get_state(ehci, async)) {
1905 case EST_INACTIVE:
1906 if (!(ehci->usbcmd & USBCMD_ASE)) {
1907 break;
1909 ehci_set_usbsts(ehci, USBSTS_ASS);
1910 ehci_set_state(ehci, async, EST_ACTIVE);
1911 // No break, fall through to ACTIVE
1913 case EST_ACTIVE:
1914 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1915 ehci_clear_usbsts(ehci, USBSTS_ASS);
1916 ehci_set_state(ehci, async, EST_INACTIVE);
1917 break;
1920 /* If the doorbell is set, the guest wants to make a change to the
1921 * schedule. The host controller needs to release cached data.
1922 * (section 4.8.2)
1924 if (ehci->usbcmd & USBCMD_IAAD) {
1925 DPRINTF("ASYNC: doorbell request acknowledged\n");
1926 ehci->usbcmd &= ~USBCMD_IAAD;
1927 ehci_set_interrupt(ehci, USBSTS_IAA);
1928 break;
1931 /* make sure guest has acknowledged */
1932 /* TO-DO: is this really needed? */
1933 if (ehci->usbsts & USBSTS_IAA) {
1934 DPRINTF("IAA status bit still set.\n");
1935 break;
1938 /* check that address register has been set */
1939 if (ehci->asynclistaddr == 0) {
1940 break;
1943 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1944 ehci_advance_state(ehci, async);
1945 break;
1947 default:
1948 /* this should only be due to a developer mistake */
1949 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1950 "Resetting to active\n", ehci->astate);
1951 assert(0);
1955 static void ehci_advance_periodic_state(EHCIState *ehci)
1957 uint32_t entry;
1958 uint32_t list;
1959 int async = 0;
1961 // 4.6
1963 switch(ehci_get_state(ehci, async)) {
1964 case EST_INACTIVE:
1965 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1966 ehci_set_usbsts(ehci, USBSTS_PSS);
1967 ehci_set_state(ehci, async, EST_ACTIVE);
1968 // No break, fall through to ACTIVE
1969 } else
1970 break;
1972 case EST_ACTIVE:
1973 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1974 ehci_clear_usbsts(ehci, USBSTS_PSS);
1975 ehci_set_state(ehci, async, EST_INACTIVE);
1976 break;
1979 list = ehci->periodiclistbase & 0xfffff000;
1980 /* check that register has been set */
1981 if (list == 0) {
1982 break;
1984 list |= ((ehci->frindex & 0x1ff8) >> 1);
1986 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1987 entry = le32_to_cpu(entry);
1989 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1990 ehci->frindex / 8, list, entry);
1991 ehci_set_fetch_addr(ehci, async,entry);
1992 ehci_set_state(ehci, async, EST_FETCHENTRY);
1993 ehci_advance_state(ehci, async);
1994 break;
1996 default:
1997 /* this should only be due to a developer mistake */
1998 fprintf(stderr, "ehci: Bad periodic state %d. "
1999 "Resetting to active\n", ehci->pstate);
2000 assert(0);
2004 static void ehci_frame_timer(void *opaque)
2006 EHCIState *ehci = opaque;
2007 int64_t expire_time, t_now;
2008 int usec_elapsed;
2009 int frames;
2010 int usec_now;
2011 int i;
2012 int skipped_frames = 0;
2015 t_now = qemu_get_clock_ns(vm_clock);
2016 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2017 if (expire_time == t_now) {
2018 expire_time++;
2021 usec_now = t_now / 1000;
2022 usec_elapsed = usec_now - ehci->last_run_usec;
2023 frames = usec_elapsed / FRAME_TIMER_USEC;
2024 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
2026 for (i = 0; i < frames; i++) {
2027 if ( !(ehci->usbsts & USBSTS_HALT)) {
2028 if (ehci->isoch_pause <= 0) {
2029 ehci->frindex += 8;
2032 if (ehci->frindex > 0x00001fff) {
2033 ehci->frindex = 0;
2034 ehci_set_interrupt(ehci, USBSTS_FLR);
2037 ehci->sofv = (ehci->frindex - 1) >> 3;
2038 ehci->sofv &= 0x000003ff;
2041 if (frames - i > 10) {
2042 skipped_frames++;
2043 } else {
2044 ehci_advance_periodic_state(ehci);
2047 ehci->last_run_usec += FRAME_TIMER_USEC;
2050 #if 0
2051 if (skipped_frames) {
2052 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2054 #endif
2056 /* Async is not inside loop since it executes everything it can once
2057 * called
2059 ehci_advance_async_state(ehci);
2061 qemu_mod_timer(ehci->frame_timer, expire_time);
2064 static CPUReadMemoryFunc *ehci_readfn[3]={
2065 ehci_mem_readb,
2066 ehci_mem_readw,
2067 ehci_mem_readl
2070 static CPUWriteMemoryFunc *ehci_writefn[3]={
2071 ehci_mem_writeb,
2072 ehci_mem_writew,
2073 ehci_mem_writel
2076 static void ehci_map(PCIDevice *pci_dev, int region_num,
2077 pcibus_t addr, pcibus_t size, int type)
2079 EHCIState *s =(EHCIState *)pci_dev;
2081 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
2082 region_num, addr, size, s->mem);
2083 s->mem_base = addr;
2084 cpu_register_physical_memory(addr, size, s->mem);
2087 static void ehci_device_destroy(USBBus *bus, USBDevice *dev)
2089 EHCIState *s = container_of(bus, EHCIState, bus);
2091 ehci_queues_rip_device(s, dev);
2094 static int usb_ehci_initfn(PCIDevice *dev);
2096 static USBPortOps ehci_port_ops = {
2097 .attach = ehci_attach,
2098 .detach = ehci_detach,
2099 .complete = ehci_async_complete_packet,
2102 static USBBusOps ehci_bus_ops = {
2103 .device_destroy = ehci_device_destroy,
2106 static PCIDeviceInfo ehci_info = {
2107 .qdev.name = "usb-ehci",
2108 .qdev.size = sizeof(EHCIState),
2109 .init = usb_ehci_initfn,
2112 static int usb_ehci_initfn(PCIDevice *dev)
2114 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2115 uint8_t *pci_conf = s->dev.config;
2116 int i;
2118 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
2119 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
2120 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2121 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2122 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2123 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2125 /* capabilities pointer */
2126 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2127 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2129 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2130 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2131 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2133 // pci_conf[0x50] = 0x01; // power management caps
2135 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2136 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2137 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2139 pci_conf[0x64] = 0x00;
2140 pci_conf[0x65] = 0x00;
2141 pci_conf[0x66] = 0x00;
2142 pci_conf[0x67] = 0x00;
2143 pci_conf[0x68] = 0x01;
2144 pci_conf[0x69] = 0x00;
2145 pci_conf[0x6a] = 0x00;
2146 pci_conf[0x6b] = 0x00; // USBLEGSUP
2147 pci_conf[0x6c] = 0x00;
2148 pci_conf[0x6d] = 0x00;
2149 pci_conf[0x6e] = 0x00;
2150 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2152 // 2.2 host controller interface version
2153 s->mmio[0x00] = (uint8_t) OPREGBASE;
2154 s->mmio[0x01] = 0x00;
2155 s->mmio[0x02] = 0x00;
2156 s->mmio[0x03] = 0x01; // HC version
2157 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2158 s->mmio[0x05] = 0x00; // No companion ports at present
2159 s->mmio[0x06] = 0x00;
2160 s->mmio[0x07] = 0x00;
2161 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2162 s->mmio[0x09] = 0x68; // EECP
2163 s->mmio[0x0a] = 0x00;
2164 s->mmio[0x0b] = 0x00;
2166 s->irq = s->dev.irq[3];
2168 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2169 for(i = 0; i < NB_PORTS; i++) {
2170 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2171 USB_SPEED_MASK_HIGH);
2172 usb_port_location(&s->ports[i], NULL, i+1);
2173 s->ports[i].dev = 0;
2176 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2177 QTAILQ_INIT(&s->queues);
2179 qemu_register_reset(ehci_reset, s);
2181 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2182 DEVICE_LITTLE_ENDIAN);
2184 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2185 ehci_map);
2187 fprintf(stderr, "*** EHCI support is under development ***\n");
2189 return 0;
2192 static void ehci_register(void)
2194 pci_qdev_register(&ehci_info);
2196 device_init(ehci_register);
2199 * vim: expandtab ts=4