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target/ppc: Add helpers for fmadds et al
[qemu.git] / target / ppc / fpu_helper.c
blob12dd889fb5f8d8056602d36f9226401a302487ef
1 /*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "fpu/softfloat.h"
25
26 static inline float128 float128_snan_to_qnan(float128 x)
27 {
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33 }
34
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
38
39 static inline bool fp_exceptions_enabled(CPUPPCState *env)
40 {
41 #ifdef CONFIG_USER_ONLY
42 return true;
43 #else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45 #endif
46 }
47
48 /*****************************************************************************/
49 /* Floating point operations helpers */
50
51 /*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55 uint64_t helper_todouble(uint32_t arg)
56 {
57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
59
60 if (likely(abs_arg >= 0x00800000)) {
61 if (unlikely(extract32(arg, 23, 8) == 0xff)) {
62 /* Inf or NAN. */
63 ret = (uint64_t)extract32(arg, 31, 1) << 63;
64 ret |= (uint64_t)0x7ff << 52;
65 ret |= (uint64_t)extract32(arg, 0, 23) << 29;
66 } else {
67 /* Normalized operand. */
68 ret = (uint64_t)extract32(arg, 30, 2) << 62;
69 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
70 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
71 }
72 } else {
73 /* Zero or Denormalized operand. */
74 ret = (uint64_t)extract32(arg, 31, 1) << 63;
75 if (unlikely(abs_arg != 0)) {
76 /*
77 * Denormalized operand.
78 * Shift fraction so that the msb is in the implicit bit position.
79 * Thus, shift is in the range [1:23].
80 */
81 int shift = clz32(abs_arg) - 8;
82 /*
83 * The first 3 terms compute the float64 exponent. We then bias
84 * this result by -1 so that we can swallow the implicit bit below.
85 */
86 int exp = -126 - shift + 1023 - 1;
87
88 ret |= (uint64_t)exp << 52;
89 ret += (uint64_t)abs_arg << (52 - 23 + shift);
90 }
91 }
92 return ret;
93 }
94
95 /*
96 * This is the non-arithmatic conversion that happens e.g. on stores.
97 * In the Power ISA pseudocode, this is called SINGLE.
98 */
99 uint32_t helper_tosingle(uint64_t arg)
100 {
101 int exp = extract64(arg, 52, 11);
102 uint32_t ret;
103
104 if (likely(exp > 896)) {
105 /* No denormalization required (includes Inf, NaN). */
106 ret = extract64(arg, 62, 2) << 30;
107 ret |= extract64(arg, 29, 30);
108 } else {
109 /*
110 * Zero or Denormal result. If the exponent is in bounds for
111 * a single-precision denormal result, extract the proper
112 * bits. If the input is not zero, and the exponent is out of
113 * bounds, then the result is undefined; this underflows to
114 * zero.
115 */
116 ret = extract64(arg, 63, 1) << 31;
117 if (unlikely(exp >= 874)) {
118 /* Denormal result. */
119 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
120 }
121 }
122 return ret;
123 }
124
125 static inline int ppc_float32_get_unbiased_exp(float32 f)
126 {
127 return ((f >> 23) & 0xFF) - 127;
128 }
129
130 static inline int ppc_float64_get_unbiased_exp(float64 f)
131 {
132 return ((f >> 52) & 0x7FF) - 1023;
133 }
134
135 /* Classify a floating-point number. */
136 enum {
137 is_normal = 1,
138 is_zero = 2,
139 is_denormal = 4,
140 is_inf = 8,
141 is_qnan = 16,
142 is_snan = 32,
143 is_neg = 64,
144 };
145
146 #define COMPUTE_CLASS(tp) \
147 static int tp##_classify(tp arg) \
148 { \
149 int ret = tp##_is_neg(arg) * is_neg; \
150 if (unlikely(tp##_is_any_nan(arg))) { \
151 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
152 ret |= (tp##_is_signaling_nan(arg, &dummy) \
153 ? is_snan : is_qnan); \
154 } else if (unlikely(tp##_is_infinity(arg))) { \
155 ret |= is_inf; \
156 } else if (tp##_is_zero(arg)) { \
157 ret |= is_zero; \
158 } else if (tp##_is_zero_or_denormal(arg)) { \
159 ret |= is_denormal; \
160 } else { \
161 ret |= is_normal; \
162 } \
163 return ret; \
164 }
165
166 COMPUTE_CLASS(float16)
167 COMPUTE_CLASS(float32)
168 COMPUTE_CLASS(float64)
169 COMPUTE_CLASS(float128)
170
171 static void set_fprf_from_class(CPUPPCState *env, int class)
172 {
173 static const uint8_t fprf[6][2] = {
174 { 0x04, 0x08 }, /* normalized */
175 { 0x02, 0x12 }, /* zero */
176 { 0x14, 0x18 }, /* denormalized */
177 { 0x05, 0x09 }, /* infinity */
178 { 0x11, 0x11 }, /* qnan */
179 { 0x00, 0x00 }, /* snan -- flags are undefined */
180 };
181 bool isneg = class & is_neg;
182
183 env->fpscr &= ~FP_FPRF;
184 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
185 }
186
187 #define COMPUTE_FPRF(tp) \
188 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
189 { \
190 set_fprf_from_class(env, tp##_classify(arg)); \
191 }
192
193 COMPUTE_FPRF(float16)
194 COMPUTE_FPRF(float32)
195 COMPUTE_FPRF(float64)
196 COMPUTE_FPRF(float128)
197
198 /* Floating-point invalid operations exception */
199 static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
200 {
201 /* Update the floating-point invalid operation summary */
202 env->fpscr |= FP_VX;
203 /* Update the floating-point exception summary */
204 env->fpscr |= FP_FX;
205 if (fpscr_ve != 0) {
206 /* Update the floating-point enabled exception summary */
207 env->fpscr |= FP_FEX;
208 if (fp_exceptions_enabled(env)) {
209 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
210 POWERPC_EXCP_FP | op, retaddr);
211 }
212 }
213 }
214
215 static void finish_invalid_op_arith(CPUPPCState *env, int op,
216 bool set_fpcc, uintptr_t retaddr)
217 {
218 env->fpscr &= ~(FP_FR | FP_FI);
219 if (fpscr_ve == 0) {
220 if (set_fpcc) {
221 env->fpscr &= ~FP_FPCC;
222 env->fpscr |= (FP_C | FP_FU);
223 }
224 }
225 finish_invalid_op_excp(env, op, retaddr);
226 }
227
228 /* Signalling NaN */
229 static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
230 {
231 env->fpscr |= FP_VXSNAN;
232 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
233 }
234
235 /* Magnitude subtraction of infinities */
236 static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
237 uintptr_t retaddr)
238 {
239 env->fpscr |= FP_VXISI;
240 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
241 }
242
243 /* Division of infinity by infinity */
244 static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
245 uintptr_t retaddr)
246 {
247 env->fpscr |= FP_VXIDI;
248 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
249 }
250
251 /* Division of zero by zero */
252 static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
253 uintptr_t retaddr)
254 {
255 env->fpscr |= FP_VXZDZ;
256 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
257 }
258
259 /* Multiplication of zero by infinity */
260 static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
261 uintptr_t retaddr)
262 {
263 env->fpscr |= FP_VXIMZ;
264 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
265 }
266
267 /* Square root of a negative number */
268 static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
269 uintptr_t retaddr)
270 {
271 env->fpscr |= FP_VXSQRT;
272 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
273 }
274
275 /* Ordered comparison of NaN */
276 static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
277 uintptr_t retaddr)
278 {
279 env->fpscr |= FP_VXVC;
280 if (set_fpcc) {
281 env->fpscr &= ~FP_FPCC;
282 env->fpscr |= (FP_C | FP_FU);
283 }
284 /* Update the floating-point invalid operation summary */
285 env->fpscr |= FP_VX;
286 /* Update the floating-point exception summary */
287 env->fpscr |= FP_FX;
288 /* We must update the target FPR before raising the exception */
289 if (fpscr_ve != 0) {
290 CPUState *cs = env_cpu(env);
291
292 cs->exception_index = POWERPC_EXCP_PROGRAM;
293 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
294 /* Update the floating-point enabled exception summary */
295 env->fpscr |= FP_FEX;
296 /* Exception is deferred */
297 }
298 }
299
300 /* Invalid conversion */
301 static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
302 uintptr_t retaddr)
303 {
304 env->fpscr |= FP_VXCVI;
305 env->fpscr &= ~(FP_FR | FP_FI);
306 if (fpscr_ve == 0) {
307 if (set_fpcc) {
308 env->fpscr &= ~FP_FPCC;
309 env->fpscr |= (FP_C | FP_FU);
310 }
311 }
312 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
313 }
314
315 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
316 {
317 env->fpscr |= FP_ZX;
318 env->fpscr &= ~(FP_FR | FP_FI);
319 /* Update the floating-point exception summary */
320 env->fpscr |= FP_FX;
321 if (fpscr_ze != 0) {
322 /* Update the floating-point enabled exception summary */
323 env->fpscr |= FP_FEX;
324 if (fp_exceptions_enabled(env)) {
325 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
326 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
327 raddr);
328 }
329 }
330 }
331
332 static inline void float_overflow_excp(CPUPPCState *env)
333 {
334 CPUState *cs = env_cpu(env);
335
336 env->fpscr |= FP_OX;
337 /* Update the floating-point exception summary */
338 env->fpscr |= FP_FX;
339 if (fpscr_oe != 0) {
340 /* XXX: should adjust the result */
341 /* Update the floating-point enabled exception summary */
342 env->fpscr |= FP_FEX;
343 /* We must update the target FPR before raising the exception */
344 cs->exception_index = POWERPC_EXCP_PROGRAM;
345 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
346 } else {
347 env->fpscr |= FP_XX;
348 env->fpscr |= FP_FI;
349 }
350 }
351
352 static inline void float_underflow_excp(CPUPPCState *env)
353 {
354 CPUState *cs = env_cpu(env);
355
356 env->fpscr |= FP_UX;
357 /* Update the floating-point exception summary */
358 env->fpscr |= FP_FX;
359 if (fpscr_ue != 0) {
360 /* XXX: should adjust the result */
361 /* Update the floating-point enabled exception summary */
362 env->fpscr |= FP_FEX;
363 /* We must update the target FPR before raising the exception */
364 cs->exception_index = POWERPC_EXCP_PROGRAM;
365 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
366 }
367 }
368
369 static inline void float_inexact_excp(CPUPPCState *env)
370 {
371 CPUState *cs = env_cpu(env);
372
373 env->fpscr |= FP_FI;
374 env->fpscr |= FP_XX;
375 /* Update the floating-point exception summary */
376 env->fpscr |= FP_FX;
377 if (fpscr_xe != 0) {
378 /* Update the floating-point enabled exception summary */
379 env->fpscr |= FP_FEX;
380 /* We must update the target FPR before raising the exception */
381 cs->exception_index = POWERPC_EXCP_PROGRAM;
382 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
383 }
384 }
385
386 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
387 {
388 uint32_t mask = 1u << bit;
389 if (env->fpscr & mask) {
390 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask);
391 }
392 }
393
394 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
395 {
396 uint32_t mask = 1u << bit;
397 if (!(env->fpscr & mask)) {
398 ppc_store_fpscr(env, env->fpscr | mask);
399 }
400 }
401
402 void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
403 {
404 target_ulong mask = 0;
405 int i;
406
407 /* TODO: push this extension back to translation time */
408 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
409 if (nibbles & (1 << i)) {
410 mask |= (target_ulong) 0xf << (4 * i);
411 }
412 }
413 val = (val & mask) | (env->fpscr & ~mask);
414 ppc_store_fpscr(env, val);
415 }
416
417 void helper_fpscr_check_status(CPUPPCState *env)
418 {
419 CPUState *cs = env_cpu(env);
420 target_ulong fpscr = env->fpscr;
421 int error = 0;
422
423 if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
424 error = POWERPC_EXCP_FP_OX;
425 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) {
426 error = POWERPC_EXCP_FP_UX;
427 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) {
428 error = POWERPC_EXCP_FP_XX;
429 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) {
430 error = POWERPC_EXCP_FP_ZX;
431 } else if (fpscr & FP_VE) {
432 if (fpscr & FP_VXSOFT) {
433 error = POWERPC_EXCP_FP_VXSOFT;
434 } else if (fpscr & FP_VXSNAN) {
435 error = POWERPC_EXCP_FP_VXSNAN;
436 } else if (fpscr & FP_VXISI) {
437 error = POWERPC_EXCP_FP_VXISI;
438 } else if (fpscr & FP_VXIDI) {
439 error = POWERPC_EXCP_FP_VXIDI;
440 } else if (fpscr & FP_VXZDZ) {
441 error = POWERPC_EXCP_FP_VXZDZ;
442 } else if (fpscr & FP_VXIMZ) {
443 error = POWERPC_EXCP_FP_VXIMZ;
444 } else if (fpscr & FP_VXVC) {
445 error = POWERPC_EXCP_FP_VXVC;
446 } else if (fpscr & FP_VXSQRT) {
447 error = POWERPC_EXCP_FP_VXSQRT;
448 } else if (fpscr & FP_VXCVI) {
449 error = POWERPC_EXCP_FP_VXCVI;
450 } else {
451 return;
452 }
453 } else {
454 return;
455 }
456 cs->exception_index = POWERPC_EXCP_PROGRAM;
457 env->error_code = error | POWERPC_EXCP_FP;
458 /* Deferred floating-point exception after target FPSCR update */
459 if (fp_exceptions_enabled(env)) {
460 raise_exception_err_ra(env, cs->exception_index,
461 env->error_code, GETPC());
462 }
463 }
464
465 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
466 {
467 CPUState *cs = env_cpu(env);
468 int status = get_float_exception_flags(&env->fp_status);
469
470 if (status & float_flag_overflow) {
471 float_overflow_excp(env);
472 } else if (status & float_flag_underflow) {
473 float_underflow_excp(env);
474 }
475 if (status & float_flag_inexact) {
476 float_inexact_excp(env);
477 } else {
478 env->fpscr &= ~FP_FI; /* clear the FPSCR[FI] bit */
479 }
480
481 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
482 (env->error_code & POWERPC_EXCP_FP)) {
483 /* Deferred floating-point exception after target FPR update */
484 if (fp_exceptions_enabled(env)) {
485 raise_exception_err_ra(env, cs->exception_index,
486 env->error_code, raddr);
487 }
488 }
489 }
490
491 void helper_float_check_status(CPUPPCState *env)
492 {
493 do_float_check_status(env, GETPC());
494 }
495
496 void helper_reset_fpstatus(CPUPPCState *env)
497 {
498 set_float_exception_flags(0, &env->fp_status);
499 }
500
501 static void float_invalid_op_addsub(CPUPPCState *env, int flags,
502 bool set_fpcc, uintptr_t retaddr)
503 {
504 if (flags & float_flag_invalid_isi) {
505 float_invalid_op_vxisi(env, set_fpcc, retaddr);
506 } else if (flags & float_flag_invalid_snan) {
507 float_invalid_op_vxsnan(env, retaddr);
508 }
509 }
510
511 /* fadd - fadd. */
512 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
513 {
514 float64 ret = float64_add(arg1, arg2, &env->fp_status);
515 int flags = get_float_exception_flags(&env->fp_status);
516
517 if (unlikely(flags & float_flag_invalid)) {
518 float_invalid_op_addsub(env, flags, 1, GETPC());
519 }
520
521 return ret;
522 }
523
524 /* fsub - fsub. */
525 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
526 {
527 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
528 int flags = get_float_exception_flags(&env->fp_status);
529
530 if (unlikely(flags & float_flag_invalid)) {
531 float_invalid_op_addsub(env, flags, 1, GETPC());
532 }
533
534 return ret;
535 }
536
537 static void float_invalid_op_mul(CPUPPCState *env, int flags,
538 bool set_fprc, uintptr_t retaddr)
539 {
540 if (flags & float_flag_invalid_imz) {
541 float_invalid_op_vximz(env, set_fprc, retaddr);
542 } else if (flags & float_flag_invalid_snan) {
543 float_invalid_op_vxsnan(env, retaddr);
544 }
545 }
546
547 /* fmul - fmul. */
548 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
549 {
550 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
551 int flags = get_float_exception_flags(&env->fp_status);
552
553 if (unlikely(flags & float_flag_invalid)) {
554 float_invalid_op_mul(env, flags, 1, GETPC());
555 }
556
557 return ret;
558 }
559
560 static void float_invalid_op_div(CPUPPCState *env, int flags,
561 bool set_fprc, uintptr_t retaddr)
562 {
563 if (flags & float_flag_invalid_idi) {
564 float_invalid_op_vxidi(env, set_fprc, retaddr);
565 } else if (flags & float_flag_invalid_zdz) {
566 float_invalid_op_vxzdz(env, set_fprc, retaddr);
567 } else if (flags & float_flag_invalid_snan) {
568 float_invalid_op_vxsnan(env, retaddr);
569 }
570 }
571
572 /* fdiv - fdiv. */
573 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
574 {
575 float64 ret = float64_div(arg1, arg2, &env->fp_status);
576 int flags = get_float_exception_flags(&env->fp_status);
577
578 if (unlikely(flags & float_flag_invalid)) {
579 float_invalid_op_div(env, flags, 1, GETPC());
580 }
581 if (unlikely(flags & float_flag_divbyzero)) {
582 float_zero_divide_excp(env, GETPC());
583 }
584
585 return ret;
586 }
587
588 static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
589 uint64_t ret, uint64_t ret_nan,
590 bool set_fprc, uintptr_t retaddr)
591 {
592 /*
593 * VXCVI is different from most in that it sets two exception bits,
594 * VXCVI and VXSNAN for an SNaN input.
595 */
596 if (flags & float_flag_invalid_snan) {
597 env->fpscr |= FP_VXSNAN;
598 }
599 float_invalid_op_vxcvi(env, set_fprc, retaddr);
600
601 return flags & float_flag_invalid_cvti ? ret : ret_nan;
602 }
603
604 #define FPU_FCTI(op, cvt, nanval) \
605 uint64_t helper_##op(CPUPPCState *env, float64 arg) \
606 { \
607 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
608 int flags = get_float_exception_flags(&env->fp_status); \
609 if (unlikely(flags & float_flag_invalid)) { \
610 ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
611 } \
612 return ret; \
613 }
614
615 FPU_FCTI(fctiw, int32, 0x80000000U)
616 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
617 FPU_FCTI(fctiwu, uint32, 0x00000000U)
618 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
619 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
620 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
621 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
622 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
623
624 #define FPU_FCFI(op, cvtr, is_single) \
625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
626 { \
627 CPU_DoubleU farg; \
628 \
629 if (is_single) { \
630 float32 tmp = cvtr(arg, &env->fp_status); \
631 farg.d = float32_to_float64(tmp, &env->fp_status); \
632 } else { \
633 farg.d = cvtr(arg, &env->fp_status); \
634 } \
635 do_float_check_status(env, GETPC()); \
636 return farg.ll; \
637 }
638
639 FPU_FCFI(fcfid, int64_to_float64, 0)
640 FPU_FCFI(fcfids, int64_to_float32, 1)
641 FPU_FCFI(fcfidu, uint64_to_float64, 0)
642 FPU_FCFI(fcfidus, uint64_to_float32, 1)
643
644 static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
645 FloatRoundMode rounding_mode)
646 {
647 FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
648 int flags;
649
650 set_float_rounding_mode(rounding_mode, &env->fp_status);
651 arg = float64_round_to_int(arg, &env->fp_status);
652 set_float_rounding_mode(old_rounding_mode, &env->fp_status);
653
654 flags = get_float_exception_flags(&env->fp_status);
655 if (flags & float_flag_invalid_snan) {
656 float_invalid_op_vxsnan(env, GETPC());
657 }
658
659 /* fri* does not set FPSCR[XX] */
660 set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status);
661 do_float_check_status(env, GETPC());
662
663 return arg;
664 }
665
666 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
667 {
668 return do_fri(env, arg, float_round_ties_away);
669 }
670
671 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
672 {
673 return do_fri(env, arg, float_round_to_zero);
674 }
675
676 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
677 {
678 return do_fri(env, arg, float_round_up);
679 }
680
681 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
682 {
683 return do_fri(env, arg, float_round_down);
684 }
685
686 static void float_invalid_op_madd(CPUPPCState *env, int flags,
687 bool set_fpcc, uintptr_t retaddr)
688 {
689 if (flags & float_flag_invalid_imz) {
690 float_invalid_op_vximz(env, set_fpcc, retaddr);
691 } else {
692 float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
693 }
694 }
695
696 static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
697 float64 c, int madd_flags, uintptr_t retaddr)
698 {
699 float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
700 int flags = get_float_exception_flags(&env->fp_status);
701
702 if (unlikely(flags & float_flag_invalid)) {
703 float_invalid_op_madd(env, flags, 1, retaddr);
704 }
705 return ret;
706 }
707
708 static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b,
709 float64 c, int madd_flags, uintptr_t retaddr)
710 {
711 float64 ret = float64r32_muladd(a, b, c, madd_flags, &env->fp_status);
712 int flags = get_float_exception_flags(&env->fp_status);
713
714 if (unlikely(flags & float_flag_invalid)) {
715 float_invalid_op_madd(env, flags, 1, retaddr);
716 }
717 return ret;
718 }
719
720 #define FPU_FMADD(op, madd_flags) \
721 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
722 uint64_t arg2, uint64_t arg3) \
723 { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } \
724 uint64_t helper_##op##s(CPUPPCState *env, uint64_t arg1, \
725 uint64_t arg2, uint64_t arg3) \
726 { return do_fmadds(env, arg1, arg2, arg3, madd_flags, GETPC()); }
727
728 #define MADD_FLGS 0
729 #define MSUB_FLGS float_muladd_negate_c
730 #define NMADD_FLGS float_muladd_negate_result
731 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
732
733 FPU_FMADD(fmadd, MADD_FLGS)
734 FPU_FMADD(fnmadd, NMADD_FLGS)
735 FPU_FMADD(fmsub, MSUB_FLGS)
736 FPU_FMADD(fnmsub, NMSUB_FLGS)
737
738 /* frsp - frsp. */
739 static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
740 {
741 float32 f32 = float64_to_float32(arg, &env->fp_status);
742 int flags = get_float_exception_flags(&env->fp_status);
743
744 if (unlikely(flags & float_flag_invalid_snan)) {
745 float_invalid_op_vxsnan(env, retaddr);
746 }
747 return helper_todouble(f32);
748 }
749
750 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
751 {
752 return do_frsp(env, arg, GETPC());
753 }
754
755 static void float_invalid_op_sqrt(CPUPPCState *env, int flags,
756 bool set_fpcc, uintptr_t retaddr)
757 {
758 if (unlikely(flags & float_flag_invalid_sqrt)) {
759 float_invalid_op_vxsqrt(env, set_fpcc, retaddr);
760 } else if (unlikely(flags & float_flag_invalid_snan)) {
761 float_invalid_op_vxsnan(env, retaddr);
762 }
763 }
764
765 /* fsqrt - fsqrt. */
766 float64 helper_fsqrt(CPUPPCState *env, float64 arg)
767 {
768 float64 ret = float64_sqrt(arg, &env->fp_status);
769 int flags = get_float_exception_flags(&env->fp_status);
770
771 if (unlikely(flags & float_flag_invalid)) {
772 float_invalid_op_sqrt(env, flags, 1, GETPC());
773 }
774
775 return ret;
776 }
777
778 /* fre - fre. */
779 float64 helper_fre(CPUPPCState *env, float64 arg)
780 {
781 /* "Estimate" the reciprocal with actual division. */
782 float64 ret = float64_div(float64_one, arg, &env->fp_status);
783 int flags = get_float_exception_flags(&env->fp_status);
784
785 if (unlikely(flags & float_flag_invalid_snan)) {
786 float_invalid_op_vxsnan(env, GETPC());
787 }
788 if (unlikely(flags & float_flag_divbyzero)) {
789 float_zero_divide_excp(env, GETPC());
790 /* For FPSCR.ZE == 0, the result is 1/2. */
791 ret = float64_set_sign(float64_half, float64_is_neg(arg));
792 }
793
794 return ret;
795 }
796
797 /* fres - fres. */
798 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
799 {
800 CPU_DoubleU farg;
801 float32 f32;
802
803 farg.ll = arg;
804
805 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
806 /* sNaN reciprocal */
807 float_invalid_op_vxsnan(env, GETPC());
808 }
809 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
810 f32 = float64_to_float32(farg.d, &env->fp_status);
811 farg.d = float32_to_float64(f32, &env->fp_status);
812
813 return farg.ll;
814 }
815
816 /* frsqrte - frsqrte. */
817 float64 helper_frsqrte(CPUPPCState *env, float64 arg)
818 {
819 /* "Estimate" the reciprocal with actual division. */
820 float64 rets = float64_sqrt(arg, &env->fp_status);
821 float64 retd = float64_div(float64_one, rets, &env->fp_status);
822 int flags = get_float_exception_flags(&env->fp_status);
823
824 if (unlikely(flags & float_flag_invalid)) {
825 float_invalid_op_sqrt(env, flags, 1, GETPC());
826 }
827 if (unlikely(flags & float_flag_divbyzero)) {
828 /* Reciprocal of (square root of) zero. */
829 float_zero_divide_excp(env, GETPC());
830 }
831
832 return retd;
833 }
834
835 /* fsel - fsel. */
836 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
837 uint64_t arg3)
838 {
839 CPU_DoubleU farg1;
840
841 farg1.ll = arg1;
842
843 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
844 !float64_is_any_nan(farg1.d)) {
845 return arg2;
846 } else {
847 return arg3;
848 }
849 }
850
851 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
852 {
853 int fe_flag = 0;
854 int fg_flag = 0;
855
856 if (unlikely(float64_is_infinity(fra) ||
857 float64_is_infinity(frb) ||
858 float64_is_zero(frb))) {
859 fe_flag = 1;
860 fg_flag = 1;
861 } else {
862 int e_a = ppc_float64_get_unbiased_exp(fra);
863 int e_b = ppc_float64_get_unbiased_exp(frb);
864
865 if (unlikely(float64_is_any_nan(fra) ||
866 float64_is_any_nan(frb))) {
867 fe_flag = 1;
868 } else if ((e_b <= -1022) || (e_b >= 1021)) {
869 fe_flag = 1;
870 } else if (!float64_is_zero(fra) &&
871 (((e_a - e_b) >= 1023) ||
872 ((e_a - e_b) <= -1021) ||
873 (e_a <= -970))) {
874 fe_flag = 1;
875 }
876
877 if (unlikely(float64_is_zero_or_denormal(frb))) {
878 /* XB is not zero because of the above check and */
879 /* so must be denormalized. */
880 fg_flag = 1;
881 }
882 }
883
884 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
885 }
886
887 uint32_t helper_ftsqrt(uint64_t frb)
888 {
889 int fe_flag = 0;
890 int fg_flag = 0;
891
892 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
893 fe_flag = 1;
894 fg_flag = 1;
895 } else {
896 int e_b = ppc_float64_get_unbiased_exp(frb);
897
898 if (unlikely(float64_is_any_nan(frb))) {
899 fe_flag = 1;
900 } else if (unlikely(float64_is_zero(frb))) {
901 fe_flag = 1;
902 } else if (unlikely(float64_is_neg(frb))) {
903 fe_flag = 1;
904 } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
905 fe_flag = 1;
906 }
907
908 if (unlikely(float64_is_zero_or_denormal(frb))) {
909 /* XB is not zero because of the above check and */
910 /* therefore must be denormalized. */
911 fg_flag = 1;
912 }
913 }
914
915 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
916 }
917
918 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
919 uint32_t crfD)
920 {
921 CPU_DoubleU farg1, farg2;
922 uint32_t ret = 0;
923
924 farg1.ll = arg1;
925 farg2.ll = arg2;
926
927 if (unlikely(float64_is_any_nan(farg1.d) ||
928 float64_is_any_nan(farg2.d))) {
929 ret = 0x01UL;
930 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
931 ret = 0x08UL;
932 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
933 ret = 0x04UL;
934 } else {
935 ret = 0x02UL;
936 }
937
938 env->fpscr &= ~FP_FPCC;
939 env->fpscr |= ret << FPSCR_FPCC;
940 env->crf[crfD] = ret;
941 if (unlikely(ret == 0x01UL
942 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
943 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
944 /* sNaN comparison */
945 float_invalid_op_vxsnan(env, GETPC());
946 }
947 }
948
949 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
950 uint32_t crfD)
951 {
952 CPU_DoubleU farg1, farg2;
953 uint32_t ret = 0;
954
955 farg1.ll = arg1;
956 farg2.ll = arg2;
957
958 if (unlikely(float64_is_any_nan(farg1.d) ||
959 float64_is_any_nan(farg2.d))) {
960 ret = 0x01UL;
961 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
962 ret = 0x08UL;
963 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
964 ret = 0x04UL;
965 } else {
966 ret = 0x02UL;
967 }
968
969 env->fpscr &= ~FP_FPCC;
970 env->fpscr |= ret << FPSCR_FPCC;
971 env->crf[crfD] = (uint32_t) ret;
972 if (unlikely(ret == 0x01UL)) {
973 float_invalid_op_vxvc(env, 1, GETPC());
974 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
975 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
976 /* sNaN comparison */
977 float_invalid_op_vxsnan(env, GETPC());
978 }
979 }
980 }
981
982 /* Single-precision floating-point conversions */
983 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
984 {
985 CPU_FloatU u;
986
987 u.f = int32_to_float32(val, &env->vec_status);
988
989 return u.l;
990 }
991
992 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
993 {
994 CPU_FloatU u;
995
996 u.f = uint32_to_float32(val, &env->vec_status);
997
998 return u.l;
999 }
1000
1001 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1002 {
1003 CPU_FloatU u;
1004
1005 u.l = val;
1006 /* NaN are not treated the same way IEEE 754 does */
1007 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1008 return 0;
1009 }
1010
1011 return float32_to_int32(u.f, &env->vec_status);
1012 }
1013
1014 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1015 {
1016 CPU_FloatU u;
1017
1018 u.l = val;
1019 /* NaN are not treated the same way IEEE 754 does */
1020 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1021 return 0;
1022 }
1023
1024 return float32_to_uint32(u.f, &env->vec_status);
1025 }
1026
1027 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1028 {
1029 CPU_FloatU u;
1030
1031 u.l = val;
1032 /* NaN are not treated the same way IEEE 754 does */
1033 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1034 return 0;
1035 }
1036
1037 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1038 }
1039
1040 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1041 {
1042 CPU_FloatU u;
1043
1044 u.l = val;
1045 /* NaN are not treated the same way IEEE 754 does */
1046 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1047 return 0;
1048 }
1049
1050 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1051 }
1052
1053 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1054 {
1055 CPU_FloatU u;
1056 float32 tmp;
1057
1058 u.f = int32_to_float32(val, &env->vec_status);
1059 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1060 u.f = float32_div(u.f, tmp, &env->vec_status);
1061
1062 return u.l;
1063 }
1064
1065 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1066 {
1067 CPU_FloatU u;
1068 float32 tmp;
1069
1070 u.f = uint32_to_float32(val, &env->vec_status);
1071 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1072 u.f = float32_div(u.f, tmp, &env->vec_status);
1073
1074 return u.l;
1075 }
1076
1077 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1078 {
1079 CPU_FloatU u;
1080 float32 tmp;
1081
1082 u.l = val;
1083 /* NaN are not treated the same way IEEE 754 does */
1084 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1085 return 0;
1086 }
1087 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1088 u.f = float32_mul(u.f, tmp, &env->vec_status);
1089
1090 return float32_to_int32(u.f, &env->vec_status);
1091 }
1092
1093 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1094 {
1095 CPU_FloatU u;
1096 float32 tmp;
1097
1098 u.l = val;
1099 /* NaN are not treated the same way IEEE 754 does */
1100 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1101 return 0;
1102 }
1103 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1104 u.f = float32_mul(u.f, tmp, &env->vec_status);
1105
1106 return float32_to_uint32(u.f, &env->vec_status);
1107 }
1108
1109 #define HELPER_SPE_SINGLE_CONV(name) \
1110 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1111 { \
1112 return e##name(env, val); \
1113 }
1114 /* efscfsi */
1115 HELPER_SPE_SINGLE_CONV(fscfsi);
1116 /* efscfui */
1117 HELPER_SPE_SINGLE_CONV(fscfui);
1118 /* efscfuf */
1119 HELPER_SPE_SINGLE_CONV(fscfuf);
1120 /* efscfsf */
1121 HELPER_SPE_SINGLE_CONV(fscfsf);
1122 /* efsctsi */
1123 HELPER_SPE_SINGLE_CONV(fsctsi);
1124 /* efsctui */
1125 HELPER_SPE_SINGLE_CONV(fsctui);
1126 /* efsctsiz */
1127 HELPER_SPE_SINGLE_CONV(fsctsiz);
1128 /* efsctuiz */
1129 HELPER_SPE_SINGLE_CONV(fsctuiz);
1130 /* efsctsf */
1131 HELPER_SPE_SINGLE_CONV(fsctsf);
1132 /* efsctuf */
1133 HELPER_SPE_SINGLE_CONV(fsctuf);
1134
1135 #define HELPER_SPE_VECTOR_CONV(name) \
1136 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1137 { \
1138 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1139 (uint64_t)e##name(env, val); \
1140 }
1141 /* evfscfsi */
1142 HELPER_SPE_VECTOR_CONV(fscfsi);
1143 /* evfscfui */
1144 HELPER_SPE_VECTOR_CONV(fscfui);
1145 /* evfscfuf */
1146 HELPER_SPE_VECTOR_CONV(fscfuf);
1147 /* evfscfsf */
1148 HELPER_SPE_VECTOR_CONV(fscfsf);
1149 /* evfsctsi */
1150 HELPER_SPE_VECTOR_CONV(fsctsi);
1151 /* evfsctui */
1152 HELPER_SPE_VECTOR_CONV(fsctui);
1153 /* evfsctsiz */
1154 HELPER_SPE_VECTOR_CONV(fsctsiz);
1155 /* evfsctuiz */
1156 HELPER_SPE_VECTOR_CONV(fsctuiz);
1157 /* evfsctsf */
1158 HELPER_SPE_VECTOR_CONV(fsctsf);
1159 /* evfsctuf */
1160 HELPER_SPE_VECTOR_CONV(fsctuf);
1161
1162 /* Single-precision floating-point arithmetic */
1163 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1164 {
1165 CPU_FloatU u1, u2;
1166
1167 u1.l = op1;
1168 u2.l = op2;
1169 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1170 return u1.l;
1171 }
1172
1173 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1174 {
1175 CPU_FloatU u1, u2;
1176
1177 u1.l = op1;
1178 u2.l = op2;
1179 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1180 return u1.l;
1181 }
1182
1183 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1184 {
1185 CPU_FloatU u1, u2;
1186
1187 u1.l = op1;
1188 u2.l = op2;
1189 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1190 return u1.l;
1191 }
1192
1193 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1194 {
1195 CPU_FloatU u1, u2;
1196
1197 u1.l = op1;
1198 u2.l = op2;
1199 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1200 return u1.l;
1201 }
1202
1203 #define HELPER_SPE_SINGLE_ARITH(name) \
1204 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1205 { \
1206 return e##name(env, op1, op2); \
1207 }
1208 /* efsadd */
1209 HELPER_SPE_SINGLE_ARITH(fsadd);
1210 /* efssub */
1211 HELPER_SPE_SINGLE_ARITH(fssub);
1212 /* efsmul */
1213 HELPER_SPE_SINGLE_ARITH(fsmul);
1214 /* efsdiv */
1215 HELPER_SPE_SINGLE_ARITH(fsdiv);
1216
1217 #define HELPER_SPE_VECTOR_ARITH(name) \
1218 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1219 { \
1220 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1221 (uint64_t)e##name(env, op1, op2); \
1222 }
1223 /* evfsadd */
1224 HELPER_SPE_VECTOR_ARITH(fsadd);
1225 /* evfssub */
1226 HELPER_SPE_VECTOR_ARITH(fssub);
1227 /* evfsmul */
1228 HELPER_SPE_VECTOR_ARITH(fsmul);
1229 /* evfsdiv */
1230 HELPER_SPE_VECTOR_ARITH(fsdiv);
1231
1232 /* Single-precision floating-point comparisons */
1233 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1234 {
1235 CPU_FloatU u1, u2;
1236
1237 u1.l = op1;
1238 u2.l = op2;
1239 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1240 }
1241
1242 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1243 {
1244 CPU_FloatU u1, u2;
1245
1246 u1.l = op1;
1247 u2.l = op2;
1248 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1249 }
1250
1251 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1252 {
1253 CPU_FloatU u1, u2;
1254
1255 u1.l = op1;
1256 u2.l = op2;
1257 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1258 }
1259
1260 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1261 {
1262 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1263 return efscmplt(env, op1, op2);
1264 }
1265
1266 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1267 {
1268 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1269 return efscmpgt(env, op1, op2);
1270 }
1271
1272 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1273 {
1274 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1275 return efscmpeq(env, op1, op2);
1276 }
1277
1278 #define HELPER_SINGLE_SPE_CMP(name) \
1279 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1280 { \
1281 return e##name(env, op1, op2); \
1282 }
1283 /* efststlt */
1284 HELPER_SINGLE_SPE_CMP(fststlt);
1285 /* efststgt */
1286 HELPER_SINGLE_SPE_CMP(fststgt);
1287 /* efststeq */
1288 HELPER_SINGLE_SPE_CMP(fststeq);
1289 /* efscmplt */
1290 HELPER_SINGLE_SPE_CMP(fscmplt);
1291 /* efscmpgt */
1292 HELPER_SINGLE_SPE_CMP(fscmpgt);
1293 /* efscmpeq */
1294 HELPER_SINGLE_SPE_CMP(fscmpeq);
1295
1296 static inline uint32_t evcmp_merge(int t0, int t1)
1297 {
1298 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1299 }
1300
1301 #define HELPER_VECTOR_SPE_CMP(name) \
1302 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1303 { \
1304 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1305 e##name(env, op1, op2)); \
1306 }
1307 /* evfststlt */
1308 HELPER_VECTOR_SPE_CMP(fststlt);
1309 /* evfststgt */
1310 HELPER_VECTOR_SPE_CMP(fststgt);
1311 /* evfststeq */
1312 HELPER_VECTOR_SPE_CMP(fststeq);
1313 /* evfscmplt */
1314 HELPER_VECTOR_SPE_CMP(fscmplt);
1315 /* evfscmpgt */
1316 HELPER_VECTOR_SPE_CMP(fscmpgt);
1317 /* evfscmpeq */
1318 HELPER_VECTOR_SPE_CMP(fscmpeq);
1319
1320 /* Double-precision floating-point conversion */
1321 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1322 {
1323 CPU_DoubleU u;
1324
1325 u.d = int32_to_float64(val, &env->vec_status);
1326
1327 return u.ll;
1328 }
1329
1330 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1331 {
1332 CPU_DoubleU u;
1333
1334 u.d = int64_to_float64(val, &env->vec_status);
1335
1336 return u.ll;
1337 }
1338
1339 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1340 {
1341 CPU_DoubleU u;
1342
1343 u.d = uint32_to_float64(val, &env->vec_status);
1344
1345 return u.ll;
1346 }
1347
1348 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1349 {
1350 CPU_DoubleU u;
1351
1352 u.d = uint64_to_float64(val, &env->vec_status);
1353
1354 return u.ll;
1355 }
1356
1357 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1358 {
1359 CPU_DoubleU u;
1360
1361 u.ll = val;
1362 /* NaN are not treated the same way IEEE 754 does */
1363 if (unlikely(float64_is_any_nan(u.d))) {
1364 return 0;
1365 }
1366
1367 return float64_to_int32(u.d, &env->vec_status);
1368 }
1369
1370 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1371 {
1372 CPU_DoubleU u;
1373
1374 u.ll = val;
1375 /* NaN are not treated the same way IEEE 754 does */
1376 if (unlikely(float64_is_any_nan(u.d))) {
1377 return 0;
1378 }
1379
1380 return float64_to_uint32(u.d, &env->vec_status);
1381 }
1382
1383 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1384 {
1385 CPU_DoubleU u;
1386
1387 u.ll = val;
1388 /* NaN are not treated the same way IEEE 754 does */
1389 if (unlikely(float64_is_any_nan(u.d))) {
1390 return 0;
1391 }
1392
1393 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1394 }
1395
1396 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1397 {
1398 CPU_DoubleU u;
1399
1400 u.ll = val;
1401 /* NaN are not treated the same way IEEE 754 does */
1402 if (unlikely(float64_is_any_nan(u.d))) {
1403 return 0;
1404 }
1405
1406 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1407 }
1408
1409 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1410 {
1411 CPU_DoubleU u;
1412
1413 u.ll = val;
1414 /* NaN are not treated the same way IEEE 754 does */
1415 if (unlikely(float64_is_any_nan(u.d))) {
1416 return 0;
1417 }
1418
1419 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1420 }
1421
1422 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1423 {
1424 CPU_DoubleU u;
1425
1426 u.ll = val;
1427 /* NaN are not treated the same way IEEE 754 does */
1428 if (unlikely(float64_is_any_nan(u.d))) {
1429 return 0;
1430 }
1431
1432 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1433 }
1434
1435 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1436 {
1437 CPU_DoubleU u;
1438 float64 tmp;
1439
1440 u.d = int32_to_float64(val, &env->vec_status);
1441 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1442 u.d = float64_div(u.d, tmp, &env->vec_status);
1443
1444 return u.ll;
1445 }
1446
1447 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1448 {
1449 CPU_DoubleU u;
1450 float64 tmp;
1451
1452 u.d = uint32_to_float64(val, &env->vec_status);
1453 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1454 u.d = float64_div(u.d, tmp, &env->vec_status);
1455
1456 return u.ll;
1457 }
1458
1459 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1460 {
1461 CPU_DoubleU u;
1462 float64 tmp;
1463
1464 u.ll = val;
1465 /* NaN are not treated the same way IEEE 754 does */
1466 if (unlikely(float64_is_any_nan(u.d))) {
1467 return 0;
1468 }
1469 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1470 u.d = float64_mul(u.d, tmp, &env->vec_status);
1471
1472 return float64_to_int32(u.d, &env->vec_status);
1473 }
1474
1475 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1476 {
1477 CPU_DoubleU u;
1478 float64 tmp;
1479
1480 u.ll = val;
1481 /* NaN are not treated the same way IEEE 754 does */
1482 if (unlikely(float64_is_any_nan(u.d))) {
1483 return 0;
1484 }
1485 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1486 u.d = float64_mul(u.d, tmp, &env->vec_status);
1487
1488 return float64_to_uint32(u.d, &env->vec_status);
1489 }
1490
1491 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1492 {
1493 CPU_DoubleU u1;
1494 CPU_FloatU u2;
1495
1496 u1.ll = val;
1497 u2.f = float64_to_float32(u1.d, &env->vec_status);
1498
1499 return u2.l;
1500 }
1501
1502 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1503 {
1504 CPU_DoubleU u2;
1505 CPU_FloatU u1;
1506
1507 u1.l = val;
1508 u2.d = float32_to_float64(u1.f, &env->vec_status);
1509
1510 return u2.ll;
1511 }
1512
1513 /* Double precision fixed-point arithmetic */
1514 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1515 {
1516 CPU_DoubleU u1, u2;
1517
1518 u1.ll = op1;
1519 u2.ll = op2;
1520 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1521 return u1.ll;
1522 }
1523
1524 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1525 {
1526 CPU_DoubleU u1, u2;
1527
1528 u1.ll = op1;
1529 u2.ll = op2;
1530 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1531 return u1.ll;
1532 }
1533
1534 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1535 {
1536 CPU_DoubleU u1, u2;
1537
1538 u1.ll = op1;
1539 u2.ll = op2;
1540 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1541 return u1.ll;
1542 }
1543
1544 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1545 {
1546 CPU_DoubleU u1, u2;
1547
1548 u1.ll = op1;
1549 u2.ll = op2;
1550 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1551 return u1.ll;
1552 }
1553
1554 /* Double precision floating point helpers */
1555 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1556 {
1557 CPU_DoubleU u1, u2;
1558
1559 u1.ll = op1;
1560 u2.ll = op2;
1561 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1562 }
1563
1564 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1565 {
1566 CPU_DoubleU u1, u2;
1567
1568 u1.ll = op1;
1569 u2.ll = op2;
1570 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1571 }
1572
1573 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1574 {
1575 CPU_DoubleU u1, u2;
1576
1577 u1.ll = op1;
1578 u2.ll = op2;
1579 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1580 }
1581
1582 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1583 {
1584 /* XXX: TODO: test special values (NaN, infinites, ...) */
1585 return helper_efdtstlt(env, op1, op2);
1586 }
1587
1588 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1589 {
1590 /* XXX: TODO: test special values (NaN, infinites, ...) */
1591 return helper_efdtstgt(env, op1, op2);
1592 }
1593
1594 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1595 {
1596 /* XXX: TODO: test special values (NaN, infinites, ...) */
1597 return helper_efdtsteq(env, op1, op2);
1598 }
1599
1600 #define float64_to_float64(x, env) x
1601
1602
1603 /*
1604 * VSX_ADD_SUB - VSX floating point add/subtract
1605 * name - instruction mnemonic
1606 * op - operation (add or sub)
1607 * nels - number of elements (1, 2 or 4)
1608 * tp - type (float32 or float64)
1609 * fld - vsr_t field (VsrD(*) or VsrW(*))
1610 * sfprf - set FPRF
1611 */
1612 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1613 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1614 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1615 { \
1616 ppc_vsr_t t = *xt; \
1617 int i; \
1618 \
1619 helper_reset_fpstatus(env); \
1620 \
1621 for (i = 0; i < nels; i++) { \
1622 float_status tstat = env->fp_status; \
1623 set_float_exception_flags(0, &tstat); \
1624 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1625 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1626 \
1627 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1628 float_invalid_op_addsub(env, tstat.float_exception_flags, \
1629 sfprf, GETPC()); \
1630 } \
1631 \
1632 if (r2sp) { \
1633 t.fld = do_frsp(env, t.fld, GETPC()); \
1634 } \
1635 \
1636 if (sfprf) { \
1637 helper_compute_fprf_float64(env, t.fld); \
1638 } \
1639 } \
1640 *xt = t; \
1641 do_float_check_status(env, GETPC()); \
1642 }
1643
1644 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1645 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1646 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1647 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1648 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1649 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1650 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1651 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1652
1653 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
1654 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1655 {
1656 ppc_vsr_t t = *xt;
1657 float_status tstat;
1658
1659 helper_reset_fpstatus(env);
1660
1661 tstat = env->fp_status;
1662 if (unlikely(Rc(opcode) != 0)) {
1663 tstat.float_rounding_mode = float_round_to_odd;
1664 }
1665
1666 set_float_exception_flags(0, &tstat);
1667 t.f128 = float128_add(xa->f128, xb->f128, &tstat);
1668 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1669
1670 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1671 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
1672 }
1673
1674 helper_compute_fprf_float128(env, t.f128);
1675
1676 *xt = t;
1677 do_float_check_status(env, GETPC());
1678 }
1679
1680 /*
1681 * VSX_MUL - VSX floating point multiply
1682 * op - instruction mnemonic
1683 * nels - number of elements (1, 2 or 4)
1684 * tp - type (float32 or float64)
1685 * fld - vsr_t field (VsrD(*) or VsrW(*))
1686 * sfprf - set FPRF
1687 */
1688 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1689 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1690 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1691 { \
1692 ppc_vsr_t t = *xt; \
1693 int i; \
1694 \
1695 helper_reset_fpstatus(env); \
1696 \
1697 for (i = 0; i < nels; i++) { \
1698 float_status tstat = env->fp_status; \
1699 set_float_exception_flags(0, &tstat); \
1700 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1701 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1702 \
1703 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1704 float_invalid_op_mul(env, tstat.float_exception_flags, \
1705 sfprf, GETPC()); \
1706 } \
1707 \
1708 if (r2sp) { \
1709 t.fld = do_frsp(env, t.fld, GETPC()); \
1710 } \
1711 \
1712 if (sfprf) { \
1713 helper_compute_fprf_float64(env, t.fld); \
1714 } \
1715 } \
1716 \
1717 *xt = t; \
1718 do_float_check_status(env, GETPC()); \
1719 }
1720
1721 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1722 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1723 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1724 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1725
1726 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
1727 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1728 {
1729 ppc_vsr_t t = *xt;
1730 float_status tstat;
1731
1732 helper_reset_fpstatus(env);
1733 tstat = env->fp_status;
1734 if (unlikely(Rc(opcode) != 0)) {
1735 tstat.float_rounding_mode = float_round_to_odd;
1736 }
1737
1738 set_float_exception_flags(0, &tstat);
1739 t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
1740 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1741
1742 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1743 float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
1744 }
1745 helper_compute_fprf_float128(env, t.f128);
1746
1747 *xt = t;
1748 do_float_check_status(env, GETPC());
1749 }
1750
1751 /*
1752 * VSX_DIV - VSX floating point divide
1753 * op - instruction mnemonic
1754 * nels - number of elements (1, 2 or 4)
1755 * tp - type (float32 or float64)
1756 * fld - vsr_t field (VsrD(*) or VsrW(*))
1757 * sfprf - set FPRF
1758 */
1759 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1760 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1761 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1762 { \
1763 ppc_vsr_t t = *xt; \
1764 int i; \
1765 \
1766 helper_reset_fpstatus(env); \
1767 \
1768 for (i = 0; i < nels; i++) { \
1769 float_status tstat = env->fp_status; \
1770 set_float_exception_flags(0, &tstat); \
1771 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1772 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1773 \
1774 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1775 float_invalid_op_div(env, tstat.float_exception_flags, \
1776 sfprf, GETPC()); \
1777 } \
1778 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1779 float_zero_divide_excp(env, GETPC()); \
1780 } \
1781 \
1782 if (r2sp) { \
1783 t.fld = do_frsp(env, t.fld, GETPC()); \
1784 } \
1785 \
1786 if (sfprf) { \
1787 helper_compute_fprf_float64(env, t.fld); \
1788 } \
1789 } \
1790 \
1791 *xt = t; \
1792 do_float_check_status(env, GETPC()); \
1793 }
1794
1795 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1796 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1797 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1798 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1799
1800 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
1801 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1802 {
1803 ppc_vsr_t t = *xt;
1804 float_status tstat;
1805
1806 helper_reset_fpstatus(env);
1807 tstat = env->fp_status;
1808 if (unlikely(Rc(opcode) != 0)) {
1809 tstat.float_rounding_mode = float_round_to_odd;
1810 }
1811
1812 set_float_exception_flags(0, &tstat);
1813 t.f128 = float128_div(xa->f128, xb->f128, &tstat);
1814 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1815
1816 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1817 float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
1818 }
1819 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
1820 float_zero_divide_excp(env, GETPC());
1821 }
1822
1823 helper_compute_fprf_float128(env, t.f128);
1824 *xt = t;
1825 do_float_check_status(env, GETPC());
1826 }
1827
1828 /*
1829 * VSX_RE - VSX floating point reciprocal estimate
1830 * op - instruction mnemonic
1831 * nels - number of elements (1, 2 or 4)
1832 * tp - type (float32 or float64)
1833 * fld - vsr_t field (VsrD(*) or VsrW(*))
1834 * sfprf - set FPRF
1835 */
1836 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
1837 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1838 { \
1839 ppc_vsr_t t = *xt; \
1840 int i; \
1841 \
1842 helper_reset_fpstatus(env); \
1843 \
1844 for (i = 0; i < nels; i++) { \
1845 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
1846 float_invalid_op_vxsnan(env, GETPC()); \
1847 } \
1848 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
1849 \
1850 if (r2sp) { \
1851 t.fld = do_frsp(env, t.fld, GETPC()); \
1852 } \
1853 \
1854 if (sfprf) { \
1855 helper_compute_fprf_float64(env, t.fld); \
1856 } \
1857 } \
1858 \
1859 *xt = t; \
1860 do_float_check_status(env, GETPC()); \
1861 }
1862
1863 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1864 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1865 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1866 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
1867
1868 /*
1869 * VSX_SQRT - VSX floating point square root
1870 * op - instruction mnemonic
1871 * nels - number of elements (1, 2 or 4)
1872 * tp - type (float32 or float64)
1873 * fld - vsr_t field (VsrD(*) or VsrW(*))
1874 * sfprf - set FPRF
1875 */
1876 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
1877 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1878 { \
1879 ppc_vsr_t t = *xt; \
1880 int i; \
1881 \
1882 helper_reset_fpstatus(env); \
1883 \
1884 for (i = 0; i < nels; i++) { \
1885 float_status tstat = env->fp_status; \
1886 set_float_exception_flags(0, &tstat); \
1887 t.fld = tp##_sqrt(xb->fld, &tstat); \
1888 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1889 \
1890 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1891 float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1892 sfprf, GETPC()); \
1893 } \
1894 \
1895 if (r2sp) { \
1896 t.fld = do_frsp(env, t.fld, GETPC()); \
1897 } \
1898 \
1899 if (sfprf) { \
1900 helper_compute_fprf_float64(env, t.fld); \
1901 } \
1902 } \
1903 \
1904 *xt = t; \
1905 do_float_check_status(env, GETPC()); \
1906 }
1907
1908 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
1909 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
1910 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
1911 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
1912
1913 /*
1914 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
1915 * op - instruction mnemonic
1916 * nels - number of elements (1, 2 or 4)
1917 * tp - type (float32 or float64)
1918 * fld - vsr_t field (VsrD(*) or VsrW(*))
1919 * sfprf - set FPRF
1920 */
1921 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
1922 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1923 { \
1924 ppc_vsr_t t = *xt; \
1925 int i; \
1926 \
1927 helper_reset_fpstatus(env); \
1928 \
1929 for (i = 0; i < nels; i++) { \
1930 float_status tstat = env->fp_status; \
1931 set_float_exception_flags(0, &tstat); \
1932 t.fld = tp##_sqrt(xb->fld, &tstat); \
1933 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
1934 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1935 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1936 float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1937 sfprf, GETPC()); \
1938 } \
1939 if (r2sp) { \
1940 t.fld = do_frsp(env, t.fld, GETPC()); \
1941 } \
1942 \
1943 if (sfprf) { \
1944 helper_compute_fprf_float64(env, t.fld); \
1945 } \
1946 } \
1947 \
1948 *xt = t; \
1949 do_float_check_status(env, GETPC()); \
1950 }
1951
1952 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
1953 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
1954 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
1955 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
1956
1957 /*
1958 * VSX_TDIV - VSX floating point test for divide
1959 * op - instruction mnemonic
1960 * nels - number of elements (1, 2 or 4)
1961 * tp - type (float32 or float64)
1962 * fld - vsr_t field (VsrD(*) or VsrW(*))
1963 * emin - minimum unbiased exponent
1964 * emax - maximum unbiased exponent
1965 * nbits - number of fraction bits
1966 */
1967 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
1968 void helper_##op(CPUPPCState *env, uint32_t opcode, \
1969 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1970 { \
1971 int i; \
1972 int fe_flag = 0; \
1973 int fg_flag = 0; \
1974 \
1975 for (i = 0; i < nels; i++) { \
1976 if (unlikely(tp##_is_infinity(xa->fld) || \
1977 tp##_is_infinity(xb->fld) || \
1978 tp##_is_zero(xb->fld))) { \
1979 fe_flag = 1; \
1980 fg_flag = 1; \
1981 } else { \
1982 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
1983 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
1984 \
1985 if (unlikely(tp##_is_any_nan(xa->fld) || \
1986 tp##_is_any_nan(xb->fld))) { \
1987 fe_flag = 1; \
1988 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
1989 fe_flag = 1; \
1990 } else if (!tp##_is_zero(xa->fld) && \
1991 (((e_a - e_b) >= emax) || \
1992 ((e_a - e_b) <= (emin + 1)) || \
1993 (e_a <= (emin + nbits)))) { \
1994 fe_flag = 1; \
1995 } \
1996 \
1997 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
1998 /* \
1999 * XB is not zero because of the above check and so \
2000 * must be denormalized. \
2001 */ \
2002 fg_flag = 1; \
2003 } \
2004 } \
2005 } \
2006 \
2007 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2008 }
2009
2010 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2011 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2012 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2013
2014 /*
2015 * VSX_TSQRT - VSX floating point test for square root
2016 * op - instruction mnemonic
2017 * nels - number of elements (1, 2 or 4)
2018 * tp - type (float32 or float64)
2019 * fld - vsr_t field (VsrD(*) or VsrW(*))
2020 * emin - minimum unbiased exponent
2021 * emax - maximum unbiased exponent
2022 * nbits - number of fraction bits
2023 */
2024 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2025 void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
2026 { \
2027 int i; \
2028 int fe_flag = 0; \
2029 int fg_flag = 0; \
2030 \
2031 for (i = 0; i < nels; i++) { \
2032 if (unlikely(tp##_is_infinity(xb->fld) || \
2033 tp##_is_zero(xb->fld))) { \
2034 fe_flag = 1; \
2035 fg_flag = 1; \
2036 } else { \
2037 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2038 \
2039 if (unlikely(tp##_is_any_nan(xb->fld))) { \
2040 fe_flag = 1; \
2041 } else if (unlikely(tp##_is_zero(xb->fld))) { \
2042 fe_flag = 1; \
2043 } else if (unlikely(tp##_is_neg(xb->fld))) { \
2044 fe_flag = 1; \
2045 } else if (!tp##_is_zero(xb->fld) && \
2046 (e_b <= (emin + nbits))) { \
2047 fe_flag = 1; \
2048 } \
2049 \
2050 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2051 /* \
2052 * XB is not zero because of the above check and \
2053 * therefore must be denormalized. \
2054 */ \
2055 fg_flag = 1; \
2056 } \
2057 } \
2058 } \
2059 \
2060 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2061 }
2062
2063 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2064 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2065 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2066
2067 /*
2068 * VSX_MADD - VSX floating point muliply/add variations
2069 * op - instruction mnemonic
2070 * nels - number of elements (1, 2 or 4)
2071 * tp - type (float32 or float64)
2072 * fld - vsr_t field (VsrD(*) or VsrW(*))
2073 * maddflgs - flags for the float*muladd routine that control the
2074 * various forms (madd, msub, nmadd, nmsub)
2075 * sfprf - set FPRF
2076 */
2077 #define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
2078 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2079 ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
2080 { \
2081 ppc_vsr_t t = *xt; \
2082 int i; \
2083 \
2084 helper_reset_fpstatus(env); \
2085 \
2086 for (i = 0; i < nels; i++) { \
2087 float_status tstat = env->fp_status; \
2088 set_float_exception_flags(0, &tstat); \
2089 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2090 /* \
2091 * Avoid double rounding errors by rounding the intermediate \
2092 * result to odd. \
2093 */ \
2094 set_float_rounding_mode(float_round_to_zero, &tstat); \
2095 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2096 maddflgs, &tstat); \
2097 t.fld |= (get_float_exception_flags(&tstat) & \
2098 float_flag_inexact) != 0; \
2099 } else { \
2100 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2101 maddflgs, &tstat); \
2102 } \
2103 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2104 \
2105 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2106 float_invalid_op_madd(env, tstat.float_exception_flags, \
2107 sfprf, GETPC()); \
2108 } \
2109 \
2110 if (r2sp) { \
2111 t.fld = do_frsp(env, t.fld, GETPC()); \
2112 } \
2113 \
2114 if (sfprf) { \
2115 helper_compute_fprf_float64(env, t.fld); \
2116 } \
2117 } \
2118 *xt = t; \
2119 do_float_check_status(env, GETPC()); \
2120 }
2121
2122 VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
2123 VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
2124 VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
2125 VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
2126 VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
2127 VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
2128 VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
2129 VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
2130
2131 VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
2132 VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
2133 VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0)
2134 VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0)
2135
2136 VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0)
2137 VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
2138 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
2139 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
2140
2141 /*
2142 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2143 * op - instruction mnemonic
2144 * cmp - comparison operation
2145 * exp - expected result of comparison
2146 * svxvc - set VXVC bit
2147 */
2148 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2149 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2150 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2151 { \
2152 ppc_vsr_t t = *xt; \
2153 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2154 \
2155 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2156 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2157 vxsnan_flag = true; \
2158 if (fpscr_ve == 0 && svxvc) { \
2159 vxvc_flag = true; \
2160 } \
2161 } else if (svxvc) { \
2162 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2163 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
2164 } \
2165 if (vxsnan_flag) { \
2166 float_invalid_op_vxsnan(env, GETPC()); \
2167 } \
2168 if (vxvc_flag) { \
2169 float_invalid_op_vxvc(env, 0, GETPC()); \
2170 } \
2171 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2172 \
2173 if (!vex_flag) { \
2174 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2175 &env->fp_status) == exp) { \
2176 t.VsrD(0) = -1; \
2177 t.VsrD(1) = 0; \
2178 } else { \
2179 t.VsrD(0) = 0; \
2180 t.VsrD(1) = 0; \
2181 } \
2182 } \
2183 *xt = t; \
2184 do_float_check_status(env, GETPC()); \
2185 }
2186
2187 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2188 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2189 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2190 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2191
2192 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2193 ppc_vsr_t *xa, ppc_vsr_t *xb)
2194 {
2195 int64_t exp_a, exp_b;
2196 uint32_t cc;
2197
2198 exp_a = extract64(xa->VsrD(0), 52, 11);
2199 exp_b = extract64(xb->VsrD(0), 52, 11);
2200
2201 if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2202 float64_is_any_nan(xb->VsrD(0)))) {
2203 cc = CRF_SO;
2204 } else {
2205 if (exp_a < exp_b) {
2206 cc = CRF_LT;
2207 } else if (exp_a > exp_b) {
2208 cc = CRF_GT;
2209 } else {
2210 cc = CRF_EQ;
2211 }
2212 }
2213
2214 env->fpscr &= ~FP_FPCC;
2215 env->fpscr |= cc << FPSCR_FPCC;
2216 env->crf[BF(opcode)] = cc;
2217
2218 do_float_check_status(env, GETPC());
2219 }
2220
2221 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
2222 ppc_vsr_t *xa, ppc_vsr_t *xb)
2223 {
2224 int64_t exp_a, exp_b;
2225 uint32_t cc;
2226
2227 exp_a = extract64(xa->VsrD(0), 48, 15);
2228 exp_b = extract64(xb->VsrD(0), 48, 15);
2229
2230 if (unlikely(float128_is_any_nan(xa->f128) ||
2231 float128_is_any_nan(xb->f128))) {
2232 cc = CRF_SO;
2233 } else {
2234 if (exp_a < exp_b) {
2235 cc = CRF_LT;
2236 } else if (exp_a > exp_b) {
2237 cc = CRF_GT;
2238 } else {
2239 cc = CRF_EQ;
2240 }
2241 }
2242
2243 env->fpscr &= ~FP_FPCC;
2244 env->fpscr |= cc << FPSCR_FPCC;
2245 env->crf[BF(opcode)] = cc;
2246
2247 do_float_check_status(env, GETPC());
2248 }
2249
2250 static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
2251 int crf_idx, bool ordered)
2252 {
2253 uint32_t cc;
2254 bool vxsnan_flag = false, vxvc_flag = false;
2255
2256 helper_reset_fpstatus(env);
2257
2258 switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {
2259 case float_relation_less:
2260 cc = CRF_LT;
2261 break;
2262 case float_relation_equal:
2263 cc = CRF_EQ;
2264 break;
2265 case float_relation_greater:
2266 cc = CRF_GT;
2267 break;
2268 case float_relation_unordered:
2269 cc = CRF_SO;
2270
2271 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
2272 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
2273 vxsnan_flag = true;
2274 if (fpscr_ve == 0 && ordered) {
2275 vxvc_flag = true;
2276 }
2277 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
2278 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) {
2279 if (ordered) {
2280 vxvc_flag = true;
2281 }
2282 }
2283
2284 break;
2285 default:
2286 g_assert_not_reached();
2287 }
2288
2289 env->fpscr &= ~FP_FPCC;
2290 env->fpscr |= cc << FPSCR_FPCC;
2291 env->crf[crf_idx] = cc;
2292
2293 if (vxsnan_flag) {
2294 float_invalid_op_vxsnan(env, GETPC());
2295 }
2296 if (vxvc_flag) {
2297 float_invalid_op_vxvc(env, 0, GETPC());
2298 }
2299
2300 do_float_check_status(env, GETPC());
2301 }
2302
2303 void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2304 ppc_vsr_t *xb)
2305 {
2306 do_scalar_cmp(env, xa, xb, BF(opcode), true);
2307 }
2308
2309 void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2310 ppc_vsr_t *xb)
2311 {
2312 do_scalar_cmp(env, xa, xb, BF(opcode), false);
2313 }
2314
2315 static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
2316 ppc_vsr_t *xb, int crf_idx, bool ordered)
2317 {
2318 uint32_t cc;
2319 bool vxsnan_flag = false, vxvc_flag = false;
2320
2321 helper_reset_fpstatus(env);
2322
2323 switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) {
2324 case float_relation_less:
2325 cc = CRF_LT;
2326 break;
2327 case float_relation_equal:
2328 cc = CRF_EQ;
2329 break;
2330 case float_relation_greater:
2331 cc = CRF_GT;
2332 break;
2333 case float_relation_unordered:
2334 cc = CRF_SO;
2335
2336 if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
2337 float128_is_signaling_nan(xb->f128, &env->fp_status)) {
2338 vxsnan_flag = true;
2339 if (fpscr_ve == 0 && ordered) {
2340 vxvc_flag = true;
2341 }
2342 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
2343 float128_is_quiet_nan(xb->f128, &env->fp_status)) {
2344 if (ordered) {
2345 vxvc_flag = true;
2346 }
2347 }
2348
2349 break;
2350 default:
2351 g_assert_not_reached();
2352 }
2353
2354 env->fpscr &= ~FP_FPCC;
2355 env->fpscr |= cc << FPSCR_FPCC;
2356 env->crf[crf_idx] = cc;
2357
2358 if (vxsnan_flag) {
2359 float_invalid_op_vxsnan(env, GETPC());
2360 }
2361 if (vxvc_flag) {
2362 float_invalid_op_vxvc(env, 0, GETPC());
2363 }
2364
2365 do_float_check_status(env, GETPC());
2366 }
2367
2368 void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2369 ppc_vsr_t *xb)
2370 {
2371 do_scalar_cmpq(env, xa, xb, BF(opcode), true);
2372 }
2373
2374 void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2375 ppc_vsr_t *xb)
2376 {
2377 do_scalar_cmpq(env, xa, xb, BF(opcode), false);
2378 }
2379
2380 /*
2381 * VSX_MAX_MIN - VSX floating point maximum/minimum
2382 * name - instruction mnemonic
2383 * op - operation (max or min)
2384 * nels - number of elements (1, 2 or 4)
2385 * tp - type (float32 or float64)
2386 * fld - vsr_t field (VsrD(*) or VsrW(*))
2387 */
2388 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2389 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2390 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2391 { \
2392 ppc_vsr_t t = *xt; \
2393 int i; \
2394 \
2395 for (i = 0; i < nels; i++) { \
2396 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2397 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2398 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2399 float_invalid_op_vxsnan(env, GETPC()); \
2400 } \
2401 } \
2402 \
2403 *xt = t; \
2404 do_float_check_status(env, GETPC()); \
2405 }
2406
2407 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2408 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2409 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2410 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2411 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2412 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2413
2414 #define VSX_MAX_MINC(name, max) \
2415 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2416 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2417 { \
2418 ppc_vsr_t t = *xt; \
2419 bool vxsnan_flag = false, vex_flag = false; \
2420 \
2421 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2422 float64_is_any_nan(xb->VsrD(0)))) { \
2423 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2424 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2425 vxsnan_flag = true; \
2426 } \
2427 t.VsrD(0) = xb->VsrD(0); \
2428 } else if ((max && \
2429 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2430 (!max && \
2431 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2432 t.VsrD(0) = xa->VsrD(0); \
2433 } else { \
2434 t.VsrD(0) = xb->VsrD(0); \
2435 } \
2436 \
2437 vex_flag = fpscr_ve & vxsnan_flag; \
2438 if (vxsnan_flag) { \
2439 float_invalid_op_vxsnan(env, GETPC()); \
2440 } \
2441 if (!vex_flag) { \
2442 *xt = t; \
2443 } \
2444 } \
2445
2446 VSX_MAX_MINC(xsmaxcdp, 1);
2447 VSX_MAX_MINC(xsmincdp, 0);
2448
2449 #define VSX_MAX_MINJ(name, max) \
2450 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2451 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2452 { \
2453 ppc_vsr_t t = *xt; \
2454 bool vxsnan_flag = false, vex_flag = false; \
2455 \
2456 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2457 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2458 vxsnan_flag = true; \
2459 } \
2460 t.VsrD(0) = xa->VsrD(0); \
2461 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2462 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2463 vxsnan_flag = true; \
2464 } \
2465 t.VsrD(0) = xb->VsrD(0); \
2466 } else if (float64_is_zero(xa->VsrD(0)) && \
2467 float64_is_zero(xb->VsrD(0))) { \
2468 if (max) { \
2469 if (!float64_is_neg(xa->VsrD(0)) || \
2470 !float64_is_neg(xb->VsrD(0))) { \
2471 t.VsrD(0) = 0ULL; \
2472 } else { \
2473 t.VsrD(0) = 0x8000000000000000ULL; \
2474 } \
2475 } else { \
2476 if (float64_is_neg(xa->VsrD(0)) || \
2477 float64_is_neg(xb->VsrD(0))) { \
2478 t.VsrD(0) = 0x8000000000000000ULL; \
2479 } else { \
2480 t.VsrD(0) = 0ULL; \
2481 } \
2482 } \
2483 } else if ((max && \
2484 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2485 (!max && \
2486 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2487 t.VsrD(0) = xa->VsrD(0); \
2488 } else { \
2489 t.VsrD(0) = xb->VsrD(0); \
2490 } \
2491 \
2492 vex_flag = fpscr_ve & vxsnan_flag; \
2493 if (vxsnan_flag) { \
2494 float_invalid_op_vxsnan(env, GETPC()); \
2495 } \
2496 if (!vex_flag) { \
2497 *xt = t; \
2498 } \
2499 } \
2500
2501 VSX_MAX_MINJ(xsmaxjdp, 1);
2502 VSX_MAX_MINJ(xsminjdp, 0);
2503
2504 /*
2505 * VSX_CMP - VSX floating point compare
2506 * op - instruction mnemonic
2507 * nels - number of elements (1, 2 or 4)
2508 * tp - type (float32 or float64)
2509 * fld - vsr_t field (VsrD(*) or VsrW(*))
2510 * cmp - comparison operation
2511 * svxvc - set VXVC bit
2512 * exp - expected result of comparison
2513 */
2514 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2515 uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2516 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2517 { \
2518 ppc_vsr_t t = *xt; \
2519 uint32_t crf6 = 0; \
2520 int i; \
2521 int all_true = 1; \
2522 int all_false = 1; \
2523 \
2524 for (i = 0; i < nels; i++) { \
2525 if (unlikely(tp##_is_any_nan(xa->fld) || \
2526 tp##_is_any_nan(xb->fld))) { \
2527 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2528 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
2529 float_invalid_op_vxsnan(env, GETPC()); \
2530 } \
2531 if (svxvc) { \
2532 float_invalid_op_vxvc(env, 0, GETPC()); \
2533 } \
2534 t.fld = 0; \
2535 all_true = 0; \
2536 } else { \
2537 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2538 t.fld = -1; \
2539 all_false = 0; \
2540 } else { \
2541 t.fld = 0; \
2542 all_true = 0; \
2543 } \
2544 } \
2545 } \
2546 \
2547 *xt = t; \
2548 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2549 return crf6; \
2550 }
2551
2552 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2553 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2554 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2555 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2556 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2557 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2558 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2559 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2560
2561 /*
2562 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2563 * op - instruction mnemonic
2564 * nels - number of elements (1, 2 or 4)
2565 * stp - source type (float32 or float64)
2566 * ttp - target type (float32 or float64)
2567 * sfld - source vsr_t field
2568 * tfld - target vsr_t field (f32 or f64)
2569 * sfprf - set FPRF
2570 */
2571 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2572 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2573 { \
2574 ppc_vsr_t t = *xt; \
2575 int i; \
2576 \
2577 for (i = 0; i < nels; i++) { \
2578 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2579 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2580 &env->fp_status))) { \
2581 float_invalid_op_vxsnan(env, GETPC()); \
2582 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2583 } \
2584 if (sfprf) { \
2585 helper_compute_fprf_##ttp(env, t.tfld); \
2586 } \
2587 } \
2588 \
2589 *xt = t; \
2590 do_float_check_status(env, GETPC()); \
2591 }
2592
2593 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2594 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2595 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
2596 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
2597
2598 /*
2599 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2600 * op - instruction mnemonic
2601 * nels - number of elements (1, 2 or 4)
2602 * stp - source type (float32 or float64)
2603 * ttp - target type (float32 or float64)
2604 * sfld - source vsr_t field
2605 * tfld - target vsr_t field (f32 or f64)
2606 * sfprf - set FPRF
2607 */
2608 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2609 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2610 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2611 { \
2612 ppc_vsr_t t = *xt; \
2613 int i; \
2614 \
2615 for (i = 0; i < nels; i++) { \
2616 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2617 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2618 &env->fp_status))) { \
2619 float_invalid_op_vxsnan(env, GETPC()); \
2620 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2621 } \
2622 if (sfprf) { \
2623 helper_compute_fprf_##ttp(env, t.tfld); \
2624 } \
2625 } \
2626 \
2627 *xt = t; \
2628 do_float_check_status(env, GETPC()); \
2629 }
2630
2631 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2632
2633 /*
2634 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2635 * involving one half precision value
2636 * op - instruction mnemonic
2637 * nels - number of elements (1, 2 or 4)
2638 * stp - source type
2639 * ttp - target type
2640 * sfld - source vsr_t field
2641 * tfld - target vsr_t field
2642 * sfprf - set FPRF
2643 */
2644 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2645 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2646 { \
2647 ppc_vsr_t t = { }; \
2648 int i; \
2649 \
2650 for (i = 0; i < nels; i++) { \
2651 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2652 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2653 &env->fp_status))) { \
2654 float_invalid_op_vxsnan(env, GETPC()); \
2655 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2656 } \
2657 if (sfprf) { \
2658 helper_compute_fprf_##ttp(env, t.tfld); \
2659 } \
2660 } \
2661 \
2662 *xt = t; \
2663 do_float_check_status(env, GETPC()); \
2664 }
2665
2666 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2667 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2668 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2669 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2670
2671 /*
2672 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2673 * added to this later.
2674 */
2675 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
2676 ppc_vsr_t *xt, ppc_vsr_t *xb)
2677 {
2678 ppc_vsr_t t = { };
2679 float_status tstat;
2680
2681 tstat = env->fp_status;
2682 if (unlikely(Rc(opcode) != 0)) {
2683 tstat.float_rounding_mode = float_round_to_odd;
2684 }
2685
2686 t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
2687 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2688 if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
2689 float_invalid_op_vxsnan(env, GETPC());
2690 t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
2691 }
2692 helper_compute_fprf_float64(env, t.VsrD(0));
2693
2694 *xt = t;
2695 do_float_check_status(env, GETPC());
2696 }
2697
2698 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2699 {
2700 uint64_t result, sign, exp, frac;
2701
2702 float_status tstat = env->fp_status;
2703 set_float_exception_flags(0, &tstat);
2704
2705 sign = extract64(xb, 63, 1);
2706 exp = extract64(xb, 52, 11);
2707 frac = extract64(xb, 0, 52) | 0x10000000000000ULL;
2708
2709 if (unlikely(exp == 0 && extract64(frac, 0, 52) != 0)) {
2710 /* DP denormal operand. */
2711 /* Exponent override to DP min exp. */
2712 exp = 1;
2713 /* Implicit bit override to 0. */
2714 frac = deposit64(frac, 53, 1, 0);
2715 }
2716
2717 if (unlikely(exp < 897 && frac != 0)) {
2718 /* SP tiny operand. */
2719 if (897 - exp > 63) {
2720 frac = 0;
2721 } else {
2722 /* Denormalize until exp = SP min exp. */
2723 frac >>= (897 - exp);
2724 }
2725 /* Exponent override to SP min exp - 1. */
2726 exp = 896;
2727 }
2728
2729 result = sign << 31;
2730 result |= extract64(exp, 10, 1) << 30;
2731 result |= extract64(exp, 0, 7) << 23;
2732 result |= extract64(frac, 29, 23);
2733
2734 /* hardware replicates result to both words of the doubleword result. */
2735 return (result << 32) | result;
2736 }
2737
2738 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2739 {
2740 float_status tstat = env->fp_status;
2741 set_float_exception_flags(0, &tstat);
2742
2743 return float32_to_float64(xb >> 32, &tstat);
2744 }
2745
2746 /*
2747 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2748 * op - instruction mnemonic
2749 * nels - number of elements (1, 2 or 4)
2750 * stp - source type (float32 or float64)
2751 * ttp - target type (int32, uint32, int64 or uint64)
2752 * sfld - source vsr_t field
2753 * tfld - target vsr_t field
2754 * rnan - resulting NaN
2755 */
2756 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2757 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2758 { \
2759 int all_flags = env->fp_status.float_exception_flags, flags; \
2760 ppc_vsr_t t = *xt; \
2761 int i; \
2762 \
2763 for (i = 0; i < nels; i++) { \
2764 env->fp_status.float_exception_flags = 0; \
2765 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2766 flags = env->fp_status.float_exception_flags; \
2767 if (unlikely(flags & float_flag_invalid)) { \
2768 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
2769 } \
2770 all_flags |= flags; \
2771 } \
2772 \
2773 *xt = t; \
2774 env->fp_status.float_exception_flags = all_flags; \
2775 do_float_check_status(env, GETPC()); \
2776 }
2777
2778 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2779 0x8000000000000000ULL)
2780 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2781 0x80000000U)
2782 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2783 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2784 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2785 0x8000000000000000ULL)
2786 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
2787 0x80000000U)
2788 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2789 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
2790 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
2791 0x8000000000000000ULL)
2792 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2793 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
2794 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2795
2796 /*
2797 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2798 * op - instruction mnemonic
2799 * stp - source type (float32 or float64)
2800 * ttp - target type (int32, uint32, int64 or uint64)
2801 * sfld - source vsr_t field
2802 * tfld - target vsr_t field
2803 * rnan - resulting NaN
2804 */
2805 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
2806 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2807 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2808 { \
2809 ppc_vsr_t t = { }; \
2810 int flags; \
2811 \
2812 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2813 flags = get_float_exception_flags(&env->fp_status); \
2814 if (flags & float_flag_invalid) { \
2815 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
2816 } \
2817 \
2818 *xt = t; \
2819 do_float_check_status(env, GETPC()); \
2820 }
2821
2822 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2823 0x8000000000000000ULL)
2824
2825 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
2826 0xffffffff80000000ULL)
2827 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2828 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
2829
2830 /*
2831 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2832 * op - instruction mnemonic
2833 * nels - number of elements (1, 2 or 4)
2834 * stp - source type (int32, uint32, int64 or uint64)
2835 * ttp - target type (float32 or float64)
2836 * sfld - source vsr_t field
2837 * tfld - target vsr_t field
2838 * jdef - definition of the j index (i or 2*i)
2839 * sfprf - set FPRF
2840 */
2841 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
2842 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2843 { \
2844 ppc_vsr_t t = *xt; \
2845 int i; \
2846 \
2847 for (i = 0; i < nels; i++) { \
2848 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2849 if (r2sp) { \
2850 t.tfld = do_frsp(env, t.tfld, GETPC()); \
2851 } \
2852 if (sfprf) { \
2853 helper_compute_fprf_float64(env, t.tfld); \
2854 } \
2855 } \
2856 \
2857 *xt = t; \
2858 do_float_check_status(env, GETPC()); \
2859 }
2860
2861 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2862 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2863 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2864 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2865 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2866 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2867 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
2868 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
2869 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2870 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2871 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2872 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2873
2874 /*
2875 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
2876 * op - instruction mnemonic
2877 * stp - source type (int32, uint32, int64 or uint64)
2878 * ttp - target type (float32 or float64)
2879 * sfld - source vsr_t field
2880 * tfld - target vsr_t field
2881 */
2882 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
2883 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2884 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2885 { \
2886 ppc_vsr_t t = *xt; \
2887 \
2888 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2889 helper_compute_fprf_##ttp(env, t.tfld); \
2890 \
2891 *xt = t; \
2892 do_float_check_status(env, GETPC()); \
2893 }
2894
2895 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
2896 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
2897
2898 /*
2899 * For "use current rounding mode", define a value that will not be
2900 * one of the existing rounding model enums.
2901 */
2902 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2903 float_round_up + float_round_to_zero)
2904
2905 /*
2906 * VSX_ROUND - VSX floating point round
2907 * op - instruction mnemonic
2908 * nels - number of elements (1, 2 or 4)
2909 * tp - type (float32 or float64)
2910 * fld - vsr_t field (VsrD(*) or VsrW(*))
2911 * rmode - rounding mode
2912 * sfprf - set FPRF
2913 */
2914 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2915 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2916 { \
2917 ppc_vsr_t t = *xt; \
2918 int i; \
2919 FloatRoundMode curr_rounding_mode; \
2920 \
2921 if (rmode != FLOAT_ROUND_CURRENT) { \
2922 curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
2923 set_float_rounding_mode(rmode, &env->fp_status); \
2924 } \
2925 \
2926 for (i = 0; i < nels; i++) { \
2927 if (unlikely(tp##_is_signaling_nan(xb->fld, \
2928 &env->fp_status))) { \
2929 float_invalid_op_vxsnan(env, GETPC()); \
2930 t.fld = tp##_snan_to_qnan(xb->fld); \
2931 } else { \
2932 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
2933 } \
2934 if (sfprf) { \
2935 helper_compute_fprf_float64(env, t.fld); \
2936 } \
2937 } \
2938 \
2939 /* \
2940 * If this is not a "use current rounding mode" instruction, \
2941 * then inhibit setting of the XX bit and restore rounding \
2942 * mode from FPSCR \
2943 */ \
2944 if (rmode != FLOAT_ROUND_CURRENT) { \
2945 set_float_rounding_mode(curr_rounding_mode, &env->fp_status); \
2946 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2947 } \
2948 \
2949 *xt = t; \
2950 do_float_check_status(env, GETPC()); \
2951 }
2952
2953 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
2954 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2955 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2956 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2957 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2958
2959 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
2960 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2961 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2962 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2963 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2964
2965 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
2966 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2967 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2968 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2969 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2970
2971 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2972 {
2973 helper_reset_fpstatus(env);
2974
2975 uint64_t xt = do_frsp(env, xb, GETPC());
2976
2977 helper_compute_fprf_float64(env, xt);
2978 do_float_check_status(env, GETPC());
2979 return xt;
2980 }
2981
2982 #define VSX_XXPERM(op, indexed) \
2983 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2984 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
2985 { \
2986 ppc_vsr_t t = *xt; \
2987 int i, idx; \
2988 \
2989 for (i = 0; i < 16; i++) { \
2990 idx = pcv->VsrB(i) & 0x1F; \
2991 if (indexed) { \
2992 idx = 31 - idx; \
2993 } \
2994 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
2995 : xt->VsrB(idx - 16); \
2996 } \
2997 *xt = t; \
2998 }
2999
3000 VSX_XXPERM(xxperm, 0)
3001 VSX_XXPERM(xxpermr, 1)
3002
3003 void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
3004 {
3005 ppc_vsr_t t = { };
3006 uint32_t exp, i, fraction;
3007
3008 for (i = 0; i < 4; i++) {
3009 exp = (xb->VsrW(i) >> 23) & 0xFF;
3010 fraction = xb->VsrW(i) & 0x7FFFFF;
3011 if (exp != 0 && exp != 255) {
3012 t.VsrW(i) = fraction | 0x00800000;
3013 } else {
3014 t.VsrW(i) = fraction;
3015 }
3016 }
3017 *xt = t;
3018 }
3019
3020 /*
3021 * VSX_TEST_DC - VSX floating point test data class
3022 * op - instruction mnemonic
3023 * nels - number of elements (1, 2 or 4)
3024 * xbn - VSR register number
3025 * tp - type (float32 or float64)
3026 * fld - vsr_t field (VsrD(*) or VsrW(*))
3027 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3028 * fld_max - target field max
3029 * scrf - set result in CR and FPCC
3030 */
3031 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3032 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3033 { \
3034 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3035 ppc_vsr_t *xb = &env->vsr[xbn]; \
3036 ppc_vsr_t t = { }; \
3037 uint32_t i, sign, dcmx; \
3038 uint32_t cc, match = 0; \
3039 \
3040 if (!scrf) { \
3041 dcmx = DCMX_XV(opcode); \
3042 } else { \
3043 t = *xt; \
3044 dcmx = DCMX(opcode); \
3045 } \
3046 \
3047 for (i = 0; i < nels; i++) { \
3048 sign = tp##_is_neg(xb->fld); \
3049 if (tp##_is_any_nan(xb->fld)) { \
3050 match = extract32(dcmx, 6, 1); \
3051 } else if (tp##_is_infinity(xb->fld)) { \
3052 match = extract32(dcmx, 4 + !sign, 1); \
3053 } else if (tp##_is_zero(xb->fld)) { \
3054 match = extract32(dcmx, 2 + !sign, 1); \
3055 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
3056 match = extract32(dcmx, 0 + !sign, 1); \
3057 } \
3058 \
3059 if (scrf) { \
3060 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3061 env->fpscr &= ~FP_FPCC; \
3062 env->fpscr |= cc << FPSCR_FPCC; \
3063 env->crf[BF(opcode)] = cc; \
3064 } else { \
3065 t.tfld = match ? fld_max : 0; \
3066 } \
3067 match = 0; \
3068 } \
3069 if (!scrf) { \
3070 *xt = t; \
3071 } \
3072 }
3073
3074 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3075 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3076 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3077 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3078
3079 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
3080 {
3081 uint32_t dcmx, sign, exp;
3082 uint32_t cc, match = 0, not_sp = 0;
3083
3084 dcmx = DCMX(opcode);
3085 exp = (xb->VsrD(0) >> 52) & 0x7FF;
3086
3087 sign = float64_is_neg(xb->VsrD(0));
3088 if (float64_is_any_nan(xb->VsrD(0))) {
3089 match = extract32(dcmx, 6, 1);
3090 } else if (float64_is_infinity(xb->VsrD(0))) {
3091 match = extract32(dcmx, 4 + !sign, 1);
3092 } else if (float64_is_zero(xb->VsrD(0))) {
3093 match = extract32(dcmx, 2 + !sign, 1);
3094 } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
3095 (exp > 0 && exp < 0x381)) {
3096 match = extract32(dcmx, 0 + !sign, 1);
3097 }
3098
3099 not_sp = !float64_eq(xb->VsrD(0),
3100 float32_to_float64(
3101 float64_to_float32(xb->VsrD(0), &env->fp_status),
3102 &env->fp_status), &env->fp_status);
3103
3104 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3105 env->fpscr &= ~FP_FPCC;
3106 env->fpscr |= cc << FPSCR_FPCC;
3107 env->crf[BF(opcode)] = cc;
3108 }
3109
3110 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
3111 ppc_vsr_t *xt, ppc_vsr_t *xb)
3112 {
3113 ppc_vsr_t t = { };
3114 uint8_t r = Rrm(opcode);
3115 uint8_t ex = Rc(opcode);
3116 uint8_t rmc = RMC(opcode);
3117 uint8_t rmode = 0;
3118 float_status tstat;
3119
3120 helper_reset_fpstatus(env);
3121
3122 if (r == 0 && rmc == 0) {
3123 rmode = float_round_ties_away;
3124 } else if (r == 0 && rmc == 0x3) {
3125 rmode = fpscr_rn;
3126 } else if (r == 1) {
3127 switch (rmc) {
3128 case 0:
3129 rmode = float_round_nearest_even;
3130 break;
3131 case 1:
3132 rmode = float_round_to_zero;
3133 break;
3134 case 2:
3135 rmode = float_round_up;
3136 break;
3137 case 3:
3138 rmode = float_round_down;
3139 break;
3140 default:
3141 abort();
3142 }
3143 }
3144
3145 tstat = env->fp_status;
3146 set_float_exception_flags(0, &tstat);
3147 set_float_rounding_mode(rmode, &tstat);
3148 t.f128 = float128_round_to_int(xb->f128, &tstat);
3149 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3150
3151 if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
3152 float_invalid_op_vxsnan(env, GETPC());
3153 }
3154
3155 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3156 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3157 }
3158
3159 helper_compute_fprf_float128(env, t.f128);
3160 do_float_check_status(env, GETPC());
3161 *xt = t;
3162 }
3163
3164 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
3165 ppc_vsr_t *xt, ppc_vsr_t *xb)
3166 {
3167 ppc_vsr_t t = { };
3168 uint8_t r = Rrm(opcode);
3169 uint8_t rmc = RMC(opcode);
3170 uint8_t rmode = 0;
3171 floatx80 round_res;
3172 float_status tstat;
3173
3174 helper_reset_fpstatus(env);
3175
3176 if (r == 0 && rmc == 0) {
3177 rmode = float_round_ties_away;
3178 } else if (r == 0 && rmc == 0x3) {
3179 rmode = fpscr_rn;
3180 } else if (r == 1) {
3181 switch (rmc) {
3182 case 0:
3183 rmode = float_round_nearest_even;
3184 break;
3185 case 1:
3186 rmode = float_round_to_zero;
3187 break;
3188 case 2:
3189 rmode = float_round_up;
3190 break;
3191 case 3:
3192 rmode = float_round_down;
3193 break;
3194 default:
3195 abort();
3196 }
3197 }
3198
3199 tstat = env->fp_status;
3200 set_float_exception_flags(0, &tstat);
3201 set_float_rounding_mode(rmode, &tstat);
3202 round_res = float128_to_floatx80(xb->f128, &tstat);
3203 t.f128 = floatx80_to_float128(round_res, &tstat);
3204 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3205
3206 if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
3207 float_invalid_op_vxsnan(env, GETPC());
3208 t.f128 = float128_snan_to_qnan(t.f128);
3209 }
3210
3211 helper_compute_fprf_float128(env, t.f128);
3212 *xt = t;
3213 do_float_check_status(env, GETPC());
3214 }
3215
3216 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
3217 ppc_vsr_t *xt, ppc_vsr_t *xb)
3218 {
3219 ppc_vsr_t t = { };
3220 float_status tstat;
3221
3222 helper_reset_fpstatus(env);
3223
3224 tstat = env->fp_status;
3225 if (unlikely(Rc(opcode) != 0)) {
3226 tstat.float_rounding_mode = float_round_to_odd;
3227 }
3228
3229 set_float_exception_flags(0, &tstat);
3230 t.f128 = float128_sqrt(xb->f128, &tstat);
3231 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3232
3233 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3234 float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC());
3235 }
3236
3237 helper_compute_fprf_float128(env, t.f128);
3238 *xt = t;
3239 do_float_check_status(env, GETPC());
3240 }
3241
3242 void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
3243 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
3244 {
3245 ppc_vsr_t t = *xt;
3246 float_status tstat;
3247
3248 helper_reset_fpstatus(env);
3249
3250 tstat = env->fp_status;
3251 if (unlikely(Rc(opcode) != 0)) {
3252 tstat.float_rounding_mode = float_round_to_odd;
3253 }
3254
3255 set_float_exception_flags(0, &tstat);
3256 t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
3257 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3258
3259 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3260 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
3261 }
3262
3263 helper_compute_fprf_float128(env, t.f128);
3264 *xt = t;
3265 do_float_check_status(env, GETPC());
3266 }
QEmu