hw/lan9118.c

   1 /*
   2  * SMSC LAN9118 Ethernet interface emulation
   3  *
   4  * Copyright (c) 2009 CodeSourcery, LLC.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU GPL v2
   8  */
   9
  10 #include "sysbus.h"
  11 #include "net.h"
  12 #include "devices.h"
  13 /* For crc32 */
  14 #include <zlib.h>
  15
  16 //#define DEBUG_LAN9118
  17
  18 #ifdef DEBUG_LAN9118
  19 #define DPRINTF(fmt, ...) \
  20 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
  21 #define BADF(fmt, ...) \
  22 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) do {} while(0)
  25 #define BADF(fmt, ...) \
  26 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  27 #endif
  28
  29 #define CSR_ID_REV      0x50
  30 #define CSR_IRQ_CFG     0x54
  31 #define CSR_INT_STS     0x58
  32 #define CSR_INT_EN      0x5c
  33 #define CSR_BYTE_TEST   0x64
  34 #define CSR_FIFO_INT    0x68
  35 #define CSR_RX_CFG      0x6c
  36 #define CSR_TX_CFG      0x70
  37 #define CSR_HW_CFG      0x74
  38 #define CSR_RX_DP_CTRL  0x78
  39 #define CSR_RX_FIFO_INF 0x7c
  40 #define CSR_TX_FIFO_INF 0x80
  41 #define CSR_PMT_CTRL    0x84
  42 #define CSR_GPIO_CFG    0x88
  43 #define CSR_GPT_CFG     0x8c /* TODO */
  44 #define CSR_GPT_CNT     0x90 /* TODO */
  45 #define CSR_WORD_SWAP   0x98
  46 #define CSR_FREE_RUN    0x9c
  47 #define CSR_RX_DROP     0xa0
  48 #define CSR_MAC_CSR_CMD 0xa4
  49 #define CSR_MAC_CSR_DATA 0xa8
  50 #define CSR_AFC_CFG     0xac
  51 #define CSR_E2P_CMD     0xb0
  52 #define CSR_E2P_DATA    0xb4
  53
  54 /* IRQ_CFG */
  55 #define IRQ_EN          0x00000100
  56 #define IRQ_POL         0x00000010
  57 #define IRQ_TYPE        0x00000001
  58
  59 /* INT_STS/INT_EN */
  60 #define SW_INT          0x80000000
  61 #define TXSTOP_INT      0x02000000
  62 #define RXSTOP_INT      0x01000000
  63 #define RXDFH_INT       0x00800000
  64 #define TX_IOC_INT      0x00200000
  65 #define RXD_INT         0x00100000
  66 #define GPT_INT         0x00080000
  67 #define PHY_INT         0x00040000
  68 #define PME_INT         0x00020000
  69 #define TXSO_INT        0x00010000
  70 #define RWT_INT         0x00008000
  71 #define RXE_INT         0x00004000
  72 #define TXE_INT         0x00002000
  73 #define TDFU_INT        0x00000800
  74 #define TDFO_INT        0x00000400
  75 #define TDFA_INT        0x00000200
  76 #define TSFF_INT        0x00000100
  77 #define TSFL_INT        0x00000080
  78 #define RXDF_INT        0x00000040
  79 #define RDFL_INT        0x00000020
  80 #define RSFF_INT        0x00000010
  81 #define RSFL_INT        0x00000008
  82 #define GPIO2_INT       0x00000004
  83 #define GPIO1_INT       0x00000002
  84 #define GPIO0_INT       0x00000001
  85 #define RESERVED_INT    0x7c001000
  86
  87 #define MAC_CR          1
  88 #define MAC_ADDRH       2
  89 #define MAC_ADDRL       3
  90 #define MAC_HASHH       4
  91 #define MAC_HASHL       5
  92 #define MAC_MII_ACC     6
  93 #define MAC_MII_DATA    7
  94 #define MAC_FLOW        8
  95 #define MAC_VLAN1       9 /* TODO */
  96 #define MAC_VLAN2       10 /* TODO */
  97 #define MAC_WUFF        11 /* TODO */
  98 #define MAC_WUCSR       12 /* TODO */
  99
 100 #define MAC_CR_RXALL    0x80000000
 101 #define MAC_CR_RCVOWN   0x00800000
 102 #define MAC_CR_LOOPBK   0x00200000
 103 #define MAC_CR_FDPX     0x00100000
 104 #define MAC_CR_MCPAS    0x00080000
 105 #define MAC_CR_PRMS     0x00040000
 106 #define MAC_CR_INVFILT  0x00020000
 107 #define MAC_CR_PASSBAD  0x00010000
 108 #define MAC_CR_HO       0x00008000
 109 #define MAC_CR_HPFILT   0x00002000
 110 #define MAC_CR_LCOLL    0x00001000
 111 #define MAC_CR_BCAST    0x00000800
 112 #define MAC_CR_DISRTY   0x00000400
 113 #define MAC_CR_PADSTR   0x00000100
 114 #define MAC_CR_BOLMT    0x000000c0
 115 #define MAC_CR_DFCHK    0x00000020
 116 #define MAC_CR_TXEN     0x00000008
 117 #define MAC_CR_RXEN     0x00000004
 118 #define MAC_CR_RESERVED 0x7f404213
 119
 120 enum tx_state {
 121     TX_IDLE,
 122     TX_B,
 123     TX_DATA
 124 };
 125
 126 typedef struct {
 127     enum tx_state state;
 128     uint32_t cmd_a;
 129     uint32_t cmd_b;
 130     int buffer_size;
 131     int offset;
 132     int pad;
 133     int fifo_used;
 134     int len;
 135     uint8_t data[2048];
 136 } LAN9118Packet;
 137
 138 typedef struct {
 139     SysBusDevice busdev;
 140     NICState *nic;
 141     NICConf conf;
 142     qemu_irq irq;
 143     int mmio_index;
 144
 145     uint32_t irq_cfg;
 146     uint32_t int_sts;
 147     uint32_t int_en;
 148     uint32_t fifo_int;
 149     uint32_t rx_cfg;
 150     uint32_t tx_cfg;
 151     uint32_t hw_cfg;
 152     uint32_t pmt_ctrl;
 153     uint32_t gpio_cfg;
 154     uint32_t word_swap;
 155     uint32_t free_timer_start;
 156     uint32_t mac_cmd;
 157     uint32_t mac_data;
 158     uint32_t afc_cfg;
 159     uint32_t e2p_cmd;
 160     uint32_t e2p_data;
 161
 162     uint32_t mac_cr;
 163     uint32_t mac_hashh;
 164     uint32_t mac_hashl;
 165     uint32_t mac_mii_acc;
 166     uint32_t mac_mii_data;
 167     uint32_t mac_flow;
 168
 169     uint32_t phy_status;
 170     uint32_t phy_control;
 171     uint32_t phy_advertise;
 172
 173     int eeprom_writable;
 174     uint8_t eeprom[8];
 175
 176     int tx_fifo_size;
 177     LAN9118Packet *txp;
 178     LAN9118Packet tx_packet;
 179
 180     int tx_status_fifo_used;
 181     int tx_status_fifo_head;
 182     uint32_t tx_status_fifo[512];
 183
 184     int rx_status_fifo_size;
 185     int rx_status_fifo_used;
 186     int rx_status_fifo_head;
 187     uint32_t rx_status_fifo[896];
 188     int rx_fifo_size;
 189     int rx_fifo_used;
 190     int rx_fifo_head;
 191     uint32_t rx_fifo[3360];
 192     int rx_packet_size_head;
 193     int rx_packet_size_tail;
 194     int rx_packet_size[1024];
 195
 196     int rxp_offset;
 197     int rxp_size;
 198     int rxp_pad;
 199 } lan9118_state;
 200
 201 static void lan9118_update(lan9118_state *s)
 202 {
 203     int level;
 204
 205     /* TODO: Implement FIFO level IRQs.  */
 206     level = (s->int_sts & s->int_en) != 0;
 207     if ((s->irq_cfg & IRQ_EN) == 0) {
 208         level = 0;
 209     }
 210     qemu_set_irq(s->irq, level);
 211 }
 212
 213 static void lan9118_mac_changed(lan9118_state *s)
 214 {
 215     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 216 }
 217
 218 static void lan9118_reload_eeprom(lan9118_state *s)
 219 {
 220     int i;
 221     if (s->eeprom[0] != 0xa5) {
 222         s->e2p_cmd &= ~0x10;
 223         DPRINTF("MACADDR load failed\n");
 224         return;
 225     }
 226     for (i = 0; i < 6; i++) {
 227         s->conf.macaddr.a[i] = s->eeprom[i + 1];
 228     }
 229     s->e2p_cmd |= 0x10;
 230     DPRINTF("MACADDR loaded from eeprom\n");
 231     lan9118_mac_changed(s);
 232 }
 233
 234 static void phy_update_link(lan9118_state *s)
 235 {
 236     /* Autonegotiation status mirrors link status.  */
 237     if (s->nic->nc.link_down) {
 238         s->phy_status &= ~0x0024;
 239     } else {
 240         s->phy_status |= 0x0024;
 241     }
 242 }
 243
 244 static void lan9118_set_link(VLANClientState *nc)
 245 {
 246     phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque);
 247 }
 248
 249 static void phy_reset(lan9118_state *s)
 250 {
 251     s->phy_status = 0x7805;
 252     s->phy_control = 0x3000;
 253     s->phy_advertise = 0x01e1;
 254     phy_update_link(s);
 255 }
 256
 257 static void lan9118_reset(DeviceState *d)
 258 {
 259     lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d));
 260
 261     s->irq_cfg &= ~(IRQ_TYPE | IRQ_POL);
 262     s->int_sts = 0;
 263     s->int_en = 0;
 264     s->fifo_int = 0x48000000;
 265     s->rx_cfg = 0;
 266     s->tx_cfg = 0;
 267     s->hw_cfg = 0x00050000;
 268     s->pmt_ctrl &= 0x45;
 269     s->gpio_cfg = 0;
 270     s->txp->fifo_used = 0;
 271     s->txp->state = TX_IDLE;
 272     s->txp->cmd_a = 0xffffffffu;
 273     s->txp->cmd_b = 0xffffffffu;
 274     s->txp->len = 0;
 275     s->txp->fifo_used = 0;
 276     s->tx_fifo_size = 4608;
 277     s->tx_status_fifo_used = 0;
 278     s->rx_status_fifo_size = 704;
 279     s->rx_fifo_size = 2640;
 280     s->rx_fifo_used = 0;
 281     s->rx_status_fifo_size = 176;
 282     s->rx_status_fifo_used = 0;
 283     s->rxp_offset = 0;
 284     s->rxp_size = 0;
 285     s->rxp_pad = 0;
 286     s->rx_packet_size_tail = s->rx_packet_size_head;
 287     s->rx_packet_size[s->rx_packet_size_head] = 0;
 288     s->mac_cmd = 0;
 289     s->mac_data = 0;
 290     s->afc_cfg = 0;
 291     s->e2p_cmd = 0;
 292     s->e2p_data = 0;
 293     s->free_timer_start = qemu_get_clock(vm_clock) / 40;
 294
 295     s->mac_cr = MAC_CR_PRMS;
 296     s->mac_hashh = 0;
 297     s->mac_hashl = 0;
 298     s->mac_mii_acc = 0;
 299     s->mac_mii_data = 0;
 300     s->mac_flow = 0;
 301
 302     phy_reset(s);
 303
 304     s->eeprom_writable = 0;
 305     lan9118_reload_eeprom(s);
 306 }
 307
 308 static int lan9118_can_receive(VLANClientState *nc)
 309 {
 310     return 1;
 311 }
 312
 313 static void rx_fifo_push(lan9118_state *s, uint32_t val)
 314 {
 315     int fifo_pos;
 316     fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
 317     if (fifo_pos >= s->rx_fifo_size)
 318       fifo_pos -= s->rx_fifo_size;
 319     s->rx_fifo[fifo_pos] = val;
 320     s->rx_fifo_used++;
 321 }
 322
 323 /* Return nonzero if the packet is accepted by the filter.  */
 324 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
 325 {
 326     int multicast;
 327     uint32_t hash;
 328
 329     if (s->mac_cr & MAC_CR_PRMS) {
 330         return 1;
 331     }
 332     if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
 333         addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
 334         return (s->mac_cr & MAC_CR_BCAST) == 0;
 335     }
 336
 337     multicast = addr[0] & 1;
 338     if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
 339         return 1;
 340     }
 341     if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
 342                   : (s->mac_cr & MAC_CR_HO) == 0) {
 343         /* Exact matching.  */
 344         hash = memcmp(addr, s->conf.macaddr.a, 6);
 345         if (s->mac_cr & MAC_CR_INVFILT) {
 346             return hash != 0;
 347         } else {
 348             return hash == 0;
 349         }
 350     } else {
 351         /* Hash matching  */
 352         hash = (crc32(~0, addr, 6) >> 26);
 353         if (hash & 0x20) {
 354             return (s->mac_hashh >> (hash & 0x1f)) & 1;
 355         } else {
 356             return (s->mac_hashl >> (hash & 0x1f)) & 1;
 357         }
 358     }
 359 }
 360
 361 static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf,
 362                                size_t size)
 363 {
 364     lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 365     int fifo_len;
 366     int offset;
 367     int src_pos;
 368     int n;
 369     int filter;
 370     uint32_t val;
 371     uint32_t crc;
 372     uint32_t status;
 373
 374     if ((s->mac_cr & MAC_CR_RXEN) == 0) {
 375         return -1;
 376     }
 377
 378     if (size >= 2048 || size < 14) {
 379         return -1;
 380     }
 381
 382     /* TODO: Implement FIFO overflow notification.  */
 383     if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
 384         return -1;
 385     }
 386
 387     filter = lan9118_filter(s, buf);
 388     if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
 389         return size;
 390     }
 391
 392     offset = (s->rx_cfg >> 8) & 0x1f;
 393     n = offset & 3;
 394     fifo_len = (size + n + 3) >> 2;
 395     /* Add a word for the CRC.  */
 396     fifo_len++;
 397     if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
 398         return -1;
 399     }
 400
 401     DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
 402             (int)size, fifo_len, filter ? "pass" : "fail");
 403     val = 0;
 404     crc = bswap32(crc32(~0, buf, size));
 405     for (src_pos = 0; src_pos < size; src_pos++) {
 406         val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
 407         n++;
 408         if (n == 4) {
 409             n = 0;
 410             rx_fifo_push(s, val);
 411             val = 0;
 412         }
 413     }
 414     if (n) {
 415         val >>= ((4 - n) * 8);
 416         val |= crc << (n * 8);
 417         rx_fifo_push(s, val);
 418         val = crc >> ((4 - n) * 8);
 419         rx_fifo_push(s, val);
 420     } else {
 421         rx_fifo_push(s, crc);
 422     }
 423     n = s->rx_status_fifo_head + s->rx_status_fifo_used;
 424     if (n >= s->rx_status_fifo_size) {
 425         n -= s->rx_status_fifo_size;
 426     }
 427     s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
 428     s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
 429     s->rx_status_fifo_used++;
 430
 431     status = (size + 4) << 16;
 432     if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
 433         buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
 434         status |= 0x00002000;
 435     } else if (buf[0] & 1) {
 436         status |= 0x00000400;
 437     }
 438     if (!filter) {
 439         status |= 0x40000000;
 440     }
 441     s->rx_status_fifo[n] = status;
 442
 443     if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
 444         s->int_sts |= RSFL_INT;
 445     }
 446     lan9118_update(s);
 447
 448     return size;
 449 }
 450
 451 static uint32_t rx_fifo_pop(lan9118_state *s)
 452 {
 453     int n;
 454     uint32_t val;
 455
 456     if (s->rxp_size == 0 && s->rxp_pad == 0) {
 457         s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
 458         s->rx_packet_size[s->rx_packet_size_head] = 0;
 459         if (s->rxp_size != 0) {
 460             s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
 461             s->rxp_offset = (s->rx_cfg >> 10) & 7;
 462             n = s->rxp_offset + s->rxp_size;
 463             switch (s->rx_cfg >> 30) {
 464             case 1:
 465                 n = (-n) & 3;
 466                 break;
 467             case 2:
 468                 n = (-n) & 7;
 469                 break;
 470             default:
 471                 n = 0;
 472                 break;
 473             }
 474             s->rxp_pad = n;
 475             DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
 476                     s->rxp_size, s->rxp_offset, s->rxp_pad);
 477         }
 478     }
 479     if (s->rxp_offset > 0) {
 480         s->rxp_offset--;
 481         val = 0;
 482     } else if (s->rxp_size > 0) {
 483         s->rxp_size--;
 484         val = s->rx_fifo[s->rx_fifo_head++];
 485         if (s->rx_fifo_head >= s->rx_fifo_size) {
 486             s->rx_fifo_head -= s->rx_fifo_size;
 487         }
 488         s->rx_fifo_used--;
 489     } else if (s->rxp_pad > 0) {
 490         s->rxp_pad--;
 491         val =  0;
 492     } else {
 493         DPRINTF("RX underflow\n");
 494         s->int_sts |= RXE_INT;
 495         val =  0;
 496     }
 497     lan9118_update(s);
 498     return val;
 499 }
 500
 501 static void do_tx_packet(lan9118_state *s)
 502 {
 503     int n;
 504     uint32_t status;
 505
 506     /* FIXME: Honor TX disable, and allow queueing of packets.  */
 507     if (s->phy_control & 0x4000)  {
 508         /* This assumes the receive routine doesn't touch the VLANClient.  */
 509         lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len);
 510     } else {
 511         qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len);
 512     }
 513     s->txp->fifo_used = 0;
 514
 515     if (s->tx_status_fifo_used == 512) {
 516         /* Status FIFO full */
 517         return;
 518     }
 519     /* Add entry to status FIFO.  */
 520     status = s->txp->cmd_b & 0xffff0000u;
 521     DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
 522     n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
 523     s->tx_status_fifo[n] = status;
 524     s->tx_status_fifo_used++;
 525     if (s->tx_status_fifo_used == 512) {
 526         s->int_sts |= TSFF_INT;
 527         /* TODO: Stop transmission.  */
 528     }
 529 }
 530
 531 static uint32_t rx_status_fifo_pop(lan9118_state *s)
 532 {
 533     uint32_t val;
 534
 535     val = s->rx_status_fifo[s->rx_status_fifo_head];
 536     if (s->rx_status_fifo_used != 0) {
 537         s->rx_status_fifo_used--;
 538         s->rx_status_fifo_head++;
 539         if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
 540             s->rx_status_fifo_head -= s->rx_status_fifo_size;
 541         }
 542         /* ??? What value should be returned when the FIFO is empty?  */
 543         DPRINTF("RX status pop 0x%08x\n", val);
 544     }
 545     return val;
 546 }
 547
 548 static uint32_t tx_status_fifo_pop(lan9118_state *s)
 549 {
 550     uint32_t val;
 551
 552     val = s->tx_status_fifo[s->tx_status_fifo_head];
 553     if (s->tx_status_fifo_used != 0) {
 554         s->tx_status_fifo_used--;
 555         s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
 556         /* ??? What value should be returned when the FIFO is empty?  */
 557     }
 558     return val;
 559 }
 560
 561 static void tx_fifo_push(lan9118_state *s, uint32_t val)
 562 {
 563     int n;
 564
 565     if (s->txp->fifo_used == s->tx_fifo_size) {
 566         s->int_sts |= TDFO_INT;
 567         return;
 568     }
 569     switch (s->txp->state) {
 570     case TX_IDLE:
 571         s->txp->cmd_a = val & 0x831f37ff;
 572         s->txp->fifo_used++;
 573         s->txp->state = TX_B;
 574         break;
 575     case TX_B:
 576         if (s->txp->cmd_a & 0x2000) {
 577             /* First segment */
 578             s->txp->cmd_b = val;
 579             s->txp->fifo_used++;
 580             s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
 581             s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f;
 582             /* End alignment does not include command words.  */
 583             n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
 584             switch ((n >> 24) & 3) {
 585             case 1:
 586                 n = (-n) & 3;
 587                 break;
 588             case 2:
 589                 n = (-n) & 7;
 590                 break;
 591             default:
 592                 n = 0;
 593             }
 594             s->txp->pad = n;
 595             s->txp->len = 0;
 596         }
 597         DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
 598                 s->txp->buffer_size, s->txp->offset, s->txp->pad,
 599                 s->txp->cmd_a);
 600         s->txp->state = TX_DATA;
 601         break;
 602     case TX_DATA:
 603         if (s->txp->offset >= 4) {
 604             s->txp->offset -= 4;
 605             break;
 606         }
 607         if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
 608             s->txp->pad--;
 609         } else {
 610             n = 4;
 611             while (s->txp->offset) {
 612                 val >>= 8;
 613                 n--;
 614                 s->txp->offset--;
 615             }
 616             /* Documentation is somewhat unclear on the ordering of bytes
 617                in FIFO words.  Empirical results show it to be little-endian.
 618                */
 619             /* TODO: FIFO overflow checking.  */
 620             while (n--) {
 621                 s->txp->data[s->txp->len] = val & 0xff;
 622                 s->txp->len++;
 623                 val >>= 8;
 624                 s->txp->buffer_size--;
 625             }
 626             s->txp->fifo_used++;
 627         }
 628         if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
 629             if (s->txp->cmd_a & 0x1000) {
 630                 do_tx_packet(s);
 631             }
 632             if (s->txp->cmd_a & 0x80000000) {
 633                 s->int_sts |= TX_IOC_INT;
 634             }
 635             s->txp->state = TX_IDLE;
 636         }
 637         break;
 638     }
 639 }
 640
 641 static uint32_t do_phy_read(lan9118_state *s, int reg)
 642 {
 643     switch (reg) {
 644     case 0: /* Basic Control */
 645         return s->phy_control;
 646     case 1: /* Basic Status */
 647         return s->phy_status;
 648     case 2: /* ID1 */
 649         return 0x0007;
 650     case 3: /* ID2 */
 651         return 0xc0d1;
 652     case 4: /* Auto-neg advertisment */
 653         return s->phy_advertise;
 654     case 5: /* Auto-neg Link Partner Ability */
 655         return 0x0f71;
 656     case 6: /* Auto-neg Expansion */
 657         return 1;
 658         /* TODO 17, 18, 27, 29, 30, 31 */
 659     default:
 660         BADF("PHY read reg %d\n", reg);
 661         return 0;
 662     }
 663 }
 664
 665 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
 666 {
 667     switch (reg) {
 668     case 0: /* Basic Control */
 669         if (val & 0x8000) {
 670             phy_reset(s);
 671             break;
 672         }
 673         s->phy_control = val & 0x7980;
 674         /* Complete autonegotiation imediately.  */
 675         if (val & 0x1000) {
 676             s->phy_status |= 0x0020;
 677         }
 678         break;
 679     case 4: /* Auto-neg advertisment */
 680         s->phy_advertise = (val & 0x2d7f) | 0x80;
 681         break;
 682         /* TODO 17, 18, 27, 29, 30, 31 */
 683     default:
 684         BADF("PHY write reg %d = 0x%04x\n", reg, val);
 685     }
 686 }
 687
 688 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
 689 {
 690     switch (reg) {
 691     case MAC_CR:
 692         if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
 693             s->int_sts |= RXSTOP_INT;
 694         }
 695         s->mac_cr = val & ~MAC_CR_RESERVED;
 696         DPRINTF("MAC_CR: %08x\n", val);
 697         break;
 698     case MAC_ADDRH:
 699         s->conf.macaddr.a[4] = val & 0xff;
 700         s->conf.macaddr.a[5] = (val >> 8) & 0xff;
 701         lan9118_mac_changed(s);
 702         break;
 703     case MAC_ADDRL:
 704         s->conf.macaddr.a[0] = val & 0xff;
 705         s->conf.macaddr.a[1] = (val >> 8) & 0xff;
 706         s->conf.macaddr.a[2] = (val >> 16) & 0xff;
 707         s->conf.macaddr.a[3] = (val >> 24) & 0xff;
 708         lan9118_mac_changed(s);
 709         break;
 710     case MAC_HASHH:
 711         s->mac_hashh = val;
 712         break;
 713     case MAC_HASHL:
 714         s->mac_hashl = val;
 715         break;
 716     case MAC_MII_ACC:
 717         s->mac_mii_acc = val & 0xffc2;
 718         if (val & 2) {
 719             DPRINTF("PHY write %d = 0x%04x\n",
 720                     (val >> 6) & 0x1f, s->mac_mii_data);
 721             do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
 722         } else {
 723             s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
 724             DPRINTF("PHY read %d = 0x%04x\n",
 725                     (val >> 6) & 0x1f, s->mac_mii_data);
 726         }
 727         break;
 728     case MAC_MII_DATA:
 729         s->mac_mii_data = val & 0xffff;
 730         break;
 731     case MAC_FLOW:
 732         s->mac_flow = val & 0xffff0000;
 733         break;
 734     default:
 735         hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
 736                  s->mac_cmd & 0xf, val);
 737     }
 738 }
 739
 740 static uint32_t do_mac_read(lan9118_state *s, int reg)
 741 {
 742     switch (reg) {
 743     case MAC_CR:
 744         return s->mac_cr;
 745     case MAC_ADDRH:
 746         return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
 747     case MAC_ADDRL:
 748         return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
 749                | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
 750     case MAC_HASHH:
 751         return s->mac_hashh;
 752         break;
 753     case MAC_HASHL:
 754         return s->mac_hashl;
 755         break;
 756     case MAC_MII_ACC:
 757         return s->mac_mii_acc;
 758     case MAC_MII_DATA:
 759         return s->mac_mii_data;
 760     case MAC_FLOW:
 761         return s->mac_flow;
 762     default:
 763         hw_error("lan9118: Unimplemented MAC register read: %d\n",
 764                  s->mac_cmd & 0xf);
 765     }
 766 }
 767
 768 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
 769 {
 770     s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr;
 771     switch (cmd) {
 772     case 0:
 773         s->e2p_data = s->eeprom[addr];
 774         DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
 775         break;
 776     case 1:
 777         s->eeprom_writable = 0;
 778         DPRINTF("EEPROM Write Disable\n");
 779         break;
 780     case 2: /* EWEN */
 781         s->eeprom_writable = 1;
 782         DPRINTF("EEPROM Write Enable\n");
 783         break;
 784     case 3: /* WRITE */
 785         if (s->eeprom_writable) {
 786             s->eeprom[addr] &= s->e2p_data;
 787             DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
 788         } else {
 789             DPRINTF("EEPROM Write %d (ignored)\n", addr);
 790         }
 791         break;
 792     case 4: /* WRAL */
 793         if (s->eeprom_writable) {
 794             for (addr = 0; addr < 128; addr++) {
 795                 s->eeprom[addr] &= s->e2p_data;
 796             }
 797             DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
 798         } else {
 799             DPRINTF("EEPROM Write All (ignored)\n");
 800         }
 801     case 5: /* ERASE */
 802         if (s->eeprom_writable) {
 803             s->eeprom[addr] = 0xff;
 804             DPRINTF("EEPROM Erase %d\n", addr);
 805         } else {
 806             DPRINTF("EEPROM Erase %d (ignored)\n", addr);
 807         }
 808         break;
 809     case 6: /* ERAL */
 810         if (s->eeprom_writable) {
 811             memset(s->eeprom, 0xff, 128);
 812             DPRINTF("EEPROM Erase All\n");
 813         } else {
 814             DPRINTF("EEPROM Erase All (ignored)\n");
 815         }
 816         break;
 817     case 7: /* RELOAD */
 818         lan9118_reload_eeprom(s);
 819         break;
 820     }
 821 }
 822
 823 static void lan9118_writel(void *opaque, target_phys_addr_t offset,
 824                            uint32_t val)
 825 {
 826     lan9118_state *s = (lan9118_state *)opaque;
 827     offset &= 0xff;
 828
 829     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
 830     if (offset >= 0x20 && offset < 0x40) {
 831         /* TX FIFO */
 832         tx_fifo_push(s, val);
 833         return;
 834     }
 835     switch (offset) {
 836     case CSR_IRQ_CFG:
 837         /* TODO: Implement interrupt deassertion intervals.  */
 838         s->irq_cfg = (val & IRQ_EN);
 839         break;
 840     case CSR_INT_STS:
 841         s->int_sts &= ~val;
 842         break;
 843     case CSR_INT_EN:
 844         s->int_en = val & ~RESERVED_INT;
 845         s->int_sts |= val & SW_INT;
 846         break;
 847     case CSR_FIFO_INT:
 848         DPRINTF("FIFO INT levels %08x\n", val);
 849         s->fifo_int = val;
 850         break;
 851     case CSR_RX_CFG:
 852         if (val & 0x8000) {
 853             /* RX_DUMP */
 854             s->rx_fifo_used = 0;
 855             s->rx_status_fifo_used = 0;
 856             s->rx_packet_size_tail = s->rx_packet_size_head;
 857             s->rx_packet_size[s->rx_packet_size_head] = 0;
 858         }
 859         s->rx_cfg = val & 0xcfff1ff0;
 860         break;
 861     case CSR_TX_CFG:
 862         if (val & 0x8000) {
 863             s->tx_status_fifo_used = 0;
 864         }
 865         if (val & 0x4000) {
 866             s->txp->state = TX_IDLE;
 867             s->txp->fifo_used = 0;
 868             s->txp->cmd_a = 0xffffffff;
 869         }
 870         s->tx_cfg = val & 6;
 871         break;
 872     case CSR_HW_CFG:
 873         if (val & 1) {
 874             /* SRST */
 875             lan9118_reset(&s->busdev.qdev);
 876         } else {
 877             s->hw_cfg = val & 0x003f300;
 878         }
 879         break;
 880     case CSR_RX_DP_CTRL:
 881         if (val & 0x80000000) {
 882             /* Skip forward to next packet.  */
 883             s->rxp_pad = 0;
 884             s->rxp_offset = 0;
 885             if (s->rxp_size == 0) {
 886                 /* Pop a word to start the next packet.  */
 887                 rx_fifo_pop(s);
 888                 s->rxp_pad = 0;
 889                 s->rxp_offset = 0;
 890             }
 891             s->rx_fifo_head += s->rxp_size;
 892             if (s->rx_fifo_head >= s->rx_fifo_size) {
 893                 s->rx_fifo_head -= s->rx_fifo_size;
 894             }
 895         }
 896         break;
 897     case CSR_PMT_CTRL:
 898         if (val & 0x400) {
 899             phy_reset(s);
 900         }
 901         s->pmt_ctrl &= ~0x34e;
 902         s->pmt_ctrl |= (val & 0x34e);
 903         break;
 904     case CSR_GPIO_CFG:
 905         /* Probably just enabling LEDs.  */
 906         s->gpio_cfg = val & 0x7777071f;
 907         break;
 908     case CSR_WORD_SWAP:
 909         /* Ignored because we're in 32-bit mode.  */
 910         s->word_swap = val;
 911         break;
 912     case CSR_MAC_CSR_CMD:
 913         s->mac_cmd = val & 0x4000000f;
 914         if (val & 0x80000000) {
 915             if (val & 0x40000000) {
 916                 s->mac_data = do_mac_read(s, val & 0xf);
 917                 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
 918             } else {
 919                 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
 920                 do_mac_write(s, val & 0xf, s->mac_data);
 921             }
 922         }
 923         break;
 924     case CSR_MAC_CSR_DATA:
 925         s->mac_data = val;
 926         break;
 927     case CSR_AFC_CFG:
 928         s->afc_cfg = val & 0x00ffffff;
 929         break;
 930     case CSR_E2P_CMD:
 931         lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0xff);
 932         break;
 933     case CSR_E2P_DATA:
 934         s->e2p_data = val & 0xff;
 935         break;
 936
 937     default:
 938         hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val);
 939         break;
 940     }
 941     lan9118_update(s);
 942 }
 943
 944 static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset)
 945 {
 946     lan9118_state *s = (lan9118_state *)opaque;
 947
 948     //DPRINTF("Read reg 0x%02x\n", (int)offset);
 949     if (offset < 0x20) {
 950         /* RX FIFO */
 951         return rx_fifo_pop(s);
 952     }
 953     switch (offset) {
 954     case 0x40:
 955         return rx_status_fifo_pop(s);
 956     case 0x44:
 957         return s->rx_status_fifo[s->tx_status_fifo_head];
 958     case 0x48:
 959         return tx_status_fifo_pop(s);
 960     case 0x4c:
 961         return s->tx_status_fifo[s->tx_status_fifo_head];
 962     case CSR_ID_REV:
 963         return 0x01180001;
 964     case CSR_IRQ_CFG:
 965         return s->irq_cfg;
 966     case CSR_INT_STS:
 967         return s->int_sts;
 968     case CSR_INT_EN:
 969         return s->int_en;
 970     case CSR_BYTE_TEST:
 971         return 0x87654321;
 972     case CSR_FIFO_INT:
 973         return s->fifo_int;
 974     case CSR_RX_CFG:
 975         return s->rx_cfg;
 976     case CSR_TX_CFG:
 977         return s->tx_cfg;
 978     case CSR_HW_CFG:
 979         return s->hw_cfg | 0x4;
 980     case CSR_RX_DP_CTRL:
 981         return 0;
 982     case CSR_RX_FIFO_INF:
 983         return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
 984     case CSR_TX_FIFO_INF:
 985         return (s->tx_status_fifo_used << 16)
 986                | (s->tx_fifo_size - s->txp->fifo_used);
 987     case CSR_PMT_CTRL:
 988         return s->pmt_ctrl;
 989     case CSR_GPIO_CFG:
 990         return s->gpio_cfg;
 991     case CSR_WORD_SWAP:
 992         return s->word_swap;
 993     case CSR_FREE_RUN:
 994         return (qemu_get_clock(vm_clock) / 40) - s->free_timer_start;
 995     case CSR_RX_DROP:
 996         /* TODO: Implement dropped frames counter.  */
 997         return 0;
 998     case CSR_MAC_CSR_CMD:
 999         return s->mac_cmd;
1000     case CSR_MAC_CSR_DATA:
1001         return s->mac_data;
1002     case CSR_AFC_CFG:
1003         return s->afc_cfg;
1004     case CSR_E2P_CMD:
1005         return s->e2p_cmd;
1006     case CSR_E2P_DATA:
1007         return s->e2p_data;
1008     }
1009     hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset);
1010     return 0;
1011 }
1012
1013 static CPUReadMemoryFunc * const lan9118_readfn[] = {
1014     lan9118_readl,
1015     lan9118_readl,
1016     lan9118_readl
1017 };
1018
1019 static CPUWriteMemoryFunc * const lan9118_writefn[] = {
1020     lan9118_writel,
1021     lan9118_writel,
1022     lan9118_writel
1023 };
1024
1025 static void lan9118_cleanup(VLANClientState *nc)
1026 {
1027     lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
1028
1029     s->nic = NULL;
1030 }
1031
1032 static NetClientInfo net_lan9118_info = {
1033     .type = NET_CLIENT_TYPE_NIC,
1034     .size = sizeof(NICState),
1035     .can_receive = lan9118_can_receive,
1036     .receive = lan9118_receive,
1037     .cleanup = lan9118_cleanup,
1038     .link_status_changed = lan9118_set_link,
1039 };
1040
1041 static int lan9118_init1(SysBusDevice *dev)
1042 {
1043     lan9118_state *s = FROM_SYSBUS(lan9118_state, dev);
1044     int i;
1045
1046     s->mmio_index = cpu_register_io_memory(lan9118_readfn,
1047                                            lan9118_writefn, s);
1048     sysbus_init_mmio(dev, 0x100, s->mmio_index);
1049     sysbus_init_irq(dev, &s->irq);
1050     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1051
1052     s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1053                           dev->qdev.info->name, dev->qdev.id, s);
1054     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1055     s->eeprom[0] = 0xa5;
1056     for (i = 0; i < 6; i++) {
1057         s->eeprom[i + 1] = s->conf.macaddr.a[i];
1058     }
1059     s->pmt_ctrl = 1;
1060     s->txp = &s->tx_packet;
1061
1062     /* ??? Save/restore.  */
1063     return 0;
1064 }
1065
1066 static SysBusDeviceInfo lan9118_info = {
1067     .init = lan9118_init1,
1068     .qdev.name  = "lan9118",
1069     .qdev.size  = sizeof(lan9118_state),
1070     .qdev.reset = lan9118_reset,
1071     .qdev.props = (Property[]) {
1072         DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1073         DEFINE_PROP_END_OF_LIST(),
1074     }
1075 };
1076
1077 static void lan9118_register_devices(void)
1078 {
1079     sysbus_register_withprop(&lan9118_info);
1080 }
1081
1082 /* Legacy helper function.  Should go away when machine config files are
1083    implemented.  */
1084 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1085 {
1086     DeviceState *dev;
1087     SysBusDevice *s;
1088
1089     qemu_check_nic_model(nd, "lan9118");
1090     dev = qdev_create(NULL, "lan9118");
1091     qdev_set_nic_properties(dev, nd);
1092     qdev_init_nofail(dev);
1093     s = sysbus_from_qdev(dev);
1094     sysbus_mmio_map(s, 0, base);
1095     sysbus_connect_irq(s, 0, irq);
1096 }
1097
1098 device_init(lan9118_register_devices)