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hw/ac97: Make a bunch of mixer registers read only
[qemu.git] / hw / ac97.c
blobc5089be495e878ac1de6fbe030d697b55e1c1fcd
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 *
16 * Contributions after 2012-01-13 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 */
19
20 #include "hw.h"
21 #include "audiodev.h"
22 #include "audio/audio.h"
23 #include "pci.h"
24 #include "dma.h"
25
26 enum {
27 AC97_Reset = 0x00,
28 AC97_Master_Volume_Mute = 0x02,
29 AC97_Headphone_Volume_Mute = 0x04,
30 AC97_Master_Volume_Mono_Mute = 0x06,
31 AC97_Master_Tone_RL = 0x08,
32 AC97_PC_BEEP_Volume_Mute = 0x0A,
33 AC97_Phone_Volume_Mute = 0x0C,
34 AC97_Mic_Volume_Mute = 0x0E,
35 AC97_Line_In_Volume_Mute = 0x10,
36 AC97_CD_Volume_Mute = 0x12,
37 AC97_Video_Volume_Mute = 0x14,
38 AC97_Aux_Volume_Mute = 0x16,
39 AC97_PCM_Out_Volume_Mute = 0x18,
40 AC97_Record_Select = 0x1A,
41 AC97_Record_Gain_Mute = 0x1C,
42 AC97_Record_Gain_Mic_Mute = 0x1E,
43 AC97_General_Purpose = 0x20,
44 AC97_3D_Control = 0x22,
45 AC97_AC_97_RESERVED = 0x24,
46 AC97_Powerdown_Ctrl_Stat = 0x26,
47 AC97_Extended_Audio_ID = 0x28,
48 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
49 AC97_PCM_Front_DAC_Rate = 0x2C,
50 AC97_PCM_Surround_DAC_Rate = 0x2E,
51 AC97_PCM_LFE_DAC_Rate = 0x30,
52 AC97_PCM_LR_ADC_Rate = 0x32,
53 AC97_MIC_ADC_Rate = 0x34,
54 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
55 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
56 AC97_Vendor_Reserved = 0x58,
57 AC97_Sigmatel_Analog = 0x6c, /* We emulate a Sigmatel codec */
58 AC97_Sigmatel_Dac2Invert = 0x6e, /* We emulate a Sigmatel codec */
59 AC97_Vendor_ID1 = 0x7c,
60 AC97_Vendor_ID2 = 0x7e
61 };
62
63 #define SOFT_VOLUME
64 #define SR_FIFOE 16 /* rwc */
65 #define SR_BCIS 8 /* rwc */
66 #define SR_LVBCI 4 /* rwc */
67 #define SR_CELV 2 /* ro */
68 #define SR_DCH 1 /* ro */
69 #define SR_VALID_MASK ((1 << 5) - 1)
70 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
71 #define SR_RO_MASK (SR_DCH | SR_CELV)
72 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
73
74 #define CR_IOCE 16 /* rw */
75 #define CR_FEIE 8 /* rw */
76 #define CR_LVBIE 4 /* rw */
77 #define CR_RR 2 /* rw */
78 #define CR_RPBM 1 /* rw */
79 #define CR_VALID_MASK ((1 << 5) - 1)
80 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
81
82 #define GC_WR 4 /* rw */
83 #define GC_CR 2 /* rw */
84 #define GC_VALID_MASK ((1 << 6) - 1)
85
86 #define GS_MD3 (1<<17) /* rw */
87 #define GS_AD3 (1<<16) /* rw */
88 #define GS_RCS (1<<15) /* rwc */
89 #define GS_B3S12 (1<<14) /* ro */
90 #define GS_B2S12 (1<<13) /* ro */
91 #define GS_B1S12 (1<<12) /* ro */
92 #define GS_S1R1 (1<<11) /* rwc */
93 #define GS_S0R1 (1<<10) /* rwc */
94 #define GS_S1CR (1<<9) /* ro */
95 #define GS_S0CR (1<<8) /* ro */
96 #define GS_MINT (1<<7) /* ro */
97 #define GS_POINT (1<<6) /* ro */
98 #define GS_PIINT (1<<5) /* ro */
99 #define GS_RSRVD ((1<<4)|(1<<3))
100 #define GS_MOINT (1<<2) /* ro */
101 #define GS_MIINT (1<<1) /* ro */
102 #define GS_GSCI 1 /* rwc */
103 #define GS_RO_MASK (GS_B3S12| \
104 GS_B2S12| \
105 GS_B1S12| \
106 GS_S1CR| \
107 GS_S0CR| \
108 GS_MINT| \
109 GS_POINT| \
110 GS_PIINT| \
111 GS_RSRVD| \
112 GS_MOINT| \
113 GS_MIINT)
114 #define GS_VALID_MASK ((1 << 18) - 1)
115 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
116
117 #define BD_IOC (1<<31)
118 #define BD_BUP (1<<30)
119
120 #define EACS_VRA 1
121 #define EACS_VRM 8
122
123 #define MUTE_SHIFT 15
124
125 #define REC_MASK 7
126 enum {
127 REC_MIC = 0,
128 REC_CD,
129 REC_VIDEO,
130 REC_AUX,
131 REC_LINE_IN,
132 REC_STEREO_MIX,
133 REC_MONO_MIX,
134 REC_PHONE
135 };
136
137 typedef struct BD {
138 uint32_t addr;
139 uint32_t ctl_len;
140 } BD;
141
142 typedef struct AC97BusMasterRegs {
143 uint32_t bdbar; /* rw 0 */
144 uint8_t civ; /* ro 0 */
145 uint8_t lvi; /* rw 0 */
146 uint16_t sr; /* rw 1 */
147 uint16_t picb; /* ro 0 */
148 uint8_t piv; /* ro 0 */
149 uint8_t cr; /* rw 0 */
150 unsigned int bd_valid;
151 BD bd;
152 } AC97BusMasterRegs;
153
154 typedef struct AC97LinkState {
155 PCIDevice dev;
156 QEMUSoundCard card;
157 uint32_t use_broken_id;
158 uint32_t glob_cnt;
159 uint32_t glob_sta;
160 uint32_t cas;
161 uint32_t last_samp;
162 AC97BusMasterRegs bm_regs[3];
163 uint8_t mixer_data[256];
164 SWVoiceIn *voice_pi;
165 SWVoiceOut *voice_po;
166 SWVoiceIn *voice_mc;
167 int invalid_freq[3];
168 uint8_t silence[128];
169 int bup_flag;
170 MemoryRegion io_nam;
171 MemoryRegion io_nabm;
172 } AC97LinkState;
173
174 enum {
175 BUP_SET = 1,
176 BUP_LAST = 2
177 };
178
179 #ifdef DEBUG_AC97
180 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
181 #else
182 #define dolog(...)
183 #endif
184
185 #define MKREGS(prefix, start) \
186 enum { \
187 prefix ## _BDBAR = start, \
188 prefix ## _CIV = start + 4, \
189 prefix ## _LVI = start + 5, \
190 prefix ## _SR = start + 6, \
191 prefix ## _PICB = start + 8, \
192 prefix ## _PIV = start + 10, \
193 prefix ## _CR = start + 11 \
194 }
195
196 enum {
197 PI_INDEX = 0,
198 PO_INDEX,
199 MC_INDEX,
200 LAST_INDEX
201 };
202
203 MKREGS (PI, PI_INDEX * 16);
204 MKREGS (PO, PO_INDEX * 16);
205 MKREGS (MC, MC_INDEX * 16);
206
207 enum {
208 GLOB_CNT = 0x2c,
209 GLOB_STA = 0x30,
210 CAS = 0x34
211 };
212
213 #define GET_BM(index) (((index) >> 4) & 3)
214
215 static void po_callback (void *opaque, int free);
216 static void pi_callback (void *opaque, int avail);
217 static void mc_callback (void *opaque, int avail);
218
219 static void warm_reset (AC97LinkState *s)
220 {
221 (void) s;
222 }
223
224 static void cold_reset (AC97LinkState * s)
225 {
226 (void) s;
227 }
228
229 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
230 {
231 uint8_t b[8];
232
233 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
234 r->bd_valid = 1;
235 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
236 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
237 r->picb = r->bd.ctl_len & 0xffff;
238 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
239 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
240 r->bd.ctl_len & 0xffff,
241 (r->bd.ctl_len & 0xffff) << 1);
242 }
243
244 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
245 {
246 int event = 0;
247 int level = 0;
248 uint32_t new_mask = new_sr & SR_INT_MASK;
249 uint32_t old_mask = r->sr & SR_INT_MASK;
250 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
251
252 if (new_mask ^ old_mask) {
253 /** @todo is IRQ deasserted when only one of status bits is cleared? */
254 if (!new_mask) {
255 event = 1;
256 level = 0;
257 }
258 else {
259 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
260 event = 1;
261 level = 1;
262 }
263 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
264 event = 1;
265 level = 1;
266 }
267 }
268 }
269
270 r->sr = new_sr;
271
272 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
273 r->sr & SR_BCIS, r->sr & SR_LVBCI,
274 r->sr,
275 event, level);
276
277 if (!event)
278 return;
279
280 if (level) {
281 s->glob_sta |= masks[r - s->bm_regs];
282 dolog ("set irq level=1\n");
283 qemu_set_irq (s->dev.irq[0], 1);
284 }
285 else {
286 s->glob_sta &= ~masks[r - s->bm_regs];
287 dolog ("set irq level=0\n");
288 qemu_set_irq (s->dev.irq[0], 0);
289 }
290 }
291
292 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
293 {
294 switch (bm_index) {
295 case PI_INDEX:
296 AUD_set_active_in (s->voice_pi, on);
297 break;
298
299 case PO_INDEX:
300 AUD_set_active_out (s->voice_po, on);
301 break;
302
303 case MC_INDEX:
304 AUD_set_active_in (s->voice_mc, on);
305 break;
306
307 default:
308 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
309 break;
310 }
311 }
312
313 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
314 {
315 dolog ("reset_bm_regs\n");
316 r->bdbar = 0;
317 r->civ = 0;
318 r->lvi = 0;
319 /** todo do we need to do that? */
320 update_sr (s, r, SR_DCH);
321 r->picb = 0;
322 r->piv = 0;
323 r->cr = r->cr & CR_DONT_CLEAR_MASK;
324 r->bd_valid = 0;
325
326 voice_set_active (s, r - s->bm_regs, 0);
327 memset (s->silence, 0, sizeof (s->silence));
328 }
329
330 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
331 {
332 if (i + 2 > sizeof (s->mixer_data)) {
333 dolog ("mixer_store: index %d out of bounds %zd\n",
334 i, sizeof (s->mixer_data));
335 return;
336 }
337
338 s->mixer_data[i + 0] = v & 0xff;
339 s->mixer_data[i + 1] = v >> 8;
340 }
341
342 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
343 {
344 uint16_t val = 0xffff;
345
346 if (i + 2 > sizeof (s->mixer_data)) {
347 dolog ("mixer_load: index %d out of bounds %zd\n",
348 i, sizeof (s->mixer_data));
349 }
350 else {
351 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
352 }
353
354 return val;
355 }
356
357 static void open_voice (AC97LinkState *s, int index, int freq)
358 {
359 struct audsettings as;
360
361 as.freq = freq;
362 as.nchannels = 2;
363 as.fmt = AUD_FMT_S16;
364 as.endianness = 0;
365
366 if (freq > 0) {
367 s->invalid_freq[index] = 0;
368 switch (index) {
369 case PI_INDEX:
370 s->voice_pi = AUD_open_in (
371 &s->card,
372 s->voice_pi,
373 "ac97.pi",
374 s,
375 pi_callback,
376 &as
377 );
378 break;
379
380 case PO_INDEX:
381 s->voice_po = AUD_open_out (
382 &s->card,
383 s->voice_po,
384 "ac97.po",
385 s,
386 po_callback,
387 &as
388 );
389 break;
390
391 case MC_INDEX:
392 s->voice_mc = AUD_open_in (
393 &s->card,
394 s->voice_mc,
395 "ac97.mc",
396 s,
397 mc_callback,
398 &as
399 );
400 break;
401 }
402 }
403 else {
404 s->invalid_freq[index] = freq;
405 switch (index) {
406 case PI_INDEX:
407 AUD_close_in (&s->card, s->voice_pi);
408 s->voice_pi = NULL;
409 break;
410
411 case PO_INDEX:
412 AUD_close_out (&s->card, s->voice_po);
413 s->voice_po = NULL;
414 break;
415
416 case MC_INDEX:
417 AUD_close_in (&s->card, s->voice_mc);
418 s->voice_mc = NULL;
419 break;
420 }
421 }
422 }
423
424 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
425 {
426 uint16_t freq;
427
428 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
429 open_voice (s, PI_INDEX, freq);
430 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
431
432 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
433 open_voice (s, PO_INDEX, freq);
434 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
435
436 freq = mixer_load (s, AC97_MIC_ADC_Rate);
437 open_voice (s, MC_INDEX, freq);
438 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
439 }
440
441 static void get_volume (uint16_t vol, uint16_t mask, int inverse,
442 int *mute, uint8_t *lvol, uint8_t *rvol)
443 {
444 *mute = (vol >> MUTE_SHIFT) & 1;
445 *rvol = (255 * (vol & mask)) / mask;
446 *lvol = (255 * ((vol >> 8) & mask)) / mask;
447
448 if (inverse) {
449 *rvol = 255 - *rvol;
450 *lvol = 255 - *lvol;
451 }
452 }
453
454 static void update_combined_volume_out (AC97LinkState *s)
455 {
456 uint8_t lvol, rvol, plvol, prvol;
457 int mute, pmute;
458
459 get_volume (mixer_load (s, AC97_Master_Volume_Mute), 0x3f, 1,
460 &mute, &lvol, &rvol);
461 /* FIXME: should be 1f according to spec */
462 get_volume (mixer_load (s, AC97_PCM_Out_Volume_Mute), 0x3f, 1,
463 &pmute, &plvol, &prvol);
464
465 mute = mute | pmute;
466 lvol = (lvol * plvol) / 255;
467 rvol = (rvol * prvol) / 255;
468
469 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
470 }
471
472 static void update_volume_in (AC97LinkState *s)
473 {
474 uint8_t lvol, rvol;
475 int mute;
476
477 get_volume (mixer_load (s, AC97_Record_Gain_Mute), 0x0f, 0,
478 &mute, &lvol, &rvol);
479
480 AUD_set_volume_in (s->voice_pi, mute, lvol, rvol);
481 }
482
483 static void set_volume (AC97LinkState *s, int index, uint32_t val)
484 {
485 mixer_store (s, index, val);
486 if (index == AC97_Master_Volume_Mute || index == AC97_PCM_Out_Volume_Mute) {
487 update_combined_volume_out (s);
488 } else if (index == AC97_Record_Gain_Mute) {
489 update_volume_in (s);
490 }
491 }
492
493 static void record_select (AC97LinkState *s, uint32_t val)
494 {
495 uint8_t rs = val & REC_MASK;
496 uint8_t ls = (val >> 8) & REC_MASK;
497 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
498 }
499
500 static void mixer_reset (AC97LinkState *s)
501 {
502 uint8_t active[LAST_INDEX];
503
504 dolog ("mixer_reset\n");
505 memset (s->mixer_data, 0, sizeof (s->mixer_data));
506 memset (active, 0, sizeof (active));
507 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
508 mixer_store (s, AC97_Headphone_Volume_Mute , 0x0000);
509 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x0000);
510 mixer_store (s, AC97_Master_Tone_RL, 0x0000);
511 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
512 mixer_store (s, AC97_Phone_Volume_Mute , 0x0000);
513 mixer_store (s, AC97_Mic_Volume_Mute , 0x0000);
514 mixer_store (s, AC97_CD_Volume_Mute , 0x0000);
515 mixer_store (s, AC97_Video_Volume_Mute , 0x0000);
516 mixer_store (s, AC97_Aux_Volume_Mute , 0x0000);
517 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x0000);
518 mixer_store (s, AC97_General_Purpose , 0x0000);
519 mixer_store (s, AC97_3D_Control , 0x0000);
520 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
521
522 /*
523 * Sigmatel 9700 (STAC9700)
524 */
525 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
526 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
527
528 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
529 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
530 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
531 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
532 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
533 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
534 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
535
536 record_select (s, 0);
537 set_volume (s, AC97_Master_Volume_Mute, 0x8000);
538 set_volume (s, AC97_PCM_Out_Volume_Mute, 0x8808);
539 set_volume (s, AC97_Line_In_Volume_Mute, 0x8808);
540
541 reset_voices (s, active);
542 }
543
544 /**
545 * Native audio mixer
546 * I/O Reads
547 */
548 static uint32_t nam_readb (void *opaque, uint32_t addr)
549 {
550 AC97LinkState *s = opaque;
551 dolog ("U nam readb %#x\n", addr);
552 s->cas = 0;
553 return ~0U;
554 }
555
556 static uint32_t nam_readw (void *opaque, uint32_t addr)
557 {
558 AC97LinkState *s = opaque;
559 uint32_t val = ~0U;
560 uint32_t index = addr;
561 s->cas = 0;
562 val = mixer_load (s, index);
563 return val;
564 }
565
566 static uint32_t nam_readl (void *opaque, uint32_t addr)
567 {
568 AC97LinkState *s = opaque;
569 dolog ("U nam readl %#x\n", addr);
570 s->cas = 0;
571 return ~0U;
572 }
573
574 /**
575 * Native audio mixer
576 * I/O Writes
577 */
578 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
579 {
580 AC97LinkState *s = opaque;
581 dolog ("U nam writeb %#x <- %#x\n", addr, val);
582 s->cas = 0;
583 }
584
585 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
586 {
587 AC97LinkState *s = opaque;
588 uint32_t index = addr;
589 s->cas = 0;
590 switch (index) {
591 case AC97_Reset:
592 mixer_reset (s);
593 break;
594 case AC97_Powerdown_Ctrl_Stat:
595 val &= ~0xf;
596 val |= mixer_load (s, index) & 0xf;
597 mixer_store (s, index, val);
598 break;
599 case AC97_PCM_Out_Volume_Mute:
600 case AC97_Master_Volume_Mute:
601 case AC97_Record_Gain_Mute:
602 case AC97_Line_In_Volume_Mute:
603 set_volume (s, index, val);
604 break;
605 case AC97_Record_Select:
606 record_select (s, val);
607 break;
608 case AC97_Vendor_ID1:
609 case AC97_Vendor_ID2:
610 dolog ("Attempt to write vendor ID to %#x\n", val);
611 break;
612 case AC97_Extended_Audio_ID:
613 dolog ("Attempt to write extended audio ID to %#x\n", val);
614 break;
615 case AC97_Extended_Audio_Ctrl_Stat:
616 if (!(val & EACS_VRA)) {
617 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
618 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
619 open_voice (s, PI_INDEX, 48000);
620 open_voice (s, PO_INDEX, 48000);
621 }
622 if (!(val & EACS_VRM)) {
623 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
624 open_voice (s, MC_INDEX, 48000);
625 }
626 dolog ("Setting extended audio control to %#x\n", val);
627 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
628 break;
629 case AC97_PCM_Front_DAC_Rate:
630 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
631 mixer_store (s, index, val);
632 dolog ("Set front DAC rate to %d\n", val);
633 open_voice (s, PO_INDEX, val);
634 }
635 else {
636 dolog ("Attempt to set front DAC rate to %d, "
637 "but VRA is not set\n",
638 val);
639 }
640 break;
641 case AC97_MIC_ADC_Rate:
642 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
643 mixer_store (s, index, val);
644 dolog ("Set MIC ADC rate to %d\n", val);
645 open_voice (s, MC_INDEX, val);
646 }
647 else {
648 dolog ("Attempt to set MIC ADC rate to %d, "
649 "but VRM is not set\n",
650 val);
651 }
652 break;
653 case AC97_PCM_LR_ADC_Rate:
654 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
655 mixer_store (s, index, val);
656 dolog ("Set front LR ADC rate to %d\n", val);
657 open_voice (s, PI_INDEX, val);
658 }
659 else {
660 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
661 val);
662 }
663 break;
664 case AC97_Headphone_Volume_Mute:
665 case AC97_Master_Volume_Mono_Mute:
666 case AC97_Master_Tone_RL:
667 case AC97_PC_BEEP_Volume_Mute:
668 case AC97_Phone_Volume_Mute:
669 case AC97_Mic_Volume_Mute:
670 case AC97_CD_Volume_Mute:
671 case AC97_Video_Volume_Mute:
672 case AC97_Aux_Volume_Mute:
673 case AC97_Record_Gain_Mic_Mute:
674 case AC97_General_Purpose:
675 case AC97_3D_Control:
676 case AC97_Sigmatel_Analog:
677 case AC97_Sigmatel_Dac2Invert:
678 /* None of the features in these regs are emulated, so they are RO */
679 break;
680 default:
681 dolog ("U nam writew %#x <- %#x\n", addr, val);
682 mixer_store (s, index, val);
683 break;
684 }
685 }
686
687 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
688 {
689 AC97LinkState *s = opaque;
690 dolog ("U nam writel %#x <- %#x\n", addr, val);
691 s->cas = 0;
692 }
693
694 /**
695 * Native audio bus master
696 * I/O Reads
697 */
698 static uint32_t nabm_readb (void *opaque, uint32_t addr)
699 {
700 AC97LinkState *s = opaque;
701 AC97BusMasterRegs *r = NULL;
702 uint32_t index = addr;
703 uint32_t val = ~0U;
704
705 switch (index) {
706 case CAS:
707 dolog ("CAS %d\n", s->cas);
708 val = s->cas;
709 s->cas = 1;
710 break;
711 case PI_CIV:
712 case PO_CIV:
713 case MC_CIV:
714 r = &s->bm_regs[GET_BM (index)];
715 val = r->civ;
716 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
717 break;
718 case PI_LVI:
719 case PO_LVI:
720 case MC_LVI:
721 r = &s->bm_regs[GET_BM (index)];
722 val = r->lvi;
723 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
724 break;
725 case PI_PIV:
726 case PO_PIV:
727 case MC_PIV:
728 r = &s->bm_regs[GET_BM (index)];
729 val = r->piv;
730 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
731 break;
732 case PI_CR:
733 case PO_CR:
734 case MC_CR:
735 r = &s->bm_regs[GET_BM (index)];
736 val = r->cr;
737 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
738 break;
739 case PI_SR:
740 case PO_SR:
741 case MC_SR:
742 r = &s->bm_regs[GET_BM (index)];
743 val = r->sr & 0xff;
744 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
745 break;
746 default:
747 dolog ("U nabm readb %#x -> %#x\n", addr, val);
748 break;
749 }
750 return val;
751 }
752
753 static uint32_t nabm_readw (void *opaque, uint32_t addr)
754 {
755 AC97LinkState *s = opaque;
756 AC97BusMasterRegs *r = NULL;
757 uint32_t index = addr;
758 uint32_t val = ~0U;
759
760 switch (index) {
761 case PI_SR:
762 case PO_SR:
763 case MC_SR:
764 r = &s->bm_regs[GET_BM (index)];
765 val = r->sr;
766 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
767 break;
768 case PI_PICB:
769 case PO_PICB:
770 case MC_PICB:
771 r = &s->bm_regs[GET_BM (index)];
772 val = r->picb;
773 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
774 break;
775 default:
776 dolog ("U nabm readw %#x -> %#x\n", addr, val);
777 break;
778 }
779 return val;
780 }
781
782 static uint32_t nabm_readl (void *opaque, uint32_t addr)
783 {
784 AC97LinkState *s = opaque;
785 AC97BusMasterRegs *r = NULL;
786 uint32_t index = addr;
787 uint32_t val = ~0U;
788
789 switch (index) {
790 case PI_BDBAR:
791 case PO_BDBAR:
792 case MC_BDBAR:
793 r = &s->bm_regs[GET_BM (index)];
794 val = r->bdbar;
795 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
796 break;
797 case PI_CIV:
798 case PO_CIV:
799 case MC_CIV:
800 r = &s->bm_regs[GET_BM (index)];
801 val = r->civ | (r->lvi << 8) | (r->sr << 16);
802 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
803 r->civ, r->lvi, r->sr);
804 break;
805 case PI_PICB:
806 case PO_PICB:
807 case MC_PICB:
808 r = &s->bm_regs[GET_BM (index)];
809 val = r->picb | (r->piv << 16) | (r->cr << 24);
810 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
811 val, r->picb, r->piv, r->cr);
812 break;
813 case GLOB_CNT:
814 val = s->glob_cnt;
815 dolog ("glob_cnt -> %#x\n", val);
816 break;
817 case GLOB_STA:
818 val = s->glob_sta | GS_S0CR;
819 dolog ("glob_sta -> %#x\n", val);
820 break;
821 default:
822 dolog ("U nabm readl %#x -> %#x\n", addr, val);
823 break;
824 }
825 return val;
826 }
827
828 /**
829 * Native audio bus master
830 * I/O Writes
831 */
832 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
833 {
834 AC97LinkState *s = opaque;
835 AC97BusMasterRegs *r = NULL;
836 uint32_t index = addr;
837 switch (index) {
838 case PI_LVI:
839 case PO_LVI:
840 case MC_LVI:
841 r = &s->bm_regs[GET_BM (index)];
842 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
843 r->sr &= ~(SR_DCH | SR_CELV);
844 r->civ = r->piv;
845 r->piv = (r->piv + 1) % 32;
846 fetch_bd (s, r);
847 }
848 r->lvi = val % 32;
849 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
850 break;
851 case PI_CR:
852 case PO_CR:
853 case MC_CR:
854 r = &s->bm_regs[GET_BM (index)];
855 if (val & CR_RR) {
856 reset_bm_regs (s, r);
857 }
858 else {
859 r->cr = val & CR_VALID_MASK;
860 if (!(r->cr & CR_RPBM)) {
861 voice_set_active (s, r - s->bm_regs, 0);
862 r->sr |= SR_DCH;
863 }
864 else {
865 r->civ = r->piv;
866 r->piv = (r->piv + 1) % 32;
867 fetch_bd (s, r);
868 r->sr &= ~SR_DCH;
869 voice_set_active (s, r - s->bm_regs, 1);
870 }
871 }
872 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
873 break;
874 case PI_SR:
875 case PO_SR:
876 case MC_SR:
877 r = &s->bm_regs[GET_BM (index)];
878 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
879 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
880 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
881 break;
882 default:
883 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
884 break;
885 }
886 }
887
888 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
889 {
890 AC97LinkState *s = opaque;
891 AC97BusMasterRegs *r = NULL;
892 uint32_t index = addr;
893 switch (index) {
894 case PI_SR:
895 case PO_SR:
896 case MC_SR:
897 r = &s->bm_regs[GET_BM (index)];
898 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
899 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
900 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
901 break;
902 default:
903 dolog ("U nabm writew %#x <- %#x\n", addr, val);
904 break;
905 }
906 }
907
908 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
909 {
910 AC97LinkState *s = opaque;
911 AC97BusMasterRegs *r = NULL;
912 uint32_t index = addr;
913 switch (index) {
914 case PI_BDBAR:
915 case PO_BDBAR:
916 case MC_BDBAR:
917 r = &s->bm_regs[GET_BM (index)];
918 r->bdbar = val & ~3;
919 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
920 GET_BM (index), val, r->bdbar);
921 break;
922 case GLOB_CNT:
923 if (val & GC_WR)
924 warm_reset (s);
925 if (val & GC_CR)
926 cold_reset (s);
927 if (!(val & (GC_WR | GC_CR)))
928 s->glob_cnt = val & GC_VALID_MASK;
929 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
930 break;
931 case GLOB_STA:
932 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
933 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
934 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
935 break;
936 default:
937 dolog ("U nabm writel %#x <- %#x\n", addr, val);
938 break;
939 }
940 }
941
942 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
943 int max, int *stop)
944 {
945 uint8_t tmpbuf[4096];
946 uint32_t addr = r->bd.addr;
947 uint32_t temp = r->picb << 1;
948 uint32_t written = 0;
949 int to_copy = 0;
950 temp = audio_MIN (temp, max);
951
952 if (!temp) {
953 *stop = 1;
954 return 0;
955 }
956
957 while (temp) {
958 int copied;
959 to_copy = audio_MIN (temp, sizeof (tmpbuf));
960 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
961 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
962 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
963 max, to_copy, copied);
964 if (!copied) {
965 *stop = 1;
966 break;
967 }
968 temp -= copied;
969 addr += copied;
970 written += copied;
971 }
972
973 if (!temp) {
974 if (to_copy < 4) {
975 dolog ("whoops\n");
976 s->last_samp = 0;
977 }
978 else {
979 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
980 }
981 }
982
983 r->bd.addr = addr;
984 return written;
985 }
986
987 static void write_bup (AC97LinkState *s, int elapsed)
988 {
989 dolog ("write_bup\n");
990 if (!(s->bup_flag & BUP_SET)) {
991 if (s->bup_flag & BUP_LAST) {
992 int i;
993 uint8_t *p = s->silence;
994 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
995 *(uint32_t *) p = s->last_samp;
996 }
997 }
998 else {
999 memset (s->silence, 0, sizeof (s->silence));
1000 }
1001 s->bup_flag |= BUP_SET;
1002 }
1003
1004 while (elapsed) {
1005 int temp = audio_MIN (elapsed, sizeof (s->silence));
1006 while (temp) {
1007 int copied = AUD_write (s->voice_po, s->silence, temp);
1008 if (!copied)
1009 return;
1010 temp -= copied;
1011 elapsed -= copied;
1012 }
1013 }
1014 }
1015
1016 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1017 int max, int *stop)
1018 {
1019 uint8_t tmpbuf[4096];
1020 uint32_t addr = r->bd.addr;
1021 uint32_t temp = r->picb << 1;
1022 uint32_t nread = 0;
1023 int to_copy = 0;
1024 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1025
1026 temp = audio_MIN (temp, max);
1027
1028 if (!temp) {
1029 *stop = 1;
1030 return 0;
1031 }
1032
1033 while (temp) {
1034 int acquired;
1035 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1036 acquired = AUD_read (voice, tmpbuf, to_copy);
1037 if (!acquired) {
1038 *stop = 1;
1039 break;
1040 }
1041 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1042 temp -= acquired;
1043 addr += acquired;
1044 nread += acquired;
1045 }
1046
1047 r->bd.addr = addr;
1048 return nread;
1049 }
1050
1051 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1052 {
1053 AC97BusMasterRegs *r = &s->bm_regs[index];
1054 int stop = 0;
1055
1056 if (s->invalid_freq[index]) {
1057 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1058 index, s->invalid_freq[index]);
1059 return;
1060 }
1061
1062 if (r->sr & SR_DCH) {
1063 if (r->cr & CR_RPBM) {
1064 switch (index) {
1065 case PO_INDEX:
1066 write_bup (s, elapsed);
1067 break;
1068 }
1069 }
1070 return;
1071 }
1072
1073 while ((elapsed >> 1) && !stop) {
1074 int temp;
1075
1076 if (!r->bd_valid) {
1077 dolog ("invalid bd\n");
1078 fetch_bd (s, r);
1079 }
1080
1081 if (!r->picb) {
1082 dolog ("fresh bd %d is empty %#x %#x\n",
1083 r->civ, r->bd.addr, r->bd.ctl_len);
1084 if (r->civ == r->lvi) {
1085 r->sr |= SR_DCH; /* CELV? */
1086 s->bup_flag = 0;
1087 break;
1088 }
1089 r->sr &= ~SR_CELV;
1090 r->civ = r->piv;
1091 r->piv = (r->piv + 1) % 32;
1092 fetch_bd (s, r);
1093 return;
1094 }
1095
1096 switch (index) {
1097 case PO_INDEX:
1098 temp = write_audio (s, r, elapsed, &stop);
1099 elapsed -= temp;
1100 r->picb -= (temp >> 1);
1101 break;
1102
1103 case PI_INDEX:
1104 case MC_INDEX:
1105 temp = read_audio (s, r, elapsed, &stop);
1106 elapsed -= temp;
1107 r->picb -= (temp >> 1);
1108 break;
1109 }
1110
1111 if (!r->picb) {
1112 uint32_t new_sr = r->sr & ~SR_CELV;
1113
1114 if (r->bd.ctl_len & BD_IOC) {
1115 new_sr |= SR_BCIS;
1116 }
1117
1118 if (r->civ == r->lvi) {
1119 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1120
1121 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1122 stop = 1;
1123 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1124 }
1125 else {
1126 r->civ = r->piv;
1127 r->piv = (r->piv + 1) % 32;
1128 fetch_bd (s, r);
1129 }
1130
1131 update_sr (s, r, new_sr);
1132 }
1133 }
1134 }
1135
1136 static void pi_callback (void *opaque, int avail)
1137 {
1138 transfer_audio (opaque, PI_INDEX, avail);
1139 }
1140
1141 static void mc_callback (void *opaque, int avail)
1142 {
1143 transfer_audio (opaque, MC_INDEX, avail);
1144 }
1145
1146 static void po_callback (void *opaque, int free)
1147 {
1148 transfer_audio (opaque, PO_INDEX, free);
1149 }
1150
1151 static const VMStateDescription vmstate_ac97_bm_regs = {
1152 .name = "ac97_bm_regs",
1153 .version_id = 1,
1154 .minimum_version_id = 1,
1155 .minimum_version_id_old = 1,
1156 .fields = (VMStateField []) {
1157 VMSTATE_UINT32 (bdbar, AC97BusMasterRegs),
1158 VMSTATE_UINT8 (civ, AC97BusMasterRegs),
1159 VMSTATE_UINT8 (lvi, AC97BusMasterRegs),
1160 VMSTATE_UINT16 (sr, AC97BusMasterRegs),
1161 VMSTATE_UINT16 (picb, AC97BusMasterRegs),
1162 VMSTATE_UINT8 (piv, AC97BusMasterRegs),
1163 VMSTATE_UINT8 (cr, AC97BusMasterRegs),
1164 VMSTATE_UINT32 (bd_valid, AC97BusMasterRegs),
1165 VMSTATE_UINT32 (bd.addr, AC97BusMasterRegs),
1166 VMSTATE_UINT32 (bd.ctl_len, AC97BusMasterRegs),
1167 VMSTATE_END_OF_LIST ()
1168 }
1169 };
1170
1171 static int ac97_post_load (void *opaque, int version_id)
1172 {
1173 uint8_t active[LAST_INDEX];
1174 AC97LinkState *s = opaque;
1175
1176 record_select (s, mixer_load (s, AC97_Record_Select));
1177 set_volume (s, AC97_Master_Volume_Mute,
1178 mixer_load (s, AC97_Master_Volume_Mute));
1179 set_volume (s, AC97_PCM_Out_Volume_Mute,
1180 mixer_load (s, AC97_PCM_Out_Volume_Mute));
1181 set_volume (s, AC97_Line_In_Volume_Mute,
1182 mixer_load (s, AC97_Line_In_Volume_Mute));
1183
1184 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1185 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1186 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1187 reset_voices (s, active);
1188
1189 s->bup_flag = 0;
1190 s->last_samp = 0;
1191 return 0;
1192 }
1193
1194 static bool is_version_2 (void *opaque, int version_id)
1195 {
1196 return version_id == 2;
1197 }
1198
1199 static const VMStateDescription vmstate_ac97 = {
1200 .name = "ac97",
1201 .version_id = 3,
1202 .minimum_version_id = 2,
1203 .minimum_version_id_old = 2,
1204 .post_load = ac97_post_load,
1205 .fields = (VMStateField []) {
1206 VMSTATE_PCI_DEVICE (dev, AC97LinkState),
1207 VMSTATE_UINT32 (glob_cnt, AC97LinkState),
1208 VMSTATE_UINT32 (glob_sta, AC97LinkState),
1209 VMSTATE_UINT32 (cas, AC97LinkState),
1210 VMSTATE_STRUCT_ARRAY (bm_regs, AC97LinkState, 3, 1,
1211 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1212 VMSTATE_BUFFER (mixer_data, AC97LinkState),
1213 VMSTATE_UNUSED_TEST (is_version_2, 3),
1214 VMSTATE_END_OF_LIST ()
1215 }
1216 };
1217
1218 static const MemoryRegionPortio nam_portio[] = {
1219 { 0, 256 * 1, 1, .read = nam_readb, },
1220 { 0, 256 * 2, 2, .read = nam_readw, },
1221 { 0, 256 * 4, 4, .read = nam_readl, },
1222 { 0, 256 * 1, 1, .write = nam_writeb, },
1223 { 0, 256 * 2, 2, .write = nam_writew, },
1224 { 0, 256 * 4, 4, .write = nam_writel, },
1225 PORTIO_END_OF_LIST (),
1226 };
1227
1228 static const MemoryRegionOps ac97_io_nam_ops = {
1229 .old_portio = nam_portio,
1230 };
1231
1232 static const MemoryRegionPortio nabm_portio[] = {
1233 { 0, 64 * 1, 1, .read = nabm_readb, },
1234 { 0, 64 * 2, 2, .read = nabm_readw, },
1235 { 0, 64 * 4, 4, .read = nabm_readl, },
1236 { 0, 64 * 1, 1, .write = nabm_writeb, },
1237 { 0, 64 * 2, 2, .write = nabm_writew, },
1238 { 0, 64 * 4, 4, .write = nabm_writel, },
1239 PORTIO_END_OF_LIST ()
1240 };
1241
1242 static const MemoryRegionOps ac97_io_nabm_ops = {
1243 .old_portio = nabm_portio,
1244 };
1245
1246 static void ac97_on_reset (void *opaque)
1247 {
1248 AC97LinkState *s = opaque;
1249
1250 reset_bm_regs (s, &s->bm_regs[0]);
1251 reset_bm_regs (s, &s->bm_regs[1]);
1252 reset_bm_regs (s, &s->bm_regs[2]);
1253
1254 /*
1255 * Reset the mixer too. The Windows XP driver seems to rely on
1256 * this. At least it wants to read the vendor id before it resets
1257 * the codec manually.
1258 */
1259 mixer_reset (s);
1260 }
1261
1262 static int ac97_initfn (PCIDevice *dev)
1263 {
1264 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1265 uint8_t *c = s->dev.config;
1266
1267 /* TODO: no need to override */
1268 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1269 c[PCI_COMMAND + 1] = 0x00;
1270
1271 /* TODO: */
1272 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1273 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1274
1275 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1276
1277 /* TODO set when bar is registered. no need to override. */
1278 /* nabmar native audio mixer base address rw */
1279 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1280 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1281 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1282 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1283
1284 /* TODO set when bar is registered. no need to override. */
1285 /* nabmbar native audio bus mastering base address rw */
1286 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1287 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1288 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1289 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1290
1291 if (s->use_broken_id) {
1292 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
1293 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1294 c[PCI_SUBSYSTEM_ID] = 0x00;
1295 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1296 }
1297
1298 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1299 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1300
1301 memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
1302 memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
1303 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1304 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1305 qemu_register_reset (ac97_on_reset, s);
1306 AUD_register_card ("ac97", &s->card);
1307 ac97_on_reset (s);
1308 return 0;
1309 }
1310
1311 static int ac97_exitfn (PCIDevice *dev)
1312 {
1313 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1314
1315 memory_region_destroy (&s->io_nam);
1316 memory_region_destroy (&s->io_nabm);
1317 return 0;
1318 }
1319
1320 int ac97_init (PCIBus *bus)
1321 {
1322 pci_create_simple (bus, -1, "AC97");
1323 return 0;
1324 }
1325
1326 static Property ac97_properties[] = {
1327 DEFINE_PROP_UINT32 ("use_broken_id", AC97LinkState, use_broken_id, 0),
1328 DEFINE_PROP_END_OF_LIST (),
1329 };
1330
1331 static void ac97_class_init (ObjectClass *klass, void *data)
1332 {
1333 DeviceClass *dc = DEVICE_CLASS (klass);
1334 PCIDeviceClass *k = PCI_DEVICE_CLASS (klass);
1335
1336 k->init = ac97_initfn;
1337 k->exit = ac97_exitfn;
1338 k->vendor_id = PCI_VENDOR_ID_INTEL;
1339 k->device_id = PCI_DEVICE_ID_INTEL_82801AA_5;
1340 k->revision = 0x01;
1341 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
1342 dc->desc = "Intel 82801AA AC97 Audio";
1343 dc->vmsd = &vmstate_ac97;
1344 dc->props = ac97_properties;
1345 }
1346
1347 static TypeInfo ac97_info = {
1348 .name = "AC97",
1349 .parent = TYPE_PCI_DEVICE,
1350 .instance_size = sizeof (AC97LinkState),
1351 .class_init = ac97_class_init,
1352 };
1353
1354 static void ac97_register_types (void)
1355 {
1356 type_register_static (&ac97_info);
1357 }
1358
1359 type_init (ac97_register_types)
QEmu