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acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors
[qemu.git] / hw / i386 / acpi-build.c
blob26932b4e2cef38e1e9a7f8d5fec4941d2092f11e
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/acpi/acpi_aml_interface.h"
41 #include "hw/input/i8042.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/acpi/erst.h"
47 #include "hw/acpi/piix4.h"
48 #include "sysemu/tpm_backend.h"
49 #include "hw/rtc/mc146818rtc_regs.h"
50 #include "migration/vmstate.h"
51 #include "hw/mem/memory-device.h"
52 #include "hw/mem/nvdimm.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "hw/hyperv/vmbus-bridge.h"
56
57 /* Supported chipsets: */
58 #include "hw/southbridge/piix.h"
59 #include "hw/acpi/pcihp.h"
60 #include "hw/i386/fw_cfg.h"
61 #include "hw/i386/ich9.h"
62 #include "hw/pci/pci_bus.h"
63 #include "hw/pci-host/q35.h"
64 #include "hw/i386/x86-iommu.h"
65
66 #include "hw/acpi/aml-build.h"
67 #include "hw/acpi/utils.h"
68 #include "hw/acpi/pci.h"
69 #include "hw/acpi/cxl.h"
70
71 #include "qom/qom-qobject.h"
72 #include "hw/i386/amd_iommu.h"
73 #include "hw/i386/intel_iommu.h"
74 #include "hw/virtio/virtio-iommu.h"
75
76 #include "hw/acpi/hmat.h"
77 #include "hw/acpi/viot.h"
78 #include "hw/acpi/cxl.h"
79
80 #include CONFIG_DEVICES
81
82 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
83 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
84 * a little bit, there should be plenty of free space since the DSDT
85 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
86 */
87 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
88 #define ACPI_BUILD_ALIGN_SIZE 0x1000
89
90 #define ACPI_BUILD_TABLE_SIZE 0x20000
91
92 /* #define DEBUG_ACPI_BUILD */
93 #ifdef DEBUG_ACPI_BUILD
94 #define ACPI_BUILD_DPRINTF(fmt, ...) \
95 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
96 #else
97 #define ACPI_BUILD_DPRINTF(fmt, ...)
98 #endif
99
100 typedef struct AcpiPmInfo {
101 bool s3_disabled;
102 bool s4_disabled;
103 bool pcihp_bridge_en;
104 bool smi_on_cpuhp;
105 bool smi_on_cpu_unplug;
106 bool pcihp_root_en;
107 uint8_t s4_val;
108 AcpiFadtData fadt;
109 uint16_t cpu_hp_io_base;
110 uint16_t pcihp_io_base;
111 uint16_t pcihp_io_len;
112 } AcpiPmInfo;
113
114 typedef struct AcpiMiscInfo {
115 bool is_piix4;
116 bool has_hpet;
117 #ifdef CONFIG_TPM
118 TPMVersion tpm_version;
119 #endif
120 const unsigned char *dsdt_code;
121 unsigned dsdt_size;
122 } AcpiMiscInfo;
123
124 typedef struct AcpiBuildPciBusHotplugState {
125 GArray *device_table;
126 GArray *notify_table;
127 struct AcpiBuildPciBusHotplugState *parent;
128 bool pcihp_bridge_en;
129 } AcpiBuildPciBusHotplugState;
130
131 typedef struct FwCfgTPMConfig {
132 uint32_t tpmppi_address;
133 uint8_t tpm_version;
134 uint8_t tpmppi_version;
135 } QEMU_PACKED FwCfgTPMConfig;
136
137 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
138
139 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
140 .space_id = AML_AS_SYSTEM_IO,
141 .address = NVDIMM_ACPI_IO_BASE,
142 .bit_width = NVDIMM_ACPI_IO_LEN << 3
143 };
144
145 static void init_common_fadt_data(MachineState *ms, Object *o,
146 AcpiFadtData *data)
147 {
148 X86MachineState *x86ms = X86_MACHINE(ms);
149 /*
150 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
151 * behavior for compatibility irrelevant to smm_enabled, which doesn't
152 * comforms to ACPI spec.
153 */
154 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
155 true : x86_machine_is_smm_enabled(x86ms);
156 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
157 AmlAddressSpace as = AML_AS_SYSTEM_IO;
158 AcpiFadtData fadt = {
159 .rev = 3,
160 .flags =
161 (1 << ACPI_FADT_F_WBINVD) |
162 (1 << ACPI_FADT_F_PROC_C1) |
163 (1 << ACPI_FADT_F_SLP_BUTTON) |
164 (1 << ACPI_FADT_F_RTC_S4) |
165 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
166 /* APIC destination mode ("Flat Logical") has an upper limit of 8
167 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
168 * used
169 */
170 ((ms->smp.max_cpus > 8) ?
171 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
172 .int_model = 1 /* Multiple APIC */,
173 .rtc_century = RTC_CENTURY,
174 .plvl2_lat = 0xfff /* C2 state not supported */,
175 .plvl3_lat = 0xfff /* C3 state not supported */,
176 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
177 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
178 .acpi_enable_cmd =
179 smm_enabled ?
180 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
181 0,
182 .acpi_disable_cmd =
183 smm_enabled ?
184 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
185 0,
186 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
187 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
188 .address = io + 0x04 },
189 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
190 .gpe0_blk = { .space_id = as, .bit_width =
191 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
192 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
193 },
194 };
195
196 /*
197 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
198 * Flags, bit offset 1 - 8042.
199 */
200 fadt.iapc_boot_arch = iapc_boot_arch_8042();
201
202 *data = fadt;
203 }
204
205 static Object *object_resolve_type_unambiguous(const char *typename)
206 {
207 bool ambig;
208 Object *o = object_resolve_path_type("", typename, &ambig);
209
210 if (ambig || !o) {
211 return NULL;
212 }
213 return o;
214 }
215
216 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
217 {
218 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
219 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
220 Object *obj = piix ? piix : lpc;
221 QObject *o;
222 pm->cpu_hp_io_base = 0;
223 pm->pcihp_io_base = 0;
224 pm->pcihp_io_len = 0;
225 pm->smi_on_cpuhp = false;
226 pm->smi_on_cpu_unplug = false;
227
228 assert(obj);
229 init_common_fadt_data(machine, obj, &pm->fadt);
230 if (piix) {
231 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
232 pm->fadt.rev = 1;
233 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
234 }
235 if (lpc) {
236 uint64_t smi_features = object_property_get_uint(lpc,
237 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
238 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
239 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
240 pm->fadt.reset_reg = r;
241 pm->fadt.reset_val = 0xf;
242 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
243 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
244 pm->smi_on_cpuhp =
245 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
246 pm->smi_on_cpu_unplug =
247 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
248 }
249 pm->pcihp_io_base =
250 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
251 pm->pcihp_io_len =
252 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
253
254 /* The above need not be conditional on machine type because the reset port
255 * happens to be the same on PIIX (pc) and ICH9 (q35). */
256 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
257
258 /* Fill in optional s3/s4 related properties */
259 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
260 if (o) {
261 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
262 } else {
263 pm->s3_disabled = false;
264 }
265 qobject_unref(o);
266 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
267 if (o) {
268 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
269 } else {
270 pm->s4_disabled = false;
271 }
272 qobject_unref(o);
273 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
274 if (o) {
275 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
276 } else {
277 pm->s4_val = false;
278 }
279 qobject_unref(o);
280
281 pm->pcihp_bridge_en =
282 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
283 NULL);
284 pm->pcihp_root_en =
285 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
286 NULL);
287 }
288
289 static void acpi_get_misc_info(AcpiMiscInfo *info)
290 {
291 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
292 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
293 assert(!!piix != !!lpc);
294
295 if (piix) {
296 info->is_piix4 = true;
297 }
298 if (lpc) {
299 info->is_piix4 = false;
300 }
301
302 info->has_hpet = hpet_find();
303 #ifdef CONFIG_TPM
304 info->tpm_version = tpm_get_version(tpm_find());
305 #endif
306 }
307
308 /*
309 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
310 * On i386 arch we only have two pci hosts, so we can look only for them.
311 */
312 Object *acpi_get_i386_pci_host(void)
313 {
314 PCIHostState *host;
315
316 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
317 if (!host) {
318 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
319 }
320
321 return OBJECT(host);
322 }
323
324 static void acpi_get_pci_holes(Range *hole, Range *hole64)
325 {
326 Object *pci_host;
327
328 pci_host = acpi_get_i386_pci_host();
329
330 if (!pci_host) {
331 return;
332 }
333
334 range_set_bounds1(hole,
335 object_property_get_uint(pci_host,
336 PCI_HOST_PROP_PCI_HOLE_START,
337 NULL),
338 object_property_get_uint(pci_host,
339 PCI_HOST_PROP_PCI_HOLE_END,
340 NULL));
341 range_set_bounds1(hole64,
342 object_property_get_uint(pci_host,
343 PCI_HOST_PROP_PCI_HOLE64_START,
344 NULL),
345 object_property_get_uint(pci_host,
346 PCI_HOST_PROP_PCI_HOLE64_END,
347 NULL));
348 }
349
350 static void acpi_align_size(GArray *blob, unsigned align)
351 {
352 /* Align size to multiple of given size. This reduces the chance
353 * we need to change size in the future (breaking cross version migration).
354 */
355 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
356 }
357
358 /*
359 * ACPI spec 1.0b,
360 * 5.2.6 Firmware ACPI Control Structure
361 */
362 static void
363 build_facs(GArray *table_data)
364 {
365 const char *sig = "FACS";
366 const uint8_t reserved[40] = {};
367
368 g_array_append_vals(table_data, sig, 4); /* Signature */
369 build_append_int_noprefix(table_data, 64, 4); /* Length */
370 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
371 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
372 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
373 build_append_int_noprefix(table_data, 0, 4); /* Flags */
374 g_array_append_vals(table_data, reserved, 40); /* Reserved */
375 }
376
377 Aml *aml_pci_device_dsm(void)
378 {
379 Aml *method;
380
381 method = aml_method("_DSM", 4, AML_SERIALIZED);
382 {
383 Aml *params = aml_local(0);
384 Aml *pkg = aml_package(2);
385 aml_append(pkg, aml_name("BSEL"));
386 aml_append(pkg, aml_name("ASUN"));
387 aml_append(method, aml_store(pkg, params));
388 aml_append(method,
389 aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
390 aml_arg(2), aml_arg(3), params))
391 );
392 }
393 return method;
394 }
395
396 static void build_append_pcihp_notify_entry(Aml *method, int slot)
397 {
398 Aml *if_ctx;
399 int32_t devfn = PCI_DEVFN(slot, 0);
400
401 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
402 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
403 aml_append(method, if_ctx);
404 }
405
406 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
407 bool pcihp_bridge_en)
408 {
409 Aml *dev, *notify_method = NULL, *method;
410 QObject *bsel;
411 PCIBus *sec;
412 int devfn;
413
414 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
415 if (bsel) {
416 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
417
418 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
419 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
420 }
421
422 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
423 DeviceClass *dc;
424 PCIDeviceClass *pc;
425 PCIDevice *pdev = bus->devices[devfn];
426 int slot = PCI_SLOT(devfn);
427 int func = PCI_FUNC(devfn);
428 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
429 int adr = slot << 16 | func;
430 bool hotpluggbale_slot = false;
431 bool bridge_in_acpi = false;
432 bool cold_plugged_bridge = false;
433
434 if (pdev) {
435 pc = PCI_DEVICE_GET_CLASS(pdev);
436 dc = DEVICE_GET_CLASS(pdev);
437
438 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
439 continue;
440 }
441
442 /*
443 * Cold plugged bridges aren't themselves hot-pluggable.
444 * Hotplugged bridges *are* hot-pluggable.
445 */
446 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
447 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
448
449 hotpluggbale_slot = bsel && dc->hotpluggable &&
450 !cold_plugged_bridge;
451
452 /*
453 * allow describing coldplugged bridges in ACPI even if they are not
454 * on function 0, as they are not unpluggable, for all other devices
455 * generate description only for function 0 per slot
456 */
457 if (func && !bridge_in_acpi) {
458 continue;
459 }
460 } else {
461 /*
462 * hotplug is supported only for non-multifunction device
463 * so generate device description only for function 0
464 */
465 if (bsel && !func) {
466 if (pci_bus_is_express(bus) && slot > 0) {
467 break;
468 }
469 /* mark it as empty hotpluggable slot */
470 hotpluggbale_slot = true;
471 } else {
472 continue;
473 }
474 }
475
476 /* start to compose PCI device descriptor */
477 dev = aml_device("S%.02X", devfn);
478 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
479
480 if (bsel) {
481 /*
482 * Can't declare _SUN here for every device as it changes 'slot'
483 * enumeration order in linux kernel, so use another variable for it
484 */
485 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
486 aml_append(dev, aml_pci_device_dsm());
487 }
488
489 call_dev_aml_func(DEVICE(pdev), dev);
490
491 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
492 if (bridge_in_acpi) {
493 /*
494 * device is coldplugged bridge,
495 * add child device descriptions into its scope
496 */
497 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
498
499 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
500 }
501
502 if (hotpluggbale_slot) {
503 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
504 /* add _EJ0 to make slot hotpluggable */
505 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
506 aml_append(method,
507 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
508 );
509 aml_append(dev, method);
510
511 build_append_pcihp_notify_entry(notify_method, slot);
512 }
513
514 /* device descriptor has been composed, add it into parent context */
515 aml_append(parent_scope, dev);
516 }
517
518 if (bsel) {
519 aml_append(parent_scope, notify_method);
520 }
521
522 /* Append PCNT method to notify about events on local and child buses.
523 * Add this method for root bus only when hotplug is enabled since DSDT
524 * expects it.
525 */
526 if (bsel || pcihp_bridge_en) {
527 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
528
529 /* If bus supports hotplug select it and notify about local events */
530 if (bsel) {
531 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
532
533 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
534 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
535 aml_int(1))); /* Device Check */
536 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
537 aml_int(3))); /* Eject Request */
538 }
539
540 /* Notify about child bus events in any case */
541 if (pcihp_bridge_en) {
542 QLIST_FOREACH(sec, &bus->child, sibling) {
543 if (pci_bus_is_root(sec)) {
544 continue;
545 }
546
547 aml_append(method, aml_name("^S%.02X.PCNT",
548 sec->parent_dev->devfn));
549 }
550 }
551
552 aml_append(parent_scope, method);
553 }
554 qobject_unref(bsel);
555 }
556
557 static Aml *aml_pci_pdsm(void)
558 {
559 Aml *method, *UUID, *ifctx, *ifctx1;
560 Aml *ret = aml_local(0);
561 Aml *caps = aml_local(1);
562 Aml *acpi_index = aml_local(2);
563 Aml *zero = aml_int(0);
564 Aml *one = aml_int(1);
565 Aml *func = aml_arg(2);
566 Aml *rev = aml_arg(1);
567 Aml *params = aml_arg(4);
568 Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
569 Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
570
571 method = aml_method("PDSM", 5, AML_SERIALIZED);
572
573 /* get supported functions */
574 ifctx = aml_if(aml_equal(func, zero));
575 {
576 uint8_t byte_list[1] = { 0 }; /* nothing supported yet */
577 aml_append(ifctx, aml_store(aml_buffer(1, byte_list), ret));
578 aml_append(ifctx, aml_store(zero, caps));
579
580 /*
581 * PCI Firmware Specification 3.1
582 * 4.6. _DSM Definitions for PCI
583 */
584 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
585 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(0), UUID)));
586 {
587 /* call is for unsupported UUID, bail out */
588 aml_append(ifctx1, aml_return(ret));
589 }
590 aml_append(ifctx, ifctx1);
591
592 ifctx1 = aml_if(aml_lless(rev, aml_int(2)));
593 {
594 /* call is for unsupported REV, bail out */
595 aml_append(ifctx1, aml_return(ret));
596 }
597 aml_append(ifctx, ifctx1);
598
599 aml_append(ifctx,
600 aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
601 /*
602 * advertise function 7 if device has acpi-index
603 * acpi_index values:
604 * 0: not present (default value)
605 * FFFFFFFF: not supported (old QEMU without PIDX reg)
606 * other: device's acpi-index
607 */
608 ifctx1 = aml_if(aml_lnot(
609 aml_or(aml_equal(acpi_index, zero),
610 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
611 ));
612 {
613 /* have supported functions */
614 aml_append(ifctx1, aml_or(caps, one, caps));
615 /* support for function 7 */
616 aml_append(ifctx1,
617 aml_or(caps, aml_shiftleft(one, aml_int(7)), caps));
618 }
619 aml_append(ifctx, ifctx1);
620
621 aml_append(ifctx, aml_store(caps, aml_index(ret, zero)));
622 aml_append(ifctx, aml_return(ret));
623 }
624 aml_append(method, ifctx);
625
626 /* handle specific functions requests */
627 /*
628 * PCI Firmware Specification 3.1
629 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
630 * Operating Systems
631 */
632 ifctx = aml_if(aml_equal(func, aml_int(7)));
633 {
634 Aml *pkg = aml_package(2);
635
636 aml_append(pkg, zero);
637 /*
638 * optional, if not impl. should return null string
639 */
640 aml_append(pkg, aml_string("%s", ""));
641 aml_append(ifctx, aml_store(pkg, ret));
642
643 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
644 /*
645 * update acpi-index to actual value
646 */
647 aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
648 aml_append(ifctx, aml_return(ret));
649 }
650
651 aml_append(method, ifctx);
652 return method;
653 }
654
655 /**
656 * build_prt_entry:
657 * @link_name: link name for PCI route entry
658 *
659 * build AML package containing a PCI route entry for @link_name
660 */
661 static Aml *build_prt_entry(const char *link_name)
662 {
663 Aml *a_zero = aml_int(0);
664 Aml *pkg = aml_package(4);
665 aml_append(pkg, a_zero);
666 aml_append(pkg, a_zero);
667 aml_append(pkg, aml_name("%s", link_name));
668 aml_append(pkg, a_zero);
669 return pkg;
670 }
671
672 /*
673 * initialize_route - Initialize the interrupt routing rule
674 * through a specific LINK:
675 * if (lnk_idx == idx)
676 * route using link 'link_name'
677 */
678 static Aml *initialize_route(Aml *route, const char *link_name,
679 Aml *lnk_idx, int idx)
680 {
681 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
682 Aml *pkg = build_prt_entry(link_name);
683
684 aml_append(if_ctx, aml_store(pkg, route));
685
686 return if_ctx;
687 }
688
689 /*
690 * build_prt - Define interrupt rounting rules
691 *
692 * Returns an array of 128 routes, one for each device,
693 * based on device location.
694 * The main goal is to equaly distribute the interrupts
695 * over the 4 existing ACPI links (works only for i440fx).
696 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
697 *
698 */
699 static Aml *build_prt(bool is_pci0_prt)
700 {
701 Aml *method, *while_ctx, *pin, *res;
702
703 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
704 res = aml_local(0);
705 pin = aml_local(1);
706 aml_append(method, aml_store(aml_package(128), res));
707 aml_append(method, aml_store(aml_int(0), pin));
708
709 /* while (pin < 128) */
710 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
711 {
712 Aml *slot = aml_local(2);
713 Aml *lnk_idx = aml_local(3);
714 Aml *route = aml_local(4);
715
716 /* slot = pin >> 2 */
717 aml_append(while_ctx,
718 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
719 /* lnk_idx = (slot + pin) & 3 */
720 aml_append(while_ctx,
721 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
722 lnk_idx));
723
724 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
725 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
726 if (is_pci0_prt) {
727 Aml *if_device_1, *if_pin_4, *else_pin_4;
728
729 /* device 1 is the power-management device, needs SCI */
730 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
731 {
732 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
733 {
734 aml_append(if_pin_4,
735 aml_store(build_prt_entry("LNKS"), route));
736 }
737 aml_append(if_device_1, if_pin_4);
738 else_pin_4 = aml_else();
739 {
740 aml_append(else_pin_4,
741 aml_store(build_prt_entry("LNKA"), route));
742 }
743 aml_append(if_device_1, else_pin_4);
744 }
745 aml_append(while_ctx, if_device_1);
746 } else {
747 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
748 }
749 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
750 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
751
752 /* route[0] = 0x[slot]FFFF */
753 aml_append(while_ctx,
754 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
755 NULL),
756 aml_index(route, aml_int(0))));
757 /* route[1] = pin & 3 */
758 aml_append(while_ctx,
759 aml_store(aml_and(pin, aml_int(3), NULL),
760 aml_index(route, aml_int(1))));
761 /* res[pin] = route */
762 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
763 /* pin++ */
764 aml_append(while_ctx, aml_increment(pin));
765 }
766 aml_append(method, while_ctx);
767 /* return res*/
768 aml_append(method, aml_return(res));
769
770 return method;
771 }
772
773 static void build_hpet_aml(Aml *table)
774 {
775 Aml *crs;
776 Aml *field;
777 Aml *method;
778 Aml *if_ctx;
779 Aml *scope = aml_scope("_SB");
780 Aml *dev = aml_device("HPET");
781 Aml *zero = aml_int(0);
782 Aml *id = aml_local(0);
783 Aml *period = aml_local(1);
784
785 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
786 aml_append(dev, aml_name_decl("_UID", zero));
787
788 aml_append(dev,
789 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
790 HPET_LEN));
791 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
792 aml_append(field, aml_named_field("VEND", 32));
793 aml_append(field, aml_named_field("PRD", 32));
794 aml_append(dev, field);
795
796 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
797 aml_append(method, aml_store(aml_name("VEND"), id));
798 aml_append(method, aml_store(aml_name("PRD"), period));
799 aml_append(method, aml_shiftright(id, aml_int(16), id));
800 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
801 aml_equal(id, aml_int(0xffff))));
802 {
803 aml_append(if_ctx, aml_return(zero));
804 }
805 aml_append(method, if_ctx);
806
807 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
808 aml_lgreater(period, aml_int(100000000))));
809 {
810 aml_append(if_ctx, aml_return(zero));
811 }
812 aml_append(method, if_ctx);
813
814 aml_append(method, aml_return(aml_int(0x0F)));
815 aml_append(dev, method);
816
817 crs = aml_resource_template();
818 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
819 aml_append(dev, aml_name_decl("_CRS", crs));
820
821 aml_append(scope, dev);
822 aml_append(table, scope);
823 }
824
825 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
826 {
827 Aml *dev;
828 Aml *method;
829 Aml *crs;
830
831 dev = aml_device("VMBS");
832 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
833 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
834 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
835 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
836
837 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
838 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
839 aml_name("STA")));
840 aml_append(dev, method);
841
842 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
843 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
844 aml_name("STA")));
845 aml_append(dev, method);
846
847 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
848 aml_append(method, aml_return(aml_name("STA")));
849 aml_append(dev, method);
850
851 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
852
853 crs = aml_resource_template();
854 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
855 aml_append(dev, aml_name_decl("_CRS", crs));
856
857 return dev;
858 }
859
860 static void build_dbg_aml(Aml *table)
861 {
862 Aml *field;
863 Aml *method;
864 Aml *while_ctx;
865 Aml *scope = aml_scope("\\");
866 Aml *buf = aml_local(0);
867 Aml *len = aml_local(1);
868 Aml *idx = aml_local(2);
869
870 aml_append(scope,
871 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
872 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
873 aml_append(field, aml_named_field("DBGB", 8));
874 aml_append(scope, field);
875
876 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
877
878 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
879 aml_append(method, aml_to_buffer(buf, buf));
880 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
881 aml_append(method, aml_store(aml_int(0), idx));
882
883 while_ctx = aml_while(aml_lless(idx, len));
884 aml_append(while_ctx,
885 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
886 aml_append(while_ctx, aml_increment(idx));
887 aml_append(method, while_ctx);
888
889 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
890 aml_append(scope, method);
891
892 aml_append(table, scope);
893 }
894
895 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
896 {
897 Aml *dev;
898 Aml *crs;
899 Aml *method;
900 uint32_t irqs[] = {5, 10, 11};
901
902 dev = aml_device("%s", name);
903 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
904 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
905
906 crs = aml_resource_template();
907 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
908 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
909 aml_append(dev, aml_name_decl("_PRS", crs));
910
911 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
912 aml_append(method, aml_return(aml_call1("IQST", reg)));
913 aml_append(dev, method);
914
915 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
916 aml_append(method, aml_or(reg, aml_int(0x80), reg));
917 aml_append(dev, method);
918
919 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
920 aml_append(method, aml_return(aml_call1("IQCR", reg)));
921 aml_append(dev, method);
922
923 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
924 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
925 aml_append(method, aml_store(aml_name("PRRI"), reg));
926 aml_append(dev, method);
927
928 return dev;
929 }
930
931 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
932 {
933 Aml *dev;
934 Aml *crs;
935 Aml *method;
936 uint32_t irqs;
937
938 dev = aml_device("%s", name);
939 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
940 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
941
942 crs = aml_resource_template();
943 irqs = gsi;
944 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
945 AML_SHARED, &irqs, 1));
946 aml_append(dev, aml_name_decl("_PRS", crs));
947
948 aml_append(dev, aml_name_decl("_CRS", crs));
949
950 /*
951 * _DIS can be no-op because the interrupt cannot be disabled.
952 */
953 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
954 aml_append(dev, method);
955
956 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
957 aml_append(dev, method);
958
959 return dev;
960 }
961
962 /* _CRS method - get current settings */
963 static Aml *build_iqcr_method(bool is_piix4)
964 {
965 Aml *if_ctx;
966 uint32_t irqs;
967 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
968 Aml *crs = aml_resource_template();
969
970 irqs = 0;
971 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
972 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
973 aml_append(method, aml_name_decl("PRR0", crs));
974
975 aml_append(method,
976 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
977
978 if (is_piix4) {
979 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
980 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
981 aml_append(method, if_ctx);
982 } else {
983 aml_append(method,
984 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
985 aml_name("PRRI")));
986 }
987
988 aml_append(method, aml_return(aml_name("PRR0")));
989 return method;
990 }
991
992 /* _STA method - get status */
993 static Aml *build_irq_status_method(void)
994 {
995 Aml *if_ctx;
996 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
997
998 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
999 aml_append(if_ctx, aml_return(aml_int(0x09)));
1000 aml_append(method, if_ctx);
1001 aml_append(method, aml_return(aml_int(0x0B)));
1002 return method;
1003 }
1004
1005 static void build_piix4_pci0_int(Aml *table)
1006 {
1007 Aml *dev;
1008 Aml *crs;
1009 Aml *field;
1010 Aml *method;
1011 uint32_t irqs;
1012 Aml *sb_scope = aml_scope("_SB");
1013 Aml *pci0_scope = aml_scope("PCI0");
1014
1015 aml_append(pci0_scope, build_prt(true));
1016 aml_append(sb_scope, pci0_scope);
1017
1018 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1019 aml_append(field, aml_named_field("PRQ0", 8));
1020 aml_append(field, aml_named_field("PRQ1", 8));
1021 aml_append(field, aml_named_field("PRQ2", 8));
1022 aml_append(field, aml_named_field("PRQ3", 8));
1023 aml_append(sb_scope, field);
1024
1025 aml_append(sb_scope, build_irq_status_method());
1026 aml_append(sb_scope, build_iqcr_method(true));
1027
1028 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1029 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1030 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1031 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1032
1033 dev = aml_device("LNKS");
1034 {
1035 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1036 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1037
1038 crs = aml_resource_template();
1039 irqs = 9;
1040 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1041 AML_ACTIVE_HIGH, AML_SHARED,
1042 &irqs, 1));
1043 aml_append(dev, aml_name_decl("_PRS", crs));
1044
1045 /* The SCI cannot be disabled and is always attached to GSI 9,
1046 * so these are no-ops. We only need this link to override the
1047 * polarity to active high and match the content of the MADT.
1048 */
1049 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1050 aml_append(method, aml_return(aml_int(0x0b)));
1051 aml_append(dev, method);
1052
1053 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1054 aml_append(dev, method);
1055
1056 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1057 aml_append(method, aml_return(aml_name("_PRS")));
1058 aml_append(dev, method);
1059
1060 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1061 aml_append(dev, method);
1062 }
1063 aml_append(sb_scope, dev);
1064
1065 aml_append(table, sb_scope);
1066 }
1067
1068 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1069 {
1070 int i;
1071 int head;
1072 Aml *pkg;
1073 char base = name[3] < 'E' ? 'A' : 'E';
1074 char *s = g_strdup(name);
1075 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1076
1077 assert(strlen(s) == 4);
1078
1079 head = name[3] - base;
1080 for (i = 0; i < 4; i++) {
1081 if (head + i > 3) {
1082 head = i * -1;
1083 }
1084 s[3] = base + head + i;
1085 pkg = aml_package(4);
1086 aml_append(pkg, a_nr);
1087 aml_append(pkg, aml_int(i));
1088 aml_append(pkg, aml_name("%s", s));
1089 aml_append(pkg, aml_int(0));
1090 aml_append(ctx, pkg);
1091 }
1092 g_free(s);
1093 }
1094
1095 static Aml *build_q35_routing_table(const char *str)
1096 {
1097 int i;
1098 Aml *pkg;
1099 char *name = g_strdup_printf("%s ", str);
1100
1101 pkg = aml_package(128);
1102 for (i = 0; i < 0x18; i++) {
1103 name[3] = 'E' + (i & 0x3);
1104 append_q35_prt_entry(pkg, i, name);
1105 }
1106
1107 name[3] = 'E';
1108 append_q35_prt_entry(pkg, 0x18, name);
1109
1110 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1111 for (i = 0x0019; i < 0x1e; i++) {
1112 name[3] = 'A';
1113 append_q35_prt_entry(pkg, i, name);
1114 }
1115
1116 /* PCIe->PCI bridge. use PIRQ[E-H] */
1117 name[3] = 'E';
1118 append_q35_prt_entry(pkg, 0x1e, name);
1119 name[3] = 'A';
1120 append_q35_prt_entry(pkg, 0x1f, name);
1121
1122 g_free(name);
1123 return pkg;
1124 }
1125
1126 static void build_q35_pci0_int(Aml *table)
1127 {
1128 Aml *field;
1129 Aml *method;
1130 Aml *sb_scope = aml_scope("_SB");
1131 Aml *pci0_scope = aml_scope("PCI0");
1132
1133 /* Zero => PIC mode, One => APIC Mode */
1134 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1135 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1136 {
1137 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1138 }
1139 aml_append(table, method);
1140
1141 aml_append(pci0_scope,
1142 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1143 aml_append(pci0_scope,
1144 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1145
1146 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1147 {
1148 Aml *if_ctx;
1149 Aml *else_ctx;
1150
1151 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1152 section 6.2.8.1 */
1153 /* Note: we provide the same info as the PCI routing
1154 table of the Bochs BIOS */
1155 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1156 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1157 aml_append(method, if_ctx);
1158 else_ctx = aml_else();
1159 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1160 aml_append(method, else_ctx);
1161 }
1162 aml_append(pci0_scope, method);
1163 aml_append(sb_scope, pci0_scope);
1164
1165 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1166 aml_append(field, aml_named_field("PRQA", 8));
1167 aml_append(field, aml_named_field("PRQB", 8));
1168 aml_append(field, aml_named_field("PRQC", 8));
1169 aml_append(field, aml_named_field("PRQD", 8));
1170 aml_append(field, aml_reserved_field(0x20));
1171 aml_append(field, aml_named_field("PRQE", 8));
1172 aml_append(field, aml_named_field("PRQF", 8));
1173 aml_append(field, aml_named_field("PRQG", 8));
1174 aml_append(field, aml_named_field("PRQH", 8));
1175 aml_append(sb_scope, field);
1176
1177 aml_append(sb_scope, build_irq_status_method());
1178 aml_append(sb_scope, build_iqcr_method(false));
1179
1180 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1181 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1182 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1183 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1184 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1185 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1186 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1187 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1188
1189 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1190 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1191 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1192 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1193 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1194 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1195 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1196 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1197
1198 aml_append(table, sb_scope);
1199 }
1200
1201 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1202 {
1203 Aml *dev;
1204 Aml *resource_template;
1205
1206 /* DRAM controller */
1207 dev = aml_device("DRAC");
1208 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1209
1210 resource_template = aml_resource_template();
1211 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1212 aml_append(resource_template,
1213 aml_qword_memory(AML_POS_DECODE,
1214 AML_MIN_FIXED,
1215 AML_MAX_FIXED,
1216 AML_NON_CACHEABLE,
1217 AML_READ_WRITE,
1218 0x0000000000000000,
1219 mcfg->base,
1220 mcfg->base + mcfg->size - 1,
1221 0x0000000000000000,
1222 mcfg->size));
1223 } else {
1224 aml_append(resource_template,
1225 aml_dword_memory(AML_POS_DECODE,
1226 AML_MIN_FIXED,
1227 AML_MAX_FIXED,
1228 AML_NON_CACHEABLE,
1229 AML_READ_WRITE,
1230 0x0000000000000000,
1231 mcfg->base,
1232 mcfg->base + mcfg->size - 1,
1233 0x0000000000000000,
1234 mcfg->size));
1235 }
1236 aml_append(dev, aml_name_decl("_CRS", resource_template));
1237
1238 return dev;
1239 }
1240
1241 static void build_q35_isa_bridge(Aml *table)
1242 {
1243 Aml *dev;
1244 Aml *scope;
1245 Object *obj;
1246 bool ambiguous;
1247
1248 /*
1249 * temporarily fish out isa bridge, build_q35_isa_bridge() will be dropped
1250 * once PCI is converted to AcpiDevAmlIf and would be ble to generate
1251 * AML for bridge itself
1252 */
1253 obj = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambiguous);
1254 assert(obj && !ambiguous);
1255
1256 scope = aml_scope("_SB.PCI0");
1257 dev = aml_device("ISA");
1258 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1259
1260 call_dev_aml_func(DEVICE(obj), dev);
1261 aml_append(scope, dev);
1262 aml_append(table, scope);
1263 }
1264
1265 static void build_piix4_isa_bridge(Aml *table)
1266 {
1267 Aml *dev;
1268 Aml *scope;
1269 Object *obj;
1270 bool ambiguous;
1271
1272 /*
1273 * temporarily fish out isa bridge, build_piix4_isa_bridge() will be dropped
1274 * once PCI is converted to AcpiDevAmlIf and would be ble to generate
1275 * AML for bridge itself
1276 */
1277 obj = object_resolve_path_type("", TYPE_PIIX3_PCI_DEVICE, &ambiguous);
1278 assert(obj && !ambiguous);
1279
1280 scope = aml_scope("_SB.PCI0");
1281 dev = aml_device("ISA");
1282 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1283
1284 call_dev_aml_func(DEVICE(obj), dev);
1285 aml_append(scope, dev);
1286 aml_append(table, scope);
1287 }
1288
1289 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1290 {
1291 Aml *scope;
1292 Aml *field;
1293 Aml *method;
1294
1295 scope = aml_scope("_SB.PCI0");
1296
1297 aml_append(scope,
1298 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1299 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1300 aml_append(field, aml_named_field("PCIU", 32));
1301 aml_append(field, aml_named_field("PCID", 32));
1302 aml_append(scope, field);
1303
1304 aml_append(scope,
1305 aml_operation_region("SEJ", AML_SYSTEM_IO,
1306 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1307 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1308 aml_append(field, aml_named_field("B0EJ", 32));
1309 aml_append(scope, field);
1310
1311 aml_append(scope,
1312 aml_operation_region("BNMR", AML_SYSTEM_IO,
1313 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1314 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1315 aml_append(field, aml_named_field("BNUM", 32));
1316 aml_append(field, aml_named_field("PIDX", 32));
1317 aml_append(scope, field);
1318
1319 aml_append(scope, aml_mutex("BLCK", 0));
1320
1321 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1322 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1323 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1324 aml_append(method,
1325 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1326 aml_append(method, aml_release(aml_name("BLCK")));
1327 aml_append(method, aml_return(aml_int(0)));
1328 aml_append(scope, method);
1329
1330 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1331 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1332 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1333 aml_append(method,
1334 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1335 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1336 aml_append(method, aml_release(aml_name("BLCK")));
1337 aml_append(method, aml_return(aml_local(0)));
1338 aml_append(scope, method);
1339
1340 aml_append(scope, aml_pci_pdsm());
1341
1342 aml_append(table, scope);
1343 }
1344
1345 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1346 {
1347 Aml *if_ctx;
1348 Aml *if_ctx2;
1349 Aml *else_ctx;
1350 Aml *method;
1351 Aml *a_cwd1 = aml_name("CDW1");
1352 Aml *a_ctrl = aml_local(0);
1353
1354 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1355 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1356
1357 if_ctx = aml_if(aml_equal(
1358 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1359 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1360 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1361
1362 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1363
1364 /*
1365 * Always allow native PME, AER (no dependencies)
1366 * Allow SHPC (PCI bridges can have SHPC controller)
1367 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1368 */
1369 aml_append(if_ctx, aml_and(a_ctrl,
1370 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1371
1372 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1373 /* Unknown revision */
1374 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1375 aml_append(if_ctx, if_ctx2);
1376
1377 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1378 /* Capabilities bits were masked */
1379 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1380 aml_append(if_ctx, if_ctx2);
1381
1382 /* Update DWORD3 in the buffer */
1383 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1384 aml_append(method, if_ctx);
1385
1386 else_ctx = aml_else();
1387 /* Unrecognized UUID */
1388 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1389 aml_append(method, else_ctx);
1390
1391 aml_append(method, aml_return(aml_arg(3)));
1392 return method;
1393 }
1394
1395 static void build_smb0(Aml *table, int devnr, int func)
1396 {
1397 Aml *scope = aml_scope("_SB.PCI0");
1398 Aml *dev = aml_device("SMB0");
1399 bool ambiguous;
1400 Object *obj;
1401 /*
1402 * temporarily fish out device hosting SMBUS, build_smb0 will be gone once
1403 * PCI enumeration will be switched to call_dev_aml_func()
1404 */
1405 obj = object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous);
1406 assert(obj && !ambiguous);
1407
1408 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1409 call_dev_aml_func(DEVICE(obj), dev);
1410 aml_append(scope, dev);
1411 aml_append(table, scope);
1412 }
1413
1414 static void build_acpi0017(Aml *table)
1415 {
1416 Aml *dev, *scope, *method;
1417
1418 scope = aml_scope("_SB");
1419 dev = aml_device("CXLM");
1420 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1421
1422 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1423 aml_append(method, aml_return(aml_int(0x01)));
1424 aml_append(dev, method);
1425
1426 aml_append(scope, dev);
1427 aml_append(table, scope);
1428 }
1429
1430 static void
1431 build_dsdt(GArray *table_data, BIOSLinker *linker,
1432 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1433 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1434 {
1435 CrsRangeEntry *entry;
1436 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1437 CrsRangeSet crs_range_set;
1438 PCMachineState *pcms = PC_MACHINE(machine);
1439 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1440 X86MachineState *x86ms = X86_MACHINE(machine);
1441 AcpiMcfgInfo mcfg;
1442 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1443 uint32_t nr_mem = machine->ram_slots;
1444 int root_bus_limit = 0xFF;
1445 PCIBus *bus = NULL;
1446 #ifdef CONFIG_TPM
1447 TPMIf *tpm = tpm_find();
1448 #endif
1449 bool cxl_present = false;
1450 int i;
1451 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1452 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1453 .oem_table_id = x86ms->oem_table_id };
1454
1455 acpi_table_begin(&table, table_data);
1456 dsdt = init_aml_allocator();
1457
1458 build_dbg_aml(dsdt);
1459 if (misc->is_piix4) {
1460 sb_scope = aml_scope("_SB");
1461 dev = aml_device("PCI0");
1462 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1463 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1464 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1465 aml_append(sb_scope, dev);
1466 aml_append(dsdt, sb_scope);
1467
1468 build_piix4_isa_bridge(dsdt);
1469 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1470 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1471 }
1472 build_piix4_pci0_int(dsdt);
1473 } else {
1474 sb_scope = aml_scope("_SB");
1475 dev = aml_device("PCI0");
1476 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1477 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1478 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1479 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1480 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1481 aml_append(sb_scope, dev);
1482 if (mcfg_valid) {
1483 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1484 }
1485
1486 if (pm->smi_on_cpuhp) {
1487 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1488 dev = aml_device("PCI0.SMI0");
1489 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1490 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1491 crs = aml_resource_template();
1492 aml_append(crs,
1493 aml_io(
1494 AML_DECODE16,
1495 ACPI_PORT_SMI_CMD,
1496 ACPI_PORT_SMI_CMD,
1497 1,
1498 2)
1499 );
1500 aml_append(dev, aml_name_decl("_CRS", crs));
1501 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1502 aml_int(ACPI_PORT_SMI_CMD), 2));
1503 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1504 AML_WRITE_AS_ZEROS);
1505 aml_append(field, aml_named_field("SMIC", 8));
1506 aml_append(field, aml_reserved_field(8));
1507 aml_append(dev, field);
1508 aml_append(sb_scope, dev);
1509 }
1510
1511 aml_append(dsdt, sb_scope);
1512
1513 build_q35_isa_bridge(dsdt);
1514 if (pm->pcihp_bridge_en) {
1515 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1516 }
1517 build_q35_pci0_int(dsdt);
1518 if (pcms->smbus) {
1519 build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1520 }
1521 }
1522
1523 if (misc->has_hpet) {
1524 build_hpet_aml(dsdt);
1525 }
1526
1527 if (vmbus_bridge) {
1528 sb_scope = aml_scope("_SB");
1529 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1530 aml_append(dsdt, sb_scope);
1531 }
1532
1533 if (pcmc->legacy_cpu_hotplug) {
1534 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1535 } else {
1536 CPUHotplugFeatures opts = {
1537 .acpi_1_compatible = true, .has_legacy_cphp = true,
1538 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1539 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1540 };
1541 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1542 "\\_SB.PCI0", "\\_GPE._E02");
1543 }
1544
1545 if (pcms->memhp_io_base && nr_mem) {
1546 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1547 "\\_GPE._E03", AML_SYSTEM_IO,
1548 pcms->memhp_io_base);
1549 }
1550
1551 scope = aml_scope("_GPE");
1552 {
1553 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1554
1555 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1556 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1557 aml_append(method,
1558 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1559 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1560 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1561 aml_append(scope, method);
1562 }
1563
1564 if (machine->nvdimms_state->is_enabled) {
1565 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1566 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1567 aml_int(0x80)));
1568 aml_append(scope, method);
1569 }
1570 }
1571 aml_append(dsdt, scope);
1572
1573 crs_range_set_init(&crs_range_set);
1574 bus = PC_MACHINE(machine)->bus;
1575 if (bus) {
1576 QLIST_FOREACH(bus, &bus->child, sibling) {
1577 uint8_t bus_num = pci_bus_num(bus);
1578 uint8_t numa_node = pci_bus_numa_node(bus);
1579
1580 /* look only for expander root buses */
1581 if (!pci_bus_is_root(bus)) {
1582 continue;
1583 }
1584
1585 if (bus_num < root_bus_limit) {
1586 root_bus_limit = bus_num - 1;
1587 }
1588
1589 scope = aml_scope("\\_SB");
1590
1591 if (pci_bus_is_cxl(bus)) {
1592 dev = aml_device("CL%.02X", bus_num);
1593 } else {
1594 dev = aml_device("PC%.02X", bus_num);
1595 }
1596 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1597 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1598 if (pci_bus_is_cxl(bus)) {
1599 struct Aml *pkg = aml_package(2);
1600
1601 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1602 aml_append(pkg, aml_eisaid("PNP0A08"));
1603 aml_append(pkg, aml_eisaid("PNP0A03"));
1604 aml_append(dev, aml_name_decl("_CID", pkg));
1605 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1606 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1607 build_cxl_osc_method(dev);
1608 } else if (pci_bus_is_express(bus)) {
1609 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1610 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1611
1612 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1613 aml_append(dev, build_q35_osc_method(true));
1614 } else {
1615 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1616 }
1617
1618 if (numa_node != NUMA_NODE_UNASSIGNED) {
1619 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1620 }
1621
1622 aml_append(dev, build_prt(false));
1623 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1624 0, 0, 0, 0);
1625 aml_append(dev, aml_name_decl("_CRS", crs));
1626 aml_append(scope, dev);
1627 aml_append(dsdt, scope);
1628
1629 /* Handle the ranges for the PXB expanders */
1630 if (pci_bus_is_cxl(bus)) {
1631 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1632 uint64_t base = mr->addr;
1633
1634 cxl_present = true;
1635 crs_range_insert(crs_range_set.mem_ranges, base,
1636 base + memory_region_size(mr) - 1);
1637 }
1638 }
1639 }
1640
1641 if (cxl_present) {
1642 build_acpi0017(dsdt);
1643 }
1644
1645 /*
1646 * At this point crs_range_set has all the ranges used by pci
1647 * busses *other* than PCI0. These ranges will be excluded from
1648 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1649 * too.
1650 */
1651 if (mcfg_valid) {
1652 crs_range_insert(crs_range_set.mem_ranges,
1653 mcfg.base, mcfg.base + mcfg.size - 1);
1654 }
1655
1656 scope = aml_scope("\\_SB.PCI0");
1657 /* build PCI0._CRS */
1658 crs = aml_resource_template();
1659 aml_append(crs,
1660 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1661 0x0000, 0x0, root_bus_limit,
1662 0x0000, root_bus_limit + 1));
1663 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1664
1665 aml_append(crs,
1666 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1667 AML_POS_DECODE, AML_ENTIRE_RANGE,
1668 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1669
1670 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1671 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1672 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1673 aml_append(crs,
1674 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1675 AML_POS_DECODE, AML_ENTIRE_RANGE,
1676 0x0000, entry->base, entry->limit,
1677 0x0000, entry->limit - entry->base + 1));
1678 }
1679
1680 aml_append(crs,
1681 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1682 AML_CACHEABLE, AML_READ_WRITE,
1683 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1684
1685 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1686 range_lob(pci_hole),
1687 range_upb(pci_hole));
1688 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1689 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1690 aml_append(crs,
1691 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1692 AML_NON_CACHEABLE, AML_READ_WRITE,
1693 0, entry->base, entry->limit,
1694 0, entry->limit - entry->base + 1));
1695 }
1696
1697 if (!range_is_empty(pci_hole64)) {
1698 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1699 range_lob(pci_hole64),
1700 range_upb(pci_hole64));
1701 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1702 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1703 aml_append(crs,
1704 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1705 AML_MAX_FIXED,
1706 AML_CACHEABLE, AML_READ_WRITE,
1707 0, entry->base, entry->limit,
1708 0, entry->limit - entry->base + 1));
1709 }
1710 }
1711
1712 #ifdef CONFIG_TPM
1713 if (TPM_IS_TIS_ISA(tpm_find())) {
1714 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1715 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1716 }
1717 #endif
1718 aml_append(scope, aml_name_decl("_CRS", crs));
1719
1720 /* reserve GPE0 block resources */
1721 dev = aml_device("GPE0");
1722 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1723 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1724 /* device present, functioning, decoding, not shown in UI */
1725 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1726 crs = aml_resource_template();
1727 aml_append(crs,
1728 aml_io(
1729 AML_DECODE16,
1730 pm->fadt.gpe0_blk.address,
1731 pm->fadt.gpe0_blk.address,
1732 1,
1733 pm->fadt.gpe0_blk.bit_width / 8)
1734 );
1735 aml_append(dev, aml_name_decl("_CRS", crs));
1736 aml_append(scope, dev);
1737
1738 crs_range_set_free(&crs_range_set);
1739
1740 /* reserve PCIHP resources */
1741 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1742 dev = aml_device("PHPR");
1743 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1744 aml_append(dev,
1745 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1746 /* device present, functioning, decoding, not shown in UI */
1747 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1748 crs = aml_resource_template();
1749 aml_append(crs,
1750 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1751 pm->pcihp_io_len)
1752 );
1753 aml_append(dev, aml_name_decl("_CRS", crs));
1754 aml_append(scope, dev);
1755 }
1756 aml_append(dsdt, scope);
1757
1758 /* create S3_ / S4_ / S5_ packages if necessary */
1759 scope = aml_scope("\\");
1760 if (!pm->s3_disabled) {
1761 pkg = aml_package(4);
1762 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1763 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1764 aml_append(pkg, aml_int(0)); /* reserved */
1765 aml_append(pkg, aml_int(0)); /* reserved */
1766 aml_append(scope, aml_name_decl("_S3", pkg));
1767 }
1768
1769 if (!pm->s4_disabled) {
1770 pkg = aml_package(4);
1771 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1772 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1773 aml_append(pkg, aml_int(pm->s4_val));
1774 aml_append(pkg, aml_int(0)); /* reserved */
1775 aml_append(pkg, aml_int(0)); /* reserved */
1776 aml_append(scope, aml_name_decl("_S4", pkg));
1777 }
1778
1779 pkg = aml_package(4);
1780 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1781 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1782 aml_append(pkg, aml_int(0)); /* reserved */
1783 aml_append(pkg, aml_int(0)); /* reserved */
1784 aml_append(scope, aml_name_decl("_S5", pkg));
1785 aml_append(dsdt, scope);
1786
1787 /* create fw_cfg node, unconditionally */
1788 {
1789 scope = aml_scope("\\_SB.PCI0");
1790 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1791 aml_append(dsdt, scope);
1792 }
1793
1794 sb_scope = aml_scope("\\_SB");
1795 {
1796 Object *pci_host = acpi_get_i386_pci_host();
1797
1798 if (pci_host) {
1799 PCIBus *bus = PCI_HOST_BRIDGE(pci_host)->bus;
1800 Aml *scope = aml_scope("PCI0");
1801 /* Scan all PCI buses. Generate tables to support hotplug. */
1802 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1803 aml_append(sb_scope, scope);
1804 }
1805 }
1806
1807 #ifdef CONFIG_TPM
1808 if (TPM_IS_CRB(tpm)) {
1809 dev = aml_device("TPM");
1810 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1811 aml_append(dev, aml_name_decl("_STR",
1812 aml_string("TPM 2.0 Device")));
1813 crs = aml_resource_template();
1814 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1815 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1816 aml_append(dev, aml_name_decl("_CRS", crs));
1817
1818 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1819 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1820
1821 tpm_build_ppi_acpi(tpm, dev);
1822
1823 aml_append(sb_scope, dev);
1824 }
1825 #endif
1826
1827 if (pcms->sgx_epc.size != 0) {
1828 uint64_t epc_base = pcms->sgx_epc.base;
1829 uint64_t epc_size = pcms->sgx_epc.size;
1830
1831 dev = aml_device("EPC");
1832 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1833 aml_append(dev, aml_name_decl("_STR",
1834 aml_unicode("Enclave Page Cache 1.0")));
1835 crs = aml_resource_template();
1836 aml_append(crs,
1837 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1838 AML_MAX_FIXED, AML_NON_CACHEABLE,
1839 AML_READ_WRITE, 0, epc_base,
1840 epc_base + epc_size - 1, 0, epc_size));
1841 aml_append(dev, aml_name_decl("_CRS", crs));
1842
1843 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1844 aml_append(method, aml_return(aml_int(0x0f)));
1845 aml_append(dev, method);
1846
1847 aml_append(sb_scope, dev);
1848 }
1849 aml_append(dsdt, sb_scope);
1850
1851 /* copy AML table into ACPI tables blob and patch header there */
1852 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1853 acpi_table_end(linker, &table);
1854 free_aml_allocator();
1855 }
1856
1857 /*
1858 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1859 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1860 */
1861 static void
1862 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1863 const char *oem_table_id)
1864 {
1865 AcpiTable table = { .sig = "HPET", .rev = 1,
1866 .oem_id = oem_id, .oem_table_id = oem_table_id };
1867
1868 acpi_table_begin(&table, table_data);
1869 /* Note timer_block_id value must be kept in sync with value advertised by
1870 * emulated hpet
1871 */
1872 /* Event Timer Block ID */
1873 build_append_int_noprefix(table_data, 0x8086a201, 4);
1874 /* BASE_ADDRESS */
1875 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1876 /* HPET Number */
1877 build_append_int_noprefix(table_data, 0, 1);
1878 /* Main Counter Minimum Clock_tick in Periodic Mode */
1879 build_append_int_noprefix(table_data, 0, 2);
1880 /* Page Protection And OEM Attribute */
1881 build_append_int_noprefix(table_data, 0, 1);
1882 acpi_table_end(linker, &table);
1883 }
1884
1885 #ifdef CONFIG_TPM
1886 /*
1887 * TCPA Description Table
1888 *
1889 * Following Level 00, Rev 00.37 of specs:
1890 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1891 * 7.1.2 ACPI Table Layout
1892 */
1893 static void
1894 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1895 const char *oem_id, const char *oem_table_id)
1896 {
1897 unsigned log_addr_offset;
1898 AcpiTable table = { .sig = "TCPA", .rev = 2,
1899 .oem_id = oem_id, .oem_table_id = oem_table_id };
1900
1901 acpi_table_begin(&table, table_data);
1902 /* Platform Class */
1903 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
1904 /* Log Area Minimum Length (LAML) */
1905 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
1906 /* Log Area Start Address (LASA) */
1907 log_addr_offset = table_data->len;
1908 build_append_int_noprefix(table_data, 0, 8);
1909
1910 /* allocate/reserve space for TPM log area */
1911 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1912 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1913 false /* high memory */);
1914 /* log area start address to be filled by Guest linker */
1915 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1916 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
1917
1918 acpi_table_end(linker, &table);
1919 }
1920 #endif
1921
1922 #define HOLE_640K_START (640 * KiB)
1923 #define HOLE_640K_END (1 * MiB)
1924
1925 /*
1926 * ACPI spec, Revision 3.0
1927 * 5.2.15 System Resource Affinity Table (SRAT)
1928 */
1929 static void
1930 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1931 {
1932 int i;
1933 int numa_mem_start, slots;
1934 uint64_t mem_len, mem_base, next_base;
1935 MachineClass *mc = MACHINE_GET_CLASS(machine);
1936 X86MachineState *x86ms = X86_MACHINE(machine);
1937 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1938 PCMachineState *pcms = PC_MACHINE(machine);
1939 int nb_numa_nodes = machine->numa_state->num_nodes;
1940 NodeInfo *numa_info = machine->numa_state->nodes;
1941 ram_addr_t hotpluggable_address_space_size =
1942 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1943 NULL);
1944 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
1945 .oem_table_id = x86ms->oem_table_id };
1946
1947 acpi_table_begin(&table, table_data);
1948 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
1949 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
1950
1951 for (i = 0; i < apic_ids->len; i++) {
1952 int node_id = apic_ids->cpus[i].props.node_id;
1953 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1954
1955 if (apic_id < 255) {
1956 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
1957 build_append_int_noprefix(table_data, 0, 1); /* Type */
1958 build_append_int_noprefix(table_data, 16, 1); /* Length */
1959 /* Proximity Domain [7:0] */
1960 build_append_int_noprefix(table_data, node_id, 1);
1961 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
1962 /* Flags, Table 5-36 */
1963 build_append_int_noprefix(table_data, 1, 4);
1964 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
1965 /* Proximity Domain [31:8] */
1966 build_append_int_noprefix(table_data, 0, 3);
1967 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1968 } else {
1969 /*
1970 * ACPI spec, Revision 4.0
1971 * 5.2.16.3 Processor Local x2APIC Affinity Structure
1972 */
1973 build_append_int_noprefix(table_data, 2, 1); /* Type */
1974 build_append_int_noprefix(table_data, 24, 1); /* Length */
1975 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
1976 /* Proximity Domain */
1977 build_append_int_noprefix(table_data, node_id, 4);
1978 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
1979 /* Flags, Table 5-39 */
1980 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
1981 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
1982 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
1983 }
1984 }
1985
1986 /* the memory map is a bit tricky, it contains at least one hole
1987 * from 640k-1M and possibly another one from 3.5G-4G.
1988 */
1989 next_base = 0;
1990 numa_mem_start = table_data->len;
1991
1992 for (i = 1; i < nb_numa_nodes + 1; ++i) {
1993 mem_base = next_base;
1994 mem_len = numa_info[i - 1].node_mem;
1995 next_base = mem_base + mem_len;
1996
1997 /* Cut out the 640K hole */
1998 if (mem_base <= HOLE_640K_START &&
1999 next_base > HOLE_640K_START) {
2000 mem_len -= next_base - HOLE_640K_START;
2001 if (mem_len > 0) {
2002 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2003 MEM_AFFINITY_ENABLED);
2004 }
2005
2006 /* Check for the rare case: 640K < RAM < 1M */
2007 if (next_base <= HOLE_640K_END) {
2008 next_base = HOLE_640K_END;
2009 continue;
2010 }
2011 mem_base = HOLE_640K_END;
2012 mem_len = next_base - HOLE_640K_END;
2013 }
2014
2015 /* Cut out the ACPI_PCI hole */
2016 if (mem_base <= x86ms->below_4g_mem_size &&
2017 next_base > x86ms->below_4g_mem_size) {
2018 mem_len -= next_base - x86ms->below_4g_mem_size;
2019 if (mem_len > 0) {
2020 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2021 MEM_AFFINITY_ENABLED);
2022 }
2023 mem_base = x86ms->above_4g_mem_start;
2024 mem_len = next_base - x86ms->below_4g_mem_size;
2025 next_base = mem_base + mem_len;
2026 }
2027
2028 if (mem_len > 0) {
2029 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2030 MEM_AFFINITY_ENABLED);
2031 }
2032 }
2033
2034 if (machine->nvdimms_state->is_enabled) {
2035 nvdimm_build_srat(table_data);
2036 }
2037
2038 sgx_epc_build_srat(table_data);
2039
2040 /*
2041 * TODO: this part is not in ACPI spec and current linux kernel boots fine
2042 * without these entries. But I recall there were issues the last time I
2043 * tried to remove it with some ancient guest OS, however I can't remember
2044 * what that was so keep this around for now
2045 */
2046 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
2047 for (; slots < nb_numa_nodes + 2; slots++) {
2048 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2049 }
2050
2051 /*
2052 * Entry is required for Windows to enable memory hotplug in OS
2053 * and for Linux to enable SWIOTLB when booted with less than
2054 * 4G of RAM. Windows works better if the entry sets proximity
2055 * to the highest NUMA node in the machine.
2056 * Memory devices may override proximity set by this entry,
2057 * providing _PXM method if necessary.
2058 */
2059 if (hotpluggable_address_space_size) {
2060 build_srat_memory(table_data, machine->device_memory->base,
2061 hotpluggable_address_space_size, nb_numa_nodes - 1,
2062 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2063 }
2064
2065 acpi_table_end(linker, &table);
2066 }
2067
2068 /*
2069 * Insert DMAR scope for PCI bridges and endpoint devcie
2070 */
2071 static void
2072 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2073 {
2074 const size_t device_scope_size = 6 /* device scope structure */ +
2075 2 /* 1 path entry */;
2076 GArray *scope_blob = opaque;
2077
2078 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2079 /* Dmar Scope Type: 0x02 for PCI Bridge */
2080 build_append_int_noprefix(scope_blob, 0x02, 1);
2081 } else {
2082 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2083 build_append_int_noprefix(scope_blob, 0x01, 1);
2084 }
2085
2086 /* length */
2087 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2088 /* reserved */
2089 build_append_int_noprefix(scope_blob, 0, 2);
2090 /* enumeration_id */
2091 build_append_int_noprefix(scope_blob, 0, 1);
2092 /* bus */
2093 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2094 /* device */
2095 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2096 /* function */
2097 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2098 }
2099
2100 /* For a given PCI host bridge, walk and insert DMAR scope */
2101 static int
2102 dmar_host_bridges(Object *obj, void *opaque)
2103 {
2104 GArray *scope_blob = opaque;
2105
2106 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2107 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2108
2109 if (bus && !pci_bus_bypass_iommu(bus)) {
2110 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2111 }
2112 }
2113
2114 return 0;
2115 }
2116
2117 /*
2118 * Intel ® Virtualization Technology for Directed I/O
2119 * Architecture Specification. Revision 3.3
2120 * 8.1 DMA Remapping Reporting Structure
2121 */
2122 static void
2123 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2124 const char *oem_table_id)
2125 {
2126 uint8_t dmar_flags = 0;
2127 uint8_t rsvd10[10] = {};
2128 /* Root complex IOAPIC uses one path only */
2129 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2130 2 /* 1 path entry */;
2131 X86IOMMUState *iommu = x86_iommu_get_default();
2132 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2133 GArray *scope_blob = g_array_new(false, true, 1);
2134
2135 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2136 .oem_table_id = oem_table_id };
2137
2138 /*
2139 * A PCI bus walk, for each PCI host bridge.
2140 * Insert scope for each PCI bridge and endpoint device which
2141 * is attached to a bus with iommu enabled.
2142 */
2143 object_child_foreach_recursive(object_get_root(),
2144 dmar_host_bridges, scope_blob);
2145
2146 assert(iommu);
2147 if (x86_iommu_ir_supported(iommu)) {
2148 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2149 }
2150
2151 acpi_table_begin(&table, table_data);
2152 /* Host Address Width */
2153 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2154 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2155 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2156
2157 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2158 build_append_int_noprefix(table_data, 0, 2); /* Type */
2159 /* Length */
2160 build_append_int_noprefix(table_data,
2161 16 + ioapic_scope_size + scope_blob->len, 2);
2162 /* Flags */
2163 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2164 1);
2165 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2166 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2167 /* Register Base Address */
2168 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2169
2170 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2171 * 8.3.1 (version Oct. 2014 or later). */
2172 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2173 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2174 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2175 /* Enumeration ID */
2176 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2177 /* Start Bus Number */
2178 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2179 /* Path, {Device, Function} pair */
2180 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2181 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2182
2183 /* Add scope found above */
2184 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2185 g_array_free(scope_blob, true);
2186
2187 if (iommu->dt_supported) {
2188 /* 8.5 Root Port ATS Capability Reporting Structure */
2189 build_append_int_noprefix(table_data, 2, 2); /* Type */
2190 build_append_int_noprefix(table_data, 8, 2); /* Length */
2191 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2192 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2193 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2194 }
2195
2196 acpi_table_end(linker, &table);
2197 }
2198
2199 /*
2200 * Windows ACPI Emulated Devices Table
2201 * (Version 1.0 - April 6, 2009)
2202 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2203 *
2204 * Helpful to speedup Windows guests and ignored by others.
2205 */
2206 static void
2207 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2208 const char *oem_table_id)
2209 {
2210 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2211 .oem_table_id = oem_table_id };
2212
2213 acpi_table_begin(&table, table_data);
2214 /*
2215 * Set "ACPI PM timer good" flag.
2216 *
2217 * Tells Windows guests that our ACPI PM timer is reliable in the
2218 * sense that guest can read it only once to obtain a reliable value.
2219 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2220 */
2221 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2222 acpi_table_end(linker, &table);
2223 }
2224
2225 /*
2226 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2227 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2228 */
2229 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2230
2231 /*
2232 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2233 * necessary for the PCI topology.
2234 */
2235 static void
2236 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2237 {
2238 GArray *table_data = opaque;
2239 uint32_t entry;
2240
2241 /* "Select" IVHD entry, type 0x2 */
2242 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2243 build_append_int_noprefix(table_data, entry, 4);
2244
2245 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2246 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2247 uint8_t sec = pci_bus_num(sec_bus);
2248 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2249
2250 if (pci_bus_is_express(sec_bus)) {
2251 /*
2252 * Walk the bus if there are subordinates, otherwise use a range
2253 * to cover an entire leaf bus. We could potentially also use a
2254 * range for traversed buses, but we'd need to take care not to
2255 * create both Select and Range entries covering the same device.
2256 * This is easier and potentially more compact.
2257 *
2258 * An example bare metal system seems to use Select entries for
2259 * root ports without a slot (ie. built-ins) and Range entries
2260 * when there is a slot. The same system also only hard-codes
2261 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2262 * making no effort to support nested bridges. We attempt to
2263 * be more thorough here.
2264 */
2265 if (sec == sub) { /* leaf bus */
2266 /* "Start of Range" IVHD entry, type 0x3 */
2267 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2268 build_append_int_noprefix(table_data, entry, 4);
2269 /* "End of Range" IVHD entry, type 0x4 */
2270 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2271 build_append_int_noprefix(table_data, entry, 4);
2272 } else {
2273 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2274 }
2275 } else {
2276 /*
2277 * If the secondary bus is conventional, then we need to create an
2278 * Alias range for everything downstream. The range covers the
2279 * first devfn on the secondary bus to the last devfn on the
2280 * subordinate bus. The alias target depends on legacy versus
2281 * express bridges, just as in pci_device_iommu_address_space().
2282 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2283 */
2284 uint16_t dev_id_a, dev_id_b;
2285
2286 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2287
2288 if (pci_is_express(dev) &&
2289 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2290 dev_id_b = dev_id_a;
2291 } else {
2292 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2293 }
2294
2295 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2296 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2297 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2298
2299 /* "End of Range" IVHD entry, type 0x4 */
2300 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2301 build_append_int_noprefix(table_data, entry, 4);
2302 }
2303 }
2304 }
2305
2306 /* For all PCI host bridges, walk and insert IVHD entries */
2307 static int
2308 ivrs_host_bridges(Object *obj, void *opaque)
2309 {
2310 GArray *ivhd_blob = opaque;
2311
2312 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2313 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2314
2315 if (bus && !pci_bus_bypass_iommu(bus)) {
2316 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2317 }
2318 }
2319
2320 return 0;
2321 }
2322
2323 static void
2324 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2325 const char *oem_table_id)
2326 {
2327 int ivhd_table_len = 24;
2328 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2329 GArray *ivhd_blob = g_array_new(false, true, 1);
2330 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2331 .oem_table_id = oem_table_id };
2332
2333 acpi_table_begin(&table, table_data);
2334 /* IVinfo - IO virtualization information common to all
2335 * IOMMU units in a system
2336 */
2337 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2338 /* reserved */
2339 build_append_int_noprefix(table_data, 0, 8);
2340
2341 /* IVHD definition - type 10h */
2342 build_append_int_noprefix(table_data, 0x10, 1);
2343 /* virtualization flags */
2344 build_append_int_noprefix(table_data,
2345 (1UL << 0) | /* HtTunEn */
2346 (1UL << 4) | /* iotblSup */
2347 (1UL << 6) | /* PrefSup */
2348 (1UL << 7), /* PPRSup */
2349 1);
2350
2351 /*
2352 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2353 * complete set of IVHD entries. Do this into a separate blob so that we
2354 * can calculate the total IVRS table length here and then append the new
2355 * blob further below. Fall back to an entry covering all devices, which
2356 * is sufficient when no aliases are present.
2357 */
2358 object_child_foreach_recursive(object_get_root(),
2359 ivrs_host_bridges, ivhd_blob);
2360
2361 if (!ivhd_blob->len) {
2362 /*
2363 * Type 1 device entry reporting all devices
2364 * These are 4-byte device entries currently reporting the range of
2365 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2366 */
2367 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2368 }
2369
2370 ivhd_table_len += ivhd_blob->len;
2371
2372 /*
2373 * When interrupt remapping is supported, we add a special IVHD device
2374 * for type IO-APIC.
2375 */
2376 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2377 ivhd_table_len += 8;
2378 }
2379
2380 /* IVHD length */
2381 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2382 /* DeviceID */
2383 build_append_int_noprefix(table_data, s->devid, 2);
2384 /* Capability offset */
2385 build_append_int_noprefix(table_data, s->capab_offset, 2);
2386 /* IOMMU base address */
2387 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2388 /* PCI Segment Group */
2389 build_append_int_noprefix(table_data, 0, 2);
2390 /* IOMMU info */
2391 build_append_int_noprefix(table_data, 0, 2);
2392 /* IOMMU Feature Reporting */
2393 build_append_int_noprefix(table_data,
2394 (48UL << 30) | /* HATS */
2395 (48UL << 28) | /* GATS */
2396 (1UL << 2) | /* GTSup */
2397 (1UL << 6), /* GASup */
2398 4);
2399
2400 /* IVHD entries as found above */
2401 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2402 g_array_free(ivhd_blob, TRUE);
2403
2404 /*
2405 * Add a special IVHD device type.
2406 * Refer to spec - Table 95: IVHD device entry type codes
2407 *
2408 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2409 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2410 */
2411 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2412 build_append_int_noprefix(table_data,
2413 (0x1ull << 56) | /* type IOAPIC */
2414 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2415 0x48, /* special device */
2416 8);
2417 }
2418 acpi_table_end(linker, &table);
2419 }
2420
2421 typedef
2422 struct AcpiBuildState {
2423 /* Copy of table in RAM (for patching). */
2424 MemoryRegion *table_mr;
2425 /* Is table patched? */
2426 uint8_t patched;
2427 void *rsdp;
2428 MemoryRegion *rsdp_mr;
2429 MemoryRegion *linker_mr;
2430 } AcpiBuildState;
2431
2432 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2433 {
2434 Object *pci_host;
2435 QObject *o;
2436
2437 pci_host = acpi_get_i386_pci_host();
2438 if (!pci_host) {
2439 return false;
2440 }
2441
2442 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2443 if (!o) {
2444 return false;
2445 }
2446 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2447 qobject_unref(o);
2448 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2449 return false;
2450 }
2451
2452 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2453 assert(o);
2454 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2455 qobject_unref(o);
2456 return true;
2457 }
2458
2459 static
2460 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2461 {
2462 PCMachineState *pcms = PC_MACHINE(machine);
2463 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2464 X86MachineState *x86ms = X86_MACHINE(machine);
2465 DeviceState *iommu = pcms->iommu;
2466 GArray *table_offsets;
2467 unsigned facs, dsdt, rsdt, fadt;
2468 AcpiPmInfo pm;
2469 AcpiMiscInfo misc;
2470 AcpiMcfgInfo mcfg;
2471 Range pci_hole = {}, pci_hole64 = {};
2472 uint8_t *u;
2473 size_t aml_len = 0;
2474 GArray *tables_blob = tables->table_data;
2475 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2476 Object *vmgenid_dev;
2477 char *oem_id;
2478 char *oem_table_id;
2479
2480 acpi_get_pm_info(machine, &pm);
2481 acpi_get_misc_info(&misc);
2482 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2483 acpi_get_slic_oem(&slic_oem);
2484
2485 if (slic_oem.id) {
2486 oem_id = slic_oem.id;
2487 } else {
2488 oem_id = x86ms->oem_id;
2489 }
2490
2491 if (slic_oem.table_id) {
2492 oem_table_id = slic_oem.table_id;
2493 } else {
2494 oem_table_id = x86ms->oem_table_id;
2495 }
2496
2497 table_offsets = g_array_new(false, true /* clear */,
2498 sizeof(uint32_t));
2499 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2500
2501 bios_linker_loader_alloc(tables->linker,
2502 ACPI_BUILD_TABLE_FILE, tables_blob,
2503 64 /* Ensure FACS is aligned */,
2504 false /* high memory */);
2505
2506 /*
2507 * FACS is pointed to by FADT.
2508 * We place it first since it's the only table that has alignment
2509 * requirements.
2510 */
2511 facs = tables_blob->len;
2512 build_facs(tables_blob);
2513
2514 /* DSDT is pointed to by FADT */
2515 dsdt = tables_blob->len;
2516 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2517 &pci_hole, &pci_hole64, machine);
2518
2519 /* Count the size of the DSDT and SSDT, we will need it for legacy
2520 * sizing of ACPI tables.
2521 */
2522 aml_len += tables_blob->len - dsdt;
2523
2524 /* ACPI tables pointed to by RSDT */
2525 fadt = tables_blob->len;
2526 acpi_add_table(table_offsets, tables_blob);
2527 pm.fadt.facs_tbl_offset = &facs;
2528 pm.fadt.dsdt_tbl_offset = &dsdt;
2529 pm.fadt.xdsdt_tbl_offset = &dsdt;
2530 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2531 aml_len += tables_blob->len - fadt;
2532
2533 acpi_add_table(table_offsets, tables_blob);
2534 acpi_build_madt(tables_blob, tables->linker, x86ms,
2535 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2536 x86ms->oem_table_id);
2537
2538 #ifdef CONFIG_ACPI_ERST
2539 {
2540 Object *erst_dev;
2541 erst_dev = find_erst_dev();
2542 if (erst_dev) {
2543 acpi_add_table(table_offsets, tables_blob);
2544 build_erst(tables_blob, tables->linker, erst_dev,
2545 x86ms->oem_id, x86ms->oem_table_id);
2546 }
2547 }
2548 #endif
2549
2550 vmgenid_dev = find_vmgenid_dev();
2551 if (vmgenid_dev) {
2552 acpi_add_table(table_offsets, tables_blob);
2553 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2554 tables->vmgenid, tables->linker, x86ms->oem_id);
2555 }
2556
2557 if (misc.has_hpet) {
2558 acpi_add_table(table_offsets, tables_blob);
2559 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2560 x86ms->oem_table_id);
2561 }
2562 #ifdef CONFIG_TPM
2563 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2564 if (misc.tpm_version == TPM_VERSION_1_2) {
2565 acpi_add_table(table_offsets, tables_blob);
2566 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2567 x86ms->oem_id, x86ms->oem_table_id);
2568 } else { /* TPM_VERSION_2_0 */
2569 acpi_add_table(table_offsets, tables_blob);
2570 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2571 x86ms->oem_id, x86ms->oem_table_id);
2572 }
2573 }
2574 #endif
2575 if (machine->numa_state->num_nodes) {
2576 acpi_add_table(table_offsets, tables_blob);
2577 build_srat(tables_blob, tables->linker, machine);
2578 if (machine->numa_state->have_numa_distance) {
2579 acpi_add_table(table_offsets, tables_blob);
2580 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2581 x86ms->oem_table_id);
2582 }
2583 if (machine->numa_state->hmat_enabled) {
2584 acpi_add_table(table_offsets, tables_blob);
2585 build_hmat(tables_blob, tables->linker, machine->numa_state,
2586 x86ms->oem_id, x86ms->oem_table_id);
2587 }
2588 }
2589 if (acpi_get_mcfg(&mcfg)) {
2590 acpi_add_table(table_offsets, tables_blob);
2591 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2592 x86ms->oem_table_id);
2593 }
2594 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2595 acpi_add_table(table_offsets, tables_blob);
2596 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2597 x86ms->oem_table_id);
2598 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2599 acpi_add_table(table_offsets, tables_blob);
2600 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2601 x86ms->oem_table_id);
2602 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2603 PCIDevice *pdev = PCI_DEVICE(iommu);
2604
2605 acpi_add_table(table_offsets, tables_blob);
2606 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2607 x86ms->oem_id, x86ms->oem_table_id);
2608 }
2609 if (machine->nvdimms_state->is_enabled) {
2610 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2611 machine->nvdimms_state, machine->ram_slots,
2612 x86ms->oem_id, x86ms->oem_table_id);
2613 }
2614 if (pcms->cxl_devices_state.is_enabled) {
2615 cxl_build_cedt(table_offsets, tables_blob, tables->linker,
2616 x86ms->oem_id, x86ms->oem_table_id, &pcms->cxl_devices_state);
2617 }
2618
2619 acpi_add_table(table_offsets, tables_blob);
2620 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2621
2622 /* Add tables supplied by user (if any) */
2623 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2624 unsigned len = acpi_table_len(u);
2625
2626 acpi_add_table(table_offsets, tables_blob);
2627 g_array_append_vals(tables_blob, u, len);
2628 }
2629
2630 /* RSDT is pointed to by RSDP */
2631 rsdt = tables_blob->len;
2632 build_rsdt(tables_blob, tables->linker, table_offsets,
2633 oem_id, oem_table_id);
2634
2635 /* RSDP is in FSEG memory, so allocate it separately */
2636 {
2637 AcpiRsdpData rsdp_data = {
2638 .revision = 0,
2639 .oem_id = x86ms->oem_id,
2640 .xsdt_tbl_offset = NULL,
2641 .rsdt_tbl_offset = &rsdt,
2642 };
2643 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2644 if (!pcmc->rsdp_in_ram) {
2645 /* We used to allocate some extra space for RSDP revision 2 but
2646 * only used the RSDP revision 0 space. The extra bytes were
2647 * zeroed out and not used.
2648 * Here we continue wasting those extra 16 bytes to make sure we
2649 * don't break migration for machine types 2.2 and older due to
2650 * RSDP blob size mismatch.
2651 */
2652 build_append_int_noprefix(tables->rsdp, 0, 16);
2653 }
2654 }
2655
2656 /* We'll expose it all to Guest so we want to reduce
2657 * chance of size changes.
2658 *
2659 * We used to align the tables to 4k, but of course this would
2660 * too simple to be enough. 4k turned out to be too small an
2661 * alignment very soon, and in fact it is almost impossible to
2662 * keep the table size stable for all (max_cpus, max_memory_slots)
2663 * combinations. So the table size is always 64k for pc-i440fx-2.1
2664 * and we give an error if the table grows beyond that limit.
2665 *
2666 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2667 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2668 * than 2.0 and we can always pad the smaller tables with zeros. We can
2669 * then use the exact size of the 2.0 tables.
2670 *
2671 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2672 */
2673 if (pcmc->legacy_acpi_table_size) {
2674 /* Subtracting aml_len gives the size of fixed tables. Then add the
2675 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2676 */
2677 int legacy_aml_len =
2678 pcmc->legacy_acpi_table_size +
2679 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2680 int legacy_table_size =
2681 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2682 ACPI_BUILD_ALIGN_SIZE);
2683 if (tables_blob->len > legacy_table_size) {
2684 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2685 warn_report("ACPI table size %u exceeds %d bytes,"
2686 " migration may not work",
2687 tables_blob->len, legacy_table_size);
2688 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2689 " or PCI bridges.");
2690 }
2691 g_array_set_size(tables_blob, legacy_table_size);
2692 } else {
2693 /* Make sure we have a buffer in case we need to resize the tables. */
2694 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2695 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2696 warn_report("ACPI table size %u exceeds %d bytes,"
2697 " migration may not work",
2698 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2699 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2700 " or PCI bridges.");
2701 }
2702 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2703 }
2704
2705 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2706
2707 /* Cleanup memory that's no longer used. */
2708 g_array_free(table_offsets, true);
2709 g_free(slic_oem.id);
2710 g_free(slic_oem.table_id);
2711 }
2712
2713 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2714 {
2715 uint32_t size = acpi_data_len(data);
2716
2717 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2718 memory_region_ram_resize(mr, size, &error_abort);
2719
2720 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2721 memory_region_set_dirty(mr, 0, size);
2722 }
2723
2724 static void acpi_build_update(void *build_opaque)
2725 {
2726 AcpiBuildState *build_state = build_opaque;
2727 AcpiBuildTables tables;
2728
2729 /* No state to update or already patched? Nothing to do. */
2730 if (!build_state || build_state->patched) {
2731 return;
2732 }
2733 build_state->patched = 1;
2734
2735 acpi_build_tables_init(&tables);
2736
2737 acpi_build(&tables, MACHINE(qdev_get_machine()));
2738
2739 acpi_ram_update(build_state->table_mr, tables.table_data);
2740
2741 if (build_state->rsdp) {
2742 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2743 } else {
2744 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2745 }
2746
2747 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2748 acpi_build_tables_cleanup(&tables, true);
2749 }
2750
2751 static void acpi_build_reset(void *build_opaque)
2752 {
2753 AcpiBuildState *build_state = build_opaque;
2754 build_state->patched = 0;
2755 }
2756
2757 static const VMStateDescription vmstate_acpi_build = {
2758 .name = "acpi_build",
2759 .version_id = 1,
2760 .minimum_version_id = 1,
2761 .fields = (VMStateField[]) {
2762 VMSTATE_UINT8(patched, AcpiBuildState),
2763 VMSTATE_END_OF_LIST()
2764 },
2765 };
2766
2767 void acpi_setup(void)
2768 {
2769 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2770 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2771 X86MachineState *x86ms = X86_MACHINE(pcms);
2772 AcpiBuildTables tables;
2773 AcpiBuildState *build_state;
2774 Object *vmgenid_dev;
2775 #ifdef CONFIG_TPM
2776 TPMIf *tpm;
2777 static FwCfgTPMConfig tpm_config;
2778 #endif
2779
2780 if (!x86ms->fw_cfg) {
2781 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2782 return;
2783 }
2784
2785 if (!pcms->acpi_build_enabled) {
2786 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2787 return;
2788 }
2789
2790 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2791 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2792 return;
2793 }
2794
2795 build_state = g_malloc0(sizeof *build_state);
2796
2797 acpi_build_tables_init(&tables);
2798 acpi_build(&tables, MACHINE(pcms));
2799
2800 /* Now expose it all to Guest */
2801 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2802 build_state, tables.table_data,
2803 ACPI_BUILD_TABLE_FILE);
2804 assert(build_state->table_mr != NULL);
2805
2806 build_state->linker_mr =
2807 acpi_add_rom_blob(acpi_build_update, build_state,
2808 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2809
2810 #ifdef CONFIG_TPM
2811 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2812 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2813
2814 tpm = tpm_find();
2815 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2816 tpm_config = (FwCfgTPMConfig) {
2817 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2818 .tpm_version = tpm_get_version(tpm),
2819 .tpmppi_version = TPM_PPI_VERSION_1_30
2820 };
2821 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2822 &tpm_config, sizeof tpm_config);
2823 }
2824 #endif
2825
2826 vmgenid_dev = find_vmgenid_dev();
2827 if (vmgenid_dev) {
2828 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2829 tables.vmgenid);
2830 }
2831
2832 if (!pcmc->rsdp_in_ram) {
2833 /*
2834 * Keep for compatibility with old machine types.
2835 * Though RSDP is small, its contents isn't immutable, so
2836 * we'll update it along with the rest of tables on guest access.
2837 */
2838 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2839
2840 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2841 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2842 acpi_build_update, NULL, build_state,
2843 build_state->rsdp, rsdp_size, true);
2844 build_state->rsdp_mr = NULL;
2845 } else {
2846 build_state->rsdp = NULL;
2847 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2848 build_state, tables.rsdp,
2849 ACPI_BUILD_RSDP_FILE);
2850 }
2851
2852 qemu_register_reset(acpi_build_reset, build_state);
2853 acpi_build_reset(build_state);
2854 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2855
2856 /* Cleanup tables but don't free the memory: we track it
2857 * in build_state.
2858 */
2859 acpi_build_tables_cleanup(&tables, false);
2860 }
QEmu