hw/display/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * see docs/specs/standard-vga.txt for virtual hardware specs.
   5  *
   6  * Copyright (c) 2003 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "vga_int.h"
  32 #include "ui/pixel_ops.h"
  33 #include "qemu/module.h"
  34 #include "qemu/timer.h"
  35 #include "hw/loader.h"
  36 #include "hw/display/edid.h"
  37 #include "qom/object.h"
  38 #include "hw/acpi/acpi_aml_interface.h"
  39
  40 enum vga_pci_flags {
  41     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  42     PCI_VGA_FLAG_ENABLE_QEXT = 2,
  43     PCI_VGA_FLAG_ENABLE_EDID = 3,
  44 };
  45
  46 struct PCIVGAState {
  47     PCIDevice dev;
  48     VGACommonState vga;
  49     uint32_t flags;
  50     qemu_edid_info edid_info;
  51     MemoryRegion mmio;
  52     MemoryRegion mrs[4];
  53     uint8_t edid[384];
  54 };
  55
  56 #define TYPE_PCI_VGA "pci-vga"
  57 OBJECT_DECLARE_SIMPLE_TYPE(PCIVGAState, PCI_VGA)
  58
  59 static const VMStateDescription vmstate_vga_pci = {
  60     .name = "vga",
  61     .version_id = 2,
  62     .minimum_version_id = 2,
  63     .fields = (VMStateField[]) {
  64         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  65         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  66         VMSTATE_END_OF_LIST()
  67     }
  68 };
  69
  70 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
  71                                     unsigned size)
  72 {
  73     VGACommonState *s = ptr;
  74     uint64_t ret = 0;
  75
  76     switch (size) {
  77     case 1:
  78         ret = vga_ioport_read(s, addr + 0x3c0);
  79         break;
  80     case 2:
  81         ret  = vga_ioport_read(s, addr + 0x3c0);
  82         ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
  83         break;
  84     }
  85     return ret;
  86 }
  87
  88 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
  89                                  uint64_t val, unsigned size)
  90 {
  91     VGACommonState *s = ptr;
  92
  93     switch (size) {
  94     case 1:
  95         vga_ioport_write(s, addr + 0x3c0, val);
  96         break;
  97     case 2:
  98         /*
  99          * Update bytes in little endian order.  Allows to update
 100          * indexed registers with a single word write because the
 101          * index byte is updated first.
 102          */
 103         vga_ioport_write(s, addr + 0x3c0, val & 0xff);
 104         vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
 105         break;
 106     }
 107 }
 108
 109 static const MemoryRegionOps pci_vga_ioport_ops = {
 110     .read = pci_vga_ioport_read,
 111     .write = pci_vga_ioport_write,
 112     .valid.min_access_size = 1,
 113     .valid.max_access_size = 4,
 114     .impl.min_access_size = 1,
 115     .impl.max_access_size = 2,
 116     .endianness = DEVICE_LITTLE_ENDIAN,
 117 };
 118
 119 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
 120                                    unsigned size)
 121 {
 122     VGACommonState *s = ptr;
 123     int index = addr >> 1;
 124
 125     vbe_ioport_write_index(s, 0, index);
 126     return vbe_ioport_read_data(s, 0);
 127 }
 128
 129 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
 130                                 uint64_t val, unsigned size)
 131 {
 132     VGACommonState *s = ptr;
 133     int index = addr >> 1;
 134
 135     vbe_ioport_write_index(s, 0, index);
 136     vbe_ioport_write_data(s, 0, val);
 137 }
 138
 139 static const MemoryRegionOps pci_vga_bochs_ops = {
 140     .read = pci_vga_bochs_read,
 141     .write = pci_vga_bochs_write,
 142     .valid.min_access_size = 1,
 143     .valid.max_access_size = 4,
 144     .impl.min_access_size = 2,
 145     .impl.max_access_size = 2,
 146     .endianness = DEVICE_LITTLE_ENDIAN,
 147 };
 148
 149 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
 150 {
 151     VGACommonState *s = ptr;
 152
 153     switch (addr) {
 154     case PCI_VGA_QEXT_REG_SIZE:
 155         return PCI_VGA_QEXT_SIZE;
 156     case PCI_VGA_QEXT_REG_BYTEORDER:
 157         return s->big_endian_fb ?
 158             PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
 159     default:
 160         return 0;
 161     }
 162 }
 163
 164 static void pci_vga_qext_write(void *ptr, hwaddr addr,
 165                                uint64_t val, unsigned size)
 166 {
 167     VGACommonState *s = ptr;
 168
 169     switch (addr) {
 170     case PCI_VGA_QEXT_REG_BYTEORDER:
 171         if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
 172             s->big_endian_fb = true;
 173         }
 174         if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
 175             s->big_endian_fb = false;
 176         }
 177         break;
 178     }
 179 }
 180
 181 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
 182 {
 183     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 184
 185     return d->vga.big_endian_fb;
 186 }
 187
 188 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 189 {
 190     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 191
 192     d->vga.big_endian_fb = value;
 193 }
 194
 195 static const MemoryRegionOps pci_vga_qext_ops = {
 196     .read = pci_vga_qext_read,
 197     .write = pci_vga_qext_write,
 198     .valid.min_access_size = 4,
 199     .valid.max_access_size = 4,
 200     .endianness = DEVICE_LITTLE_ENDIAN,
 201 };
 202
 203 void pci_std_vga_mmio_region_init(VGACommonState *s,
 204                                   Object *owner,
 205                                   MemoryRegion *parent,
 206                                   MemoryRegion *subs,
 207                                   bool qext, bool edid)
 208 {
 209     PCIVGAState *d = container_of(s, PCIVGAState, vga);
 210
 211     memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
 212                           "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 213     memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
 214                                 &subs[0]);
 215
 216     memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
 217                           "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 218     memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
 219                                 &subs[1]);
 220
 221     if (qext) {
 222         memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
 223                               "qemu extended regs", PCI_VGA_QEXT_SIZE);
 224         memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
 225                                     &subs[2]);
 226     }
 227
 228     if (edid) {
 229         qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
 230         qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
 231         memory_region_add_subregion(parent, 0, &subs[3]);
 232     }
 233 }
 234
 235 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
 236 {
 237     PCIVGAState *d = PCI_VGA(dev);
 238     VGACommonState *s = &d->vga;
 239     bool qext = false;
 240     bool edid = false;
 241
 242     /* vga + console init */
 243     if (!vga_common_init(s, OBJECT(dev), errp)) {
 244         return;
 245     }
 246     vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
 247              true);
 248
 249     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 250
 251     /* XXX: VGA_RAM_SIZE must be a power of two */
 252     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 253
 254     /* mmio bar for vga register access */
 255     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 256         memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
 257                               "vga.mmio", PCI_VGA_MMIO_SIZE);
 258
 259         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 260             qext = true;
 261             pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 262         }
 263         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 264             edid = true;
 265         }
 266         pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
 267                                      qext, edid);
 268
 269         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 270     }
 271 }
 272
 273 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
 274 {
 275     PCIVGAState *d = PCI_VGA(dev);
 276     VGACommonState *s = &d->vga;
 277     bool qext = false;
 278     bool edid = false;
 279
 280     /* vga + console init */
 281     if (!vga_common_init(s, OBJECT(dev), errp)) {
 282         return;
 283     }
 284     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 285
 286     /* mmio bar */
 287     memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
 288                           "vga.mmio", PCI_VGA_MMIO_SIZE);
 289
 290     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 291         qext = true;
 292         pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 293     }
 294     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 295         edid = true;
 296     }
 297     pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
 298
 299     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 300     pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 301 }
 302
 303 static void pci_secondary_vga_exit(PCIDevice *dev)
 304 {
 305     PCIVGAState *d = PCI_VGA(dev);
 306     VGACommonState *s = &d->vga;
 307
 308     graphic_console_close(s->con);
 309     memory_region_del_subregion(&d->mmio, &d->mrs[0]);
 310     memory_region_del_subregion(&d->mmio, &d->mrs[1]);
 311     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 312         memory_region_del_subregion(&d->mmio, &d->mrs[2]);
 313     }
 314     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
 315         memory_region_del_subregion(&d->mmio, &d->mrs[3]);
 316     }
 317 }
 318
 319 static void pci_secondary_vga_init(Object *obj)
 320 {
 321     /* Expose framebuffer byteorder via QOM */
 322     object_property_add_bool(obj, "big-endian-framebuffer",
 323                              vga_get_big_endian_fb, vga_set_big_endian_fb);
 324 }
 325
 326 static void pci_secondary_vga_reset(DeviceState *dev)
 327 {
 328     PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
 329     vga_common_reset(&d->vga);
 330 }
 331
 332 static Property vga_pci_properties[] = {
 333     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 334     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 335     DEFINE_PROP_BIT("qemu-extended-regs",
 336                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 337     DEFINE_PROP_BIT("edid",
 338                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
 339     DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
 340     DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
 341     DEFINE_PROP_END_OF_LIST(),
 342 };
 343
 344 static Property secondary_pci_properties[] = {
 345     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 346     DEFINE_PROP_BIT("qemu-extended-regs",
 347                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 348     DEFINE_PROP_BIT("edid",
 349                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
 350     DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
 351     DEFINE_PROP_END_OF_LIST(),
 352 };
 353
 354 static void vga_pci_class_init(ObjectClass *klass, void *data)
 355 {
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 358     AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
 359
 360     k->vendor_id = PCI_VENDOR_ID_QEMU;
 361     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 362     dc->vmsd = &vmstate_vga_pci;
 363     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 364     adevc->build_dev_aml = build_vga_aml;
 365 }
 366
 367 static const TypeInfo vga_pci_type_info = {
 368     .name = TYPE_PCI_VGA,
 369     .parent = TYPE_PCI_DEVICE,
 370     .instance_size = sizeof(PCIVGAState),
 371     .abstract = true,
 372     .class_init = vga_pci_class_init,
 373     .interfaces = (InterfaceInfo[]) {
 374         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 375         { TYPE_ACPI_DEV_AML_IF },
 376         { },
 377     },
 378 };
 379
 380 static void vga_class_init(ObjectClass *klass, void *data)
 381 {
 382     DeviceClass *dc = DEVICE_CLASS(klass);
 383     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 384
 385     k->realize = pci_std_vga_realize;
 386     k->romfile = "vgabios-stdvga.bin";
 387     k->class_id = PCI_CLASS_DISPLAY_VGA;
 388     device_class_set_props(dc, vga_pci_properties);
 389     dc->hotpluggable = false;
 390
 391     /* Expose framebuffer byteorder via QOM */
 392     object_class_property_add_bool(klass, "big-endian-framebuffer",
 393                                    vga_get_big_endian_fb, vga_set_big_endian_fb);
 394 }
 395
 396 static void secondary_class_init(ObjectClass *klass, void *data)
 397 {
 398     DeviceClass *dc = DEVICE_CLASS(klass);
 399     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 400
 401     k->realize = pci_secondary_vga_realize;
 402     k->exit = pci_secondary_vga_exit;
 403     k->class_id = PCI_CLASS_DISPLAY_OTHER;
 404     device_class_set_props(dc, secondary_pci_properties);
 405     dc->reset = pci_secondary_vga_reset;
 406 }
 407
 408 static const TypeInfo vga_info = {
 409     .name          = "VGA",
 410     .parent        = TYPE_PCI_VGA,
 411     .class_init    = vga_class_init,
 412 };
 413
 414 static const TypeInfo secondary_info = {
 415     .name          = "secondary-vga",
 416     .parent        = TYPE_PCI_VGA,
 417     .instance_init = pci_secondary_vga_init,
 418     .class_init    = secondary_class_init,
 419 };
 420
 421 static void vga_register_types(void)
 422 {
 423     type_register_static(&vga_pci_type_info);
 424     type_register_static(&vga_info);
 425     type_register_static(&secondary_info);
 426 }
 427
 428 type_init(vga_register_types)