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target-xtensa: add target to the configure script
[qemu.git] / hw / ppc405_uc.c
blob9d5d2af5d8b88d09d86548c0202355d6ba1e6481
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31 #include "exec-memory.h"
32
33 #define DEBUG_OPBA
34 #define DEBUG_SDRAM
35 #define DEBUG_GPIO
36 #define DEBUG_SERIAL
37 #define DEBUG_OCM
38 //#define DEBUG_I2C
39 #define DEBUG_GPT
40 #define DEBUG_MAL
41 #define DEBUG_CLOCKS
42 //#define DEBUG_CLOCKS_LL
43
44 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
45 uint32_t flags)
46 {
47 ram_addr_t bdloc;
48 int i, n;
49
50 /* We put the bd structure at the top of memory */
51 if (bd->bi_memsize >= 0x01000000UL)
52 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
53 else
54 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
55 stl_be_phys(bdloc + 0x00, bd->bi_memstart);
56 stl_be_phys(bdloc + 0x04, bd->bi_memsize);
57 stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
58 stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
59 stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
60 stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
61 stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
62 stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
63 stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
64 for (i = 0; i < 6; i++) {
65 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
66 }
67 stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
68 stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
69 stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
70 stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
71 for (i = 0; i < 4; i++) {
72 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
73 }
74 for (i = 0; i < 32; i++) {
75 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
76 }
77 stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
78 stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
79 for (i = 0; i < 6; i++) {
80 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
81 }
82 n = 0x6A;
83 if (flags & 0x00000001) {
84 for (i = 0; i < 6; i++)
85 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
86 }
87 stl_be_phys(bdloc + n, bd->bi_opbfreq);
88 n += 4;
89 for (i = 0; i < 2; i++) {
90 stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
91 n += 4;
92 }
93
94 return bdloc;
95 }
96
97 /*****************************************************************************/
98 /* Shared peripherals */
99
100 /*****************************************************************************/
101 /* Peripheral local bus arbitrer */
102 enum {
103 PLB0_BESR = 0x084,
104 PLB0_BEAR = 0x086,
105 PLB0_ACR = 0x087,
106 };
107
108 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
109 struct ppc4xx_plb_t {
110 uint32_t acr;
111 uint32_t bear;
112 uint32_t besr;
113 };
114
115 static uint32_t dcr_read_plb (void *opaque, int dcrn)
116 {
117 ppc4xx_plb_t *plb;
118 uint32_t ret;
119
120 plb = opaque;
121 switch (dcrn) {
122 case PLB0_ACR:
123 ret = plb->acr;
124 break;
125 case PLB0_BEAR:
126 ret = plb->bear;
127 break;
128 case PLB0_BESR:
129 ret = plb->besr;
130 break;
131 default:
132 /* Avoid gcc warning */
133 ret = 0;
134 break;
135 }
136
137 return ret;
138 }
139
140 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
141 {
142 ppc4xx_plb_t *plb;
143
144 plb = opaque;
145 switch (dcrn) {
146 case PLB0_ACR:
147 /* We don't care about the actual parameters written as
148 * we don't manage any priorities on the bus
149 */
150 plb->acr = val & 0xF8000000;
151 break;
152 case PLB0_BEAR:
153 /* Read only */
154 break;
155 case PLB0_BESR:
156 /* Write-clear */
157 plb->besr &= ~val;
158 break;
159 }
160 }
161
162 static void ppc4xx_plb_reset (void *opaque)
163 {
164 ppc4xx_plb_t *plb;
165
166 plb = opaque;
167 plb->acr = 0x00000000;
168 plb->bear = 0x00000000;
169 plb->besr = 0x00000000;
170 }
171
172 static void ppc4xx_plb_init(CPUState *env)
173 {
174 ppc4xx_plb_t *plb;
175
176 plb = g_malloc0(sizeof(ppc4xx_plb_t));
177 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
179 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
180 qemu_register_reset(ppc4xx_plb_reset, plb);
181 }
182
183 /*****************************************************************************/
184 /* PLB to OPB bridge */
185 enum {
186 POB0_BESR0 = 0x0A0,
187 POB0_BESR1 = 0x0A2,
188 POB0_BEAR = 0x0A4,
189 };
190
191 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
192 struct ppc4xx_pob_t {
193 uint32_t bear;
194 uint32_t besr[2];
195 };
196
197 static uint32_t dcr_read_pob (void *opaque, int dcrn)
198 {
199 ppc4xx_pob_t *pob;
200 uint32_t ret;
201
202 pob = opaque;
203 switch (dcrn) {
204 case POB0_BEAR:
205 ret = pob->bear;
206 break;
207 case POB0_BESR0:
208 case POB0_BESR1:
209 ret = pob->besr[dcrn - POB0_BESR0];
210 break;
211 default:
212 /* Avoid gcc warning */
213 ret = 0;
214 break;
215 }
216
217 return ret;
218 }
219
220 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
221 {
222 ppc4xx_pob_t *pob;
223
224 pob = opaque;
225 switch (dcrn) {
226 case POB0_BEAR:
227 /* Read only */
228 break;
229 case POB0_BESR0:
230 case POB0_BESR1:
231 /* Write-clear */
232 pob->besr[dcrn - POB0_BESR0] &= ~val;
233 break;
234 }
235 }
236
237 static void ppc4xx_pob_reset (void *opaque)
238 {
239 ppc4xx_pob_t *pob;
240
241 pob = opaque;
242 /* No error */
243 pob->bear = 0x00000000;
244 pob->besr[0] = 0x0000000;
245 pob->besr[1] = 0x0000000;
246 }
247
248 static void ppc4xx_pob_init(CPUState *env)
249 {
250 ppc4xx_pob_t *pob;
251
252 pob = g_malloc0(sizeof(ppc4xx_pob_t));
253 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
254 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
255 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
256 qemu_register_reset(ppc4xx_pob_reset, pob);
257 }
258
259 /*****************************************************************************/
260 /* OPB arbitrer */
261 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
262 struct ppc4xx_opba_t {
263 MemoryRegion io;
264 uint8_t cr;
265 uint8_t pr;
266 };
267
268 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
269 {
270 ppc4xx_opba_t *opba;
271 uint32_t ret;
272
273 #ifdef DEBUG_OPBA
274 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
275 #endif
276 opba = opaque;
277 switch (addr) {
278 case 0x00:
279 ret = opba->cr;
280 break;
281 case 0x01:
282 ret = opba->pr;
283 break;
284 default:
285 ret = 0x00;
286 break;
287 }
288
289 return ret;
290 }
291
292 static void opba_writeb (void *opaque,
293 target_phys_addr_t addr, uint32_t value)
294 {
295 ppc4xx_opba_t *opba;
296
297 #ifdef DEBUG_OPBA
298 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
299 value);
300 #endif
301 opba = opaque;
302 switch (addr) {
303 case 0x00:
304 opba->cr = value & 0xF8;
305 break;
306 case 0x01:
307 opba->pr = value & 0xFF;
308 break;
309 default:
310 break;
311 }
312 }
313
314 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
315 {
316 uint32_t ret;
317
318 #ifdef DEBUG_OPBA
319 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
320 #endif
321 ret = opba_readb(opaque, addr) << 8;
322 ret |= opba_readb(opaque, addr + 1);
323
324 return ret;
325 }
326
327 static void opba_writew (void *opaque,
328 target_phys_addr_t addr, uint32_t value)
329 {
330 #ifdef DEBUG_OPBA
331 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
332 value);
333 #endif
334 opba_writeb(opaque, addr, value >> 8);
335 opba_writeb(opaque, addr + 1, value);
336 }
337
338 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
339 {
340 uint32_t ret;
341
342 #ifdef DEBUG_OPBA
343 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
344 #endif
345 ret = opba_readb(opaque, addr) << 24;
346 ret |= opba_readb(opaque, addr + 1) << 16;
347
348 return ret;
349 }
350
351 static void opba_writel (void *opaque,
352 target_phys_addr_t addr, uint32_t value)
353 {
354 #ifdef DEBUG_OPBA
355 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
356 value);
357 #endif
358 opba_writeb(opaque, addr, value >> 24);
359 opba_writeb(opaque, addr + 1, value >> 16);
360 }
361
362 static const MemoryRegionOps opba_ops = {
363 .old_mmio = {
364 .read = { opba_readb, opba_readw, opba_readl, },
365 .write = { opba_writeb, opba_writew, opba_writel, },
366 },
367 .endianness = DEVICE_NATIVE_ENDIAN,
368 };
369
370 static void ppc4xx_opba_reset (void *opaque)
371 {
372 ppc4xx_opba_t *opba;
373
374 opba = opaque;
375 opba->cr = 0x00; /* No dynamic priorities - park disabled */
376 opba->pr = 0x11;
377 }
378
379 static void ppc4xx_opba_init(target_phys_addr_t base)
380 {
381 ppc4xx_opba_t *opba;
382
383 opba = g_malloc0(sizeof(ppc4xx_opba_t));
384 #ifdef DEBUG_OPBA
385 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
386 #endif
387 memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
388 memory_region_add_subregion(get_system_memory(), base, &opba->io);
389 qemu_register_reset(ppc4xx_opba_reset, opba);
390 }
391
392 /*****************************************************************************/
393 /* Code decompression controller */
394 /* XXX: TODO */
395
396 /*****************************************************************************/
397 /* Peripheral controller */
398 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
399 struct ppc4xx_ebc_t {
400 uint32_t addr;
401 uint32_t bcr[8];
402 uint32_t bap[8];
403 uint32_t bear;
404 uint32_t besr0;
405 uint32_t besr1;
406 uint32_t cfg;
407 };
408
409 enum {
410 EBC0_CFGADDR = 0x012,
411 EBC0_CFGDATA = 0x013,
412 };
413
414 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
415 {
416 ppc4xx_ebc_t *ebc;
417 uint32_t ret;
418
419 ebc = opaque;
420 switch (dcrn) {
421 case EBC0_CFGADDR:
422 ret = ebc->addr;
423 break;
424 case EBC0_CFGDATA:
425 switch (ebc->addr) {
426 case 0x00: /* B0CR */
427 ret = ebc->bcr[0];
428 break;
429 case 0x01: /* B1CR */
430 ret = ebc->bcr[1];
431 break;
432 case 0x02: /* B2CR */
433 ret = ebc->bcr[2];
434 break;
435 case 0x03: /* B3CR */
436 ret = ebc->bcr[3];
437 break;
438 case 0x04: /* B4CR */
439 ret = ebc->bcr[4];
440 break;
441 case 0x05: /* B5CR */
442 ret = ebc->bcr[5];
443 break;
444 case 0x06: /* B6CR */
445 ret = ebc->bcr[6];
446 break;
447 case 0x07: /* B7CR */
448 ret = ebc->bcr[7];
449 break;
450 case 0x10: /* B0AP */
451 ret = ebc->bap[0];
452 break;
453 case 0x11: /* B1AP */
454 ret = ebc->bap[1];
455 break;
456 case 0x12: /* B2AP */
457 ret = ebc->bap[2];
458 break;
459 case 0x13: /* B3AP */
460 ret = ebc->bap[3];
461 break;
462 case 0x14: /* B4AP */
463 ret = ebc->bap[4];
464 break;
465 case 0x15: /* B5AP */
466 ret = ebc->bap[5];
467 break;
468 case 0x16: /* B6AP */
469 ret = ebc->bap[6];
470 break;
471 case 0x17: /* B7AP */
472 ret = ebc->bap[7];
473 break;
474 case 0x20: /* BEAR */
475 ret = ebc->bear;
476 break;
477 case 0x21: /* BESR0 */
478 ret = ebc->besr0;
479 break;
480 case 0x22: /* BESR1 */
481 ret = ebc->besr1;
482 break;
483 case 0x23: /* CFG */
484 ret = ebc->cfg;
485 break;
486 default:
487 ret = 0x00000000;
488 break;
489 }
490 break;
491 default:
492 ret = 0x00000000;
493 break;
494 }
495
496 return ret;
497 }
498
499 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
500 {
501 ppc4xx_ebc_t *ebc;
502
503 ebc = opaque;
504 switch (dcrn) {
505 case EBC0_CFGADDR:
506 ebc->addr = val;
507 break;
508 case EBC0_CFGDATA:
509 switch (ebc->addr) {
510 case 0x00: /* B0CR */
511 break;
512 case 0x01: /* B1CR */
513 break;
514 case 0x02: /* B2CR */
515 break;
516 case 0x03: /* B3CR */
517 break;
518 case 0x04: /* B4CR */
519 break;
520 case 0x05: /* B5CR */
521 break;
522 case 0x06: /* B6CR */
523 break;
524 case 0x07: /* B7CR */
525 break;
526 case 0x10: /* B0AP */
527 break;
528 case 0x11: /* B1AP */
529 break;
530 case 0x12: /* B2AP */
531 break;
532 case 0x13: /* B3AP */
533 break;
534 case 0x14: /* B4AP */
535 break;
536 case 0x15: /* B5AP */
537 break;
538 case 0x16: /* B6AP */
539 break;
540 case 0x17: /* B7AP */
541 break;
542 case 0x20: /* BEAR */
543 break;
544 case 0x21: /* BESR0 */
545 break;
546 case 0x22: /* BESR1 */
547 break;
548 case 0x23: /* CFG */
549 break;
550 default:
551 break;
552 }
553 break;
554 default:
555 break;
556 }
557 }
558
559 static void ebc_reset (void *opaque)
560 {
561 ppc4xx_ebc_t *ebc;
562 int i;
563
564 ebc = opaque;
565 ebc->addr = 0x00000000;
566 ebc->bap[0] = 0x7F8FFE80;
567 ebc->bcr[0] = 0xFFE28000;
568 for (i = 0; i < 8; i++) {
569 ebc->bap[i] = 0x00000000;
570 ebc->bcr[i] = 0x00000000;
571 }
572 ebc->besr0 = 0x00000000;
573 ebc->besr1 = 0x00000000;
574 ebc->cfg = 0x80400000;
575 }
576
577 static void ppc405_ebc_init(CPUState *env)
578 {
579 ppc4xx_ebc_t *ebc;
580
581 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
582 qemu_register_reset(&ebc_reset, ebc);
583 ppc_dcr_register(env, EBC0_CFGADDR,
584 ebc, &dcr_read_ebc, &dcr_write_ebc);
585 ppc_dcr_register(env, EBC0_CFGDATA,
586 ebc, &dcr_read_ebc, &dcr_write_ebc);
587 }
588
589 /*****************************************************************************/
590 /* DMA controller */
591 enum {
592 DMA0_CR0 = 0x100,
593 DMA0_CT0 = 0x101,
594 DMA0_DA0 = 0x102,
595 DMA0_SA0 = 0x103,
596 DMA0_SG0 = 0x104,
597 DMA0_CR1 = 0x108,
598 DMA0_CT1 = 0x109,
599 DMA0_DA1 = 0x10A,
600 DMA0_SA1 = 0x10B,
601 DMA0_SG1 = 0x10C,
602 DMA0_CR2 = 0x110,
603 DMA0_CT2 = 0x111,
604 DMA0_DA2 = 0x112,
605 DMA0_SA2 = 0x113,
606 DMA0_SG2 = 0x114,
607 DMA0_CR3 = 0x118,
608 DMA0_CT3 = 0x119,
609 DMA0_DA3 = 0x11A,
610 DMA0_SA3 = 0x11B,
611 DMA0_SG3 = 0x11C,
612 DMA0_SR = 0x120,
613 DMA0_SGC = 0x123,
614 DMA0_SLP = 0x125,
615 DMA0_POL = 0x126,
616 };
617
618 typedef struct ppc405_dma_t ppc405_dma_t;
619 struct ppc405_dma_t {
620 qemu_irq irqs[4];
621 uint32_t cr[4];
622 uint32_t ct[4];
623 uint32_t da[4];
624 uint32_t sa[4];
625 uint32_t sg[4];
626 uint32_t sr;
627 uint32_t sgc;
628 uint32_t slp;
629 uint32_t pol;
630 };
631
632 static uint32_t dcr_read_dma (void *opaque, int dcrn)
633 {
634 return 0;
635 }
636
637 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
638 {
639 }
640
641 static void ppc405_dma_reset (void *opaque)
642 {
643 ppc405_dma_t *dma;
644 int i;
645
646 dma = opaque;
647 for (i = 0; i < 4; i++) {
648 dma->cr[i] = 0x00000000;
649 dma->ct[i] = 0x00000000;
650 dma->da[i] = 0x00000000;
651 dma->sa[i] = 0x00000000;
652 dma->sg[i] = 0x00000000;
653 }
654 dma->sr = 0x00000000;
655 dma->sgc = 0x00000000;
656 dma->slp = 0x7C000000;
657 dma->pol = 0x00000000;
658 }
659
660 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
661 {
662 ppc405_dma_t *dma;
663
664 dma = g_malloc0(sizeof(ppc405_dma_t));
665 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
666 qemu_register_reset(&ppc405_dma_reset, dma);
667 ppc_dcr_register(env, DMA0_CR0,
668 dma, &dcr_read_dma, &dcr_write_dma);
669 ppc_dcr_register(env, DMA0_CT0,
670 dma, &dcr_read_dma, &dcr_write_dma);
671 ppc_dcr_register(env, DMA0_DA0,
672 dma, &dcr_read_dma, &dcr_write_dma);
673 ppc_dcr_register(env, DMA0_SA0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_SG0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_CR1,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_CT1,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_DA1,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SA1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SG1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CR2,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_CT2,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_DA2,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SA2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_SG2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CR3,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_CT3,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_DA3,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SA3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_SG3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_SR,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SGC,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SLP,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_POL,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 }
716
717 /*****************************************************************************/
718 /* GPIO */
719 typedef struct ppc405_gpio_t ppc405_gpio_t;
720 struct ppc405_gpio_t {
721 MemoryRegion io;
722 uint32_t or;
723 uint32_t tcr;
724 uint32_t osrh;
725 uint32_t osrl;
726 uint32_t tsrh;
727 uint32_t tsrl;
728 uint32_t odr;
729 uint32_t ir;
730 uint32_t rr1;
731 uint32_t isr1h;
732 uint32_t isr1l;
733 };
734
735 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
736 {
737 #ifdef DEBUG_GPIO
738 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
739 #endif
740
741 return 0;
742 }
743
744 static void ppc405_gpio_writeb (void *opaque,
745 target_phys_addr_t addr, uint32_t value)
746 {
747 #ifdef DEBUG_GPIO
748 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
749 value);
750 #endif
751 }
752
753 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
754 {
755 #ifdef DEBUG_GPIO
756 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
757 #endif
758
759 return 0;
760 }
761
762 static void ppc405_gpio_writew (void *opaque,
763 target_phys_addr_t addr, uint32_t value)
764 {
765 #ifdef DEBUG_GPIO
766 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
767 value);
768 #endif
769 }
770
771 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
772 {
773 #ifdef DEBUG_GPIO
774 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
775 #endif
776
777 return 0;
778 }
779
780 static void ppc405_gpio_writel (void *opaque,
781 target_phys_addr_t addr, uint32_t value)
782 {
783 #ifdef DEBUG_GPIO
784 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
785 value);
786 #endif
787 }
788
789 static const MemoryRegionOps ppc405_gpio_ops = {
790 .old_mmio = {
791 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
792 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
793 },
794 .endianness = DEVICE_NATIVE_ENDIAN,
795 };
796
797 static void ppc405_gpio_reset (void *opaque)
798 {
799 }
800
801 static void ppc405_gpio_init(target_phys_addr_t base)
802 {
803 ppc405_gpio_t *gpio;
804
805 gpio = g_malloc0(sizeof(ppc405_gpio_t));
806 #ifdef DEBUG_GPIO
807 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
808 #endif
809 memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
810 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
811 qemu_register_reset(&ppc405_gpio_reset, gpio);
812 }
813
814 /*****************************************************************************/
815 /* On Chip Memory */
816 enum {
817 OCM0_ISARC = 0x018,
818 OCM0_ISACNTL = 0x019,
819 OCM0_DSARC = 0x01A,
820 OCM0_DSACNTL = 0x01B,
821 };
822
823 typedef struct ppc405_ocm_t ppc405_ocm_t;
824 struct ppc405_ocm_t {
825 MemoryRegion ram;
826 MemoryRegion isarc_ram;
827 MemoryRegion dsarc_ram;
828 uint32_t isarc;
829 uint32_t isacntl;
830 uint32_t dsarc;
831 uint32_t dsacntl;
832 };
833
834 static void ocm_update_mappings (ppc405_ocm_t *ocm,
835 uint32_t isarc, uint32_t isacntl,
836 uint32_t dsarc, uint32_t dsacntl)
837 {
838 #ifdef DEBUG_OCM
839 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
840 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
841 " (%08" PRIx32 " %08" PRIx32 ")\n",
842 isarc, isacntl, dsarc, dsacntl,
843 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
844 #endif
845 if (ocm->isarc != isarc ||
846 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
847 if (ocm->isacntl & 0x80000000) {
848 /* Unmap previously assigned memory region */
849 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
850 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
851 }
852 if (isacntl & 0x80000000) {
853 /* Map new instruction memory region */
854 #ifdef DEBUG_OCM
855 printf("OCM map ISA %08" PRIx32 "\n", isarc);
856 #endif
857 memory_region_add_subregion(get_system_memory(), isarc,
858 &ocm->isarc_ram);
859 }
860 }
861 if (ocm->dsarc != dsarc ||
862 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
863 if (ocm->dsacntl & 0x80000000) {
864 /* Beware not to unmap the region we just mapped */
865 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
866 /* Unmap previously assigned memory region */
867 #ifdef DEBUG_OCM
868 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
869 #endif
870 memory_region_del_subregion(get_system_memory(),
871 &ocm->dsarc_ram);
872 }
873 }
874 if (dsacntl & 0x80000000) {
875 /* Beware not to remap the region we just mapped */
876 if (!(isacntl & 0x80000000) || dsarc != isarc) {
877 /* Map new data memory region */
878 #ifdef DEBUG_OCM
879 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
880 #endif
881 memory_region_add_subregion(get_system_memory(), dsarc,
882 &ocm->dsarc_ram);
883 }
884 }
885 }
886 }
887
888 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
889 {
890 ppc405_ocm_t *ocm;
891 uint32_t ret;
892
893 ocm = opaque;
894 switch (dcrn) {
895 case OCM0_ISARC:
896 ret = ocm->isarc;
897 break;
898 case OCM0_ISACNTL:
899 ret = ocm->isacntl;
900 break;
901 case OCM0_DSARC:
902 ret = ocm->dsarc;
903 break;
904 case OCM0_DSACNTL:
905 ret = ocm->dsacntl;
906 break;
907 default:
908 ret = 0;
909 break;
910 }
911
912 return ret;
913 }
914
915 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
916 {
917 ppc405_ocm_t *ocm;
918 uint32_t isarc, dsarc, isacntl, dsacntl;
919
920 ocm = opaque;
921 isarc = ocm->isarc;
922 dsarc = ocm->dsarc;
923 isacntl = ocm->isacntl;
924 dsacntl = ocm->dsacntl;
925 switch (dcrn) {
926 case OCM0_ISARC:
927 isarc = val & 0xFC000000;
928 break;
929 case OCM0_ISACNTL:
930 isacntl = val & 0xC0000000;
931 break;
932 case OCM0_DSARC:
933 isarc = val & 0xFC000000;
934 break;
935 case OCM0_DSACNTL:
936 isacntl = val & 0xC0000000;
937 break;
938 }
939 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
940 ocm->isarc = isarc;
941 ocm->dsarc = dsarc;
942 ocm->isacntl = isacntl;
943 ocm->dsacntl = dsacntl;
944 }
945
946 static void ocm_reset (void *opaque)
947 {
948 ppc405_ocm_t *ocm;
949 uint32_t isarc, dsarc, isacntl, dsacntl;
950
951 ocm = opaque;
952 isarc = 0x00000000;
953 isacntl = 0x00000000;
954 dsarc = 0x00000000;
955 dsacntl = 0x00000000;
956 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
957 ocm->isarc = isarc;
958 ocm->dsarc = dsarc;
959 ocm->isacntl = isacntl;
960 ocm->dsacntl = dsacntl;
961 }
962
963 static void ppc405_ocm_init(CPUState *env)
964 {
965 ppc405_ocm_t *ocm;
966
967 ocm = g_malloc0(sizeof(ppc405_ocm_t));
968 /* XXX: Size is 4096 or 0x04000000 */
969 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
970 memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
971 0, 4096);
972 qemu_register_reset(&ocm_reset, ocm);
973 ppc_dcr_register(env, OCM0_ISARC,
974 ocm, &dcr_read_ocm, &dcr_write_ocm);
975 ppc_dcr_register(env, OCM0_ISACNTL,
976 ocm, &dcr_read_ocm, &dcr_write_ocm);
977 ppc_dcr_register(env, OCM0_DSARC,
978 ocm, &dcr_read_ocm, &dcr_write_ocm);
979 ppc_dcr_register(env, OCM0_DSACNTL,
980 ocm, &dcr_read_ocm, &dcr_write_ocm);
981 }
982
983 /*****************************************************************************/
984 /* I2C controller */
985 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
986 struct ppc4xx_i2c_t {
987 qemu_irq irq;
988 MemoryRegion iomem;
989 uint8_t mdata;
990 uint8_t lmadr;
991 uint8_t hmadr;
992 uint8_t cntl;
993 uint8_t mdcntl;
994 uint8_t sts;
995 uint8_t extsts;
996 uint8_t sdata;
997 uint8_t lsadr;
998 uint8_t hsadr;
999 uint8_t clkdiv;
1000 uint8_t intrmsk;
1001 uint8_t xfrcnt;
1002 uint8_t xtcntlss;
1003 uint8_t directcntl;
1004 };
1005
1006 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1007 {
1008 ppc4xx_i2c_t *i2c;
1009 uint32_t ret;
1010
1011 #ifdef DEBUG_I2C
1012 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1013 #endif
1014 i2c = opaque;
1015 switch (addr) {
1016 case 0x00:
1017 // i2c_readbyte(&i2c->mdata);
1018 ret = i2c->mdata;
1019 break;
1020 case 0x02:
1021 ret = i2c->sdata;
1022 break;
1023 case 0x04:
1024 ret = i2c->lmadr;
1025 break;
1026 case 0x05:
1027 ret = i2c->hmadr;
1028 break;
1029 case 0x06:
1030 ret = i2c->cntl;
1031 break;
1032 case 0x07:
1033 ret = i2c->mdcntl;
1034 break;
1035 case 0x08:
1036 ret = i2c->sts;
1037 break;
1038 case 0x09:
1039 ret = i2c->extsts;
1040 break;
1041 case 0x0A:
1042 ret = i2c->lsadr;
1043 break;
1044 case 0x0B:
1045 ret = i2c->hsadr;
1046 break;
1047 case 0x0C:
1048 ret = i2c->clkdiv;
1049 break;
1050 case 0x0D:
1051 ret = i2c->intrmsk;
1052 break;
1053 case 0x0E:
1054 ret = i2c->xfrcnt;
1055 break;
1056 case 0x0F:
1057 ret = i2c->xtcntlss;
1058 break;
1059 case 0x10:
1060 ret = i2c->directcntl;
1061 break;
1062 default:
1063 ret = 0x00;
1064 break;
1065 }
1066 #ifdef DEBUG_I2C
1067 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1068 #endif
1069
1070 return ret;
1071 }
1072
1073 static void ppc4xx_i2c_writeb (void *opaque,
1074 target_phys_addr_t addr, uint32_t value)
1075 {
1076 ppc4xx_i2c_t *i2c;
1077
1078 #ifdef DEBUG_I2C
1079 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1080 value);
1081 #endif
1082 i2c = opaque;
1083 switch (addr) {
1084 case 0x00:
1085 i2c->mdata = value;
1086 // i2c_sendbyte(&i2c->mdata);
1087 break;
1088 case 0x02:
1089 i2c->sdata = value;
1090 break;
1091 case 0x04:
1092 i2c->lmadr = value;
1093 break;
1094 case 0x05:
1095 i2c->hmadr = value;
1096 break;
1097 case 0x06:
1098 i2c->cntl = value;
1099 break;
1100 case 0x07:
1101 i2c->mdcntl = value & 0xDF;
1102 break;
1103 case 0x08:
1104 i2c->sts &= ~(value & 0x0A);
1105 break;
1106 case 0x09:
1107 i2c->extsts &= ~(value & 0x8F);
1108 break;
1109 case 0x0A:
1110 i2c->lsadr = value;
1111 break;
1112 case 0x0B:
1113 i2c->hsadr = value;
1114 break;
1115 case 0x0C:
1116 i2c->clkdiv = value;
1117 break;
1118 case 0x0D:
1119 i2c->intrmsk = value;
1120 break;
1121 case 0x0E:
1122 i2c->xfrcnt = value & 0x77;
1123 break;
1124 case 0x0F:
1125 i2c->xtcntlss = value;
1126 break;
1127 case 0x10:
1128 i2c->directcntl = value & 0x7;
1129 break;
1130 }
1131 }
1132
1133 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1134 {
1135 uint32_t ret;
1136
1137 #ifdef DEBUG_I2C
1138 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1139 #endif
1140 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1141 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1142
1143 return ret;
1144 }
1145
1146 static void ppc4xx_i2c_writew (void *opaque,
1147 target_phys_addr_t addr, uint32_t value)
1148 {
1149 #ifdef DEBUG_I2C
1150 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1151 value);
1152 #endif
1153 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1154 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1155 }
1156
1157 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1158 {
1159 uint32_t ret;
1160
1161 #ifdef DEBUG_I2C
1162 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1163 #endif
1164 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1165 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1166 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1167 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1168
1169 return ret;
1170 }
1171
1172 static void ppc4xx_i2c_writel (void *opaque,
1173 target_phys_addr_t addr, uint32_t value)
1174 {
1175 #ifdef DEBUG_I2C
1176 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1177 value);
1178 #endif
1179 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1180 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1181 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1182 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1183 }
1184
1185 static const MemoryRegionOps i2c_ops = {
1186 .old_mmio = {
1187 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1188 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1189 },
1190 .endianness = DEVICE_NATIVE_ENDIAN,
1191 };
1192
1193 static void ppc4xx_i2c_reset (void *opaque)
1194 {
1195 ppc4xx_i2c_t *i2c;
1196
1197 i2c = opaque;
1198 i2c->mdata = 0x00;
1199 i2c->sdata = 0x00;
1200 i2c->cntl = 0x00;
1201 i2c->mdcntl = 0x00;
1202 i2c->sts = 0x00;
1203 i2c->extsts = 0x00;
1204 i2c->clkdiv = 0x00;
1205 i2c->xfrcnt = 0x00;
1206 i2c->directcntl = 0x0F;
1207 }
1208
1209 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1210 {
1211 ppc4xx_i2c_t *i2c;
1212
1213 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1214 i2c->irq = irq;
1215 #ifdef DEBUG_I2C
1216 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1217 #endif
1218 memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
1219 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1220 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1221 }
1222
1223 /*****************************************************************************/
1224 /* General purpose timers */
1225 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1226 struct ppc4xx_gpt_t {
1227 MemoryRegion iomem;
1228 int64_t tb_offset;
1229 uint32_t tb_freq;
1230 struct QEMUTimer *timer;
1231 qemu_irq irqs[5];
1232 uint32_t oe;
1233 uint32_t ol;
1234 uint32_t im;
1235 uint32_t is;
1236 uint32_t ie;
1237 uint32_t comp[5];
1238 uint32_t mask[5];
1239 };
1240
1241 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1242 {
1243 #ifdef DEBUG_GPT
1244 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1245 #endif
1246 /* XXX: generate a bus fault */
1247 return -1;
1248 }
1249
1250 static void ppc4xx_gpt_writeb (void *opaque,
1251 target_phys_addr_t addr, uint32_t value)
1252 {
1253 #ifdef DEBUG_I2C
1254 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1255 value);
1256 #endif
1257 /* XXX: generate a bus fault */
1258 }
1259
1260 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1261 {
1262 #ifdef DEBUG_GPT
1263 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1264 #endif
1265 /* XXX: generate a bus fault */
1266 return -1;
1267 }
1268
1269 static void ppc4xx_gpt_writew (void *opaque,
1270 target_phys_addr_t addr, uint32_t value)
1271 {
1272 #ifdef DEBUG_I2C
1273 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1274 value);
1275 #endif
1276 /* XXX: generate a bus fault */
1277 }
1278
1279 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1280 {
1281 /* XXX: TODO */
1282 return 0;
1283 }
1284
1285 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1286 {
1287 /* XXX: TODO */
1288 }
1289
1290 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1291 {
1292 uint32_t mask;
1293 int i;
1294
1295 mask = 0x80000000;
1296 for (i = 0; i < 5; i++) {
1297 if (gpt->oe & mask) {
1298 /* Output is enabled */
1299 if (ppc4xx_gpt_compare(gpt, i)) {
1300 /* Comparison is OK */
1301 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1302 } else {
1303 /* Comparison is KO */
1304 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1305 }
1306 }
1307 mask = mask >> 1;
1308 }
1309 }
1310
1311 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1312 {
1313 uint32_t mask;
1314 int i;
1315
1316 mask = 0x00008000;
1317 for (i = 0; i < 5; i++) {
1318 if (gpt->is & gpt->im & mask)
1319 qemu_irq_raise(gpt->irqs[i]);
1320 else
1321 qemu_irq_lower(gpt->irqs[i]);
1322 mask = mask >> 1;
1323 }
1324 }
1325
1326 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1327 {
1328 /* XXX: TODO */
1329 }
1330
1331 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1332 {
1333 ppc4xx_gpt_t *gpt;
1334 uint32_t ret;
1335 int idx;
1336
1337 #ifdef DEBUG_GPT
1338 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1339 #endif
1340 gpt = opaque;
1341 switch (addr) {
1342 case 0x00:
1343 /* Time base counter */
1344 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1345 gpt->tb_freq, get_ticks_per_sec());
1346 break;
1347 case 0x10:
1348 /* Output enable */
1349 ret = gpt->oe;
1350 break;
1351 case 0x14:
1352 /* Output level */
1353 ret = gpt->ol;
1354 break;
1355 case 0x18:
1356 /* Interrupt mask */
1357 ret = gpt->im;
1358 break;
1359 case 0x1C:
1360 case 0x20:
1361 /* Interrupt status */
1362 ret = gpt->is;
1363 break;
1364 case 0x24:
1365 /* Interrupt enable */
1366 ret = gpt->ie;
1367 break;
1368 case 0x80 ... 0x90:
1369 /* Compare timer */
1370 idx = (addr - 0x80) >> 2;
1371 ret = gpt->comp[idx];
1372 break;
1373 case 0xC0 ... 0xD0:
1374 /* Compare mask */
1375 idx = (addr - 0xC0) >> 2;
1376 ret = gpt->mask[idx];
1377 break;
1378 default:
1379 ret = -1;
1380 break;
1381 }
1382
1383 return ret;
1384 }
1385
1386 static void ppc4xx_gpt_writel (void *opaque,
1387 target_phys_addr_t addr, uint32_t value)
1388 {
1389 ppc4xx_gpt_t *gpt;
1390 int idx;
1391
1392 #ifdef DEBUG_I2C
1393 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1394 value);
1395 #endif
1396 gpt = opaque;
1397 switch (addr) {
1398 case 0x00:
1399 /* Time base counter */
1400 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1401 - qemu_get_clock_ns(vm_clock);
1402 ppc4xx_gpt_compute_timer(gpt);
1403 break;
1404 case 0x10:
1405 /* Output enable */
1406 gpt->oe = value & 0xF8000000;
1407 ppc4xx_gpt_set_outputs(gpt);
1408 break;
1409 case 0x14:
1410 /* Output level */
1411 gpt->ol = value & 0xF8000000;
1412 ppc4xx_gpt_set_outputs(gpt);
1413 break;
1414 case 0x18:
1415 /* Interrupt mask */
1416 gpt->im = value & 0x0000F800;
1417 break;
1418 case 0x1C:
1419 /* Interrupt status set */
1420 gpt->is |= value & 0x0000F800;
1421 ppc4xx_gpt_set_irqs(gpt);
1422 break;
1423 case 0x20:
1424 /* Interrupt status clear */
1425 gpt->is &= ~(value & 0x0000F800);
1426 ppc4xx_gpt_set_irqs(gpt);
1427 break;
1428 case 0x24:
1429 /* Interrupt enable */
1430 gpt->ie = value & 0x0000F800;
1431 ppc4xx_gpt_set_irqs(gpt);
1432 break;
1433 case 0x80 ... 0x90:
1434 /* Compare timer */
1435 idx = (addr - 0x80) >> 2;
1436 gpt->comp[idx] = value & 0xF8000000;
1437 ppc4xx_gpt_compute_timer(gpt);
1438 break;
1439 case 0xC0 ... 0xD0:
1440 /* Compare mask */
1441 idx = (addr - 0xC0) >> 2;
1442 gpt->mask[idx] = value & 0xF8000000;
1443 ppc4xx_gpt_compute_timer(gpt);
1444 break;
1445 }
1446 }
1447
1448 static const MemoryRegionOps gpt_ops = {
1449 .old_mmio = {
1450 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1451 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1452 },
1453 .endianness = DEVICE_NATIVE_ENDIAN,
1454 };
1455
1456 static void ppc4xx_gpt_cb (void *opaque)
1457 {
1458 ppc4xx_gpt_t *gpt;
1459
1460 gpt = opaque;
1461 ppc4xx_gpt_set_irqs(gpt);
1462 ppc4xx_gpt_set_outputs(gpt);
1463 ppc4xx_gpt_compute_timer(gpt);
1464 }
1465
1466 static void ppc4xx_gpt_reset (void *opaque)
1467 {
1468 ppc4xx_gpt_t *gpt;
1469 int i;
1470
1471 gpt = opaque;
1472 qemu_del_timer(gpt->timer);
1473 gpt->oe = 0x00000000;
1474 gpt->ol = 0x00000000;
1475 gpt->im = 0x00000000;
1476 gpt->is = 0x00000000;
1477 gpt->ie = 0x00000000;
1478 for (i = 0; i < 5; i++) {
1479 gpt->comp[i] = 0x00000000;
1480 gpt->mask[i] = 0x00000000;
1481 }
1482 }
1483
1484 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1485 {
1486 ppc4xx_gpt_t *gpt;
1487 int i;
1488
1489 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1490 for (i = 0; i < 5; i++) {
1491 gpt->irqs[i] = irqs[i];
1492 }
1493 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1494 #ifdef DEBUG_GPT
1495 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1496 #endif
1497 memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
1498 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1499 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1500 }
1501
1502 /*****************************************************************************/
1503 /* MAL */
1504 enum {
1505 MAL0_CFG = 0x180,
1506 MAL0_ESR = 0x181,
1507 MAL0_IER = 0x182,
1508 MAL0_TXCASR = 0x184,
1509 MAL0_TXCARR = 0x185,
1510 MAL0_TXEOBISR = 0x186,
1511 MAL0_TXDEIR = 0x187,
1512 MAL0_RXCASR = 0x190,
1513 MAL0_RXCARR = 0x191,
1514 MAL0_RXEOBISR = 0x192,
1515 MAL0_RXDEIR = 0x193,
1516 MAL0_TXCTP0R = 0x1A0,
1517 MAL0_TXCTP1R = 0x1A1,
1518 MAL0_TXCTP2R = 0x1A2,
1519 MAL0_TXCTP3R = 0x1A3,
1520 MAL0_RXCTP0R = 0x1C0,
1521 MAL0_RXCTP1R = 0x1C1,
1522 MAL0_RCBS0 = 0x1E0,
1523 MAL0_RCBS1 = 0x1E1,
1524 };
1525
1526 typedef struct ppc40x_mal_t ppc40x_mal_t;
1527 struct ppc40x_mal_t {
1528 qemu_irq irqs[4];
1529 uint32_t cfg;
1530 uint32_t esr;
1531 uint32_t ier;
1532 uint32_t txcasr;
1533 uint32_t txcarr;
1534 uint32_t txeobisr;
1535 uint32_t txdeir;
1536 uint32_t rxcasr;
1537 uint32_t rxcarr;
1538 uint32_t rxeobisr;
1539 uint32_t rxdeir;
1540 uint32_t txctpr[4];
1541 uint32_t rxctpr[2];
1542 uint32_t rcbs[2];
1543 };
1544
1545 static void ppc40x_mal_reset (void *opaque);
1546
1547 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1548 {
1549 ppc40x_mal_t *mal;
1550 uint32_t ret;
1551
1552 mal = opaque;
1553 switch (dcrn) {
1554 case MAL0_CFG:
1555 ret = mal->cfg;
1556 break;
1557 case MAL0_ESR:
1558 ret = mal->esr;
1559 break;
1560 case MAL0_IER:
1561 ret = mal->ier;
1562 break;
1563 case MAL0_TXCASR:
1564 ret = mal->txcasr;
1565 break;
1566 case MAL0_TXCARR:
1567 ret = mal->txcarr;
1568 break;
1569 case MAL0_TXEOBISR:
1570 ret = mal->txeobisr;
1571 break;
1572 case MAL0_TXDEIR:
1573 ret = mal->txdeir;
1574 break;
1575 case MAL0_RXCASR:
1576 ret = mal->rxcasr;
1577 break;
1578 case MAL0_RXCARR:
1579 ret = mal->rxcarr;
1580 break;
1581 case MAL0_RXEOBISR:
1582 ret = mal->rxeobisr;
1583 break;
1584 case MAL0_RXDEIR:
1585 ret = mal->rxdeir;
1586 break;
1587 case MAL0_TXCTP0R:
1588 ret = mal->txctpr[0];
1589 break;
1590 case MAL0_TXCTP1R:
1591 ret = mal->txctpr[1];
1592 break;
1593 case MAL0_TXCTP2R:
1594 ret = mal->txctpr[2];
1595 break;
1596 case MAL0_TXCTP3R:
1597 ret = mal->txctpr[3];
1598 break;
1599 case MAL0_RXCTP0R:
1600 ret = mal->rxctpr[0];
1601 break;
1602 case MAL0_RXCTP1R:
1603 ret = mal->rxctpr[1];
1604 break;
1605 case MAL0_RCBS0:
1606 ret = mal->rcbs[0];
1607 break;
1608 case MAL0_RCBS1:
1609 ret = mal->rcbs[1];
1610 break;
1611 default:
1612 ret = 0;
1613 break;
1614 }
1615
1616 return ret;
1617 }
1618
1619 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1620 {
1621 ppc40x_mal_t *mal;
1622 int idx;
1623
1624 mal = opaque;
1625 switch (dcrn) {
1626 case MAL0_CFG:
1627 if (val & 0x80000000)
1628 ppc40x_mal_reset(mal);
1629 mal->cfg = val & 0x00FFC087;
1630 break;
1631 case MAL0_ESR:
1632 /* Read/clear */
1633 mal->esr &= ~val;
1634 break;
1635 case MAL0_IER:
1636 mal->ier = val & 0x0000001F;
1637 break;
1638 case MAL0_TXCASR:
1639 mal->txcasr = val & 0xF0000000;
1640 break;
1641 case MAL0_TXCARR:
1642 mal->txcarr = val & 0xF0000000;
1643 break;
1644 case MAL0_TXEOBISR:
1645 /* Read/clear */
1646 mal->txeobisr &= ~val;
1647 break;
1648 case MAL0_TXDEIR:
1649 /* Read/clear */
1650 mal->txdeir &= ~val;
1651 break;
1652 case MAL0_RXCASR:
1653 mal->rxcasr = val & 0xC0000000;
1654 break;
1655 case MAL0_RXCARR:
1656 mal->rxcarr = val & 0xC0000000;
1657 break;
1658 case MAL0_RXEOBISR:
1659 /* Read/clear */
1660 mal->rxeobisr &= ~val;
1661 break;
1662 case MAL0_RXDEIR:
1663 /* Read/clear */
1664 mal->rxdeir &= ~val;
1665 break;
1666 case MAL0_TXCTP0R:
1667 idx = 0;
1668 goto update_tx_ptr;
1669 case MAL0_TXCTP1R:
1670 idx = 1;
1671 goto update_tx_ptr;
1672 case MAL0_TXCTP2R:
1673 idx = 2;
1674 goto update_tx_ptr;
1675 case MAL0_TXCTP3R:
1676 idx = 3;
1677 update_tx_ptr:
1678 mal->txctpr[idx] = val;
1679 break;
1680 case MAL0_RXCTP0R:
1681 idx = 0;
1682 goto update_rx_ptr;
1683 case MAL0_RXCTP1R:
1684 idx = 1;
1685 update_rx_ptr:
1686 mal->rxctpr[idx] = val;
1687 break;
1688 case MAL0_RCBS0:
1689 idx = 0;
1690 goto update_rx_size;
1691 case MAL0_RCBS1:
1692 idx = 1;
1693 update_rx_size:
1694 mal->rcbs[idx] = val & 0x000000FF;
1695 break;
1696 }
1697 }
1698
1699 static void ppc40x_mal_reset (void *opaque)
1700 {
1701 ppc40x_mal_t *mal;
1702
1703 mal = opaque;
1704 mal->cfg = 0x0007C000;
1705 mal->esr = 0x00000000;
1706 mal->ier = 0x00000000;
1707 mal->rxcasr = 0x00000000;
1708 mal->rxdeir = 0x00000000;
1709 mal->rxeobisr = 0x00000000;
1710 mal->txcasr = 0x00000000;
1711 mal->txdeir = 0x00000000;
1712 mal->txeobisr = 0x00000000;
1713 }
1714
1715 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1716 {
1717 ppc40x_mal_t *mal;
1718 int i;
1719
1720 mal = g_malloc0(sizeof(ppc40x_mal_t));
1721 for (i = 0; i < 4; i++)
1722 mal->irqs[i] = irqs[i];
1723 qemu_register_reset(&ppc40x_mal_reset, mal);
1724 ppc_dcr_register(env, MAL0_CFG,
1725 mal, &dcr_read_mal, &dcr_write_mal);
1726 ppc_dcr_register(env, MAL0_ESR,
1727 mal, &dcr_read_mal, &dcr_write_mal);
1728 ppc_dcr_register(env, MAL0_IER,
1729 mal, &dcr_read_mal, &dcr_write_mal);
1730 ppc_dcr_register(env, MAL0_TXCASR,
1731 mal, &dcr_read_mal, &dcr_write_mal);
1732 ppc_dcr_register(env, MAL0_TXCARR,
1733 mal, &dcr_read_mal, &dcr_write_mal);
1734 ppc_dcr_register(env, MAL0_TXEOBISR,
1735 mal, &dcr_read_mal, &dcr_write_mal);
1736 ppc_dcr_register(env, MAL0_TXDEIR,
1737 mal, &dcr_read_mal, &dcr_write_mal);
1738 ppc_dcr_register(env, MAL0_RXCASR,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_RXCARR,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_RXEOBISR,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_RXDEIR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_TXCTP0R,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_TXCTP1R,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_TXCTP2R,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_TXCTP3R,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_RXCTP0R,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_RXCTP1R,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_RCBS0,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_RCBS1,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 }
1763
1764 /*****************************************************************************/
1765 /* SPR */
1766 void ppc40x_core_reset (CPUState *env)
1767 {
1768 target_ulong dbsr;
1769
1770 printf("Reset PowerPC core\n");
1771 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1772 /* XXX: TOFIX */
1773 #if 0
1774 cpu_reset(env);
1775 #else
1776 qemu_system_reset_request();
1777 #endif
1778 dbsr = env->spr[SPR_40x_DBSR];
1779 dbsr &= ~0x00000300;
1780 dbsr |= 0x00000100;
1781 env->spr[SPR_40x_DBSR] = dbsr;
1782 }
1783
1784 void ppc40x_chip_reset (CPUState *env)
1785 {
1786 target_ulong dbsr;
1787
1788 printf("Reset PowerPC chip\n");
1789 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1790 /* XXX: TOFIX */
1791 #if 0
1792 cpu_reset(env);
1793 #else
1794 qemu_system_reset_request();
1795 #endif
1796 /* XXX: TODO reset all internal peripherals */
1797 dbsr = env->spr[SPR_40x_DBSR];
1798 dbsr &= ~0x00000300;
1799 dbsr |= 0x00000200;
1800 env->spr[SPR_40x_DBSR] = dbsr;
1801 }
1802
1803 void ppc40x_system_reset (CPUState *env)
1804 {
1805 printf("Reset PowerPC system\n");
1806 qemu_system_reset_request();
1807 }
1808
1809 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1810 {
1811 switch ((val >> 28) & 0x3) {
1812 case 0x0:
1813 /* No action */
1814 break;
1815 case 0x1:
1816 /* Core reset */
1817 ppc40x_core_reset(env);
1818 break;
1819 case 0x2:
1820 /* Chip reset */
1821 ppc40x_chip_reset(env);
1822 break;
1823 case 0x3:
1824 /* System reset */
1825 ppc40x_system_reset(env);
1826 break;
1827 }
1828 }
1829
1830 /*****************************************************************************/
1831 /* PowerPC 405CR */
1832 enum {
1833 PPC405CR_CPC0_PLLMR = 0x0B0,
1834 PPC405CR_CPC0_CR0 = 0x0B1,
1835 PPC405CR_CPC0_CR1 = 0x0B2,
1836 PPC405CR_CPC0_PSR = 0x0B4,
1837 PPC405CR_CPC0_JTAGID = 0x0B5,
1838 PPC405CR_CPC0_ER = 0x0B9,
1839 PPC405CR_CPC0_FR = 0x0BA,
1840 PPC405CR_CPC0_SR = 0x0BB,
1841 };
1842
1843 enum {
1844 PPC405CR_CPU_CLK = 0,
1845 PPC405CR_TMR_CLK = 1,
1846 PPC405CR_PLB_CLK = 2,
1847 PPC405CR_SDRAM_CLK = 3,
1848 PPC405CR_OPB_CLK = 4,
1849 PPC405CR_EXT_CLK = 5,
1850 PPC405CR_UART_CLK = 6,
1851 PPC405CR_CLK_NB = 7,
1852 };
1853
1854 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1855 struct ppc405cr_cpc_t {
1856 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1857 uint32_t sysclk;
1858 uint32_t psr;
1859 uint32_t cr0;
1860 uint32_t cr1;
1861 uint32_t jtagid;
1862 uint32_t pllmr;
1863 uint32_t er;
1864 uint32_t fr;
1865 };
1866
1867 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1868 {
1869 uint64_t VCO_out, PLL_out;
1870 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1871 int M, D0, D1, D2;
1872
1873 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1874 if (cpc->pllmr & 0x80000000) {
1875 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1876 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1877 M = D0 * D1 * D2;
1878 VCO_out = cpc->sysclk * M;
1879 if (VCO_out < 400000000 || VCO_out > 800000000) {
1880 /* PLL cannot lock */
1881 cpc->pllmr &= ~0x80000000;
1882 goto bypass_pll;
1883 }
1884 PLL_out = VCO_out / D2;
1885 } else {
1886 /* Bypass PLL */
1887 bypass_pll:
1888 M = D0;
1889 PLL_out = cpc->sysclk * M;
1890 }
1891 CPU_clk = PLL_out;
1892 if (cpc->cr1 & 0x00800000)
1893 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1894 else
1895 TMR_clk = CPU_clk;
1896 PLB_clk = CPU_clk / D0;
1897 SDRAM_clk = PLB_clk;
1898 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1899 OPB_clk = PLB_clk / D0;
1900 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1901 EXT_clk = PLB_clk / D0;
1902 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1903 UART_clk = CPU_clk / D0;
1904 /* Setup CPU clocks */
1905 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1906 /* Setup time-base clock */
1907 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1908 /* Setup PLB clock */
1909 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1910 /* Setup SDRAM clock */
1911 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1912 /* Setup OPB clock */
1913 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1914 /* Setup external clock */
1915 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1916 /* Setup UART clock */
1917 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1918 }
1919
1920 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1921 {
1922 ppc405cr_cpc_t *cpc;
1923 uint32_t ret;
1924
1925 cpc = opaque;
1926 switch (dcrn) {
1927 case PPC405CR_CPC0_PLLMR:
1928 ret = cpc->pllmr;
1929 break;
1930 case PPC405CR_CPC0_CR0:
1931 ret = cpc->cr0;
1932 break;
1933 case PPC405CR_CPC0_CR1:
1934 ret = cpc->cr1;
1935 break;
1936 case PPC405CR_CPC0_PSR:
1937 ret = cpc->psr;
1938 break;
1939 case PPC405CR_CPC0_JTAGID:
1940 ret = cpc->jtagid;
1941 break;
1942 case PPC405CR_CPC0_ER:
1943 ret = cpc->er;
1944 break;
1945 case PPC405CR_CPC0_FR:
1946 ret = cpc->fr;
1947 break;
1948 case PPC405CR_CPC0_SR:
1949 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1950 break;
1951 default:
1952 /* Avoid gcc warning */
1953 ret = 0;
1954 break;
1955 }
1956
1957 return ret;
1958 }
1959
1960 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1961 {
1962 ppc405cr_cpc_t *cpc;
1963
1964 cpc = opaque;
1965 switch (dcrn) {
1966 case PPC405CR_CPC0_PLLMR:
1967 cpc->pllmr = val & 0xFFF77C3F;
1968 break;
1969 case PPC405CR_CPC0_CR0:
1970 cpc->cr0 = val & 0x0FFFFFFE;
1971 break;
1972 case PPC405CR_CPC0_CR1:
1973 cpc->cr1 = val & 0x00800000;
1974 break;
1975 case PPC405CR_CPC0_PSR:
1976 /* Read-only */
1977 break;
1978 case PPC405CR_CPC0_JTAGID:
1979 /* Read-only */
1980 break;
1981 case PPC405CR_CPC0_ER:
1982 cpc->er = val & 0xBFFC0000;
1983 break;
1984 case PPC405CR_CPC0_FR:
1985 cpc->fr = val & 0xBFFC0000;
1986 break;
1987 case PPC405CR_CPC0_SR:
1988 /* Read-only */
1989 break;
1990 }
1991 }
1992
1993 static void ppc405cr_cpc_reset (void *opaque)
1994 {
1995 ppc405cr_cpc_t *cpc;
1996 int D;
1997
1998 cpc = opaque;
1999 /* Compute PLLMR value from PSR settings */
2000 cpc->pllmr = 0x80000000;
2001 /* PFWD */
2002 switch ((cpc->psr >> 30) & 3) {
2003 case 0:
2004 /* Bypass */
2005 cpc->pllmr &= ~0x80000000;
2006 break;
2007 case 1:
2008 /* Divide by 3 */
2009 cpc->pllmr |= 5 << 16;
2010 break;
2011 case 2:
2012 /* Divide by 4 */
2013 cpc->pllmr |= 4 << 16;
2014 break;
2015 case 3:
2016 /* Divide by 6 */
2017 cpc->pllmr |= 2 << 16;
2018 break;
2019 }
2020 /* PFBD */
2021 D = (cpc->psr >> 28) & 3;
2022 cpc->pllmr |= (D + 1) << 20;
2023 /* PT */
2024 D = (cpc->psr >> 25) & 7;
2025 switch (D) {
2026 case 0x2:
2027 cpc->pllmr |= 0x13;
2028 break;
2029 case 0x4:
2030 cpc->pllmr |= 0x15;
2031 break;
2032 case 0x5:
2033 cpc->pllmr |= 0x16;
2034 break;
2035 default:
2036 break;
2037 }
2038 /* PDC */
2039 D = (cpc->psr >> 23) & 3;
2040 cpc->pllmr |= D << 26;
2041 /* ODP */
2042 D = (cpc->psr >> 21) & 3;
2043 cpc->pllmr |= D << 10;
2044 /* EBPD */
2045 D = (cpc->psr >> 17) & 3;
2046 cpc->pllmr |= D << 24;
2047 cpc->cr0 = 0x0000003C;
2048 cpc->cr1 = 0x2B0D8800;
2049 cpc->er = 0x00000000;
2050 cpc->fr = 0x00000000;
2051 ppc405cr_clk_setup(cpc);
2052 }
2053
2054 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2055 {
2056 int D;
2057
2058 /* XXX: this should be read from IO pins */
2059 cpc->psr = 0x00000000; /* 8 bits ROM */
2060 /* PFWD */
2061 D = 0x2; /* Divide by 4 */
2062 cpc->psr |= D << 30;
2063 /* PFBD */
2064 D = 0x1; /* Divide by 2 */
2065 cpc->psr |= D << 28;
2066 /* PDC */
2067 D = 0x1; /* Divide by 2 */
2068 cpc->psr |= D << 23;
2069 /* PT */
2070 D = 0x5; /* M = 16 */
2071 cpc->psr |= D << 25;
2072 /* ODP */
2073 D = 0x1; /* Divide by 2 */
2074 cpc->psr |= D << 21;
2075 /* EBDP */
2076 D = 0x2; /* Divide by 4 */
2077 cpc->psr |= D << 17;
2078 }
2079
2080 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2081 uint32_t sysclk)
2082 {
2083 ppc405cr_cpc_t *cpc;
2084
2085 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2086 memcpy(cpc->clk_setup, clk_setup,
2087 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2088 cpc->sysclk = sysclk;
2089 cpc->jtagid = 0x42051049;
2090 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2091 &dcr_read_crcpc, &dcr_write_crcpc);
2092 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2093 &dcr_read_crcpc, &dcr_write_crcpc);
2094 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2095 &dcr_read_crcpc, &dcr_write_crcpc);
2096 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2097 &dcr_read_crcpc, &dcr_write_crcpc);
2098 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2099 &dcr_read_crcpc, &dcr_write_crcpc);
2100 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2101 &dcr_read_crcpc, &dcr_write_crcpc);
2102 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2103 &dcr_read_crcpc, &dcr_write_crcpc);
2104 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc405cr_clk_init(cpc);
2107 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2108 }
2109
2110 CPUState *ppc405cr_init (MemoryRegion ram_memories[4],
2111 target_phys_addr_t ram_bases[4],
2112 target_phys_addr_t ram_sizes[4],
2113 uint32_t sysclk, qemu_irq **picp,
2114 int do_init)
2115 {
2116 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2117 qemu_irq dma_irqs[4];
2118 CPUState *env;
2119 qemu_irq *pic, *irqs;
2120
2121 memset(clk_setup, 0, sizeof(clk_setup));
2122 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2123 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2124 /* Memory mapped devices registers */
2125 /* PLB arbitrer */
2126 ppc4xx_plb_init(env);
2127 /* PLB to OPB bridge */
2128 ppc4xx_pob_init(env);
2129 /* OBP arbitrer */
2130 ppc4xx_opba_init(0xef600600);
2131 /* Universal interrupt controller */
2132 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2133 irqs[PPCUIC_OUTPUT_INT] =
2134 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2135 irqs[PPCUIC_OUTPUT_CINT] =
2136 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2137 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2138 *picp = pic;
2139 /* SDRAM controller */
2140 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2141 ram_bases, ram_sizes, do_init);
2142 /* External bus controller */
2143 ppc405_ebc_init(env);
2144 /* DMA controller */
2145 dma_irqs[0] = pic[26];
2146 dma_irqs[1] = pic[25];
2147 dma_irqs[2] = pic[24];
2148 dma_irqs[3] = pic[23];
2149 ppc405_dma_init(env, dma_irqs);
2150 /* Serial ports */
2151 if (serial_hds[0] != NULL) {
2152 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2153 serial_hds[0], 1, 1);
2154 }
2155 if (serial_hds[1] != NULL) {
2156 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2157 serial_hds[1], 1, 1);
2158 }
2159 /* IIC controller */
2160 ppc405_i2c_init(0xef600500, pic[2]);
2161 /* GPIO */
2162 ppc405_gpio_init(0xef600700);
2163 /* CPU control */
2164 ppc405cr_cpc_init(env, clk_setup, sysclk);
2165
2166 return env;
2167 }
2168
2169 /*****************************************************************************/
2170 /* PowerPC 405EP */
2171 /* CPU control */
2172 enum {
2173 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2174 PPC405EP_CPC0_BOOT = 0x0F1,
2175 PPC405EP_CPC0_EPCTL = 0x0F3,
2176 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2177 PPC405EP_CPC0_UCR = 0x0F5,
2178 PPC405EP_CPC0_SRR = 0x0F6,
2179 PPC405EP_CPC0_JTAGID = 0x0F7,
2180 PPC405EP_CPC0_PCI = 0x0F9,
2181 #if 0
2182 PPC405EP_CPC0_ER = xxx,
2183 PPC405EP_CPC0_FR = xxx,
2184 PPC405EP_CPC0_SR = xxx,
2185 #endif
2186 };
2187
2188 enum {
2189 PPC405EP_CPU_CLK = 0,
2190 PPC405EP_PLB_CLK = 1,
2191 PPC405EP_OPB_CLK = 2,
2192 PPC405EP_EBC_CLK = 3,
2193 PPC405EP_MAL_CLK = 4,
2194 PPC405EP_PCI_CLK = 5,
2195 PPC405EP_UART0_CLK = 6,
2196 PPC405EP_UART1_CLK = 7,
2197 PPC405EP_CLK_NB = 8,
2198 };
2199
2200 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2201 struct ppc405ep_cpc_t {
2202 uint32_t sysclk;
2203 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2204 uint32_t boot;
2205 uint32_t epctl;
2206 uint32_t pllmr[2];
2207 uint32_t ucr;
2208 uint32_t srr;
2209 uint32_t jtagid;
2210 uint32_t pci;
2211 /* Clock and power management */
2212 uint32_t er;
2213 uint32_t fr;
2214 uint32_t sr;
2215 };
2216
2217 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2218 {
2219 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2220 uint32_t UART0_clk, UART1_clk;
2221 uint64_t VCO_out, PLL_out;
2222 int M, D;
2223
2224 VCO_out = 0;
2225 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2226 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2227 #ifdef DEBUG_CLOCKS_LL
2228 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2229 #endif
2230 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2231 #ifdef DEBUG_CLOCKS_LL
2232 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2233 #endif
2234 VCO_out = cpc->sysclk * M * D;
2235 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2236 /* Error - unlock the PLL */
2237 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2238 #if 0
2239 cpc->pllmr[1] &= ~0x80000000;
2240 goto pll_bypass;
2241 #endif
2242 }
2243 PLL_out = VCO_out / D;
2244 /* Pretend the PLL is locked */
2245 cpc->boot |= 0x00000001;
2246 } else {
2247 #if 0
2248 pll_bypass:
2249 #endif
2250 PLL_out = cpc->sysclk;
2251 if (cpc->pllmr[1] & 0x40000000) {
2252 /* Pretend the PLL is not locked */
2253 cpc->boot &= ~0x00000001;
2254 }
2255 }
2256 /* Now, compute all other clocks */
2257 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2258 #ifdef DEBUG_CLOCKS_LL
2259 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2260 #endif
2261 CPU_clk = PLL_out / D;
2262 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2263 #ifdef DEBUG_CLOCKS_LL
2264 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2265 #endif
2266 PLB_clk = CPU_clk / D;
2267 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2268 #ifdef DEBUG_CLOCKS_LL
2269 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2270 #endif
2271 OPB_clk = PLB_clk / D;
2272 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2273 #ifdef DEBUG_CLOCKS_LL
2274 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2275 #endif
2276 EBC_clk = PLB_clk / D;
2277 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2278 #ifdef DEBUG_CLOCKS_LL
2279 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2280 #endif
2281 MAL_clk = PLB_clk / D;
2282 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2283 #ifdef DEBUG_CLOCKS_LL
2284 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2285 #endif
2286 PCI_clk = PLB_clk / D;
2287 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2288 #ifdef DEBUG_CLOCKS_LL
2289 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2290 #endif
2291 UART0_clk = PLL_out / D;
2292 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2293 #ifdef DEBUG_CLOCKS_LL
2294 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2295 #endif
2296 UART1_clk = PLL_out / D;
2297 #ifdef DEBUG_CLOCKS
2298 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2299 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2300 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2301 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2302 " UART1 %" PRIu32 "\n",
2303 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2304 UART0_clk, UART1_clk);
2305 #endif
2306 /* Setup CPU clocks */
2307 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2308 /* Setup PLB clock */
2309 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2310 /* Setup OPB clock */
2311 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2312 /* Setup external clock */
2313 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2314 /* Setup MAL clock */
2315 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2316 /* Setup PCI clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2318 /* Setup UART0 clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2320 /* Setup UART1 clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2322 }
2323
2324 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2325 {
2326 ppc405ep_cpc_t *cpc;
2327 uint32_t ret;
2328
2329 cpc = opaque;
2330 switch (dcrn) {
2331 case PPC405EP_CPC0_BOOT:
2332 ret = cpc->boot;
2333 break;
2334 case PPC405EP_CPC0_EPCTL:
2335 ret = cpc->epctl;
2336 break;
2337 case PPC405EP_CPC0_PLLMR0:
2338 ret = cpc->pllmr[0];
2339 break;
2340 case PPC405EP_CPC0_PLLMR1:
2341 ret = cpc->pllmr[1];
2342 break;
2343 case PPC405EP_CPC0_UCR:
2344 ret = cpc->ucr;
2345 break;
2346 case PPC405EP_CPC0_SRR:
2347 ret = cpc->srr;
2348 break;
2349 case PPC405EP_CPC0_JTAGID:
2350 ret = cpc->jtagid;
2351 break;
2352 case PPC405EP_CPC0_PCI:
2353 ret = cpc->pci;
2354 break;
2355 default:
2356 /* Avoid gcc warning */
2357 ret = 0;
2358 break;
2359 }
2360
2361 return ret;
2362 }
2363
2364 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2365 {
2366 ppc405ep_cpc_t *cpc;
2367
2368 cpc = opaque;
2369 switch (dcrn) {
2370 case PPC405EP_CPC0_BOOT:
2371 /* Read-only register */
2372 break;
2373 case PPC405EP_CPC0_EPCTL:
2374 /* Don't care for now */
2375 cpc->epctl = val & 0xC00000F3;
2376 break;
2377 case PPC405EP_CPC0_PLLMR0:
2378 cpc->pllmr[0] = val & 0x00633333;
2379 ppc405ep_compute_clocks(cpc);
2380 break;
2381 case PPC405EP_CPC0_PLLMR1:
2382 cpc->pllmr[1] = val & 0xC0F73FFF;
2383 ppc405ep_compute_clocks(cpc);
2384 break;
2385 case PPC405EP_CPC0_UCR:
2386 /* UART control - don't care for now */
2387 cpc->ucr = val & 0x003F7F7F;
2388 break;
2389 case PPC405EP_CPC0_SRR:
2390 cpc->srr = val;
2391 break;
2392 case PPC405EP_CPC0_JTAGID:
2393 /* Read-only */
2394 break;
2395 case PPC405EP_CPC0_PCI:
2396 cpc->pci = val;
2397 break;
2398 }
2399 }
2400
2401 static void ppc405ep_cpc_reset (void *opaque)
2402 {
2403 ppc405ep_cpc_t *cpc = opaque;
2404
2405 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2406 cpc->epctl = 0x00000000;
2407 cpc->pllmr[0] = 0x00011010;
2408 cpc->pllmr[1] = 0x40000000;
2409 cpc->ucr = 0x00000000;
2410 cpc->srr = 0x00040000;
2411 cpc->pci = 0x00000000;
2412 cpc->er = 0x00000000;
2413 cpc->fr = 0x00000000;
2414 cpc->sr = 0x00000000;
2415 ppc405ep_compute_clocks(cpc);
2416 }
2417
2418 /* XXX: sysclk should be between 25 and 100 MHz */
2419 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2420 uint32_t sysclk)
2421 {
2422 ppc405ep_cpc_t *cpc;
2423
2424 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2425 memcpy(cpc->clk_setup, clk_setup,
2426 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2427 cpc->jtagid = 0x20267049;
2428 cpc->sysclk = sysclk;
2429 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2430 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2431 &dcr_read_epcpc, &dcr_write_epcpc);
2432 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2433 &dcr_read_epcpc, &dcr_write_epcpc);
2434 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2435 &dcr_read_epcpc, &dcr_write_epcpc);
2436 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2437 &dcr_read_epcpc, &dcr_write_epcpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 #if 0
2447 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2453 #endif
2454 }
2455
2456 CPUState *ppc405ep_init (MemoryRegion ram_memories[2],
2457 target_phys_addr_t ram_bases[2],
2458 target_phys_addr_t ram_sizes[2],
2459 uint32_t sysclk, qemu_irq **picp,
2460 int do_init)
2461 {
2462 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2463 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2464 CPUState *env;
2465 qemu_irq *pic, *irqs;
2466
2467 memset(clk_setup, 0, sizeof(clk_setup));
2468 /* init CPUs */
2469 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2470 &tlb_clk_setup, sysclk);
2471 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2472 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2473 /* Internal devices init */
2474 /* Memory mapped devices registers */
2475 /* PLB arbitrer */
2476 ppc4xx_plb_init(env);
2477 /* PLB to OPB bridge */
2478 ppc4xx_pob_init(env);
2479 /* OBP arbitrer */
2480 ppc4xx_opba_init(0xef600600);
2481 /* Universal interrupt controller */
2482 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2483 irqs[PPCUIC_OUTPUT_INT] =
2484 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2485 irqs[PPCUIC_OUTPUT_CINT] =
2486 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2487 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2488 *picp = pic;
2489 /* SDRAM controller */
2490 /* XXX 405EP has no ECC interrupt */
2491 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2492 ram_bases, ram_sizes, do_init);
2493 /* External bus controller */
2494 ppc405_ebc_init(env);
2495 /* DMA controller */
2496 dma_irqs[0] = pic[5];
2497 dma_irqs[1] = pic[6];
2498 dma_irqs[2] = pic[7];
2499 dma_irqs[3] = pic[8];
2500 ppc405_dma_init(env, dma_irqs);
2501 /* IIC controller */
2502 ppc405_i2c_init(0xef600500, pic[2]);
2503 /* GPIO */
2504 ppc405_gpio_init(0xef600700);
2505 /* Serial ports */
2506 if (serial_hds[0] != NULL) {
2507 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2508 serial_hds[0], 1, 1);
2509 }
2510 if (serial_hds[1] != NULL) {
2511 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2512 serial_hds[1], 1, 1);
2513 }
2514 /* OCM */
2515 ppc405_ocm_init(env);
2516 /* GPT */
2517 gpt_irqs[0] = pic[19];
2518 gpt_irqs[1] = pic[20];
2519 gpt_irqs[2] = pic[21];
2520 gpt_irqs[3] = pic[22];
2521 gpt_irqs[4] = pic[23];
2522 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2523 /* PCI */
2524 /* Uses pic[3], pic[16], pic[18] */
2525 /* MAL */
2526 mal_irqs[0] = pic[11];
2527 mal_irqs[1] = pic[12];
2528 mal_irqs[2] = pic[13];
2529 mal_irqs[3] = pic[14];
2530 ppc405_mal_init(env, mal_irqs);
2531 /* Ethernet */
2532 /* Uses pic[9], pic[15], pic[17] */
2533 /* CPU control */
2534 ppc405ep_cpc_init(env, clk_setup, sysclk);
2535
2536 return env;
2537 }
QEmu