2 * i.MX Fast Ethernet Controller emulation.
4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
26 #include "hw/net/imx_fec.h"
27 #include "hw/qdev-properties.h"
28 #include "migration/vmstate.h"
29 #include "sysemu/dma.h"
31 #include "qemu/module.h"
32 #include "net/checksum.h"
39 #define IMX_MAX_DESC 1024
41 static const char *imx_default_reg_name(IMXFECState
*s
, uint32_t index
)
44 sprintf(tmp
, "index %d", index
);
48 static const char *imx_fec_reg_name(IMXFECState
*s
, uint32_t index
)
55 case ENET_MIIGSK_CFGR
:
60 return imx_default_reg_name(s
, index
);
64 static const char *imx_enet_reg_name(IMXFECState
*s
, uint32_t index
)
122 return imx_default_reg_name(s
, index
);
126 static const char *imx_eth_reg_name(IMXFECState
*s
, uint32_t index
)
173 return imx_fec_reg_name(s
, index
);
175 return imx_enet_reg_name(s
, index
);
181 * Versions of this device with more than one TX descriptor save the
182 * 2nd and 3rd descriptors in a subsection, to maintain migration
183 * compatibility with previous versions of the device that only
184 * supported a single descriptor.
186 static bool imx_eth_is_multi_tx_ring(void *opaque
)
188 IMXFECState
*s
= IMX_FEC(opaque
);
190 return s
->tx_ring_num
> 1;
193 static const VMStateDescription vmstate_imx_eth_txdescs
= {
194 .name
= "imx.fec/txdescs",
196 .minimum_version_id
= 1,
197 .needed
= imx_eth_is_multi_tx_ring
,
198 .fields
= (VMStateField
[]) {
199 VMSTATE_UINT32(tx_descriptor
[1], IMXFECState
),
200 VMSTATE_UINT32(tx_descriptor
[2], IMXFECState
),
201 VMSTATE_END_OF_LIST()
205 static const VMStateDescription vmstate_imx_eth
= {
206 .name
= TYPE_IMX_FEC
,
208 .minimum_version_id
= 2,
209 .fields
= (VMStateField
[]) {
210 VMSTATE_UINT32_ARRAY(regs
, IMXFECState
, ENET_MAX
),
211 VMSTATE_UINT32(rx_descriptor
, IMXFECState
),
212 VMSTATE_UINT32(tx_descriptor
[0], IMXFECState
),
213 VMSTATE_UINT32(phy_status
, IMXFECState
),
214 VMSTATE_UINT32(phy_control
, IMXFECState
),
215 VMSTATE_UINT32(phy_advertise
, IMXFECState
),
216 VMSTATE_UINT32(phy_int
, IMXFECState
),
217 VMSTATE_UINT32(phy_int_mask
, IMXFECState
),
218 VMSTATE_END_OF_LIST()
220 .subsections
= (const VMStateDescription
* []) {
221 &vmstate_imx_eth_txdescs
,
226 #define PHY_INT_ENERGYON (1 << 7)
227 #define PHY_INT_AUTONEG_COMPLETE (1 << 6)
228 #define PHY_INT_FAULT (1 << 5)
229 #define PHY_INT_DOWN (1 << 4)
230 #define PHY_INT_AUTONEG_LP (1 << 3)
231 #define PHY_INT_PARFAULT (1 << 2)
232 #define PHY_INT_AUTONEG_PAGE (1 << 1)
234 static void imx_eth_update(IMXFECState
*s
);
237 * The MII phy could raise a GPIO to the processor which in turn
238 * could be handled as an interrpt by the OS.
239 * For now we don't handle any GPIO/interrupt line, so the OS will
240 * have to poll for the PHY status.
242 static void imx_phy_update_irq(IMXFECState
*s
)
247 static void imx_phy_update_link(IMXFECState
*s
)
249 /* Autonegotiation status mirrors link status. */
250 if (qemu_get_queue(s
->nic
)->link_down
) {
251 trace_imx_phy_update_link("down");
252 s
->phy_status
&= ~0x0024;
253 s
->phy_int
|= PHY_INT_DOWN
;
255 trace_imx_phy_update_link("up");
256 s
->phy_status
|= 0x0024;
257 s
->phy_int
|= PHY_INT_ENERGYON
;
258 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
260 imx_phy_update_irq(s
);
263 static void imx_eth_set_link(NetClientState
*nc
)
265 imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc
)));
268 static void imx_phy_reset(IMXFECState
*s
)
270 trace_imx_phy_reset();
272 s
->phy_status
= 0x7809;
273 s
->phy_control
= 0x3000;
274 s
->phy_advertise
= 0x01e1;
277 imx_phy_update_link(s
);
280 static uint32_t imx_phy_read(IMXFECState
*s
, int reg
)
283 uint32_t phy
= reg
/ 32;
285 if (phy
!= s
->phy_num
) {
286 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad phy num %u\n",
287 TYPE_IMX_FEC
, __func__
, phy
);
294 case 0: /* Basic Control */
295 val
= s
->phy_control
;
297 case 1: /* Basic Status */
306 case 4: /* Auto-neg advertisement */
307 val
= s
->phy_advertise
;
309 case 5: /* Auto-neg Link Partner Ability */
312 case 6: /* Auto-neg Expansion */
315 case 29: /* Interrupt source. */
318 imx_phy_update_irq(s
);
320 case 30: /* Interrupt mask */
321 val
= s
->phy_int_mask
;
327 qemu_log_mask(LOG_UNIMP
, "[%s.phy]%s: reg %d not implemented\n",
328 TYPE_IMX_FEC
, __func__
, reg
);
332 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad address at offset %d\n",
333 TYPE_IMX_FEC
, __func__
, reg
);
338 trace_imx_phy_read(val
, phy
, reg
);
343 static void imx_phy_write(IMXFECState
*s
, int reg
, uint32_t val
)
345 uint32_t phy
= reg
/ 32;
347 if (phy
!= s
->phy_num
) {
348 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad phy num %u\n",
349 TYPE_IMX_FEC
, __func__
, phy
);
355 trace_imx_phy_write(val
, phy
, reg
);
358 case 0: /* Basic Control */
362 s
->phy_control
= val
& 0x7980;
363 /* Complete autonegotiation immediately. */
365 s
->phy_status
|= 0x0020;
369 case 4: /* Auto-neg advertisement */
370 s
->phy_advertise
= (val
& 0x2d7f) | 0x80;
372 case 30: /* Interrupt mask */
373 s
->phy_int_mask
= val
& 0xff;
374 imx_phy_update_irq(s
);
380 qemu_log_mask(LOG_UNIMP
, "[%s.phy)%s: reg %d not implemented\n",
381 TYPE_IMX_FEC
, __func__
, reg
);
384 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad address at offset %d\n",
385 TYPE_IMX_FEC
, __func__
, reg
);
390 static void imx_fec_read_bd(IMXFECBufDesc
*bd
, dma_addr_t addr
)
392 dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
));
394 trace_imx_fec_read_bd(addr
, bd
->flags
, bd
->length
, bd
->data
);
397 static void imx_fec_write_bd(IMXFECBufDesc
*bd
, dma_addr_t addr
)
399 dma_memory_write(&address_space_memory
, addr
, bd
, sizeof(*bd
));
402 static void imx_enet_read_bd(IMXENETBufDesc
*bd
, dma_addr_t addr
)
404 dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
));
406 trace_imx_enet_read_bd(addr
, bd
->flags
, bd
->length
, bd
->data
,
407 bd
->option
, bd
->status
);
410 static void imx_enet_write_bd(IMXENETBufDesc
*bd
, dma_addr_t addr
)
412 dma_memory_write(&address_space_memory
, addr
, bd
, sizeof(*bd
));
415 static void imx_eth_update(IMXFECState
*s
)
418 * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
419 * interrupts swapped. This worked with older versions of Linux (4.14
420 * and older) since Linux associated both interrupt lines with Ethernet
421 * MAC interrupts. Specifically,
422 * - Linux 4.15 and later have separate interrupt handlers for the MAC and
423 * timer interrupts. Those versions of Linux fail with versions of QEMU
424 * with swapped interrupt assignments.
425 * - In linux 4.14, both interrupt lines were registered with the Ethernet
426 * MAC interrupt handler. As a result, all versions of qemu happen to
427 * work, though that is accidental.
428 * - In Linux 4.9 and older, the timer interrupt was registered directly
429 * with the Ethernet MAC interrupt handler. The MAC interrupt was
430 * redirected to a GPIO interrupt to work around erratum ERR006687.
431 * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
432 * interrupt never fired since IOMUX is currently not supported in qemu.
433 * Linux instead received MAC interrupts on the timer interrupt.
434 * As a result, qemu versions with the swapped interrupt assignment work,
435 * albeit accidentally, but qemu versions with the correct interrupt
438 * To ensure that all versions of Linux work, generate ENET_INT_MAC
439 * interrrupts on both interrupt lines. This should be changed if and when
440 * qemu supports IOMUX.
442 if (s
->regs
[ENET_EIR
] & s
->regs
[ENET_EIMR
] &
443 (ENET_INT_MAC
| ENET_INT_TS_TIMER
)) {
444 qemu_set_irq(s
->irq
[1], 1);
446 qemu_set_irq(s
->irq
[1], 0);
449 if (s
->regs
[ENET_EIR
] & s
->regs
[ENET_EIMR
] & ENET_INT_MAC
) {
450 qemu_set_irq(s
->irq
[0], 1);
452 qemu_set_irq(s
->irq
[0], 0);
456 static void imx_fec_do_tx(IMXFECState
*s
)
458 int frame_size
= 0, descnt
= 0;
459 uint8_t *ptr
= s
->frame
;
460 uint32_t addr
= s
->tx_descriptor
[0];
462 while (descnt
++ < IMX_MAX_DESC
) {
466 imx_fec_read_bd(&bd
, addr
);
467 if ((bd
.flags
& ENET_BD_R
) == 0) {
469 /* Run out of descriptors to transmit. */
470 trace_imx_eth_tx_bd_busy();
475 if (frame_size
+ len
> ENET_MAX_FRAME_SIZE
) {
476 len
= ENET_MAX_FRAME_SIZE
- frame_size
;
477 s
->regs
[ENET_EIR
] |= ENET_INT_BABT
;
479 dma_memory_read(&address_space_memory
, bd
.data
, ptr
, len
);
482 if (bd
.flags
& ENET_BD_L
) {
483 /* Last buffer in frame. */
484 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
487 s
->regs
[ENET_EIR
] |= ENET_INT_TXF
;
489 s
->regs
[ENET_EIR
] |= ENET_INT_TXB
;
490 bd
.flags
&= ~ENET_BD_R
;
491 /* Write back the modified descriptor. */
492 imx_fec_write_bd(&bd
, addr
);
493 /* Advance to the next descriptor. */
494 if ((bd
.flags
& ENET_BD_W
) != 0) {
495 addr
= s
->regs
[ENET_TDSR
];
501 s
->tx_descriptor
[0] = addr
;
506 static void imx_enet_do_tx(IMXFECState
*s
, uint32_t index
)
508 int frame_size
= 0, descnt
= 0;
510 uint8_t *ptr
= s
->frame
;
511 uint32_t addr
, int_txb
, int_txf
, tdsr
;
517 int_txb
= ENET_INT_TXB
;
518 int_txf
= ENET_INT_TXF
;
523 int_txb
= ENET_INT_TXB1
;
524 int_txf
= ENET_INT_TXF1
;
529 int_txb
= ENET_INT_TXB2
;
530 int_txf
= ENET_INT_TXF2
;
534 qemu_log_mask(LOG_GUEST_ERROR
,
535 "%s: bogus value for index %x\n",
541 addr
= s
->tx_descriptor
[ring
];
543 while (descnt
++ < IMX_MAX_DESC
) {
547 imx_enet_read_bd(&bd
, addr
);
548 if ((bd
.flags
& ENET_BD_R
) == 0) {
549 /* Run out of descriptors to transmit. */
551 trace_imx_eth_tx_bd_busy();
556 if (frame_size
+ len
> ENET_MAX_FRAME_SIZE
) {
557 len
= ENET_MAX_FRAME_SIZE
- frame_size
;
558 s
->regs
[ENET_EIR
] |= ENET_INT_BABT
;
560 dma_memory_read(&address_space_memory
, bd
.data
, ptr
, len
);
563 if (bd
.flags
& ENET_BD_L
) {
566 if (bd
.option
& ENET_BD_PINS
) {
567 csum
|= (CSUM_TCP
| CSUM_UDP
);
569 if (bd
.option
& ENET_BD_IINS
) {
573 net_checksum_calculate(s
->frame
, frame_size
, csum
);
576 /* Last buffer in frame. */
578 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
582 if (bd
.option
& ENET_BD_TX_INT
) {
583 s
->regs
[ENET_EIR
] |= int_txf
;
585 /* Indicate that we've updated the last buffer descriptor. */
586 bd
.last_buffer
= ENET_BD_BDU
;
588 if (bd
.option
& ENET_BD_TX_INT
) {
589 s
->regs
[ENET_EIR
] |= int_txb
;
591 bd
.flags
&= ~ENET_BD_R
;
592 /* Write back the modified descriptor. */
593 imx_enet_write_bd(&bd
, addr
);
594 /* Advance to the next descriptor. */
595 if ((bd
.flags
& ENET_BD_W
) != 0) {
596 addr
= s
->regs
[tdsr
];
602 s
->tx_descriptor
[ring
] = addr
;
607 static void imx_eth_do_tx(IMXFECState
*s
, uint32_t index
)
609 if (!s
->is_fec
&& (s
->regs
[ENET_ECR
] & ENET_ECR_EN1588
)) {
610 imx_enet_do_tx(s
, index
);
616 static void imx_eth_enable_rx(IMXFECState
*s
, bool flush
)
620 imx_fec_read_bd(&bd
, s
->rx_descriptor
);
622 s
->regs
[ENET_RDAR
] = (bd
.flags
& ENET_BD_E
) ? ENET_RDAR_RDAR
: 0;
624 if (!s
->regs
[ENET_RDAR
]) {
625 trace_imx_eth_rx_bd_full();
627 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
631 static void imx_eth_reset(DeviceState
*d
)
633 IMXFECState
*s
= IMX_FEC(d
);
635 /* Reset the Device */
636 memset(s
->regs
, 0, sizeof(s
->regs
));
637 s
->regs
[ENET_ECR
] = 0xf0000000;
638 s
->regs
[ENET_MIBC
] = 0xc0000000;
639 s
->regs
[ENET_RCR
] = 0x05ee0001;
640 s
->regs
[ENET_OPD
] = 0x00010000;
642 s
->regs
[ENET_PALR
] = (s
->conf
.macaddr
.a
[0] << 24)
643 | (s
->conf
.macaddr
.a
[1] << 16)
644 | (s
->conf
.macaddr
.a
[2] << 8)
645 | s
->conf
.macaddr
.a
[3];
646 s
->regs
[ENET_PAUR
] = (s
->conf
.macaddr
.a
[4] << 24)
647 | (s
->conf
.macaddr
.a
[5] << 16)
651 s
->regs
[ENET_FRBR
] = 0x00000600;
652 s
->regs
[ENET_FRSR
] = 0x00000500;
653 s
->regs
[ENET_MIIGSK_ENR
] = 0x00000006;
655 s
->regs
[ENET_RAEM
] = 0x00000004;
656 s
->regs
[ENET_RAFL
] = 0x00000004;
657 s
->regs
[ENET_TAEM
] = 0x00000004;
658 s
->regs
[ENET_TAFL
] = 0x00000008;
659 s
->regs
[ENET_TIPG
] = 0x0000000c;
660 s
->regs
[ENET_FTRL
] = 0x000007ff;
661 s
->regs
[ENET_ATPER
] = 0x3b9aca00;
664 s
->rx_descriptor
= 0;
665 memset(s
->tx_descriptor
, 0, sizeof(s
->tx_descriptor
));
667 /* We also reset the PHY */
671 static uint32_t imx_default_read(IMXFECState
*s
, uint32_t index
)
673 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
674 PRIx32
"\n", TYPE_IMX_FEC
, __func__
, index
* 4);
678 static uint32_t imx_fec_read(IMXFECState
*s
, uint32_t index
)
683 case ENET_MIIGSK_CFGR
:
684 case ENET_MIIGSK_ENR
:
685 return s
->regs
[index
];
687 return imx_default_read(s
, index
);
691 static uint32_t imx_enet_read(IMXFECState
*s
, uint32_t index
)
721 return s
->regs
[index
];
723 return imx_default_read(s
, index
);
727 static uint64_t imx_eth_read(void *opaque
, hwaddr offset
, unsigned size
)
730 IMXFECState
*s
= IMX_FEC(opaque
);
731 uint32_t index
= offset
>> 2;
755 value
= s
->regs
[index
];
759 value
= imx_fec_read(s
, index
);
761 value
= imx_enet_read(s
, index
);
766 trace_imx_eth_read(index
, imx_eth_reg_name(s
, index
), value
);
771 static void imx_default_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
773 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad address at offset 0x%"
774 PRIx32
"\n", TYPE_IMX_FEC
, __func__
, index
* 4);
778 static void imx_fec_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
782 /* FRBR is read only */
783 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Register FRBR is read only\n",
784 TYPE_IMX_FEC
, __func__
);
787 s
->regs
[index
] = (value
& 0x000003fc) | 0x00000400;
789 case ENET_MIIGSK_CFGR
:
790 s
->regs
[index
] = value
& 0x00000053;
792 case ENET_MIIGSK_ENR
:
793 s
->regs
[index
] = (value
& 0x00000002) ? 0x00000006 : 0;
796 imx_default_write(s
, index
, value
);
801 static void imx_enet_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
811 s
->regs
[index
] = value
& 0x000001ff;
814 s
->regs
[index
] = value
& 0x0000001f;
817 s
->regs
[index
] = value
& 0x00003fff;
820 s
->regs
[index
] = value
& 0x00000019;
823 s
->regs
[index
] = value
& 0x000000C7;
826 s
->regs
[index
] = value
& 0x00002a9d;
831 s
->regs
[index
] = value
;
834 /* ATSTMP is read only */
835 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Register ATSTMP is read only\n",
836 TYPE_IMX_FEC
, __func__
);
839 s
->regs
[index
] = value
& 0x7fffffff;
842 s
->regs
[index
] = value
& 0x00007f7f;
845 /* implement clear timer flag */
846 s
->regs
[index
] &= ~(value
& 0x0000000f); /* all bits W1C */
852 s
->regs
[index
] &= ~(value
& 0x00000080); /* W1C bits */
853 s
->regs
[index
] &= ~0x0000007d; /* writable fields */
854 s
->regs
[index
] |= (value
& 0x0000007d);
860 s
->regs
[index
] = value
;
863 imx_default_write(s
, index
, value
);
868 static void imx_eth_write(void *opaque
, hwaddr offset
, uint64_t value
,
871 IMXFECState
*s
= IMX_FEC(opaque
);
872 const bool single_tx_ring
= !imx_eth_is_multi_tx_ring(s
);
873 uint32_t index
= offset
>> 2;
875 trace_imx_eth_write(index
, imx_eth_reg_name(s
, index
), value
);
879 s
->regs
[index
] &= ~value
;
882 s
->regs
[index
] = value
;
885 if (s
->regs
[ENET_ECR
] & ENET_ECR_ETHEREN
) {
886 if (!s
->regs
[index
]) {
887 imx_eth_enable_rx(s
, true);
895 if (unlikely(single_tx_ring
)) {
896 qemu_log_mask(LOG_GUEST_ERROR
,
897 "[%s]%s: trying to access TDAR2 or TDAR1\n",
898 TYPE_IMX_FEC
, __func__
);
903 if (s
->regs
[ENET_ECR
] & ENET_ECR_ETHEREN
) {
904 s
->regs
[index
] = ENET_TDAR_TDAR
;
905 imx_eth_do_tx(s
, index
);
910 if (value
& ENET_ECR_RESET
) {
911 return imx_eth_reset(DEVICE(s
));
913 s
->regs
[index
] = value
;
914 if ((s
->regs
[index
] & ENET_ECR_ETHEREN
) == 0) {
915 s
->regs
[ENET_RDAR
] = 0;
916 s
->rx_descriptor
= s
->regs
[ENET_RDSR
];
917 s
->regs
[ENET_TDAR
] = 0;
918 s
->regs
[ENET_TDAR1
] = 0;
919 s
->regs
[ENET_TDAR2
] = 0;
920 s
->tx_descriptor
[0] = s
->regs
[ENET_TDSR
];
921 s
->tx_descriptor
[1] = s
->regs
[ENET_TDSR1
];
922 s
->tx_descriptor
[2] = s
->regs
[ENET_TDSR2
];
926 s
->regs
[index
] = value
;
927 if (extract32(value
, 29, 1)) {
928 /* This is a read operation */
929 s
->regs
[ENET_MMFR
] = deposit32(s
->regs
[ENET_MMFR
], 0, 16,
934 /* This is a write operation */
935 imx_phy_write(s
, extract32(value
, 18, 10), extract32(value
, 0, 16));
937 /* raise the interrupt as the PHY operation is done */
938 s
->regs
[ENET_EIR
] |= ENET_INT_MII
;
941 s
->regs
[index
] = value
& 0xfe;
944 /* TODO: Implement MIB. */
945 s
->regs
[index
] = (value
& 0x80000000) ? 0xc0000000 : 0;
948 s
->regs
[index
] = value
& 0x07ff003f;
949 /* TODO: Implement LOOP mode. */
952 /* We transmit immediately, so raise GRA immediately. */
953 s
->regs
[index
] = value
;
955 s
->regs
[ENET_EIR
] |= ENET_INT_GRA
;
959 s
->regs
[index
] = value
;
960 s
->conf
.macaddr
.a
[0] = value
>> 24;
961 s
->conf
.macaddr
.a
[1] = value
>> 16;
962 s
->conf
.macaddr
.a
[2] = value
>> 8;
963 s
->conf
.macaddr
.a
[3] = value
;
966 s
->regs
[index
] = (value
| 0x0000ffff) & 0xffff8808;
967 s
->conf
.macaddr
.a
[4] = value
>> 24;
968 s
->conf
.macaddr
.a
[5] = value
>> 16;
971 s
->regs
[index
] = (value
& 0x0000ffff) | 0x00010000;
977 /* TODO: implement MAC hash filtering. */
981 s
->regs
[index
] = value
& 0x3;
983 s
->regs
[index
] = value
& 0x13f;
988 s
->regs
[index
] = value
& ~3;
990 s
->regs
[index
] = value
& ~7;
992 s
->rx_descriptor
= s
->regs
[index
];
996 s
->regs
[index
] = value
& ~3;
998 s
->regs
[index
] = value
& ~7;
1000 s
->tx_descriptor
[0] = s
->regs
[index
];
1003 if (unlikely(single_tx_ring
)) {
1004 qemu_log_mask(LOG_GUEST_ERROR
,
1005 "[%s]%s: trying to access TDSR1\n",
1006 TYPE_IMX_FEC
, __func__
);
1010 s
->regs
[index
] = value
& ~7;
1011 s
->tx_descriptor
[1] = s
->regs
[index
];
1014 if (unlikely(single_tx_ring
)) {
1015 qemu_log_mask(LOG_GUEST_ERROR
,
1016 "[%s]%s: trying to access TDSR2\n",
1017 TYPE_IMX_FEC
, __func__
);
1021 s
->regs
[index
] = value
& ~7;
1022 s
->tx_descriptor
[2] = s
->regs
[index
];
1025 s
->regs
[index
] = value
& 0x00003ff0;
1029 imx_fec_write(s
, index
, value
);
1031 imx_enet_write(s
, index
, value
);
1039 static bool imx_eth_can_receive(NetClientState
*nc
)
1041 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1043 return !!s
->regs
[ENET_RDAR
];
1046 static ssize_t
imx_fec_receive(NetClientState
*nc
, const uint8_t *buf
,
1049 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1056 unsigned int buf_len
;
1059 trace_imx_fec_receive(size
);
1061 if (!s
->regs
[ENET_RDAR
]) {
1062 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Unexpected packet\n",
1063 TYPE_IMX_FEC
, __func__
);
1067 /* 4 bytes for the CRC. */
1069 crc
= cpu_to_be32(crc32(~0, buf
, size
));
1070 crc_ptr
= (uint8_t *) &crc
;
1072 /* Huge frames are truncated. */
1073 if (size
> ENET_MAX_FRAME_SIZE
) {
1074 size
= ENET_MAX_FRAME_SIZE
;
1075 flags
|= ENET_BD_TR
| ENET_BD_LG
;
1078 /* Frames larger than the user limit just set error flags. */
1079 if (size
> (s
->regs
[ENET_RCR
] >> 16)) {
1080 flags
|= ENET_BD_LG
;
1083 addr
= s
->rx_descriptor
;
1085 imx_fec_read_bd(&bd
, addr
);
1086 if ((bd
.flags
& ENET_BD_E
) == 0) {
1087 /* No descriptors available. Bail out. */
1089 * FIXME: This is wrong. We should probably either
1090 * save the remainder for when more RX buffers are
1091 * available, or flag an error.
1093 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Lost end of frame\n",
1094 TYPE_IMX_FEC
, __func__
);
1097 buf_len
= (size
<= s
->regs
[ENET_MRBR
]) ? size
: s
->regs
[ENET_MRBR
];
1098 bd
.length
= buf_len
;
1101 trace_imx_fec_receive_len(addr
, bd
.length
);
1103 /* The last 4 bytes are the CRC. */
1105 buf_len
+= size
- 4;
1108 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
1111 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
1113 crc_ptr
+= 4 - size
;
1115 bd
.flags
&= ~ENET_BD_E
;
1117 /* Last buffer in frame. */
1118 bd
.flags
|= flags
| ENET_BD_L
;
1120 trace_imx_fec_receive_last(bd
.flags
);
1122 s
->regs
[ENET_EIR
] |= ENET_INT_RXF
;
1124 s
->regs
[ENET_EIR
] |= ENET_INT_RXB
;
1126 imx_fec_write_bd(&bd
, addr
);
1127 /* Advance to the next descriptor. */
1128 if ((bd
.flags
& ENET_BD_W
) != 0) {
1129 addr
= s
->regs
[ENET_RDSR
];
1134 s
->rx_descriptor
= addr
;
1135 imx_eth_enable_rx(s
, false);
1140 static ssize_t
imx_enet_receive(NetClientState
*nc
, const uint8_t *buf
,
1143 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1150 unsigned int buf_len
;
1152 bool shift16
= s
->regs
[ENET_RACC
] & ENET_RACC_SHIFT16
;
1154 trace_imx_enet_receive(size
);
1156 if (!s
->regs
[ENET_RDAR
]) {
1157 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Unexpected packet\n",
1158 TYPE_IMX_FEC
, __func__
);
1162 /* 4 bytes for the CRC. */
1164 crc
= cpu_to_be32(crc32(~0, buf
, size
));
1165 crc_ptr
= (uint8_t *) &crc
;
1171 /* Huge frames are truncated. */
1172 if (size
> s
->regs
[ENET_FTRL
]) {
1173 size
= s
->regs
[ENET_FTRL
];
1174 flags
|= ENET_BD_TR
| ENET_BD_LG
;
1177 /* Frames larger than the user limit just set error flags. */
1178 if (size
> (s
->regs
[ENET_RCR
] >> 16)) {
1179 flags
|= ENET_BD_LG
;
1182 addr
= s
->rx_descriptor
;
1184 imx_enet_read_bd(&bd
, addr
);
1185 if ((bd
.flags
& ENET_BD_E
) == 0) {
1186 /* No descriptors available. Bail out. */
1188 * FIXME: This is wrong. We should probably either
1189 * save the remainder for when more RX buffers are
1190 * available, or flag an error.
1192 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Lost end of frame\n",
1193 TYPE_IMX_FEC
, __func__
);
1196 buf_len
= MIN(size
, s
->regs
[ENET_MRBR
]);
1197 bd
.length
= buf_len
;
1200 trace_imx_enet_receive_len(addr
, bd
.length
);
1202 /* The last 4 bytes are the CRC. */
1204 buf_len
+= size
- 4;
1210 * If SHIFT16 bit of ENETx_RACC register is set we need to
1211 * align the payload to 4-byte boundary.
1213 const uint8_t zeros
[2] = { 0 };
1215 dma_memory_write(&address_space_memory
, buf_addr
,
1216 zeros
, sizeof(zeros
));
1218 buf_addr
+= sizeof(zeros
);
1219 buf_len
-= sizeof(zeros
);
1221 /* We only do this once per Ethernet frame */
1225 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
1228 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
1230 crc_ptr
+= 4 - size
;
1232 bd
.flags
&= ~ENET_BD_E
;
1234 /* Last buffer in frame. */
1235 bd
.flags
|= flags
| ENET_BD_L
;
1237 trace_imx_enet_receive_last(bd
.flags
);
1239 /* Indicate that we've updated the last buffer descriptor. */
1240 bd
.last_buffer
= ENET_BD_BDU
;
1241 if (bd
.option
& ENET_BD_RX_INT
) {
1242 s
->regs
[ENET_EIR
] |= ENET_INT_RXF
;
1245 if (bd
.option
& ENET_BD_RX_INT
) {
1246 s
->regs
[ENET_EIR
] |= ENET_INT_RXB
;
1249 imx_enet_write_bd(&bd
, addr
);
1250 /* Advance to the next descriptor. */
1251 if ((bd
.flags
& ENET_BD_W
) != 0) {
1252 addr
= s
->regs
[ENET_RDSR
];
1257 s
->rx_descriptor
= addr
;
1258 imx_eth_enable_rx(s
, false);
1263 static ssize_t
imx_eth_receive(NetClientState
*nc
, const uint8_t *buf
,
1266 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1268 if (!s
->is_fec
&& (s
->regs
[ENET_ECR
] & ENET_ECR_EN1588
)) {
1269 return imx_enet_receive(nc
, buf
, len
);
1271 return imx_fec_receive(nc
, buf
, len
);
1275 static const MemoryRegionOps imx_eth_ops
= {
1276 .read
= imx_eth_read
,
1277 .write
= imx_eth_write
,
1278 .valid
.min_access_size
= 4,
1279 .valid
.max_access_size
= 4,
1280 .endianness
= DEVICE_NATIVE_ENDIAN
,
1283 static void imx_eth_cleanup(NetClientState
*nc
)
1285 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1290 static NetClientInfo imx_eth_net_info
= {
1291 .type
= NET_CLIENT_DRIVER_NIC
,
1292 .size
= sizeof(NICState
),
1293 .can_receive
= imx_eth_can_receive
,
1294 .receive
= imx_eth_receive
,
1295 .cleanup
= imx_eth_cleanup
,
1296 .link_status_changed
= imx_eth_set_link
,
1300 static void imx_eth_realize(DeviceState
*dev
, Error
**errp
)
1302 IMXFECState
*s
= IMX_FEC(dev
);
1303 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1305 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx_eth_ops
, s
,
1306 TYPE_IMX_FEC
, FSL_IMX25_FEC_SIZE
);
1307 sysbus_init_mmio(sbd
, &s
->iomem
);
1308 sysbus_init_irq(sbd
, &s
->irq
[0]);
1309 sysbus_init_irq(sbd
, &s
->irq
[1]);
1311 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1313 s
->nic
= qemu_new_nic(&imx_eth_net_info
, &s
->conf
,
1314 object_get_typename(OBJECT(dev
)),
1317 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1320 static Property imx_eth_properties
[] = {
1321 DEFINE_NIC_PROPERTIES(IMXFECState
, conf
),
1322 DEFINE_PROP_UINT32("tx-ring-num", IMXFECState
, tx_ring_num
, 1),
1323 DEFINE_PROP_UINT32("phy-num", IMXFECState
, phy_num
, 0),
1324 DEFINE_PROP_END_OF_LIST(),
1327 static void imx_eth_class_init(ObjectClass
*klass
, void *data
)
1329 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1331 dc
->vmsd
= &vmstate_imx_eth
;
1332 dc
->reset
= imx_eth_reset
;
1333 device_class_set_props(dc
, imx_eth_properties
);
1334 dc
->realize
= imx_eth_realize
;
1335 dc
->desc
= "i.MX FEC/ENET Ethernet Controller";
1338 static void imx_fec_init(Object
*obj
)
1340 IMXFECState
*s
= IMX_FEC(obj
);
1345 static void imx_enet_init(Object
*obj
)
1347 IMXFECState
*s
= IMX_FEC(obj
);
1352 static const TypeInfo imx_fec_info
= {
1353 .name
= TYPE_IMX_FEC
,
1354 .parent
= TYPE_SYS_BUS_DEVICE
,
1355 .instance_size
= sizeof(IMXFECState
),
1356 .instance_init
= imx_fec_init
,
1357 .class_init
= imx_eth_class_init
,
1360 static const TypeInfo imx_enet_info
= {
1361 .name
= TYPE_IMX_ENET
,
1362 .parent
= TYPE_IMX_FEC
,
1363 .instance_init
= imx_enet_init
,
1366 static void imx_eth_register_types(void)
1368 type_register_static(&imx_fec_info
);
1369 type_register_static(&imx_enet_info
);
1372 type_init(imx_eth_register_types
)