2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 int gen_new_label(void);
28 static inline void tcg_gen_op1_i32(TCGOpcode opc
, TCGv_i32 arg1
)
31 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
34 static inline void tcg_gen_op1_i64(TCGOpcode opc
, TCGv_i64 arg1
)
37 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
40 static inline void tcg_gen_op1i(TCGOpcode opc
, TCGArg arg1
)
43 *gen_opparam_ptr
++ = arg1
;
46 static inline void tcg_gen_op2_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
)
49 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
50 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
53 static inline void tcg_gen_op2_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
)
56 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
57 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
60 static inline void tcg_gen_op2i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGArg arg2
)
63 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
64 *gen_opparam_ptr
++ = arg2
;
67 static inline void tcg_gen_op2i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGArg arg2
)
70 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
71 *gen_opparam_ptr
++ = arg2
;
74 static inline void tcg_gen_op2ii(TCGOpcode opc
, TCGArg arg1
, TCGArg arg2
)
77 *gen_opparam_ptr
++ = arg1
;
78 *gen_opparam_ptr
++ = arg2
;
81 static inline void tcg_gen_op3_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
85 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
86 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
87 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
90 static inline void tcg_gen_op3_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
94 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
95 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
96 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
99 static inline void tcg_gen_op3i_i32(TCGOpcode opc
, TCGv_i32 arg1
,
100 TCGv_i32 arg2
, TCGArg arg3
)
102 *gen_opc_ptr
++ = opc
;
103 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
104 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
105 *gen_opparam_ptr
++ = arg3
;
108 static inline void tcg_gen_op3i_i64(TCGOpcode opc
, TCGv_i64 arg1
,
109 TCGv_i64 arg2
, TCGArg arg3
)
111 *gen_opc_ptr
++ = opc
;
112 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
113 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
114 *gen_opparam_ptr
++ = arg3
;
117 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc
, TCGv_i32 val
,
118 TCGv_ptr base
, TCGArg offset
)
120 *gen_opc_ptr
++ = opc
;
121 *gen_opparam_ptr
++ = GET_TCGV_I32(val
);
122 *gen_opparam_ptr
++ = GET_TCGV_PTR(base
);
123 *gen_opparam_ptr
++ = offset
;
126 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc
, TCGv_i64 val
,
127 TCGv_ptr base
, TCGArg offset
)
129 *gen_opc_ptr
++ = opc
;
130 *gen_opparam_ptr
++ = GET_TCGV_I64(val
);
131 *gen_opparam_ptr
++ = GET_TCGV_PTR(base
);
132 *gen_opparam_ptr
++ = offset
;
135 static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc
, TCGv_i64 val
,
136 TCGv_i32 addr
, TCGArg mem_index
)
138 *gen_opc_ptr
++ = opc
;
139 *gen_opparam_ptr
++ = GET_TCGV_I64(val
);
140 *gen_opparam_ptr
++ = GET_TCGV_I32(addr
);
141 *gen_opparam_ptr
++ = mem_index
;
144 static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc
, TCGv_i64 val
,
145 TCGv_i64 addr
, TCGArg mem_index
)
147 *gen_opc_ptr
++ = opc
;
148 *gen_opparam_ptr
++ = GET_TCGV_I64(val
);
149 *gen_opparam_ptr
++ = GET_TCGV_I64(addr
);
150 *gen_opparam_ptr
++ = mem_index
;
153 static inline void tcg_gen_op4_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
154 TCGv_i32 arg3
, TCGv_i32 arg4
)
156 *gen_opc_ptr
++ = opc
;
157 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
158 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
159 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
160 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
163 static inline void tcg_gen_op4_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
164 TCGv_i64 arg3
, TCGv_i64 arg4
)
166 *gen_opc_ptr
++ = opc
;
167 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
168 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
169 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
170 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
173 static inline void tcg_gen_op4i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
174 TCGv_i32 arg3
, TCGArg arg4
)
176 *gen_opc_ptr
++ = opc
;
177 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
178 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
179 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
180 *gen_opparam_ptr
++ = arg4
;
183 static inline void tcg_gen_op4i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
184 TCGv_i64 arg3
, TCGArg arg4
)
186 *gen_opc_ptr
++ = opc
;
187 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
188 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
189 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
190 *gen_opparam_ptr
++ = arg4
;
193 static inline void tcg_gen_op4ii_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
194 TCGArg arg3
, TCGArg arg4
)
196 *gen_opc_ptr
++ = opc
;
197 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
198 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
199 *gen_opparam_ptr
++ = arg3
;
200 *gen_opparam_ptr
++ = arg4
;
203 static inline void tcg_gen_op4ii_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
204 TCGArg arg3
, TCGArg arg4
)
206 *gen_opc_ptr
++ = opc
;
207 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
208 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
209 *gen_opparam_ptr
++ = arg3
;
210 *gen_opparam_ptr
++ = arg4
;
213 static inline void tcg_gen_op5_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
214 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGv_i32 arg5
)
216 *gen_opc_ptr
++ = opc
;
217 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
218 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
219 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
220 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
221 *gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
224 static inline void tcg_gen_op5_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
225 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGv_i64 arg5
)
227 *gen_opc_ptr
++ = opc
;
228 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
229 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
230 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
231 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
232 *gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
235 static inline void tcg_gen_op5i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
236 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGArg arg5
)
238 *gen_opc_ptr
++ = opc
;
239 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
240 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
241 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
242 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
243 *gen_opparam_ptr
++ = arg5
;
246 static inline void tcg_gen_op5i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
247 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGArg arg5
)
249 *gen_opc_ptr
++ = opc
;
250 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
251 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
252 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
253 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
254 *gen_opparam_ptr
++ = arg5
;
257 static inline void tcg_gen_op5ii_i32(TCGOpcode opc
, TCGv_i32 arg1
,
258 TCGv_i32 arg2
, TCGv_i32 arg3
,
259 TCGArg arg4
, TCGArg arg5
)
261 *gen_opc_ptr
++ = opc
;
262 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
263 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
264 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
265 *gen_opparam_ptr
++ = arg4
;
266 *gen_opparam_ptr
++ = arg5
;
269 static inline void tcg_gen_op5ii_i64(TCGOpcode opc
, TCGv_i64 arg1
,
270 TCGv_i64 arg2
, TCGv_i64 arg3
,
271 TCGArg arg4
, TCGArg arg5
)
273 *gen_opc_ptr
++ = opc
;
274 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
275 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
276 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
277 *gen_opparam_ptr
++ = arg4
;
278 *gen_opparam_ptr
++ = arg5
;
281 static inline void tcg_gen_op6_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
282 TCGv_i32 arg3
, TCGv_i32 arg4
, TCGv_i32 arg5
,
285 *gen_opc_ptr
++ = opc
;
286 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
287 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
288 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
289 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
290 *gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
291 *gen_opparam_ptr
++ = GET_TCGV_I32(arg6
);
294 static inline void tcg_gen_op6_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
295 TCGv_i64 arg3
, TCGv_i64 arg4
, TCGv_i64 arg5
,
298 *gen_opc_ptr
++ = opc
;
299 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
300 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
301 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
302 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
303 *gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
304 *gen_opparam_ptr
++ = GET_TCGV_I64(arg6
);
307 static inline void tcg_gen_op6i_i32(TCGOpcode opc
, TCGv_i32 arg1
, TCGv_i32 arg2
,
308 TCGv_i32 arg3
, TCGv_i32 arg4
,
309 TCGv_i32 arg5
, TCGArg arg6
)
311 *gen_opc_ptr
++ = opc
;
312 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
313 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
314 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
315 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
316 *gen_opparam_ptr
++ = GET_TCGV_I32(arg5
);
317 *gen_opparam_ptr
++ = arg6
;
320 static inline void tcg_gen_op6i_i64(TCGOpcode opc
, TCGv_i64 arg1
, TCGv_i64 arg2
,
321 TCGv_i64 arg3
, TCGv_i64 arg4
,
322 TCGv_i64 arg5
, TCGArg arg6
)
324 *gen_opc_ptr
++ = opc
;
325 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
326 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
327 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
328 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
329 *gen_opparam_ptr
++ = GET_TCGV_I64(arg5
);
330 *gen_opparam_ptr
++ = arg6
;
333 static inline void tcg_gen_op6ii_i32(TCGOpcode opc
, TCGv_i32 arg1
,
334 TCGv_i32 arg2
, TCGv_i32 arg3
,
335 TCGv_i32 arg4
, TCGArg arg5
, TCGArg arg6
)
337 *gen_opc_ptr
++ = opc
;
338 *gen_opparam_ptr
++ = GET_TCGV_I32(arg1
);
339 *gen_opparam_ptr
++ = GET_TCGV_I32(arg2
);
340 *gen_opparam_ptr
++ = GET_TCGV_I32(arg3
);
341 *gen_opparam_ptr
++ = GET_TCGV_I32(arg4
);
342 *gen_opparam_ptr
++ = arg5
;
343 *gen_opparam_ptr
++ = arg6
;
346 static inline void tcg_gen_op6ii_i64(TCGOpcode opc
, TCGv_i64 arg1
,
347 TCGv_i64 arg2
, TCGv_i64 arg3
,
348 TCGv_i64 arg4
, TCGArg arg5
, TCGArg arg6
)
350 *gen_opc_ptr
++ = opc
;
351 *gen_opparam_ptr
++ = GET_TCGV_I64(arg1
);
352 *gen_opparam_ptr
++ = GET_TCGV_I64(arg2
);
353 *gen_opparam_ptr
++ = GET_TCGV_I64(arg3
);
354 *gen_opparam_ptr
++ = GET_TCGV_I64(arg4
);
355 *gen_opparam_ptr
++ = arg5
;
356 *gen_opparam_ptr
++ = arg6
;
359 static inline void gen_set_label(int n
)
361 tcg_gen_op1i(INDEX_op_set_label
, n
);
364 static inline void tcg_gen_br(int label
)
366 tcg_gen_op1i(INDEX_op_br
, label
);
369 static inline void tcg_gen_mov_i32(TCGv_i32 ret
, TCGv_i32 arg
)
371 if (!TCGV_EQUAL_I32(ret
, arg
))
372 tcg_gen_op2_i32(INDEX_op_mov_i32
, ret
, arg
);
375 static inline void tcg_gen_movi_i32(TCGv_i32 ret
, int32_t arg
)
377 tcg_gen_op2i_i32(INDEX_op_movi_i32
, ret
, arg
);
380 /* A version of dh_sizemask from def-helper.h that doesn't rely on
381 preprocessor magic. */
382 static inline int tcg_gen_sizemask(int n
, int is_64bit
, int is_signed
)
384 return (is_64bit
<< n
*2) | (is_signed
<< (n
*2 + 1));
388 static inline void tcg_gen_helperN(void *func
, int flags
, int sizemask
,
389 TCGArg ret
, int nargs
, TCGArg
*args
)
392 fn
= tcg_const_ptr(func
);
393 tcg_gen_callN(&tcg_ctx
, fn
, flags
, sizemask
, ret
,
395 tcg_temp_free_ptr(fn
);
398 /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
399 reserved for helpers in tcg-runtime.c. These helpers are all const
400 and pure, hence the call to tcg_gen_callN() with TCG_CALL_CONST |
401 TCG_CALL_PURE. This may need to be adjusted if these functions
402 start to be used with other helpers. */
403 static inline void tcg_gen_helper32(void *func
, int sizemask
, TCGv_i32 ret
,
404 TCGv_i32 a
, TCGv_i32 b
)
408 fn
= tcg_const_ptr(func
);
409 args
[0] = GET_TCGV_I32(a
);
410 args
[1] = GET_TCGV_I32(b
);
411 tcg_gen_callN(&tcg_ctx
, fn
, TCG_CALL_CONST
| TCG_CALL_PURE
, sizemask
,
412 GET_TCGV_I32(ret
), 2, args
);
413 tcg_temp_free_ptr(fn
);
416 static inline void tcg_gen_helper64(void *func
, int sizemask
, TCGv_i64 ret
,
417 TCGv_i64 a
, TCGv_i64 b
)
421 fn
= tcg_const_ptr(func
);
422 args
[0] = GET_TCGV_I64(a
);
423 args
[1] = GET_TCGV_I64(b
);
424 tcg_gen_callN(&tcg_ctx
, fn
, TCG_CALL_CONST
| TCG_CALL_PURE
, sizemask
,
425 GET_TCGV_I64(ret
), 2, args
);
426 tcg_temp_free_ptr(fn
);
431 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
433 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32
, ret
, arg2
, offset
);
436 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
438 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32
, ret
, arg2
, offset
);
441 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
443 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32
, ret
, arg2
, offset
);
446 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
448 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32
, ret
, arg2
, offset
);
451 static inline void tcg_gen_ld_i32(TCGv_i32 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
453 tcg_gen_ldst_op_i32(INDEX_op_ld_i32
, ret
, arg2
, offset
);
456 static inline void tcg_gen_st8_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
458 tcg_gen_ldst_op_i32(INDEX_op_st8_i32
, arg1
, arg2
, offset
);
461 static inline void tcg_gen_st16_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
463 tcg_gen_ldst_op_i32(INDEX_op_st16_i32
, arg1
, arg2
, offset
);
466 static inline void tcg_gen_st_i32(TCGv_i32 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
468 tcg_gen_ldst_op_i32(INDEX_op_st_i32
, arg1
, arg2
, offset
);
471 static inline void tcg_gen_add_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
473 tcg_gen_op3_i32(INDEX_op_add_i32
, ret
, arg1
, arg2
);
476 static inline void tcg_gen_addi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
478 /* some cases can be optimized here */
480 tcg_gen_mov_i32(ret
, arg1
);
482 TCGv_i32 t0
= tcg_const_i32(arg2
);
483 tcg_gen_add_i32(ret
, arg1
, t0
);
484 tcg_temp_free_i32(t0
);
488 static inline void tcg_gen_sub_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
490 tcg_gen_op3_i32(INDEX_op_sub_i32
, ret
, arg1
, arg2
);
493 static inline void tcg_gen_subfi_i32(TCGv_i32 ret
, int32_t arg1
, TCGv_i32 arg2
)
495 TCGv_i32 t0
= tcg_const_i32(arg1
);
496 tcg_gen_sub_i32(ret
, t0
, arg2
);
497 tcg_temp_free_i32(t0
);
500 static inline void tcg_gen_subi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
502 /* some cases can be optimized here */
504 tcg_gen_mov_i32(ret
, arg1
);
506 TCGv_i32 t0
= tcg_const_i32(arg2
);
507 tcg_gen_sub_i32(ret
, arg1
, t0
);
508 tcg_temp_free_i32(t0
);
512 static inline void tcg_gen_and_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
514 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
515 tcg_gen_mov_i32(ret
, arg1
);
517 tcg_gen_op3_i32(INDEX_op_and_i32
, ret
, arg1
, arg2
);
521 static inline void tcg_gen_andi_i32(TCGv_i32 ret
, TCGv_i32 arg1
, uint32_t arg2
)
524 /* Some cases can be optimized here. */
527 tcg_gen_movi_i32(ret
, 0);
530 tcg_gen_mov_i32(ret
, arg1
);
533 /* Don't recurse with tcg_gen_ext8u_i32. */
534 if (TCG_TARGET_HAS_ext8u_i32
) {
535 tcg_gen_op2_i32(INDEX_op_ext8u_i32
, ret
, arg1
);
540 if (TCG_TARGET_HAS_ext16u_i32
) {
541 tcg_gen_op2_i32(INDEX_op_ext16u_i32
, ret
, arg1
);
546 t0
= tcg_const_i32(arg2
);
547 tcg_gen_and_i32(ret
, arg1
, t0
);
548 tcg_temp_free_i32(t0
);
551 static inline void tcg_gen_or_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
553 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
554 tcg_gen_mov_i32(ret
, arg1
);
556 tcg_gen_op3_i32(INDEX_op_or_i32
, ret
, arg1
, arg2
);
560 static inline void tcg_gen_ori_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
562 /* Some cases can be optimized here. */
564 tcg_gen_movi_i32(ret
, -1);
565 } else if (arg2
== 0) {
566 tcg_gen_mov_i32(ret
, arg1
);
568 TCGv_i32 t0
= tcg_const_i32(arg2
);
569 tcg_gen_or_i32(ret
, arg1
, t0
);
570 tcg_temp_free_i32(t0
);
574 static inline void tcg_gen_xor_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
576 if (TCGV_EQUAL_I32(arg1
, arg2
)) {
577 tcg_gen_movi_i32(ret
, 0);
579 tcg_gen_op3_i32(INDEX_op_xor_i32
, ret
, arg1
, arg2
);
583 static inline void tcg_gen_xori_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
585 /* Some cases can be optimized here. */
587 tcg_gen_mov_i32(ret
, arg1
);
588 } else if (arg2
== -1 && TCG_TARGET_HAS_not_i32
) {
589 /* Don't recurse with tcg_gen_not_i32. */
590 tcg_gen_op2_i32(INDEX_op_not_i32
, ret
, arg1
);
592 TCGv_i32 t0
= tcg_const_i32(arg2
);
593 tcg_gen_xor_i32(ret
, arg1
, t0
);
594 tcg_temp_free_i32(t0
);
598 static inline void tcg_gen_shl_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
600 tcg_gen_op3_i32(INDEX_op_shl_i32
, ret
, arg1
, arg2
);
603 static inline void tcg_gen_shli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
606 tcg_gen_mov_i32(ret
, arg1
);
608 TCGv_i32 t0
= tcg_const_i32(arg2
);
609 tcg_gen_shl_i32(ret
, arg1
, t0
);
610 tcg_temp_free_i32(t0
);
614 static inline void tcg_gen_shr_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
616 tcg_gen_op3_i32(INDEX_op_shr_i32
, ret
, arg1
, arg2
);
619 static inline void tcg_gen_shri_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
622 tcg_gen_mov_i32(ret
, arg1
);
624 TCGv_i32 t0
= tcg_const_i32(arg2
);
625 tcg_gen_shr_i32(ret
, arg1
, t0
);
626 tcg_temp_free_i32(t0
);
630 static inline void tcg_gen_sar_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
632 tcg_gen_op3_i32(INDEX_op_sar_i32
, ret
, arg1
, arg2
);
635 static inline void tcg_gen_sari_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
638 tcg_gen_mov_i32(ret
, arg1
);
640 TCGv_i32 t0
= tcg_const_i32(arg2
);
641 tcg_gen_sar_i32(ret
, arg1
, t0
);
642 tcg_temp_free_i32(t0
);
646 static inline void tcg_gen_brcond_i32(TCGCond cond
, TCGv_i32 arg1
,
647 TCGv_i32 arg2
, int label_index
)
649 if (cond
== TCG_COND_ALWAYS
) {
650 tcg_gen_br(label_index
);
651 } else if (cond
!= TCG_COND_NEVER
) {
652 tcg_gen_op4ii_i32(INDEX_op_brcond_i32
, arg1
, arg2
, cond
, label_index
);
656 static inline void tcg_gen_brcondi_i32(TCGCond cond
, TCGv_i32 arg1
,
657 int32_t arg2
, int label_index
)
659 if (cond
== TCG_COND_ALWAYS
) {
660 tcg_gen_br(label_index
);
661 } else if (cond
!= TCG_COND_NEVER
) {
662 TCGv_i32 t0
= tcg_const_i32(arg2
);
663 tcg_gen_brcond_i32(cond
, arg1
, t0
, label_index
);
664 tcg_temp_free_i32(t0
);
668 static inline void tcg_gen_setcond_i32(TCGCond cond
, TCGv_i32 ret
,
669 TCGv_i32 arg1
, TCGv_i32 arg2
)
671 if (cond
== TCG_COND_ALWAYS
) {
672 tcg_gen_movi_i32(ret
, 1);
673 } else if (cond
== TCG_COND_NEVER
) {
674 tcg_gen_movi_i32(ret
, 0);
676 tcg_gen_op4i_i32(INDEX_op_setcond_i32
, ret
, arg1
, arg2
, cond
);
680 static inline void tcg_gen_setcondi_i32(TCGCond cond
, TCGv_i32 ret
,
681 TCGv_i32 arg1
, int32_t arg2
)
683 if (cond
== TCG_COND_ALWAYS
) {
684 tcg_gen_movi_i32(ret
, 1);
685 } else if (cond
== TCG_COND_NEVER
) {
686 tcg_gen_movi_i32(ret
, 0);
688 TCGv_i32 t0
= tcg_const_i32(arg2
);
689 tcg_gen_setcond_i32(cond
, ret
, arg1
, t0
);
690 tcg_temp_free_i32(t0
);
694 static inline void tcg_gen_mul_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
696 tcg_gen_op3_i32(INDEX_op_mul_i32
, ret
, arg1
, arg2
);
699 static inline void tcg_gen_muli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
701 TCGv_i32 t0
= tcg_const_i32(arg2
);
702 tcg_gen_mul_i32(ret
, arg1
, t0
);
703 tcg_temp_free_i32(t0
);
706 static inline void tcg_gen_div_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
708 if (TCG_TARGET_HAS_div_i32
) {
709 tcg_gen_op3_i32(INDEX_op_div_i32
, ret
, arg1
, arg2
);
710 } else if (TCG_TARGET_HAS_div2_i32
) {
711 TCGv_i32 t0
= tcg_temp_new_i32();
712 tcg_gen_sari_i32(t0
, arg1
, 31);
713 tcg_gen_op5_i32(INDEX_op_div2_i32
, ret
, t0
, arg1
, t0
, arg2
);
714 tcg_temp_free_i32(t0
);
717 /* Return value and both arguments are 32-bit and signed. */
718 sizemask
|= tcg_gen_sizemask(0, 0, 1);
719 sizemask
|= tcg_gen_sizemask(1, 0, 1);
720 sizemask
|= tcg_gen_sizemask(2, 0, 1);
721 tcg_gen_helper32(tcg_helper_div_i32
, sizemask
, ret
, arg1
, arg2
);
725 static inline void tcg_gen_rem_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
727 if (TCG_TARGET_HAS_div_i32
) {
728 tcg_gen_op3_i32(INDEX_op_rem_i32
, ret
, arg1
, arg2
);
729 } else if (TCG_TARGET_HAS_div2_i32
) {
730 TCGv_i32 t0
= tcg_temp_new_i32();
731 tcg_gen_sari_i32(t0
, arg1
, 31);
732 tcg_gen_op5_i32(INDEX_op_div2_i32
, t0
, ret
, arg1
, t0
, arg2
);
733 tcg_temp_free_i32(t0
);
736 /* Return value and both arguments are 32-bit and signed. */
737 sizemask
|= tcg_gen_sizemask(0, 0, 1);
738 sizemask
|= tcg_gen_sizemask(1, 0, 1);
739 sizemask
|= tcg_gen_sizemask(2, 0, 1);
740 tcg_gen_helper32(tcg_helper_rem_i32
, sizemask
, ret
, arg1
, arg2
);
744 static inline void tcg_gen_divu_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
746 if (TCG_TARGET_HAS_div_i32
) {
747 tcg_gen_op3_i32(INDEX_op_divu_i32
, ret
, arg1
, arg2
);
748 } else if (TCG_TARGET_HAS_div2_i32
) {
749 TCGv_i32 t0
= tcg_temp_new_i32();
750 tcg_gen_movi_i32(t0
, 0);
751 tcg_gen_op5_i32(INDEX_op_divu2_i32
, ret
, t0
, arg1
, t0
, arg2
);
752 tcg_temp_free_i32(t0
);
755 /* Return value and both arguments are 32-bit and unsigned. */
756 sizemask
|= tcg_gen_sizemask(0, 0, 0);
757 sizemask
|= tcg_gen_sizemask(1, 0, 0);
758 sizemask
|= tcg_gen_sizemask(2, 0, 0);
759 tcg_gen_helper32(tcg_helper_divu_i32
, sizemask
, ret
, arg1
, arg2
);
763 static inline void tcg_gen_remu_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
765 if (TCG_TARGET_HAS_div_i32
) {
766 tcg_gen_op3_i32(INDEX_op_remu_i32
, ret
, arg1
, arg2
);
767 } else if (TCG_TARGET_HAS_div2_i32
) {
768 TCGv_i32 t0
= tcg_temp_new_i32();
769 tcg_gen_movi_i32(t0
, 0);
770 tcg_gen_op5_i32(INDEX_op_divu2_i32
, t0
, ret
, arg1
, t0
, arg2
);
771 tcg_temp_free_i32(t0
);
774 /* Return value and both arguments are 32-bit and unsigned. */
775 sizemask
|= tcg_gen_sizemask(0, 0, 0);
776 sizemask
|= tcg_gen_sizemask(1, 0, 0);
777 sizemask
|= tcg_gen_sizemask(2, 0, 0);
778 tcg_gen_helper32(tcg_helper_remu_i32
, sizemask
, ret
, arg1
, arg2
);
782 #if TCG_TARGET_REG_BITS == 32
784 static inline void tcg_gen_mov_i64(TCGv_i64 ret
, TCGv_i64 arg
)
786 if (!TCGV_EQUAL_I64(ret
, arg
)) {
787 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
788 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
792 static inline void tcg_gen_movi_i64(TCGv_i64 ret
, int64_t arg
)
794 tcg_gen_movi_i32(TCGV_LOW(ret
), arg
);
795 tcg_gen_movi_i32(TCGV_HIGH(ret
), arg
>> 32);
798 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
799 tcg_target_long offset
)
801 tcg_gen_ld8u_i32(TCGV_LOW(ret
), arg2
, offset
);
802 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
805 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
806 tcg_target_long offset
)
808 tcg_gen_ld8s_i32(TCGV_LOW(ret
), arg2
, offset
);
809 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_HIGH(ret
), 31);
812 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
813 tcg_target_long offset
)
815 tcg_gen_ld16u_i32(TCGV_LOW(ret
), arg2
, offset
);
816 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
819 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
820 tcg_target_long offset
)
822 tcg_gen_ld16s_i32(TCGV_LOW(ret
), arg2
, offset
);
823 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
826 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
827 tcg_target_long offset
)
829 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
830 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
833 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
834 tcg_target_long offset
)
836 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
837 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
840 static inline void tcg_gen_ld_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
841 tcg_target_long offset
)
843 /* since arg2 and ret have different types, they cannot be the
845 #ifdef TCG_TARGET_WORDS_BIGENDIAN
846 tcg_gen_ld_i32(TCGV_HIGH(ret
), arg2
, offset
);
847 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
+ 4);
849 tcg_gen_ld_i32(TCGV_LOW(ret
), arg2
, offset
);
850 tcg_gen_ld_i32(TCGV_HIGH(ret
), arg2
, offset
+ 4);
854 static inline void tcg_gen_st8_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
855 tcg_target_long offset
)
857 tcg_gen_st8_i32(TCGV_LOW(arg1
), arg2
, offset
);
860 static inline void tcg_gen_st16_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
861 tcg_target_long offset
)
863 tcg_gen_st16_i32(TCGV_LOW(arg1
), arg2
, offset
);
866 static inline void tcg_gen_st32_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
867 tcg_target_long offset
)
869 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
);
872 static inline void tcg_gen_st_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
873 tcg_target_long offset
)
875 #ifdef TCG_TARGET_WORDS_BIGENDIAN
876 tcg_gen_st_i32(TCGV_HIGH(arg1
), arg2
, offset
);
877 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
+ 4);
879 tcg_gen_st_i32(TCGV_LOW(arg1
), arg2
, offset
);
880 tcg_gen_st_i32(TCGV_HIGH(arg1
), arg2
, offset
+ 4);
884 static inline void tcg_gen_add_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
886 tcg_gen_op6_i32(INDEX_op_add2_i32
, TCGV_LOW(ret
), TCGV_HIGH(ret
),
887 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
891 static inline void tcg_gen_sub_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
893 tcg_gen_op6_i32(INDEX_op_sub2_i32
, TCGV_LOW(ret
), TCGV_HIGH(ret
),
894 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
898 static inline void tcg_gen_and_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
900 tcg_gen_and_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
901 tcg_gen_and_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
904 static inline void tcg_gen_andi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
906 tcg_gen_andi_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
907 tcg_gen_andi_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
910 static inline void tcg_gen_or_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
912 tcg_gen_or_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
913 tcg_gen_or_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
916 static inline void tcg_gen_ori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
918 tcg_gen_ori_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
919 tcg_gen_ori_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
922 static inline void tcg_gen_xor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
924 tcg_gen_xor_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
925 tcg_gen_xor_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
928 static inline void tcg_gen_xori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
930 tcg_gen_xori_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), arg2
);
931 tcg_gen_xori_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), arg2
>> 32);
934 /* XXX: use generic code when basic block handling is OK or CPU
935 specific code (x86) */
936 static inline void tcg_gen_shl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
939 /* Return value and both arguments are 64-bit and signed. */
940 sizemask
|= tcg_gen_sizemask(0, 1, 1);
941 sizemask
|= tcg_gen_sizemask(1, 1, 1);
942 sizemask
|= tcg_gen_sizemask(2, 1, 1);
944 tcg_gen_helper64(tcg_helper_shl_i64
, sizemask
, ret
, arg1
, arg2
);
947 static inline void tcg_gen_shli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
949 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 0, 0);
952 static inline void tcg_gen_shr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
955 /* Return value and both arguments are 64-bit and signed. */
956 sizemask
|= tcg_gen_sizemask(0, 1, 1);
957 sizemask
|= tcg_gen_sizemask(1, 1, 1);
958 sizemask
|= tcg_gen_sizemask(2, 1, 1);
960 tcg_gen_helper64(tcg_helper_shr_i64
, sizemask
, ret
, arg1
, arg2
);
963 static inline void tcg_gen_shri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
965 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 1, 0);
968 static inline void tcg_gen_sar_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
971 /* Return value and both arguments are 64-bit and signed. */
972 sizemask
|= tcg_gen_sizemask(0, 1, 1);
973 sizemask
|= tcg_gen_sizemask(1, 1, 1);
974 sizemask
|= tcg_gen_sizemask(2, 1, 1);
976 tcg_gen_helper64(tcg_helper_sar_i64
, sizemask
, ret
, arg1
, arg2
);
979 static inline void tcg_gen_sari_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
981 tcg_gen_shifti_i64(ret
, arg1
, arg2
, 1, 1);
984 static inline void tcg_gen_brcond_i64(TCGCond cond
, TCGv_i64 arg1
,
985 TCGv_i64 arg2
, int label_index
)
987 if (cond
== TCG_COND_ALWAYS
) {
988 tcg_gen_br(label_index
);
989 } else if (cond
!= TCG_COND_NEVER
) {
990 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32
,
991 TCGV_LOW(arg1
), TCGV_HIGH(arg1
), TCGV_LOW(arg2
),
992 TCGV_HIGH(arg2
), cond
, label_index
);
996 static inline void tcg_gen_setcond_i64(TCGCond cond
, TCGv_i64 ret
,
997 TCGv_i64 arg1
, TCGv_i64 arg2
)
999 if (cond
== TCG_COND_ALWAYS
) {
1000 tcg_gen_movi_i32(TCGV_LOW(ret
), 1);
1001 } else if (cond
== TCG_COND_NEVER
) {
1002 tcg_gen_movi_i32(TCGV_LOW(ret
), 0);
1004 tcg_gen_op6i_i32(INDEX_op_setcond2_i32
, TCGV_LOW(ret
),
1005 TCGV_LOW(arg1
), TCGV_HIGH(arg1
),
1006 TCGV_LOW(arg2
), TCGV_HIGH(arg2
), cond
);
1008 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1011 static inline void tcg_gen_mul_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1016 t0
= tcg_temp_new_i64();
1017 t1
= tcg_temp_new_i32();
1019 tcg_gen_op4_i32(INDEX_op_mulu2_i32
, TCGV_LOW(t0
), TCGV_HIGH(t0
),
1020 TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1022 tcg_gen_mul_i32(t1
, TCGV_LOW(arg1
), TCGV_HIGH(arg2
));
1023 tcg_gen_add_i32(TCGV_HIGH(t0
), TCGV_HIGH(t0
), t1
);
1024 tcg_gen_mul_i32(t1
, TCGV_HIGH(arg1
), TCGV_LOW(arg2
));
1025 tcg_gen_add_i32(TCGV_HIGH(t0
), TCGV_HIGH(t0
), t1
);
1027 tcg_gen_mov_i64(ret
, t0
);
1028 tcg_temp_free_i64(t0
);
1029 tcg_temp_free_i32(t1
);
1032 static inline void tcg_gen_div_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1035 /* Return value and both arguments are 64-bit and signed. */
1036 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1037 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1038 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1040 tcg_gen_helper64(tcg_helper_div_i64
, sizemask
, ret
, arg1
, arg2
);
1043 static inline void tcg_gen_rem_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1046 /* Return value and both arguments are 64-bit and signed. */
1047 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1048 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1049 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1051 tcg_gen_helper64(tcg_helper_rem_i64
, sizemask
, ret
, arg1
, arg2
);
1054 static inline void tcg_gen_divu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1057 /* Return value and both arguments are 64-bit and unsigned. */
1058 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1059 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1060 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1062 tcg_gen_helper64(tcg_helper_divu_i64
, sizemask
, ret
, arg1
, arg2
);
1065 static inline void tcg_gen_remu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1068 /* Return value and both arguments are 64-bit and unsigned. */
1069 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1070 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1071 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1073 tcg_gen_helper64(tcg_helper_remu_i64
, sizemask
, ret
, arg1
, arg2
);
1078 static inline void tcg_gen_mov_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1080 if (!TCGV_EQUAL_I64(ret
, arg
))
1081 tcg_gen_op2_i64(INDEX_op_mov_i64
, ret
, arg
);
1084 static inline void tcg_gen_movi_i64(TCGv_i64 ret
, int64_t arg
)
1086 tcg_gen_op2i_i64(INDEX_op_movi_i64
, ret
, arg
);
1089 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1090 tcg_target_long offset
)
1092 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64
, ret
, arg2
, offset
);
1095 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1096 tcg_target_long offset
)
1098 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64
, ret
, arg2
, offset
);
1101 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1102 tcg_target_long offset
)
1104 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64
, ret
, arg2
, offset
);
1107 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1108 tcg_target_long offset
)
1110 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64
, ret
, arg2
, offset
);
1113 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1114 tcg_target_long offset
)
1116 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64
, ret
, arg2
, offset
);
1119 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret
, TCGv_ptr arg2
,
1120 tcg_target_long offset
)
1122 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64
, ret
, arg2
, offset
);
1125 static inline void tcg_gen_ld_i64(TCGv_i64 ret
, TCGv_ptr arg2
, tcg_target_long offset
)
1127 tcg_gen_ldst_op_i64(INDEX_op_ld_i64
, ret
, arg2
, offset
);
1130 static inline void tcg_gen_st8_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1131 tcg_target_long offset
)
1133 tcg_gen_ldst_op_i64(INDEX_op_st8_i64
, arg1
, arg2
, offset
);
1136 static inline void tcg_gen_st16_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1137 tcg_target_long offset
)
1139 tcg_gen_ldst_op_i64(INDEX_op_st16_i64
, arg1
, arg2
, offset
);
1142 static inline void tcg_gen_st32_i64(TCGv_i64 arg1
, TCGv_ptr arg2
,
1143 tcg_target_long offset
)
1145 tcg_gen_ldst_op_i64(INDEX_op_st32_i64
, arg1
, arg2
, offset
);
1148 static inline void tcg_gen_st_i64(TCGv_i64 arg1
, TCGv_ptr arg2
, tcg_target_long offset
)
1150 tcg_gen_ldst_op_i64(INDEX_op_st_i64
, arg1
, arg2
, offset
);
1153 static inline void tcg_gen_add_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1155 tcg_gen_op3_i64(INDEX_op_add_i64
, ret
, arg1
, arg2
);
1158 static inline void tcg_gen_sub_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1160 tcg_gen_op3_i64(INDEX_op_sub_i64
, ret
, arg1
, arg2
);
1163 static inline void tcg_gen_and_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1165 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1166 tcg_gen_mov_i64(ret
, arg1
);
1168 tcg_gen_op3_i64(INDEX_op_and_i64
, ret
, arg1
, arg2
);
1172 static inline void tcg_gen_andi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, uint64_t arg2
)
1175 /* Some cases can be optimized here. */
1178 tcg_gen_movi_i64(ret
, 0);
1180 case 0xffffffffffffffffull
:
1181 tcg_gen_mov_i64(ret
, arg1
);
1184 /* Don't recurse with tcg_gen_ext8u_i32. */
1185 if (TCG_TARGET_HAS_ext8u_i64
) {
1186 tcg_gen_op2_i64(INDEX_op_ext8u_i64
, ret
, arg1
);
1191 if (TCG_TARGET_HAS_ext16u_i64
) {
1192 tcg_gen_op2_i64(INDEX_op_ext16u_i64
, ret
, arg1
);
1197 if (TCG_TARGET_HAS_ext32u_i64
) {
1198 tcg_gen_op2_i64(INDEX_op_ext32u_i64
, ret
, arg1
);
1203 t0
= tcg_const_i64(arg2
);
1204 tcg_gen_and_i64(ret
, arg1
, t0
);
1205 tcg_temp_free_i64(t0
);
1208 static inline void tcg_gen_or_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1210 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1211 tcg_gen_mov_i64(ret
, arg1
);
1213 tcg_gen_op3_i64(INDEX_op_or_i64
, ret
, arg1
, arg2
);
1217 static inline void tcg_gen_ori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1219 /* Some cases can be optimized here. */
1221 tcg_gen_movi_i64(ret
, -1);
1222 } else if (arg2
== 0) {
1223 tcg_gen_mov_i64(ret
, arg1
);
1225 TCGv_i64 t0
= tcg_const_i64(arg2
);
1226 tcg_gen_or_i64(ret
, arg1
, t0
);
1227 tcg_temp_free_i64(t0
);
1231 static inline void tcg_gen_xor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1233 if (TCGV_EQUAL_I64(arg1
, arg2
)) {
1234 tcg_gen_movi_i64(ret
, 0);
1236 tcg_gen_op3_i64(INDEX_op_xor_i64
, ret
, arg1
, arg2
);
1240 static inline void tcg_gen_xori_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1242 /* Some cases can be optimized here. */
1244 tcg_gen_mov_i64(ret
, arg1
);
1245 } else if (arg2
== -1 && TCG_TARGET_HAS_not_i64
) {
1246 /* Don't recurse with tcg_gen_not_i64. */
1247 tcg_gen_op2_i64(INDEX_op_not_i64
, ret
, arg1
);
1249 TCGv_i64 t0
= tcg_const_i64(arg2
);
1250 tcg_gen_xor_i64(ret
, arg1
, t0
);
1251 tcg_temp_free_i64(t0
);
1255 static inline void tcg_gen_shl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1257 tcg_gen_op3_i64(INDEX_op_shl_i64
, ret
, arg1
, arg2
);
1260 static inline void tcg_gen_shli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1263 tcg_gen_mov_i64(ret
, arg1
);
1265 TCGv_i64 t0
= tcg_const_i64(arg2
);
1266 tcg_gen_shl_i64(ret
, arg1
, t0
);
1267 tcg_temp_free_i64(t0
);
1271 static inline void tcg_gen_shr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1273 tcg_gen_op3_i64(INDEX_op_shr_i64
, ret
, arg1
, arg2
);
1276 static inline void tcg_gen_shri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1279 tcg_gen_mov_i64(ret
, arg1
);
1281 TCGv_i64 t0
= tcg_const_i64(arg2
);
1282 tcg_gen_shr_i64(ret
, arg1
, t0
);
1283 tcg_temp_free_i64(t0
);
1287 static inline void tcg_gen_sar_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1289 tcg_gen_op3_i64(INDEX_op_sar_i64
, ret
, arg1
, arg2
);
1292 static inline void tcg_gen_sari_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1295 tcg_gen_mov_i64(ret
, arg1
);
1297 TCGv_i64 t0
= tcg_const_i64(arg2
);
1298 tcg_gen_sar_i64(ret
, arg1
, t0
);
1299 tcg_temp_free_i64(t0
);
1303 static inline void tcg_gen_brcond_i64(TCGCond cond
, TCGv_i64 arg1
,
1304 TCGv_i64 arg2
, int label_index
)
1306 if (cond
== TCG_COND_ALWAYS
) {
1307 tcg_gen_br(label_index
);
1308 } else if (cond
!= TCG_COND_NEVER
) {
1309 tcg_gen_op4ii_i64(INDEX_op_brcond_i64
, arg1
, arg2
, cond
, label_index
);
1313 static inline void tcg_gen_setcond_i64(TCGCond cond
, TCGv_i64 ret
,
1314 TCGv_i64 arg1
, TCGv_i64 arg2
)
1316 if (cond
== TCG_COND_ALWAYS
) {
1317 tcg_gen_movi_i64(ret
, 1);
1318 } else if (cond
== TCG_COND_NEVER
) {
1319 tcg_gen_movi_i64(ret
, 0);
1321 tcg_gen_op4i_i64(INDEX_op_setcond_i64
, ret
, arg1
, arg2
, cond
);
1325 static inline void tcg_gen_mul_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1327 tcg_gen_op3_i64(INDEX_op_mul_i64
, ret
, arg1
, arg2
);
1330 static inline void tcg_gen_div_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1332 if (TCG_TARGET_HAS_div_i64
) {
1333 tcg_gen_op3_i64(INDEX_op_div_i64
, ret
, arg1
, arg2
);
1334 } else if (TCG_TARGET_HAS_div2_i64
) {
1335 TCGv_i64 t0
= tcg_temp_new_i64();
1336 tcg_gen_sari_i64(t0
, arg1
, 63);
1337 tcg_gen_op5_i64(INDEX_op_div2_i64
, ret
, t0
, arg1
, t0
, arg2
);
1338 tcg_temp_free_i64(t0
);
1341 /* Return value and both arguments are 64-bit and signed. */
1342 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1343 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1344 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1345 tcg_gen_helper64(tcg_helper_div_i64
, sizemask
, ret
, arg1
, arg2
);
1349 static inline void tcg_gen_rem_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1351 if (TCG_TARGET_HAS_div_i64
) {
1352 tcg_gen_op3_i64(INDEX_op_rem_i64
, ret
, arg1
, arg2
);
1353 } else if (TCG_TARGET_HAS_div2_i64
) {
1354 TCGv_i64 t0
= tcg_temp_new_i64();
1355 tcg_gen_sari_i64(t0
, arg1
, 63);
1356 tcg_gen_op5_i64(INDEX_op_div2_i64
, t0
, ret
, arg1
, t0
, arg2
);
1357 tcg_temp_free_i64(t0
);
1360 /* Return value and both arguments are 64-bit and signed. */
1361 sizemask
|= tcg_gen_sizemask(0, 1, 1);
1362 sizemask
|= tcg_gen_sizemask(1, 1, 1);
1363 sizemask
|= tcg_gen_sizemask(2, 1, 1);
1364 tcg_gen_helper64(tcg_helper_rem_i64
, sizemask
, ret
, arg1
, arg2
);
1368 static inline void tcg_gen_divu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1370 if (TCG_TARGET_HAS_div_i64
) {
1371 tcg_gen_op3_i64(INDEX_op_divu_i64
, ret
, arg1
, arg2
);
1372 } else if (TCG_TARGET_HAS_div2_i64
) {
1373 TCGv_i64 t0
= tcg_temp_new_i64();
1374 tcg_gen_movi_i64(t0
, 0);
1375 tcg_gen_op5_i64(INDEX_op_divu2_i64
, ret
, t0
, arg1
, t0
, arg2
);
1376 tcg_temp_free_i64(t0
);
1379 /* Return value and both arguments are 64-bit and unsigned. */
1380 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1381 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1382 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1383 tcg_gen_helper64(tcg_helper_divu_i64
, sizemask
, ret
, arg1
, arg2
);
1387 static inline void tcg_gen_remu_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1389 if (TCG_TARGET_HAS_div_i64
) {
1390 tcg_gen_op3_i64(INDEX_op_remu_i64
, ret
, arg1
, arg2
);
1391 } else if (TCG_TARGET_HAS_div2_i64
) {
1392 TCGv_i64 t0
= tcg_temp_new_i64();
1393 tcg_gen_movi_i64(t0
, 0);
1394 tcg_gen_op5_i64(INDEX_op_divu2_i64
, t0
, ret
, arg1
, t0
, arg2
);
1395 tcg_temp_free_i64(t0
);
1398 /* Return value and both arguments are 64-bit and unsigned. */
1399 sizemask
|= tcg_gen_sizemask(0, 1, 0);
1400 sizemask
|= tcg_gen_sizemask(1, 1, 0);
1401 sizemask
|= tcg_gen_sizemask(2, 1, 0);
1402 tcg_gen_helper64(tcg_helper_remu_i64
, sizemask
, ret
, arg1
, arg2
);
1405 #endif /* TCG_TARGET_REG_BITS == 32 */
1407 static inline void tcg_gen_addi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1409 /* some cases can be optimized here */
1411 tcg_gen_mov_i64(ret
, arg1
);
1413 TCGv_i64 t0
= tcg_const_i64(arg2
);
1414 tcg_gen_add_i64(ret
, arg1
, t0
);
1415 tcg_temp_free_i64(t0
);
1419 static inline void tcg_gen_subfi_i64(TCGv_i64 ret
, int64_t arg1
, TCGv_i64 arg2
)
1421 TCGv_i64 t0
= tcg_const_i64(arg1
);
1422 tcg_gen_sub_i64(ret
, t0
, arg2
);
1423 tcg_temp_free_i64(t0
);
1426 static inline void tcg_gen_subi_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1428 /* some cases can be optimized here */
1430 tcg_gen_mov_i64(ret
, arg1
);
1432 TCGv_i64 t0
= tcg_const_i64(arg2
);
1433 tcg_gen_sub_i64(ret
, arg1
, t0
);
1434 tcg_temp_free_i64(t0
);
1437 static inline void tcg_gen_brcondi_i64(TCGCond cond
, TCGv_i64 arg1
,
1438 int64_t arg2
, int label_index
)
1440 if (cond
== TCG_COND_ALWAYS
) {
1441 tcg_gen_br(label_index
);
1442 } else if (cond
!= TCG_COND_NEVER
) {
1443 TCGv_i64 t0
= tcg_const_i64(arg2
);
1444 tcg_gen_brcond_i64(cond
, arg1
, t0
, label_index
);
1445 tcg_temp_free_i64(t0
);
1449 static inline void tcg_gen_setcondi_i64(TCGCond cond
, TCGv_i64 ret
,
1450 TCGv_i64 arg1
, int64_t arg2
)
1452 TCGv_i64 t0
= tcg_const_i64(arg2
);
1453 tcg_gen_setcond_i64(cond
, ret
, arg1
, t0
);
1454 tcg_temp_free_i64(t0
);
1457 static inline void tcg_gen_muli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
1459 TCGv_i64 t0
= tcg_const_i64(arg2
);
1460 tcg_gen_mul_i64(ret
, arg1
, t0
);
1461 tcg_temp_free_i64(t0
);
1465 /***************************************/
1466 /* optional operations */
1468 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1470 if (TCG_TARGET_HAS_ext8s_i32
) {
1471 tcg_gen_op2_i32(INDEX_op_ext8s_i32
, ret
, arg
);
1473 tcg_gen_shli_i32(ret
, arg
, 24);
1474 tcg_gen_sari_i32(ret
, ret
, 24);
1478 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1480 if (TCG_TARGET_HAS_ext16s_i32
) {
1481 tcg_gen_op2_i32(INDEX_op_ext16s_i32
, ret
, arg
);
1483 tcg_gen_shli_i32(ret
, arg
, 16);
1484 tcg_gen_sari_i32(ret
, ret
, 16);
1488 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1490 if (TCG_TARGET_HAS_ext8u_i32
) {
1491 tcg_gen_op2_i32(INDEX_op_ext8u_i32
, ret
, arg
);
1493 tcg_gen_andi_i32(ret
, arg
, 0xffu
);
1497 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1499 if (TCG_TARGET_HAS_ext16u_i32
) {
1500 tcg_gen_op2_i32(INDEX_op_ext16u_i32
, ret
, arg
);
1502 tcg_gen_andi_i32(ret
, arg
, 0xffffu
);
1506 /* Note: we assume the two high bytes are set to zero */
1507 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1509 if (TCG_TARGET_HAS_bswap16_i32
) {
1510 tcg_gen_op2_i32(INDEX_op_bswap16_i32
, ret
, arg
);
1512 TCGv_i32 t0
= tcg_temp_new_i32();
1514 tcg_gen_ext8u_i32(t0
, arg
);
1515 tcg_gen_shli_i32(t0
, t0
, 8);
1516 tcg_gen_shri_i32(ret
, arg
, 8);
1517 tcg_gen_or_i32(ret
, ret
, t0
);
1518 tcg_temp_free_i32(t0
);
1522 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1524 if (TCG_TARGET_HAS_bswap32_i32
) {
1525 tcg_gen_op2_i32(INDEX_op_bswap32_i32
, ret
, arg
);
1528 t0
= tcg_temp_new_i32();
1529 t1
= tcg_temp_new_i32();
1531 tcg_gen_shli_i32(t0
, arg
, 24);
1533 tcg_gen_andi_i32(t1
, arg
, 0x0000ff00);
1534 tcg_gen_shli_i32(t1
, t1
, 8);
1535 tcg_gen_or_i32(t0
, t0
, t1
);
1537 tcg_gen_shri_i32(t1
, arg
, 8);
1538 tcg_gen_andi_i32(t1
, t1
, 0x0000ff00);
1539 tcg_gen_or_i32(t0
, t0
, t1
);
1541 tcg_gen_shri_i32(t1
, arg
, 24);
1542 tcg_gen_or_i32(ret
, t0
, t1
);
1543 tcg_temp_free_i32(t0
);
1544 tcg_temp_free_i32(t1
);
1548 #if TCG_TARGET_REG_BITS == 32
1549 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1551 tcg_gen_ext8s_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1552 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1555 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1557 tcg_gen_ext16s_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1558 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1561 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1563 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1564 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1567 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1569 tcg_gen_ext8u_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1570 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1573 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1575 tcg_gen_ext16u_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1576 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1579 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1581 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1582 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1585 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret
, TCGv_i64 arg
)
1587 tcg_gen_mov_i32(ret
, TCGV_LOW(arg
));
1590 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1592 tcg_gen_mov_i32(TCGV_LOW(ret
), arg
);
1593 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
1596 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1598 tcg_gen_mov_i32(TCGV_LOW(ret
), arg
);
1599 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
1602 /* Note: we assume the six high bytes are set to zero */
1603 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1605 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1606 tcg_gen_bswap16_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1609 /* Note: we assume the four high bytes are set to zero */
1610 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1612 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1613 tcg_gen_bswap32_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1616 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1619 t0
= tcg_temp_new_i32();
1620 t1
= tcg_temp_new_i32();
1622 tcg_gen_bswap32_i32(t0
, TCGV_LOW(arg
));
1623 tcg_gen_bswap32_i32(t1
, TCGV_HIGH(arg
));
1624 tcg_gen_mov_i32(TCGV_LOW(ret
), t1
);
1625 tcg_gen_mov_i32(TCGV_HIGH(ret
), t0
);
1626 tcg_temp_free_i32(t0
);
1627 tcg_temp_free_i32(t1
);
1631 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1633 if (TCG_TARGET_HAS_ext8s_i64
) {
1634 tcg_gen_op2_i64(INDEX_op_ext8s_i64
, ret
, arg
);
1636 tcg_gen_shli_i64(ret
, arg
, 56);
1637 tcg_gen_sari_i64(ret
, ret
, 56);
1641 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1643 if (TCG_TARGET_HAS_ext16s_i64
) {
1644 tcg_gen_op2_i64(INDEX_op_ext16s_i64
, ret
, arg
);
1646 tcg_gen_shli_i64(ret
, arg
, 48);
1647 tcg_gen_sari_i64(ret
, ret
, 48);
1651 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1653 if (TCG_TARGET_HAS_ext32s_i64
) {
1654 tcg_gen_op2_i64(INDEX_op_ext32s_i64
, ret
, arg
);
1656 tcg_gen_shli_i64(ret
, arg
, 32);
1657 tcg_gen_sari_i64(ret
, ret
, 32);
1661 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1663 if (TCG_TARGET_HAS_ext8u_i64
) {
1664 tcg_gen_op2_i64(INDEX_op_ext8u_i64
, ret
, arg
);
1666 tcg_gen_andi_i64(ret
, arg
, 0xffu
);
1670 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1672 if (TCG_TARGET_HAS_ext16u_i64
) {
1673 tcg_gen_op2_i64(INDEX_op_ext16u_i64
, ret
, arg
);
1675 tcg_gen_andi_i64(ret
, arg
, 0xffffu
);
1679 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1681 if (TCG_TARGET_HAS_ext32u_i64
) {
1682 tcg_gen_op2_i64(INDEX_op_ext32u_i64
, ret
, arg
);
1684 tcg_gen_andi_i64(ret
, arg
, 0xffffffffu
);
1688 /* Note: we assume the target supports move between 32 and 64 bit
1689 registers. This will probably break MIPS64 targets. */
1690 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret
, TCGv_i64 arg
)
1692 tcg_gen_mov_i32(ret
, MAKE_TCGV_I32(GET_TCGV_I64(arg
)));
1695 /* Note: we assume the target supports move between 32 and 64 bit
1697 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1699 tcg_gen_ext32u_i64(ret
, MAKE_TCGV_I64(GET_TCGV_I32(arg
)));
1702 /* Note: we assume the target supports move between 32 and 64 bit
1704 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret
, TCGv_i32 arg
)
1706 tcg_gen_ext32s_i64(ret
, MAKE_TCGV_I64(GET_TCGV_I32(arg
)));
1709 /* Note: we assume the six high bytes are set to zero */
1710 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1712 if (TCG_TARGET_HAS_bswap16_i64
) {
1713 tcg_gen_op2_i64(INDEX_op_bswap16_i64
, ret
, arg
);
1715 TCGv_i64 t0
= tcg_temp_new_i64();
1717 tcg_gen_ext8u_i64(t0
, arg
);
1718 tcg_gen_shli_i64(t0
, t0
, 8);
1719 tcg_gen_shri_i64(ret
, arg
, 8);
1720 tcg_gen_or_i64(ret
, ret
, t0
);
1721 tcg_temp_free_i64(t0
);
1725 /* Note: we assume the four high bytes are set to zero */
1726 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1728 if (TCG_TARGET_HAS_bswap32_i64
) {
1729 tcg_gen_op2_i64(INDEX_op_bswap32_i64
, ret
, arg
);
1732 t0
= tcg_temp_new_i64();
1733 t1
= tcg_temp_new_i64();
1735 tcg_gen_shli_i64(t0
, arg
, 24);
1736 tcg_gen_ext32u_i64(t0
, t0
);
1738 tcg_gen_andi_i64(t1
, arg
, 0x0000ff00);
1739 tcg_gen_shli_i64(t1
, t1
, 8);
1740 tcg_gen_or_i64(t0
, t0
, t1
);
1742 tcg_gen_shri_i64(t1
, arg
, 8);
1743 tcg_gen_andi_i64(t1
, t1
, 0x0000ff00);
1744 tcg_gen_or_i64(t0
, t0
, t1
);
1746 tcg_gen_shri_i64(t1
, arg
, 24);
1747 tcg_gen_or_i64(ret
, t0
, t1
);
1748 tcg_temp_free_i64(t0
);
1749 tcg_temp_free_i64(t1
);
1753 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1755 if (TCG_TARGET_HAS_bswap64_i64
) {
1756 tcg_gen_op2_i64(INDEX_op_bswap64_i64
, ret
, arg
);
1758 TCGv_i64 t0
= tcg_temp_new_i64();
1759 TCGv_i64 t1
= tcg_temp_new_i64();
1761 tcg_gen_shli_i64(t0
, arg
, 56);
1763 tcg_gen_andi_i64(t1
, arg
, 0x0000ff00);
1764 tcg_gen_shli_i64(t1
, t1
, 40);
1765 tcg_gen_or_i64(t0
, t0
, t1
);
1767 tcg_gen_andi_i64(t1
, arg
, 0x00ff0000);
1768 tcg_gen_shli_i64(t1
, t1
, 24);
1769 tcg_gen_or_i64(t0
, t0
, t1
);
1771 tcg_gen_andi_i64(t1
, arg
, 0xff000000);
1772 tcg_gen_shli_i64(t1
, t1
, 8);
1773 tcg_gen_or_i64(t0
, t0
, t1
);
1775 tcg_gen_shri_i64(t1
, arg
, 8);
1776 tcg_gen_andi_i64(t1
, t1
, 0xff000000);
1777 tcg_gen_or_i64(t0
, t0
, t1
);
1779 tcg_gen_shri_i64(t1
, arg
, 24);
1780 tcg_gen_andi_i64(t1
, t1
, 0x00ff0000);
1781 tcg_gen_or_i64(t0
, t0
, t1
);
1783 tcg_gen_shri_i64(t1
, arg
, 40);
1784 tcg_gen_andi_i64(t1
, t1
, 0x0000ff00);
1785 tcg_gen_or_i64(t0
, t0
, t1
);
1787 tcg_gen_shri_i64(t1
, arg
, 56);
1788 tcg_gen_or_i64(ret
, t0
, t1
);
1789 tcg_temp_free_i64(t0
);
1790 tcg_temp_free_i64(t1
);
1796 static inline void tcg_gen_neg_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1798 if (TCG_TARGET_HAS_neg_i32
) {
1799 tcg_gen_op2_i32(INDEX_op_neg_i32
, ret
, arg
);
1801 TCGv_i32 t0
= tcg_const_i32(0);
1802 tcg_gen_sub_i32(ret
, t0
, arg
);
1803 tcg_temp_free_i32(t0
);
1807 static inline void tcg_gen_neg_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1809 if (TCG_TARGET_HAS_neg_i64
) {
1810 tcg_gen_op2_i64(INDEX_op_neg_i64
, ret
, arg
);
1812 TCGv_i64 t0
= tcg_const_i64(0);
1813 tcg_gen_sub_i64(ret
, t0
, arg
);
1814 tcg_temp_free_i64(t0
);
1818 static inline void tcg_gen_not_i32(TCGv_i32 ret
, TCGv_i32 arg
)
1820 if (TCG_TARGET_HAS_not_i32
) {
1821 tcg_gen_op2_i32(INDEX_op_not_i32
, ret
, arg
);
1823 tcg_gen_xori_i32(ret
, arg
, -1);
1827 static inline void tcg_gen_not_i64(TCGv_i64 ret
, TCGv_i64 arg
)
1829 #if TCG_TARGET_REG_BITS == 64
1830 if (TCG_TARGET_HAS_not_i64
) {
1831 tcg_gen_op2_i64(INDEX_op_not_i64
, ret
, arg
);
1833 tcg_gen_xori_i64(ret
, arg
, -1);
1836 tcg_gen_not_i32(TCGV_LOW(ret
), TCGV_LOW(arg
));
1837 tcg_gen_not_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg
));
1841 static inline void tcg_gen_discard_i32(TCGv_i32 arg
)
1843 tcg_gen_op1_i32(INDEX_op_discard
, arg
);
1846 static inline void tcg_gen_discard_i64(TCGv_i64 arg
)
1848 #if TCG_TARGET_REG_BITS == 32
1849 tcg_gen_discard_i32(TCGV_LOW(arg
));
1850 tcg_gen_discard_i32(TCGV_HIGH(arg
));
1852 tcg_gen_op1_i64(INDEX_op_discard
, arg
);
1856 static inline void tcg_gen_andc_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1858 if (TCG_TARGET_HAS_andc_i32
) {
1859 tcg_gen_op3_i32(INDEX_op_andc_i32
, ret
, arg1
, arg2
);
1861 TCGv_i32 t0
= tcg_temp_new_i32();
1862 tcg_gen_not_i32(t0
, arg2
);
1863 tcg_gen_and_i32(ret
, arg1
, t0
);
1864 tcg_temp_free_i32(t0
);
1868 static inline void tcg_gen_andc_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1870 #if TCG_TARGET_REG_BITS == 64
1871 if (TCG_TARGET_HAS_andc_i64
) {
1872 tcg_gen_op3_i64(INDEX_op_andc_i64
, ret
, arg1
, arg2
);
1874 TCGv_i64 t0
= tcg_temp_new_i64();
1875 tcg_gen_not_i64(t0
, arg2
);
1876 tcg_gen_and_i64(ret
, arg1
, t0
);
1877 tcg_temp_free_i64(t0
);
1880 tcg_gen_andc_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1881 tcg_gen_andc_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1885 static inline void tcg_gen_eqv_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1887 if (TCG_TARGET_HAS_eqv_i32
) {
1888 tcg_gen_op3_i32(INDEX_op_eqv_i32
, ret
, arg1
, arg2
);
1890 tcg_gen_xor_i32(ret
, arg1
, arg2
);
1891 tcg_gen_not_i32(ret
, ret
);
1895 static inline void tcg_gen_eqv_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1897 #if TCG_TARGET_REG_BITS == 64
1898 if (TCG_TARGET_HAS_eqv_i64
) {
1899 tcg_gen_op3_i64(INDEX_op_eqv_i64
, ret
, arg1
, arg2
);
1901 tcg_gen_xor_i64(ret
, arg1
, arg2
);
1902 tcg_gen_not_i64(ret
, ret
);
1905 tcg_gen_eqv_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1906 tcg_gen_eqv_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1910 static inline void tcg_gen_nand_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1912 if (TCG_TARGET_HAS_nand_i32
) {
1913 tcg_gen_op3_i32(INDEX_op_nand_i32
, ret
, arg1
, arg2
);
1915 tcg_gen_and_i32(ret
, arg1
, arg2
);
1916 tcg_gen_not_i32(ret
, ret
);
1920 static inline void tcg_gen_nand_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1922 #if TCG_TARGET_REG_BITS == 64
1923 if (TCG_TARGET_HAS_nand_i64
) {
1924 tcg_gen_op3_i64(INDEX_op_nand_i64
, ret
, arg1
, arg2
);
1926 tcg_gen_and_i64(ret
, arg1
, arg2
);
1927 tcg_gen_not_i64(ret
, ret
);
1930 tcg_gen_nand_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1931 tcg_gen_nand_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1935 static inline void tcg_gen_nor_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1937 if (TCG_TARGET_HAS_nor_i32
) {
1938 tcg_gen_op3_i32(INDEX_op_nor_i32
, ret
, arg1
, arg2
);
1940 tcg_gen_or_i32(ret
, arg1
, arg2
);
1941 tcg_gen_not_i32(ret
, ret
);
1945 static inline void tcg_gen_nor_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1947 #if TCG_TARGET_REG_BITS == 64
1948 if (TCG_TARGET_HAS_nor_i64
) {
1949 tcg_gen_op3_i64(INDEX_op_nor_i64
, ret
, arg1
, arg2
);
1951 tcg_gen_or_i64(ret
, arg1
, arg2
);
1952 tcg_gen_not_i64(ret
, ret
);
1955 tcg_gen_nor_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1956 tcg_gen_nor_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1960 static inline void tcg_gen_orc_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1962 if (TCG_TARGET_HAS_orc_i32
) {
1963 tcg_gen_op3_i32(INDEX_op_orc_i32
, ret
, arg1
, arg2
);
1965 TCGv_i32 t0
= tcg_temp_new_i32();
1966 tcg_gen_not_i32(t0
, arg2
);
1967 tcg_gen_or_i32(ret
, arg1
, t0
);
1968 tcg_temp_free_i32(t0
);
1972 static inline void tcg_gen_orc_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
1974 #if TCG_TARGET_REG_BITS == 64
1975 if (TCG_TARGET_HAS_orc_i64
) {
1976 tcg_gen_op3_i64(INDEX_op_orc_i64
, ret
, arg1
, arg2
);
1978 TCGv_i64 t0
= tcg_temp_new_i64();
1979 tcg_gen_not_i64(t0
, arg2
);
1980 tcg_gen_or_i64(ret
, arg1
, t0
);
1981 tcg_temp_free_i64(t0
);
1984 tcg_gen_orc_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
), TCGV_LOW(arg2
));
1985 tcg_gen_orc_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
), TCGV_HIGH(arg2
));
1989 static inline void tcg_gen_rotl_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
1991 if (TCG_TARGET_HAS_rot_i32
) {
1992 tcg_gen_op3_i32(INDEX_op_rotl_i32
, ret
, arg1
, arg2
);
1996 t0
= tcg_temp_new_i32();
1997 t1
= tcg_temp_new_i32();
1998 tcg_gen_shl_i32(t0
, arg1
, arg2
);
1999 tcg_gen_subfi_i32(t1
, 32, arg2
);
2000 tcg_gen_shr_i32(t1
, arg1
, t1
);
2001 tcg_gen_or_i32(ret
, t0
, t1
);
2002 tcg_temp_free_i32(t0
);
2003 tcg_temp_free_i32(t1
);
2007 static inline void tcg_gen_rotl_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2009 if (TCG_TARGET_HAS_rot_i64
) {
2010 tcg_gen_op3_i64(INDEX_op_rotl_i64
, ret
, arg1
, arg2
);
2013 t0
= tcg_temp_new_i64();
2014 t1
= tcg_temp_new_i64();
2015 tcg_gen_shl_i64(t0
, arg1
, arg2
);
2016 tcg_gen_subfi_i64(t1
, 64, arg2
);
2017 tcg_gen_shr_i64(t1
, arg1
, t1
);
2018 tcg_gen_or_i64(ret
, t0
, t1
);
2019 tcg_temp_free_i64(t0
);
2020 tcg_temp_free_i64(t1
);
2024 static inline void tcg_gen_rotli_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
2026 /* some cases can be optimized here */
2028 tcg_gen_mov_i32(ret
, arg1
);
2029 } else if (TCG_TARGET_HAS_rot_i32
) {
2030 TCGv_i32 t0
= tcg_const_i32(arg2
);
2031 tcg_gen_rotl_i32(ret
, arg1
, t0
);
2032 tcg_temp_free_i32(t0
);
2035 t0
= tcg_temp_new_i32();
2036 t1
= tcg_temp_new_i32();
2037 tcg_gen_shli_i32(t0
, arg1
, arg2
);
2038 tcg_gen_shri_i32(t1
, arg1
, 32 - arg2
);
2039 tcg_gen_or_i32(ret
, t0
, t1
);
2040 tcg_temp_free_i32(t0
);
2041 tcg_temp_free_i32(t1
);
2045 static inline void tcg_gen_rotli_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
2047 /* some cases can be optimized here */
2049 tcg_gen_mov_i64(ret
, arg1
);
2050 } else if (TCG_TARGET_HAS_rot_i64
) {
2051 TCGv_i64 t0
= tcg_const_i64(arg2
);
2052 tcg_gen_rotl_i64(ret
, arg1
, t0
);
2053 tcg_temp_free_i64(t0
);
2056 t0
= tcg_temp_new_i64();
2057 t1
= tcg_temp_new_i64();
2058 tcg_gen_shli_i64(t0
, arg1
, arg2
);
2059 tcg_gen_shri_i64(t1
, arg1
, 64 - arg2
);
2060 tcg_gen_or_i64(ret
, t0
, t1
);
2061 tcg_temp_free_i64(t0
);
2062 tcg_temp_free_i64(t1
);
2066 static inline void tcg_gen_rotr_i32(TCGv_i32 ret
, TCGv_i32 arg1
, TCGv_i32 arg2
)
2068 if (TCG_TARGET_HAS_rot_i32
) {
2069 tcg_gen_op3_i32(INDEX_op_rotr_i32
, ret
, arg1
, arg2
);
2073 t0
= tcg_temp_new_i32();
2074 t1
= tcg_temp_new_i32();
2075 tcg_gen_shr_i32(t0
, arg1
, arg2
);
2076 tcg_gen_subfi_i32(t1
, 32, arg2
);
2077 tcg_gen_shl_i32(t1
, arg1
, t1
);
2078 tcg_gen_or_i32(ret
, t0
, t1
);
2079 tcg_temp_free_i32(t0
);
2080 tcg_temp_free_i32(t1
);
2084 static inline void tcg_gen_rotr_i64(TCGv_i64 ret
, TCGv_i64 arg1
, TCGv_i64 arg2
)
2086 if (TCG_TARGET_HAS_rot_i64
) {
2087 tcg_gen_op3_i64(INDEX_op_rotr_i64
, ret
, arg1
, arg2
);
2090 t0
= tcg_temp_new_i64();
2091 t1
= tcg_temp_new_i64();
2092 tcg_gen_shr_i64(t0
, arg1
, arg2
);
2093 tcg_gen_subfi_i64(t1
, 64, arg2
);
2094 tcg_gen_shl_i64(t1
, arg1
, t1
);
2095 tcg_gen_or_i64(ret
, t0
, t1
);
2096 tcg_temp_free_i64(t0
);
2097 tcg_temp_free_i64(t1
);
2101 static inline void tcg_gen_rotri_i32(TCGv_i32 ret
, TCGv_i32 arg1
, int32_t arg2
)
2103 /* some cases can be optimized here */
2105 tcg_gen_mov_i32(ret
, arg1
);
2107 tcg_gen_rotli_i32(ret
, arg1
, 32 - arg2
);
2111 static inline void tcg_gen_rotri_i64(TCGv_i64 ret
, TCGv_i64 arg1
, int64_t arg2
)
2113 /* some cases can be optimized here */
2115 tcg_gen_mov_i64(ret
, arg1
);
2117 tcg_gen_rotli_i64(ret
, arg1
, 64 - arg2
);
2121 static inline void tcg_gen_deposit_i32(TCGv_i32 ret
, TCGv_i32 arg1
,
2122 TCGv_i32 arg2
, unsigned int ofs
,
2128 tcg_debug_assert(ofs
< 32);
2129 tcg_debug_assert(len
<= 32);
2130 tcg_debug_assert(ofs
+ len
<= 32);
2132 if (ofs
== 0 && len
== 32) {
2133 tcg_gen_mov_i32(ret
, arg2
);
2136 if (TCG_TARGET_HAS_deposit_i32
&& TCG_TARGET_deposit_i32_valid(ofs
, len
)) {
2137 tcg_gen_op5ii_i32(INDEX_op_deposit_i32
, ret
, arg1
, arg2
, ofs
, len
);
2141 mask
= (1u << len
) - 1;
2142 t1
= tcg_temp_new_i32();
2144 if (ofs
+ len
< 32) {
2145 tcg_gen_andi_i32(t1
, arg2
, mask
);
2146 tcg_gen_shli_i32(t1
, t1
, ofs
);
2148 tcg_gen_shli_i32(t1
, arg2
, ofs
);
2150 tcg_gen_andi_i32(ret
, arg1
, ~(mask
<< ofs
));
2151 tcg_gen_or_i32(ret
, ret
, t1
);
2153 tcg_temp_free_i32(t1
);
2156 static inline void tcg_gen_deposit_i64(TCGv_i64 ret
, TCGv_i64 arg1
,
2157 TCGv_i64 arg2
, unsigned int ofs
,
2163 tcg_debug_assert(ofs
< 64);
2164 tcg_debug_assert(len
<= 64);
2165 tcg_debug_assert(ofs
+ len
<= 64);
2167 if (ofs
== 0 && len
== 64) {
2168 tcg_gen_mov_i64(ret
, arg2
);
2171 if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(ofs
, len
)) {
2172 tcg_gen_op5ii_i64(INDEX_op_deposit_i64
, ret
, arg1
, arg2
, ofs
, len
);
2176 #if TCG_TARGET_REG_BITS == 32
2178 tcg_gen_mov_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
));
2179 tcg_gen_deposit_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
),
2180 TCGV_LOW(arg2
), ofs
- 32, len
);
2183 if (ofs
+ len
<= 32) {
2184 tcg_gen_deposit_i32(TCGV_LOW(ret
), TCGV_LOW(arg1
),
2185 TCGV_LOW(arg2
), ofs
, len
);
2186 tcg_gen_mov_i32(TCGV_HIGH(ret
), TCGV_HIGH(arg1
));
2191 mask
= (1ull << len
) - 1;
2192 t1
= tcg_temp_new_i64();
2194 if (ofs
+ len
< 64) {
2195 tcg_gen_andi_i64(t1
, arg2
, mask
);
2196 tcg_gen_shli_i64(t1
, t1
, ofs
);
2198 tcg_gen_shli_i64(t1
, arg2
, ofs
);
2200 tcg_gen_andi_i64(ret
, arg1
, ~(mask
<< ofs
));
2201 tcg_gen_or_i64(ret
, ret
, t1
);
2203 tcg_temp_free_i64(t1
);
2206 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest
, TCGv_i32 low
,
2209 #if TCG_TARGET_REG_BITS == 32
2210 tcg_gen_mov_i32(TCGV_LOW(dest
), low
);
2211 tcg_gen_mov_i32(TCGV_HIGH(dest
), high
);
2213 TCGv_i64 tmp
= tcg_temp_new_i64();
2214 /* These extensions are only needed for type correctness.
2215 We may be able to do better given target specific information. */
2216 tcg_gen_extu_i32_i64(tmp
, high
);
2217 tcg_gen_extu_i32_i64(dest
, low
);
2218 /* If deposit is available, use it. Otherwise use the extra
2219 knowledge that we have of the zero-extensions above. */
2220 if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(32, 32)) {
2221 tcg_gen_deposit_i64(dest
, dest
, tmp
, 32, 32);
2223 tcg_gen_shli_i64(tmp
, tmp
, 32);
2224 tcg_gen_or_i64(dest
, dest
, tmp
);
2226 tcg_temp_free_i64(tmp
);
2230 static inline void tcg_gen_concat32_i64(TCGv_i64 dest
, TCGv_i64 low
,
2233 tcg_gen_deposit_i64(dest
, low
, high
, 32, 32);
2236 static inline void tcg_gen_movcond_i32(TCGCond cond
, TCGv_i32 ret
,
2237 TCGv_i32 c1
, TCGv_i32 c2
,
2238 TCGv_i32 v1
, TCGv_i32 v2
)
2240 if (TCG_TARGET_HAS_movcond_i32
) {
2241 tcg_gen_op6i_i32(INDEX_op_movcond_i32
, ret
, c1
, c2
, v1
, v2
, cond
);
2243 TCGv_i32 t0
= tcg_temp_new_i32();
2244 TCGv_i32 t1
= tcg_temp_new_i32();
2245 tcg_gen_setcond_i32(cond
, t0
, c1
, c2
);
2246 tcg_gen_neg_i32(t0
, t0
);
2247 tcg_gen_and_i32(t1
, v1
, t0
);
2248 tcg_gen_andc_i32(ret
, v2
, t0
);
2249 tcg_gen_or_i32(ret
, ret
, t1
);
2250 tcg_temp_free_i32(t0
);
2251 tcg_temp_free_i32(t1
);
2255 static inline void tcg_gen_movcond_i64(TCGCond cond
, TCGv_i64 ret
,
2256 TCGv_i64 c1
, TCGv_i64 c2
,
2257 TCGv_i64 v1
, TCGv_i64 v2
)
2259 #if TCG_TARGET_REG_BITS == 32
2260 TCGv_i32 t0
= tcg_temp_new_i32();
2261 TCGv_i32 t1
= tcg_temp_new_i32();
2262 tcg_gen_op6i_i32(INDEX_op_setcond2_i32
, t0
,
2263 TCGV_LOW(c1
), TCGV_HIGH(c1
),
2264 TCGV_LOW(c2
), TCGV_HIGH(c2
), cond
);
2266 if (TCG_TARGET_HAS_movcond_i32
) {
2267 tcg_gen_movi_i32(t1
, 0);
2268 tcg_gen_movcond_i32(TCG_COND_NE
, TCGV_LOW(ret
), t0
, t1
,
2269 TCGV_LOW(v1
), TCGV_LOW(v2
));
2270 tcg_gen_movcond_i32(TCG_COND_NE
, TCGV_HIGH(ret
), t0
, t1
,
2271 TCGV_HIGH(v1
), TCGV_HIGH(v2
));
2273 tcg_gen_neg_i32(t0
, t0
);
2275 tcg_gen_and_i32(t1
, TCGV_LOW(v1
), t0
);
2276 tcg_gen_andc_i32(TCGV_LOW(ret
), TCGV_LOW(v2
), t0
);
2277 tcg_gen_or_i32(TCGV_LOW(ret
), TCGV_LOW(ret
), t1
);
2279 tcg_gen_and_i32(t1
, TCGV_HIGH(v1
), t0
);
2280 tcg_gen_andc_i32(TCGV_HIGH(ret
), TCGV_HIGH(v2
), t0
);
2281 tcg_gen_or_i32(TCGV_HIGH(ret
), TCGV_HIGH(ret
), t1
);
2283 tcg_temp_free_i32(t0
);
2284 tcg_temp_free_i32(t1
);
2286 if (TCG_TARGET_HAS_movcond_i64
) {
2287 tcg_gen_op6i_i64(INDEX_op_movcond_i64
, ret
, c1
, c2
, v1
, v2
, cond
);
2289 TCGv_i64 t0
= tcg_temp_new_i64();
2290 TCGv_i64 t1
= tcg_temp_new_i64();
2291 tcg_gen_setcond_i64(cond
, t0
, c1
, c2
);
2292 tcg_gen_neg_i64(t0
, t0
);
2293 tcg_gen_and_i64(t1
, v1
, t0
);
2294 tcg_gen_andc_i64(ret
, v2
, t0
);
2295 tcg_gen_or_i64(ret
, ret
, t1
);
2296 tcg_temp_free_i64(t0
);
2297 tcg_temp_free_i64(t1
);
2302 /***************************************/
2303 /* QEMU specific operations. Their type depend on the QEMU CPU
2305 #ifndef TARGET_LONG_BITS
2306 #error must include QEMU headers
2309 #if TARGET_LONG_BITS == 32
2310 #define TCGv TCGv_i32
2311 #define tcg_temp_new() tcg_temp_new_i32()
2312 #define tcg_global_reg_new tcg_global_reg_new_i32
2313 #define tcg_global_mem_new tcg_global_mem_new_i32
2314 #define tcg_temp_local_new() tcg_temp_local_new_i32()
2315 #define tcg_temp_free tcg_temp_free_i32
2316 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2317 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2318 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2319 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2321 #define TCGv TCGv_i64
2322 #define tcg_temp_new() tcg_temp_new_i64()
2323 #define tcg_global_reg_new tcg_global_reg_new_i64
2324 #define tcg_global_mem_new tcg_global_mem_new_i64
2325 #define tcg_temp_local_new() tcg_temp_local_new_i64()
2326 #define tcg_temp_free tcg_temp_free_i64
2327 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2328 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2329 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2330 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2333 /* debug info: write the PC of the corresponding QEMU CPU instruction */
2334 static inline void tcg_gen_debug_insn_start(uint64_t pc
)
2336 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2337 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2338 tcg_gen_op2ii(INDEX_op_debug_insn_start
,
2339 (uint32_t)(pc
), (uint32_t)(pc
>> 32));
2341 tcg_gen_op1i(INDEX_op_debug_insn_start
, pc
);
2345 static inline void tcg_gen_exit_tb(tcg_target_long val
)
2347 tcg_gen_op1i(INDEX_op_exit_tb
, val
);
2350 static inline void tcg_gen_goto_tb(unsigned idx
)
2352 /* We only support two chained exits. */
2353 tcg_debug_assert(idx
<= 1);
2354 #ifdef CONFIG_DEBUG_TCG
2355 /* Verify that we havn't seen this numbered exit before. */
2356 tcg_debug_assert((tcg_ctx
.goto_tb_issue_mask
& (1 << idx
)) == 0);
2357 tcg_ctx
.goto_tb_issue_mask
|= 1 << idx
;
2359 tcg_gen_op1i(INDEX_op_goto_tb
, idx
);
2362 #if TCG_TARGET_REG_BITS == 32
2363 static inline void tcg_gen_qemu_ld8u(TCGv ret
, TCGv addr
, int mem_index
)
2365 #if TARGET_LONG_BITS == 32
2366 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u
, ret
, addr
, mem_index
);
2368 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2369 TCGV_HIGH(addr
), mem_index
);
2370 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
2374 static inline void tcg_gen_qemu_ld8s(TCGv ret
, TCGv addr
, int mem_index
)
2376 #if TARGET_LONG_BITS == 32
2377 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s
, ret
, addr
, mem_index
);
2379 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2380 TCGV_HIGH(addr
), mem_index
);
2381 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
2385 static inline void tcg_gen_qemu_ld16u(TCGv ret
, TCGv addr
, int mem_index
)
2387 #if TARGET_LONG_BITS == 32
2388 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u
, ret
, addr
, mem_index
);
2390 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2391 TCGV_HIGH(addr
), mem_index
);
2392 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
2396 static inline void tcg_gen_qemu_ld16s(TCGv ret
, TCGv addr
, int mem_index
)
2398 #if TARGET_LONG_BITS == 32
2399 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s
, ret
, addr
, mem_index
);
2401 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2402 TCGV_HIGH(addr
), mem_index
);
2403 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
2407 static inline void tcg_gen_qemu_ld32u(TCGv ret
, TCGv addr
, int mem_index
)
2409 #if TARGET_LONG_BITS == 32
2410 tcg_gen_op3i_i32(INDEX_op_qemu_ld32
, ret
, addr
, mem_index
);
2412 tcg_gen_op4i_i32(INDEX_op_qemu_ld32
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2413 TCGV_HIGH(addr
), mem_index
);
2414 tcg_gen_movi_i32(TCGV_HIGH(ret
), 0);
2418 static inline void tcg_gen_qemu_ld32s(TCGv ret
, TCGv addr
, int mem_index
)
2420 #if TARGET_LONG_BITS == 32
2421 tcg_gen_op3i_i32(INDEX_op_qemu_ld32
, ret
, addr
, mem_index
);
2423 tcg_gen_op4i_i32(INDEX_op_qemu_ld32
, TCGV_LOW(ret
), TCGV_LOW(addr
),
2424 TCGV_HIGH(addr
), mem_index
);
2425 tcg_gen_sari_i32(TCGV_HIGH(ret
), TCGV_LOW(ret
), 31);
2429 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret
, TCGv addr
, int mem_index
)
2431 #if TARGET_LONG_BITS == 32
2432 tcg_gen_op4i_i32(INDEX_op_qemu_ld64
, TCGV_LOW(ret
), TCGV_HIGH(ret
), addr
, mem_index
);
2434 tcg_gen_op5i_i32(INDEX_op_qemu_ld64
, TCGV_LOW(ret
), TCGV_HIGH(ret
),
2435 TCGV_LOW(addr
), TCGV_HIGH(addr
), mem_index
);
2439 static inline void tcg_gen_qemu_st8(TCGv arg
, TCGv addr
, int mem_index
)
2441 #if TARGET_LONG_BITS == 32
2442 tcg_gen_op3i_i32(INDEX_op_qemu_st8
, arg
, addr
, mem_index
);
2444 tcg_gen_op4i_i32(INDEX_op_qemu_st8
, TCGV_LOW(arg
), TCGV_LOW(addr
),
2445 TCGV_HIGH(addr
), mem_index
);
2449 static inline void tcg_gen_qemu_st16(TCGv arg
, TCGv addr
, int mem_index
)
2451 #if TARGET_LONG_BITS == 32
2452 tcg_gen_op3i_i32(INDEX_op_qemu_st16
, arg
, addr
, mem_index
);
2454 tcg_gen_op4i_i32(INDEX_op_qemu_st16
, TCGV_LOW(arg
), TCGV_LOW(addr
),
2455 TCGV_HIGH(addr
), mem_index
);
2459 static inline void tcg_gen_qemu_st32(TCGv arg
, TCGv addr
, int mem_index
)
2461 #if TARGET_LONG_BITS == 32
2462 tcg_gen_op3i_i32(INDEX_op_qemu_st32
, arg
, addr
, mem_index
);
2464 tcg_gen_op4i_i32(INDEX_op_qemu_st32
, TCGV_LOW(arg
), TCGV_LOW(addr
),
2465 TCGV_HIGH(addr
), mem_index
);
2469 static inline void tcg_gen_qemu_st64(TCGv_i64 arg
, TCGv addr
, int mem_index
)
2471 #if TARGET_LONG_BITS == 32
2472 tcg_gen_op4i_i32(INDEX_op_qemu_st64
, TCGV_LOW(arg
), TCGV_HIGH(arg
), addr
,
2475 tcg_gen_op5i_i32(INDEX_op_qemu_st64
, TCGV_LOW(arg
), TCGV_HIGH(arg
),
2476 TCGV_LOW(addr
), TCGV_HIGH(addr
), mem_index
);
2480 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2481 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2483 #else /* TCG_TARGET_REG_BITS == 32 */
2485 static inline void tcg_gen_qemu_ld8u(TCGv ret
, TCGv addr
, int mem_index
)
2487 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u
, ret
, addr
, mem_index
);
2490 static inline void tcg_gen_qemu_ld8s(TCGv ret
, TCGv addr
, int mem_index
)
2492 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s
, ret
, addr
, mem_index
);
2495 static inline void tcg_gen_qemu_ld16u(TCGv ret
, TCGv addr
, int mem_index
)
2497 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u
, ret
, addr
, mem_index
);
2500 static inline void tcg_gen_qemu_ld16s(TCGv ret
, TCGv addr
, int mem_index
)
2502 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s
, ret
, addr
, mem_index
);
2505 static inline void tcg_gen_qemu_ld32u(TCGv ret
, TCGv addr
, int mem_index
)
2507 #if TARGET_LONG_BITS == 32
2508 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32
, ret
, addr
, mem_index
);
2510 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u
, ret
, addr
, mem_index
);
2514 static inline void tcg_gen_qemu_ld32s(TCGv ret
, TCGv addr
, int mem_index
)
2516 #if TARGET_LONG_BITS == 32
2517 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32
, ret
, addr
, mem_index
);
2519 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s
, ret
, addr
, mem_index
);
2523 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret
, TCGv addr
, int mem_index
)
2525 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64
, ret
, addr
, mem_index
);
2528 static inline void tcg_gen_qemu_st8(TCGv arg
, TCGv addr
, int mem_index
)
2530 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8
, arg
, addr
, mem_index
);
2533 static inline void tcg_gen_qemu_st16(TCGv arg
, TCGv addr
, int mem_index
)
2535 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16
, arg
, addr
, mem_index
);
2538 static inline void tcg_gen_qemu_st32(TCGv arg
, TCGv addr
, int mem_index
)
2540 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32
, arg
, addr
, mem_index
);
2543 static inline void tcg_gen_qemu_st64(TCGv_i64 arg
, TCGv addr
, int mem_index
)
2545 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64
, arg
, addr
, mem_index
);
2548 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2549 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2551 #endif /* TCG_TARGET_REG_BITS != 32 */
2553 #if TARGET_LONG_BITS == 64
2554 #define tcg_gen_movi_tl tcg_gen_movi_i64
2555 #define tcg_gen_mov_tl tcg_gen_mov_i64
2556 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2557 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2558 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2559 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2560 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2561 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2562 #define tcg_gen_ld_tl tcg_gen_ld_i64
2563 #define tcg_gen_st8_tl tcg_gen_st8_i64
2564 #define tcg_gen_st16_tl tcg_gen_st16_i64
2565 #define tcg_gen_st32_tl tcg_gen_st32_i64
2566 #define tcg_gen_st_tl tcg_gen_st_i64
2567 #define tcg_gen_add_tl tcg_gen_add_i64
2568 #define tcg_gen_addi_tl tcg_gen_addi_i64
2569 #define tcg_gen_sub_tl tcg_gen_sub_i64
2570 #define tcg_gen_neg_tl tcg_gen_neg_i64
2571 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2572 #define tcg_gen_subi_tl tcg_gen_subi_i64
2573 #define tcg_gen_and_tl tcg_gen_and_i64
2574 #define tcg_gen_andi_tl tcg_gen_andi_i64
2575 #define tcg_gen_or_tl tcg_gen_or_i64
2576 #define tcg_gen_ori_tl tcg_gen_ori_i64
2577 #define tcg_gen_xor_tl tcg_gen_xor_i64
2578 #define tcg_gen_xori_tl tcg_gen_xori_i64
2579 #define tcg_gen_not_tl tcg_gen_not_i64
2580 #define tcg_gen_shl_tl tcg_gen_shl_i64
2581 #define tcg_gen_shli_tl tcg_gen_shli_i64
2582 #define tcg_gen_shr_tl tcg_gen_shr_i64
2583 #define tcg_gen_shri_tl tcg_gen_shri_i64
2584 #define tcg_gen_sar_tl tcg_gen_sar_i64
2585 #define tcg_gen_sari_tl tcg_gen_sari_i64
2586 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2587 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2588 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2589 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2590 #define tcg_gen_mul_tl tcg_gen_mul_i64
2591 #define tcg_gen_muli_tl tcg_gen_muli_i64
2592 #define tcg_gen_div_tl tcg_gen_div_i64
2593 #define tcg_gen_rem_tl tcg_gen_rem_i64
2594 #define tcg_gen_divu_tl tcg_gen_divu_i64
2595 #define tcg_gen_remu_tl tcg_gen_remu_i64
2596 #define tcg_gen_discard_tl tcg_gen_discard_i64
2597 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2598 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2599 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2600 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2601 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2602 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2603 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2604 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2605 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2606 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2607 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2608 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2609 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2610 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2611 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2612 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2613 #define tcg_gen_andc_tl tcg_gen_andc_i64
2614 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2615 #define tcg_gen_nand_tl tcg_gen_nand_i64
2616 #define tcg_gen_nor_tl tcg_gen_nor_i64
2617 #define tcg_gen_orc_tl tcg_gen_orc_i64
2618 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2619 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2620 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2621 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2622 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
2623 #define tcg_const_tl tcg_const_i64
2624 #define tcg_const_local_tl tcg_const_local_i64
2625 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
2627 #define tcg_gen_movi_tl tcg_gen_movi_i32
2628 #define tcg_gen_mov_tl tcg_gen_mov_i32
2629 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2630 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2631 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2632 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2633 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2634 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2635 #define tcg_gen_ld_tl tcg_gen_ld_i32
2636 #define tcg_gen_st8_tl tcg_gen_st8_i32
2637 #define tcg_gen_st16_tl tcg_gen_st16_i32
2638 #define tcg_gen_st32_tl tcg_gen_st_i32
2639 #define tcg_gen_st_tl tcg_gen_st_i32
2640 #define tcg_gen_add_tl tcg_gen_add_i32
2641 #define tcg_gen_addi_tl tcg_gen_addi_i32
2642 #define tcg_gen_sub_tl tcg_gen_sub_i32
2643 #define tcg_gen_neg_tl tcg_gen_neg_i32
2644 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2645 #define tcg_gen_subi_tl tcg_gen_subi_i32
2646 #define tcg_gen_and_tl tcg_gen_and_i32
2647 #define tcg_gen_andi_tl tcg_gen_andi_i32
2648 #define tcg_gen_or_tl tcg_gen_or_i32
2649 #define tcg_gen_ori_tl tcg_gen_ori_i32
2650 #define tcg_gen_xor_tl tcg_gen_xor_i32
2651 #define tcg_gen_xori_tl tcg_gen_xori_i32
2652 #define tcg_gen_not_tl tcg_gen_not_i32
2653 #define tcg_gen_shl_tl tcg_gen_shl_i32
2654 #define tcg_gen_shli_tl tcg_gen_shli_i32
2655 #define tcg_gen_shr_tl tcg_gen_shr_i32
2656 #define tcg_gen_shri_tl tcg_gen_shri_i32
2657 #define tcg_gen_sar_tl tcg_gen_sar_i32
2658 #define tcg_gen_sari_tl tcg_gen_sari_i32
2659 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2660 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2661 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2662 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2663 #define tcg_gen_mul_tl tcg_gen_mul_i32
2664 #define tcg_gen_muli_tl tcg_gen_muli_i32
2665 #define tcg_gen_div_tl tcg_gen_div_i32
2666 #define tcg_gen_rem_tl tcg_gen_rem_i32
2667 #define tcg_gen_divu_tl tcg_gen_divu_i32
2668 #define tcg_gen_remu_tl tcg_gen_remu_i32
2669 #define tcg_gen_discard_tl tcg_gen_discard_i32
2670 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2671 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2672 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2673 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2674 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2675 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2676 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2677 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2678 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2679 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2680 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2681 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2682 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2683 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2684 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2685 #define tcg_gen_andc_tl tcg_gen_andc_i32
2686 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2687 #define tcg_gen_nand_tl tcg_gen_nand_i32
2688 #define tcg_gen_nor_tl tcg_gen_nor_i32
2689 #define tcg_gen_orc_tl tcg_gen_orc_i32
2690 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2691 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2692 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2693 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2694 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
2695 #define tcg_const_tl tcg_const_i32
2696 #define tcg_const_local_tl tcg_const_local_i32
2697 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
2700 #if TCG_TARGET_REG_BITS == 32
2701 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2702 TCGV_PTR_TO_NAT(A), \
2704 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2705 TCGV_PTR_TO_NAT(A), (B))
2706 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2707 #else /* TCG_TARGET_REG_BITS == 32 */
2708 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2709 TCGV_PTR_TO_NAT(A), \
2711 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
2712 TCGV_PTR_TO_NAT(A), (B))
2713 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2714 #endif /* TCG_TARGET_REG_BITS != 32 */