4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/pci/pci_bridge.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pcie_regs.h"
30 #include "qemu/range.h"
34 # define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
39 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
43 /***************************************************************************
44 * pci express capability helper functions
48 pcie_cap_v1_fill(uint8_t *exp_cap
, uint8_t port
, uint8_t type
, uint8_t version
)
50 /* capability register
51 interrupt message number defaults to 0 */
52 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
53 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
56 /* device capability register
58 * roll based error reporting bit must be set by all
59 * Functions conforming to the ECN, PCI Express Base
60 * Specification, Revision 1.1., or subsequent PCI Express Base
61 * Specification revisions.
63 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
65 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
66 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
67 PCI_EXP_LNKCAP_ASPMS_0S
|
71 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
72 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
|PCI_EXP_LNKSTA_DLLLA
);
75 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
, uint8_t port
)
77 /* PCIe cap v2 init */
81 assert(pci_is_express(dev
));
83 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
, PCI_EXP_VER2_SIZEOF
);
87 dev
->exp
.exp_cap
= pos
;
88 exp_cap
= dev
->config
+ pos
;
90 /* Filling values common with v1 */
91 pcie_cap_v1_fill(exp_cap
, port
, type
, PCI_EXP_FLAGS_VER2
);
93 /* Filling v2 specific values */
94 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
95 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
97 pci_set_word(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
, PCI_EXP_DEVCTL2_EETLPPB
);
101 int pcie_cap_v1_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
,
104 /* PCIe cap v1 init */
108 assert(pci_is_express(dev
));
110 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
, PCI_EXP_VER1_SIZEOF
);
114 dev
->exp
.exp_cap
= pos
;
115 exp_cap
= dev
->config
+ pos
;
117 pcie_cap_v1_fill(exp_cap
, port
, type
, PCI_EXP_FLAGS_VER1
);
123 pcie_endpoint_cap_common_init(PCIDevice
*dev
, uint8_t offset
, uint8_t cap_size
)
125 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
128 * Windows guests will report Code 10, device cannot start, if
129 * a regular Endpoint type is exposed on a root complex. These
130 * should instead be Root Complex Integrated Endpoints.
132 if (pci_bus_is_express(dev
->bus
) && pci_bus_is_root(dev
->bus
)) {
133 type
= PCI_EXP_TYPE_RC_END
;
136 return (cap_size
== PCI_EXP_VER1_SIZEOF
)
137 ? pcie_cap_v1_init(dev
, offset
, type
, 0)
138 : pcie_cap_init(dev
, offset
, type
, 0);
141 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
143 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER2_SIZEOF
);
146 int pcie_endpoint_cap_v1_init(PCIDevice
*dev
, uint8_t offset
)
148 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER1_SIZEOF
);
151 void pcie_cap_exit(PCIDevice
*dev
)
153 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
156 void pcie_cap_v1_exit(PCIDevice
*dev
)
158 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER1_SIZEOF
);
161 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
163 uint32_t pos
= dev
->exp
.exp_cap
;
165 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
166 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
170 /* pci express interrupt message number */
171 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
172 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
174 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
176 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
177 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
178 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
181 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
183 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
184 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
187 void pcie_cap_deverr_init(PCIDevice
*dev
)
189 uint32_t pos
= dev
->exp
.exp_cap
;
190 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
191 PCI_EXP_DEVCAP_RBER
);
192 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
193 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
194 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
195 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
196 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
197 PCI_EXP_DEVSTA_FED
| PCI_EXP_DEVSTA_URD
);
200 void pcie_cap_deverr_reset(PCIDevice
*dev
)
202 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
203 pci_long_test_and_clear_mask(devctl
,
204 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
205 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
208 static void hotplug_event_update_event_status(PCIDevice
*dev
)
210 uint32_t pos
= dev
->exp
.exp_cap
;
211 uint8_t *exp_cap
= dev
->config
+ pos
;
212 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
213 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
215 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
216 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
219 static void hotplug_event_notify(PCIDevice
*dev
)
221 bool prev
= dev
->exp
.hpev_notified
;
223 hotplug_event_update_event_status(dev
);
225 if (prev
== dev
->exp
.hpev_notified
) {
229 /* Note: the logic above does not take into account whether interrupts
230 * are masked. The result is that interrupt will be sent when it is
231 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
232 * The Port may optionally send an MSI when there are hot-plug events that
233 * occur while interrupt generation is disabled, and interrupt generation is
234 * subsequently enabled. */
235 if (msix_enabled(dev
)) {
236 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
237 } else if (msi_enabled(dev
)) {
238 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
240 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
244 static void hotplug_event_clear(PCIDevice
*dev
)
246 hotplug_event_update_event_status(dev
);
247 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
248 pci_irq_deassert(dev
);
253 * A PCI Express Hot-Plug Event has occurred, so update slot status register
254 * and notify OS of the event if necessary.
256 * 6.7.3 PCI Express Hot-Plug Events
257 * 6.7.3.4 Software Notification of Hot-Plug Events
259 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
261 /* Minor optimization: if nothing changed - no event is needed. */
262 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
263 PCI_EXP_SLTSTA
, event
)) {
266 hotplug_event_notify(dev
);
269 static void pcie_cap_slot_hotplug_common(PCIDevice
*hotplug_dev
,
271 uint8_t **exp_cap
, Error
**errp
)
273 *exp_cap
= hotplug_dev
->config
+ hotplug_dev
->exp
.exp_cap
;
274 uint16_t sltsta
= pci_get_word(*exp_cap
+ PCI_EXP_SLTSTA
);
276 PCIE_DEV_PRINTF(PCI_DEVICE(dev
), "hotplug state: 0x%x\n", sltsta
);
277 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
278 /* the slot is electromechanically locked.
279 * This error is propagated up to qdev and then to HMP/QMP.
281 error_setg_errno(errp
, EBUSY
, "slot is electromechanically locked");
285 void pcie_cap_slot_hotplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
289 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
291 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
293 /* Don't send event when device is enabled during qemu machine creation:
294 * it is present on boot, no hotplug event is necessary. We do send an
295 * event when the device is disabled later. */
296 if (!dev
->hotplugged
) {
297 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
302 /* To enable multifunction hot-plug, we just ensure the function
303 * 0 added last. When function 0 is added, we set the sltsta and
304 * inform OS via event notification.
306 if (pci_get_function_0(pci_dev
)) {
307 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
309 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev
),
310 PCI_EXP_HP_EV_PDC
| PCI_EXP_HP_EV_ABP
);
314 static void pcie_unplug_device(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
316 object_unparent(OBJECT(dev
));
319 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler
*hotplug_dev
,
320 DeviceState
*dev
, Error
**errp
)
323 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
324 PCIBus
*bus
= pci_dev
->bus
;
326 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
328 /* In case user cancel the operation of multi-function hot-add,
329 * remove the function that is unexposed to guest individually,
330 * without interaction with guest.
332 if (pci_dev
->devfn
&&
334 pcie_unplug_device(bus
, pci_dev
, NULL
);
339 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev
));
342 /* pci express slot for pci express root/downstream port
343 PCI express capability slot registers */
344 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
346 uint32_t pos
= dev
->exp
.exp_cap
;
348 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
351 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
352 ~PCI_EXP_SLTCAP_PSN
);
353 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
354 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
362 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
363 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
365 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
367 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
371 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
374 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
375 PCI_EXP_SLTCTL_PIC_OFF
|
376 PCI_EXP_SLTCTL_AIC_OFF
);
377 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
380 PCI_EXP_SLTCTL_HPIE
|
381 PCI_EXP_SLTCTL_CCIE
|
382 PCI_EXP_SLTCTL_PDCE
|
383 PCI_EXP_SLTCTL_ABPE
);
384 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
385 * make the bit writable here in order to detect 1b is written.
386 * pcie_cap_slot_write_config() test-and-clear the bit, so
387 * this bit always returns 0 to the guest.
389 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
392 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
393 PCI_EXP_HP_EV_SUPPORTED
);
395 dev
->exp
.hpev_notified
= false;
397 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))),
401 void pcie_cap_slot_reset(PCIDevice
*dev
)
403 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
404 uint8_t port_type
= pcie_cap_get_type(dev
);
406 assert(port_type
== PCI_EXP_TYPE_DOWNSTREAM
||
407 port_type
== PCI_EXP_TYPE_ROOT_PORT
);
409 PCIE_DEV_PRINTF(dev
, "reset\n");
411 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
415 PCI_EXP_SLTCTL_HPIE
|
416 PCI_EXP_SLTCTL_CCIE
|
417 PCI_EXP_SLTCTL_PDCE
|
418 PCI_EXP_SLTCTL_ABPE
);
419 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
420 PCI_EXP_SLTCTL_AIC_OFF
);
422 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
423 /* Downstream ports enforce device number 0. */
424 bool populated
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))->devices
[0];
428 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
431 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
435 pic
= populated
? PCI_EXP_SLTCTL_PIC_ON
: PCI_EXP_SLTCTL_PIC_OFF
;
436 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
, pic
);
439 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
440 PCI_EXP_SLTSTA_EIS
|/* on reset,
441 the lock is released */
446 hotplug_event_update_event_status(dev
);
449 void pcie_cap_slot_write_config(PCIDevice
*dev
,
450 uint32_t addr
, uint32_t val
, int len
)
452 uint32_t pos
= dev
->exp
.exp_cap
;
453 uint8_t *exp_cap
= dev
->config
+ pos
;
454 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
456 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
457 hotplug_event_clear(dev
);
460 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
464 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
465 PCI_EXP_SLTCTL_EIC
)) {
466 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
467 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
468 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
469 "sltsta -> 0x%02"PRIx16
"\n",
474 * If the slot is polulated, power indicator is off and power
475 * controller is off, it is safe to detach the devices.
477 if ((sltsta
& PCI_EXP_SLTSTA_PDS
) && (val
& PCI_EXP_SLTCTL_PCC
) &&
478 ((val
& PCI_EXP_SLTCTL_PIC_OFF
) == PCI_EXP_SLTCTL_PIC_OFF
)) {
479 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
480 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
481 pcie_unplug_device
, NULL
);
483 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
485 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
489 hotplug_event_notify(dev
);
492 * 6.7.3.2 Command Completed Events
494 * Software issues a command to a hot-plug capable Downstream Port by
495 * issuing a write transaction that targets any portion of the Port’s Slot
496 * Control register. A single write to the Slot Control register is
497 * considered to be a single command, even if the write affects more than
498 * one field in the Slot Control register. In response to this transaction,
499 * the Port must carry out the requested actions and then set the
500 * associated status field for the command completed event. */
502 /* Real hardware might take a while to complete requested command because
503 * physical movement would be involved like locking the electromechanical
504 * lock. However in our case, command is completed instantaneously above,
505 * so send a command completion event right now.
507 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
510 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
512 PCIDevice
*dev
= opaque
;
513 hotplug_event_update_event_status(dev
);
517 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
519 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
522 /* root control/capabilities/status. PME isn't emulated for now */
523 void pcie_cap_root_init(PCIDevice
*dev
)
525 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
526 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
527 PCI_EXP_RTCTL_SEFEE
);
530 void pcie_cap_root_reset(PCIDevice
*dev
)
532 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
535 /* function level reset(FLR) */
536 void pcie_cap_flr_init(PCIDevice
*dev
)
538 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
541 /* Although reading BCR_FLR returns always 0,
542 * the bit is made writable here in order to detect the 1b is written
543 * pcie_cap_flr_write_config() test-and-clear the bit, so
544 * this bit always returns 0 to the guest.
546 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
547 PCI_EXP_DEVCTL_BCR_FLR
);
550 void pcie_cap_flr_write_config(PCIDevice
*dev
,
551 uint32_t addr
, uint32_t val
, int len
)
553 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
554 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
555 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
556 so the handler can detect FLR by looking at this bit. */
557 pci_device_reset(dev
);
558 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
562 /* Alternative Routing-ID Interpretation (ARI)
563 * forwarding support for root and downstream ports
565 void pcie_cap_arifwd_init(PCIDevice
*dev
)
567 uint32_t pos
= dev
->exp
.exp_cap
;
568 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
569 PCI_EXP_DEVCAP2_ARI
);
570 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
571 PCI_EXP_DEVCTL2_ARI
);
574 void pcie_cap_arifwd_reset(PCIDevice
*dev
)
576 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
577 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
580 bool pcie_cap_is_arifwd_enabled(const PCIDevice
*dev
)
582 if (!pci_is_express(dev
)) {
585 if (!dev
->exp
.exp_cap
) {
589 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
593 /**************************************************************************
594 * pci express extended capability list management functions
595 * uint16_t ext_cap_id (16 bit)
596 * uint8_t cap_ver (4 bit)
597 * uint16_t cap_offset (12 bit)
598 * uint16_t ext_cap_size
601 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint16_t cap_id
,
606 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
609 /* no extended capability */
613 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
614 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
616 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
617 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
619 header
= pci_get_long(dev
->config
+ next
);
620 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
632 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
634 return pcie_find_capability_list(dev
, cap_id
, NULL
);
637 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
639 uint32_t header
= pci_get_long(dev
->config
+ pos
);
640 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
641 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
642 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
643 pci_set_long(dev
->config
+ pos
, header
);
647 * caller must supply valid (offset, size) * such that the range shouldn't
648 * overlap with other capability or other registers.
649 * This function doesn't check it.
651 void pcie_add_capability(PCIDevice
*dev
,
652 uint16_t cap_id
, uint8_t cap_ver
,
653 uint16_t offset
, uint16_t size
)
658 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
659 assert(offset
< offset
+ size
);
660 assert(offset
+ size
<= PCIE_CONFIG_SPACE_SIZE
);
662 assert(pci_is_express(dev
));
664 if (offset
== PCI_CONFIG_SPACE_SIZE
) {
665 header
= pci_get_long(dev
->config
+ offset
);
666 next
= PCI_EXT_CAP_NEXT(header
);
670 /* 0 is reserved cap id. use internally to find the last capability
671 in the linked list */
672 next
= pcie_find_capability_list(dev
, 0, &prev
);
674 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
676 pcie_ext_cap_set_next(dev
, prev
, offset
);
678 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, next
));
680 /* Make capability read-only by default */
681 memset(dev
->wmask
+ offset
, 0, size
);
682 memset(dev
->w1cmask
+ offset
, 0, size
);
683 /* Check capability by default */
684 memset(dev
->cmask
+ offset
, 0xFF, size
);
687 /**************************************************************************
688 * pci express extended capability helper functions
692 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
694 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
695 offset
, PCI_ARI_SIZEOF
);
696 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, (nextfn
& 0xff) << 8);
699 void pcie_dev_ser_num_init(PCIDevice
*dev
, uint16_t offset
, uint64_t ser_num
)
701 static const int pci_dsn_ver
= 1;
702 static const int pci_dsn_cap
= 4;
704 pcie_add_capability(dev
, PCI_EXT_CAP_ID_DSN
, pci_dsn_ver
, offset
,
705 PCI_EXT_CAP_DSN_SIZEOF
);
706 pci_set_quad(dev
->config
+ offset
+ pci_dsn_cap
, ser_num
);