4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
25 #include "translate.h"
26 #include "internals.h"
27 #include "qemu/host-utils.h"
29 #include "exec/semihost.h"
30 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
38 static TCGv_i64 cpu_X
[32];
39 static TCGv_i64 cpu_pc
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_high
;
44 static const char *regnames
[] = {
45 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
46 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
47 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
48 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
52 A64_SHIFT_TYPE_LSL
= 0,
53 A64_SHIFT_TYPE_LSR
= 1,
54 A64_SHIFT_TYPE_ASR
= 2,
55 A64_SHIFT_TYPE_ROR
= 3
58 /* Table based decoder typedefs - used when the relevant bits for decode
59 * are too awkwardly scattered across the instruction (eg SIMD).
61 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
63 typedef struct AArch64DecodeTable
{
66 AArch64DecodeFn
*disas_fn
;
69 /* Function prototype for gen_ functions for calling Neon helpers */
70 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
71 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
72 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
73 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
74 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
75 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
76 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
77 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
78 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
79 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
80 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
81 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
84 /* initialize TCG globals. */
85 void a64_translate_init(void)
89 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
90 offsetof(CPUARMState
, pc
),
92 for (i
= 0; i
< 32; i
++) {
93 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
94 offsetof(CPUARMState
, xregs
[i
]),
98 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
102 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
104 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
105 * if EL1, access as if EL0; otherwise access at current EL
107 switch (s
->mmu_idx
) {
108 case ARMMMUIdx_S12NSE1
:
109 return ARMMMUIdx_S12NSE0
;
110 case ARMMMUIdx_S1SE1
:
111 return ARMMMUIdx_S1SE0
;
113 g_assert_not_reached();
119 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
120 fprintf_function cpu_fprintf
, int flags
)
122 ARMCPU
*cpu
= ARM_CPU(cs
);
123 CPUARMState
*env
= &cpu
->env
;
124 uint32_t psr
= pstate_read(env
);
126 int el
= arm_current_el(env
);
127 const char *ns_status
;
129 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
130 env
->pc
, env
->xregs
[31]);
131 for (i
= 0; i
< 31; i
++) {
132 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
134 cpu_fprintf(f
, "\n");
140 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
141 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
146 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
148 psr
& PSTATE_N
? 'N' : '-',
149 psr
& PSTATE_Z
? 'Z' : '-',
150 psr
& PSTATE_C
? 'C' : '-',
151 psr
& PSTATE_V
? 'V' : '-',
154 psr
& PSTATE_SP
? 'h' : 't');
156 if (flags
& CPU_DUMP_FPU
) {
158 for (i
= 0; i
< numvfpregs
; i
+= 2) {
159 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
160 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
161 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
163 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
164 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
165 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
168 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
169 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
173 void gen_a64_set_pc_im(uint64_t val
)
175 tcg_gen_movi_i64(cpu_pc
, val
);
178 typedef struct DisasCompare64
{
183 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
187 arm_test_cc(&c32
, cc
);
189 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
190 * properly. The NE/EQ comparisons are also fine with this choice. */
191 c64
->cond
= c32
.cond
;
192 c64
->value
= tcg_temp_new_i64();
193 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
198 static void a64_free_cc(DisasCompare64
*c64
)
200 tcg_temp_free_i64(c64
->value
);
203 static void gen_exception_internal(int excp
)
205 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
207 assert(excp_is_internal(excp
));
208 gen_helper_exception_internal(cpu_env
, tcg_excp
);
209 tcg_temp_free_i32(tcg_excp
);
212 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
214 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
215 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
216 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
218 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
220 tcg_temp_free_i32(tcg_el
);
221 tcg_temp_free_i32(tcg_syn
);
222 tcg_temp_free_i32(tcg_excp
);
225 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
227 gen_a64_set_pc_im(s
->pc
- offset
);
228 gen_exception_internal(excp
);
229 s
->is_jmp
= DISAS_EXC
;
232 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
233 uint32_t syndrome
, uint32_t target_el
)
235 gen_a64_set_pc_im(s
->pc
- offset
);
236 gen_exception(excp
, syndrome
, target_el
);
237 s
->is_jmp
= DISAS_EXC
;
240 static void gen_ss_advance(DisasContext
*s
)
242 /* If the singlestep state is Active-not-pending, advance to
247 gen_helper_clear_pstate_ss(cpu_env
);
251 static void gen_step_complete_exception(DisasContext
*s
)
253 /* We just completed step of an insn. Move from Active-not-pending
254 * to Active-pending, and then also take the swstep exception.
255 * This corresponds to making the (IMPDEF) choice to prioritize
256 * swstep exceptions over asynchronous exceptions taken to an exception
257 * level where debug is disabled. This choice has the advantage that
258 * we do not need to maintain internal state corresponding to the
259 * ISV/EX syndrome bits between completion of the step and generation
260 * of the exception, and our syndrome information is always correct.
263 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
264 default_exception_el(s
));
265 s
->is_jmp
= DISAS_EXC
;
268 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
270 /* No direct tb linking with singlestep (either QEMU's or the ARM
271 * debug architecture kind) or deterministic io
273 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
277 /* Only link tbs from inside the same guest page */
278 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
285 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
287 TranslationBlock
*tb
;
290 if (use_goto_tb(s
, n
, dest
)) {
292 gen_a64_set_pc_im(dest
);
293 tcg_gen_exit_tb((intptr_t)tb
+ n
);
294 s
->is_jmp
= DISAS_TB_JUMP
;
296 gen_a64_set_pc_im(dest
);
298 gen_step_complete_exception(s
);
299 } else if (s
->singlestep_enabled
) {
300 gen_exception_internal(EXCP_DEBUG
);
303 s
->is_jmp
= DISAS_TB_JUMP
;
308 static void unallocated_encoding(DisasContext
*s
)
310 /* Unallocated and reserved encodings are uncategorized */
311 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
312 default_exception_el(s
));
315 #define unsupported_encoding(s, insn) \
317 qemu_log_mask(LOG_UNIMP, \
318 "%s:%d: unsupported instruction encoding 0x%08x " \
319 "at pc=%016" PRIx64 "\n", \
320 __FILE__, __LINE__, insn, s->pc - 4); \
321 unallocated_encoding(s); \
324 static void init_tmp_a64_array(DisasContext
*s
)
326 #ifdef CONFIG_DEBUG_TCG
328 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
329 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
332 s
->tmp_a64_count
= 0;
335 static void free_tmp_a64(DisasContext
*s
)
338 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
339 tcg_temp_free_i64(s
->tmp_a64
[i
]);
341 init_tmp_a64_array(s
);
344 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
346 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
347 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
350 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
352 TCGv_i64 t
= new_tmp_a64(s
);
353 tcg_gen_movi_i64(t
, 0);
358 * Register access functions
360 * These functions are used for directly accessing a register in where
361 * changes to the final register value are likely to be made. If you
362 * need to use a register for temporary calculation (e.g. index type
363 * operations) use the read_* form.
365 * B1.2.1 Register mappings
367 * In instruction register encoding 31 can refer to ZR (zero register) or
368 * the SP (stack pointer) depending on context. In QEMU's case we map SP
369 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
370 * This is the point of the _sp forms.
372 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
375 return new_tmp_a64_zero(s
);
381 /* register access for when 31 == SP */
382 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
387 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
388 * representing the register contents. This TCGv is an auto-freed
389 * temporary so it need not be explicitly freed, and may be modified.
391 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
393 TCGv_i64 v
= new_tmp_a64(s
);
396 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
398 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
401 tcg_gen_movi_i64(v
, 0);
406 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
408 TCGv_i64 v
= new_tmp_a64(s
);
410 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
412 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
417 /* We should have at some point before trying to access an FP register
418 * done the necessary access check, so assert that
419 * (a) we did the check and
420 * (b) we didn't then just plough ahead anyway if it failed.
421 * Print the instruction pattern in the abort message so we can figure
422 * out what we need to fix if a user encounters this problem in the wild.
424 static inline void assert_fp_access_checked(DisasContext
*s
)
426 #ifdef CONFIG_DEBUG_TCG
427 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
428 fprintf(stderr
, "target-arm: FP access check missing for "
429 "instruction 0x%08x\n", s
->insn
);
435 /* Return the offset into CPUARMState of an element of specified
436 * size, 'element' places in from the least significant end of
437 * the FP/vector register Qn.
439 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
440 int element
, TCGMemOp size
)
442 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
443 #ifdef HOST_WORDS_BIGENDIAN
444 /* This is complicated slightly because vfp.regs[2n] is
445 * still the low half and vfp.regs[2n+1] the high half
446 * of the 128 bit vector, even on big endian systems.
447 * Calculate the offset assuming a fully bigendian 128 bits,
448 * then XOR to account for the order of the two 64 bit halves.
450 offs
+= (16 - ((element
+ 1) * (1 << size
)));
453 offs
+= element
* (1 << size
);
455 assert_fp_access_checked(s
);
459 /* Return the offset into CPUARMState of a slice (from
460 * the least significant end) of FP register Qn (ie
462 * (Note that this is not the same mapping as for A32; see cpu.h)
464 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
466 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
467 #ifdef HOST_WORDS_BIGENDIAN
468 offs
+= (8 - (1 << size
));
470 assert_fp_access_checked(s
);
474 /* Offset of the high half of the 128 bit vector Qn */
475 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
477 assert_fp_access_checked(s
);
478 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
481 /* Convenience accessors for reading and writing single and double
482 * FP registers. Writing clears the upper parts of the associated
483 * 128 bit vector register, as required by the architecture.
484 * Note that unlike the GP register accessors, the values returned
485 * by the read functions must be manually freed.
487 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
489 TCGv_i64 v
= tcg_temp_new_i64();
491 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
495 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
497 TCGv_i32 v
= tcg_temp_new_i32();
499 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
503 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
505 TCGv_i64 tcg_zero
= tcg_const_i64(0);
507 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
508 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
509 tcg_temp_free_i64(tcg_zero
);
512 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
514 TCGv_i64 tmp
= tcg_temp_new_i64();
516 tcg_gen_extu_i32_i64(tmp
, v
);
517 write_fp_dreg(s
, reg
, tmp
);
518 tcg_temp_free_i64(tmp
);
521 static TCGv_ptr
get_fpstatus_ptr(void)
523 TCGv_ptr statusptr
= tcg_temp_new_ptr();
526 /* In A64 all instructions (both FP and Neon) use the FPCR;
527 * there is no equivalent of the A32 Neon "standard FPSCR value"
528 * and all operations use vfp.fp_status.
530 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
531 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
535 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
536 * than the 32 bit equivalent.
538 static inline void gen_set_NZ64(TCGv_i64 result
)
540 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
541 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
544 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
545 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
548 gen_set_NZ64(result
);
550 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
551 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
553 tcg_gen_movi_i32(cpu_CF
, 0);
554 tcg_gen_movi_i32(cpu_VF
, 0);
557 /* dest = T0 + T1; compute C, N, V and Z flags */
558 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
561 TCGv_i64 result
, flag
, tmp
;
562 result
= tcg_temp_new_i64();
563 flag
= tcg_temp_new_i64();
564 tmp
= tcg_temp_new_i64();
566 tcg_gen_movi_i64(tmp
, 0);
567 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
569 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
571 gen_set_NZ64(result
);
573 tcg_gen_xor_i64(flag
, result
, t0
);
574 tcg_gen_xor_i64(tmp
, t0
, t1
);
575 tcg_gen_andc_i64(flag
, flag
, tmp
);
576 tcg_temp_free_i64(tmp
);
577 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
579 tcg_gen_mov_i64(dest
, result
);
580 tcg_temp_free_i64(result
);
581 tcg_temp_free_i64(flag
);
583 /* 32 bit arithmetic */
584 TCGv_i32 t0_32
= tcg_temp_new_i32();
585 TCGv_i32 t1_32
= tcg_temp_new_i32();
586 TCGv_i32 tmp
= tcg_temp_new_i32();
588 tcg_gen_movi_i32(tmp
, 0);
589 tcg_gen_extrl_i64_i32(t0_32
, t0
);
590 tcg_gen_extrl_i64_i32(t1_32
, t1
);
591 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
592 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
593 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
594 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
595 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
596 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
598 tcg_temp_free_i32(tmp
);
599 tcg_temp_free_i32(t0_32
);
600 tcg_temp_free_i32(t1_32
);
604 /* dest = T0 - T1; compute C, N, V and Z flags */
605 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
608 /* 64 bit arithmetic */
609 TCGv_i64 result
, flag
, tmp
;
611 result
= tcg_temp_new_i64();
612 flag
= tcg_temp_new_i64();
613 tcg_gen_sub_i64(result
, t0
, t1
);
615 gen_set_NZ64(result
);
617 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
618 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
620 tcg_gen_xor_i64(flag
, result
, t0
);
621 tmp
= tcg_temp_new_i64();
622 tcg_gen_xor_i64(tmp
, t0
, t1
);
623 tcg_gen_and_i64(flag
, flag
, tmp
);
624 tcg_temp_free_i64(tmp
);
625 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
626 tcg_gen_mov_i64(dest
, result
);
627 tcg_temp_free_i64(flag
);
628 tcg_temp_free_i64(result
);
630 /* 32 bit arithmetic */
631 TCGv_i32 t0_32
= tcg_temp_new_i32();
632 TCGv_i32 t1_32
= tcg_temp_new_i32();
635 tcg_gen_extrl_i64_i32(t0_32
, t0
);
636 tcg_gen_extrl_i64_i32(t1_32
, t1
);
637 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
638 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
639 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
640 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
641 tmp
= tcg_temp_new_i32();
642 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
643 tcg_temp_free_i32(t0_32
);
644 tcg_temp_free_i32(t1_32
);
645 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
646 tcg_temp_free_i32(tmp
);
647 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
651 /* dest = T0 + T1 + CF; do not compute flags. */
652 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
654 TCGv_i64 flag
= tcg_temp_new_i64();
655 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
656 tcg_gen_add_i64(dest
, t0
, t1
);
657 tcg_gen_add_i64(dest
, dest
, flag
);
658 tcg_temp_free_i64(flag
);
661 tcg_gen_ext32u_i64(dest
, dest
);
665 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
666 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
669 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
670 result
= tcg_temp_new_i64();
671 cf_64
= tcg_temp_new_i64();
672 vf_64
= tcg_temp_new_i64();
673 tmp
= tcg_const_i64(0);
675 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
676 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
677 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
678 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
679 gen_set_NZ64(result
);
681 tcg_gen_xor_i64(vf_64
, result
, t0
);
682 tcg_gen_xor_i64(tmp
, t0
, t1
);
683 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
684 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
686 tcg_gen_mov_i64(dest
, result
);
688 tcg_temp_free_i64(tmp
);
689 tcg_temp_free_i64(vf_64
);
690 tcg_temp_free_i64(cf_64
);
691 tcg_temp_free_i64(result
);
693 TCGv_i32 t0_32
, t1_32
, tmp
;
694 t0_32
= tcg_temp_new_i32();
695 t1_32
= tcg_temp_new_i32();
696 tmp
= tcg_const_i32(0);
698 tcg_gen_extrl_i64_i32(t0_32
, t0
);
699 tcg_gen_extrl_i64_i32(t1_32
, t1
);
700 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
701 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
703 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
704 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
705 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
706 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
707 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
709 tcg_temp_free_i32(tmp
);
710 tcg_temp_free_i32(t1_32
);
711 tcg_temp_free_i32(t0_32
);
716 * Load/Store generators
720 * Store from GPR register to memory.
722 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
723 TCGv_i64 tcg_addr
, int size
, int memidx
)
726 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
729 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
730 TCGv_i64 tcg_addr
, int size
)
732 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
736 * Load from memory to GPR register
738 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
739 int size
, bool is_signed
, bool extend
, int memidx
)
741 TCGMemOp memop
= s
->be_data
+ size
;
749 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
751 if (extend
&& is_signed
) {
753 tcg_gen_ext32u_i64(dest
, dest
);
757 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
758 int size
, bool is_signed
, bool extend
)
760 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
765 * Store from FP register to memory
767 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
769 /* This writes the bottom N bits of a 128 bit wide vector to memory */
770 TCGv_i64 tmp
= tcg_temp_new_i64();
771 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
773 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
776 bool be
= s
->be_data
== MO_BE
;
777 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
779 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
780 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
782 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
783 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
785 tcg_temp_free_i64(tcg_hiaddr
);
788 tcg_temp_free_i64(tmp
);
792 * Load from memory to FP register
794 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
796 /* This always zero-extends and writes to a full 128 bit wide vector */
797 TCGv_i64 tmplo
= tcg_temp_new_i64();
801 TCGMemOp memop
= s
->be_data
+ size
;
802 tmphi
= tcg_const_i64(0);
803 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
805 bool be
= s
->be_data
== MO_BE
;
808 tmphi
= tcg_temp_new_i64();
809 tcg_hiaddr
= tcg_temp_new_i64();
811 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
812 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
814 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
816 tcg_temp_free_i64(tcg_hiaddr
);
819 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
820 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
822 tcg_temp_free_i64(tmplo
);
823 tcg_temp_free_i64(tmphi
);
827 * Vector load/store helpers.
829 * The principal difference between this and a FP load is that we don't
830 * zero extend as we are filling a partial chunk of the vector register.
831 * These functions don't support 128 bit loads/stores, which would be
832 * normal load/store operations.
834 * The _i32 versions are useful when operating on 32 bit quantities
835 * (eg for floating point single or using Neon helper functions).
838 /* Get value of an element within a vector register */
839 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
840 int element
, TCGMemOp memop
)
842 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
845 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
848 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
851 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
854 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
857 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
860 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
864 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
867 g_assert_not_reached();
871 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
872 int element
, TCGMemOp memop
)
874 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
877 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
880 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
883 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
886 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
890 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
893 g_assert_not_reached();
897 /* Set value of an element within a vector register */
898 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
899 int element
, TCGMemOp memop
)
901 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
904 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
907 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
910 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
913 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
916 g_assert_not_reached();
920 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
921 int destidx
, int element
, TCGMemOp memop
)
923 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
926 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
929 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
932 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
935 g_assert_not_reached();
939 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
940 * vector ops all need to do this).
942 static void clear_vec_high(DisasContext
*s
, int rd
)
944 TCGv_i64 tcg_zero
= tcg_const_i64(0);
946 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
947 tcg_temp_free_i64(tcg_zero
);
950 /* Store from vector register to memory */
951 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
952 TCGv_i64 tcg_addr
, int size
)
954 TCGMemOp memop
= s
->be_data
+ size
;
955 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
957 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
958 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
960 tcg_temp_free_i64(tcg_tmp
);
963 /* Load from memory to vector register */
964 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
965 TCGv_i64 tcg_addr
, int size
)
967 TCGMemOp memop
= s
->be_data
+ size
;
968 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
970 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
971 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
973 tcg_temp_free_i64(tcg_tmp
);
976 /* Check that FP/Neon access is enabled. If it is, return
977 * true. If not, emit code to generate an appropriate exception,
978 * and return false; the caller should not emit any code for
979 * the instruction. Note that this check must happen after all
980 * unallocated-encoding checks (otherwise the syndrome information
981 * for the resulting exception will be incorrect).
983 static inline bool fp_access_check(DisasContext
*s
)
985 assert(!s
->fp_access_checked
);
986 s
->fp_access_checked
= true;
988 if (!s
->fp_excp_el
) {
992 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
998 * This utility function is for doing register extension with an
999 * optional shift. You will likely want to pass a temporary for the
1000 * destination register. See DecodeRegExtend() in the ARM ARM.
1002 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1003 int option
, unsigned int shift
)
1005 int extsize
= extract32(option
, 0, 2);
1006 bool is_signed
= extract32(option
, 2, 1);
1011 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1014 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1017 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1020 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1026 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1029 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1032 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1035 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1041 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1045 static inline void gen_check_sp_alignment(DisasContext
*s
)
1047 /* The AArch64 architecture mandates that (if enabled via PSTATE
1048 * or SCTLR bits) there is a check that SP is 16-aligned on every
1049 * SP-relative load or store (with an exception generated if it is not).
1050 * In line with general QEMU practice regarding misaligned accesses,
1051 * we omit these checks for the sake of guest program performance.
1052 * This function is provided as a hook so we can more easily add these
1053 * checks in future (possibly as a "favour catching guest program bugs
1054 * over speed" user selectable option).
1059 * This provides a simple table based table lookup decoder. It is
1060 * intended to be used when the relevant bits for decode are too
1061 * awkwardly placed and switch/if based logic would be confusing and
1062 * deeply nested. Since it's a linear search through the table, tables
1063 * should be kept small.
1065 * It returns the first handler where insn & mask == pattern, or
1066 * NULL if there is no match.
1067 * The table is terminated by an empty mask (i.e. 0)
1069 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1072 const AArch64DecodeTable
*tptr
= table
;
1074 while (tptr
->mask
) {
1075 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1076 return tptr
->disas_fn
;
1084 * the instruction disassembly implemented here matches
1085 * the instruction encoding classifications in chapter 3 (C3)
1086 * of the ARM Architecture Reference Manual (DDI0487A_a)
1089 /* C3.2.7 Unconditional branch (immediate)
1091 * +----+-----------+-------------------------------------+
1092 * | op | 0 0 1 0 1 | imm26 |
1093 * +----+-----------+-------------------------------------+
1095 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1097 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1099 if (insn
& (1U << 31)) {
1100 /* C5.6.26 BL Branch with link */
1101 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1104 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1105 gen_goto_tb(s
, 0, addr
);
1108 /* C3.2.1 Compare & branch (immediate)
1109 * 31 30 25 24 23 5 4 0
1110 * +----+-------------+----+---------------------+--------+
1111 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1112 * +----+-------------+----+---------------------+--------+
1114 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1116 unsigned int sf
, op
, rt
;
1118 TCGLabel
*label_match
;
1121 sf
= extract32(insn
, 31, 1);
1122 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1123 rt
= extract32(insn
, 0, 5);
1124 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1126 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1127 label_match
= gen_new_label();
1129 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1130 tcg_cmp
, 0, label_match
);
1132 gen_goto_tb(s
, 0, s
->pc
);
1133 gen_set_label(label_match
);
1134 gen_goto_tb(s
, 1, addr
);
1137 /* C3.2.5 Test & branch (immediate)
1138 * 31 30 25 24 23 19 18 5 4 0
1139 * +----+-------------+----+-------+-------------+------+
1140 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1141 * +----+-------------+----+-------+-------------+------+
1143 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1145 unsigned int bit_pos
, op
, rt
;
1147 TCGLabel
*label_match
;
1150 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1151 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1152 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1153 rt
= extract32(insn
, 0, 5);
1155 tcg_cmp
= tcg_temp_new_i64();
1156 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1157 label_match
= gen_new_label();
1158 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1159 tcg_cmp
, 0, label_match
);
1160 tcg_temp_free_i64(tcg_cmp
);
1161 gen_goto_tb(s
, 0, s
->pc
);
1162 gen_set_label(label_match
);
1163 gen_goto_tb(s
, 1, addr
);
1166 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1167 * 31 25 24 23 5 4 3 0
1168 * +---------------+----+---------------------+----+------+
1169 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1170 * +---------------+----+---------------------+----+------+
1172 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1177 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1178 unallocated_encoding(s
);
1181 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1182 cond
= extract32(insn
, 0, 4);
1185 /* genuinely conditional branches */
1186 TCGLabel
*label_match
= gen_new_label();
1187 arm_gen_test_cc(cond
, label_match
);
1188 gen_goto_tb(s
, 0, s
->pc
);
1189 gen_set_label(label_match
);
1190 gen_goto_tb(s
, 1, addr
);
1192 /* 0xe and 0xf are both "always" conditions */
1193 gen_goto_tb(s
, 0, addr
);
1198 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1199 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1201 unsigned int selector
= crm
<< 3 | op2
;
1204 unallocated_encoding(s
);
1212 s
->is_jmp
= DISAS_WFI
;
1215 s
->is_jmp
= DISAS_YIELD
;
1218 s
->is_jmp
= DISAS_WFE
;
1222 /* we treat all as NOP at least for now */
1225 /* default specified as NOP equivalent */
1230 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1232 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1235 /* CLREX, DSB, DMB, ISB */
1236 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1237 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1240 unallocated_encoding(s
);
1250 /* We don't emulate caches so barriers are no-ops */
1253 /* We need to break the TB after this insn to execute
1254 * a self-modified code correctly and also to take
1255 * any pending interrupts immediately.
1257 s
->is_jmp
= DISAS_UPDATE
;
1260 unallocated_encoding(s
);
1265 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1266 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1267 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1269 int op
= op1
<< 3 | op2
;
1271 case 0x05: /* SPSel */
1272 if (s
->current_el
== 0) {
1273 unallocated_encoding(s
);
1277 case 0x1e: /* DAIFSet */
1278 case 0x1f: /* DAIFClear */
1280 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1281 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1282 gen_a64_set_pc_im(s
->pc
- 4);
1283 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1284 tcg_temp_free_i32(tcg_imm
);
1285 tcg_temp_free_i32(tcg_op
);
1286 s
->is_jmp
= DISAS_UPDATE
;
1290 unallocated_encoding(s
);
1295 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1297 TCGv_i32 tmp
= tcg_temp_new_i32();
1298 TCGv_i32 nzcv
= tcg_temp_new_i32();
1300 /* build bit 31, N */
1301 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1302 /* build bit 30, Z */
1303 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1304 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1305 /* build bit 29, C */
1306 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1307 /* build bit 28, V */
1308 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1309 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1310 /* generate result */
1311 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1313 tcg_temp_free_i32(nzcv
);
1314 tcg_temp_free_i32(tmp
);
1317 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1320 TCGv_i32 nzcv
= tcg_temp_new_i32();
1322 /* take NZCV from R[t] */
1323 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1326 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1328 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1329 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1331 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1332 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1334 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1335 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1336 tcg_temp_free_i32(nzcv
);
1339 /* C5.6.129 MRS - move from system register
1340 * C5.6.131 MSR (register) - move to system register
1343 * These are all essentially the same insn in 'read' and 'write'
1344 * versions, with varying op0 fields.
1346 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1347 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1348 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1350 const ARMCPRegInfo
*ri
;
1353 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1354 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1355 crn
, crm
, op0
, op1
, op2
));
1358 /* Unknown register; this might be a guest error or a QEMU
1359 * unimplemented feature.
1361 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1362 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1363 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1364 unallocated_encoding(s
);
1368 /* Check access permissions */
1369 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1370 unallocated_encoding(s
);
1375 /* Emit code to perform further access permissions checks at
1376 * runtime; this may result in an exception.
1379 TCGv_i32 tcg_syn
, tcg_isread
;
1382 gen_a64_set_pc_im(s
->pc
- 4);
1383 tmpptr
= tcg_const_ptr(ri
);
1384 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1385 tcg_syn
= tcg_const_i32(syndrome
);
1386 tcg_isread
= tcg_const_i32(isread
);
1387 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1388 tcg_temp_free_ptr(tmpptr
);
1389 tcg_temp_free_i32(tcg_syn
);
1390 tcg_temp_free_i32(tcg_isread
);
1393 /* Handle special cases first */
1394 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1398 tcg_rt
= cpu_reg(s
, rt
);
1400 gen_get_nzcv(tcg_rt
);
1402 gen_set_nzcv(tcg_rt
);
1405 case ARM_CP_CURRENTEL
:
1406 /* Reads as current EL value from pstate, which is
1407 * guaranteed to be constant by the tb flags.
1409 tcg_rt
= cpu_reg(s
, rt
);
1410 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1413 /* Writes clear the aligned block of memory which rt points into. */
1414 tcg_rt
= cpu_reg(s
, rt
);
1415 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1421 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1425 tcg_rt
= cpu_reg(s
, rt
);
1428 if (ri
->type
& ARM_CP_CONST
) {
1429 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1430 } else if (ri
->readfn
) {
1432 tmpptr
= tcg_const_ptr(ri
);
1433 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1434 tcg_temp_free_ptr(tmpptr
);
1436 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1439 if (ri
->type
& ARM_CP_CONST
) {
1440 /* If not forbidden by access permissions, treat as WI */
1442 } else if (ri
->writefn
) {
1444 tmpptr
= tcg_const_ptr(ri
);
1445 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1446 tcg_temp_free_ptr(tmpptr
);
1448 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1452 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1453 /* I/O operations must end the TB here (whether read or write) */
1455 s
->is_jmp
= DISAS_UPDATE
;
1456 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1457 /* We default to ending the TB on a coprocessor register write,
1458 * but allow this to be suppressed by the register definition
1459 * (usually only necessary to work around guest bugs).
1461 s
->is_jmp
= DISAS_UPDATE
;
1466 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1467 * +---------------------+---+-----+-----+-------+-------+-----+------+
1468 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1469 * +---------------------+---+-----+-----+-------+-------+-----+------+
1471 static void disas_system(DisasContext
*s
, uint32_t insn
)
1473 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1474 l
= extract32(insn
, 21, 1);
1475 op0
= extract32(insn
, 19, 2);
1476 op1
= extract32(insn
, 16, 3);
1477 crn
= extract32(insn
, 12, 4);
1478 crm
= extract32(insn
, 8, 4);
1479 op2
= extract32(insn
, 5, 3);
1480 rt
= extract32(insn
, 0, 5);
1483 if (l
|| rt
!= 31) {
1484 unallocated_encoding(s
);
1488 case 2: /* C5.6.68 HINT */
1489 handle_hint(s
, insn
, op1
, op2
, crm
);
1491 case 3: /* CLREX, DSB, DMB, ISB */
1492 handle_sync(s
, insn
, op1
, op2
, crm
);
1494 case 4: /* C5.6.130 MSR (immediate) */
1495 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1498 unallocated_encoding(s
);
1503 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1506 /* C3.2.3 Exception generation
1508 * 31 24 23 21 20 5 4 2 1 0
1509 * +-----------------+-----+------------------------+-----+----+
1510 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1511 * +-----------------------+------------------------+----------+
1513 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1515 int opc
= extract32(insn
, 21, 3);
1516 int op2_ll
= extract32(insn
, 0, 5);
1517 int imm16
= extract32(insn
, 5, 16);
1522 /* For SVC, HVC and SMC we advance the single-step state
1523 * machine before taking the exception. This is architecturally
1524 * mandated, to ensure that single-stepping a system call
1525 * instruction works properly.
1530 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1531 default_exception_el(s
));
1534 if (s
->current_el
== 0) {
1535 unallocated_encoding(s
);
1538 /* The pre HVC helper handles cases when HVC gets trapped
1539 * as an undefined insn by runtime configuration.
1541 gen_a64_set_pc_im(s
->pc
- 4);
1542 gen_helper_pre_hvc(cpu_env
);
1544 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1547 if (s
->current_el
== 0) {
1548 unallocated_encoding(s
);
1551 gen_a64_set_pc_im(s
->pc
- 4);
1552 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1553 gen_helper_pre_smc(cpu_env
, tmp
);
1554 tcg_temp_free_i32(tmp
);
1556 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1559 unallocated_encoding(s
);
1565 unallocated_encoding(s
);
1569 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1570 default_exception_el(s
));
1574 unallocated_encoding(s
);
1577 /* HLT. This has two purposes.
1578 * Architecturally, it is an external halting debug instruction.
1579 * Since QEMU doesn't implement external debug, we treat this as
1580 * it is required for halting debug disabled: it will UNDEF.
1581 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1583 if (semihosting_enabled() && imm16
== 0xf000) {
1584 #ifndef CONFIG_USER_ONLY
1585 /* In system mode, don't allow userspace access to semihosting,
1586 * to provide some semblance of security (and for consistency
1587 * with our 32-bit semihosting).
1589 if (s
->current_el
== 0) {
1590 unsupported_encoding(s
, insn
);
1594 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1596 unsupported_encoding(s
, insn
);
1600 if (op2_ll
< 1 || op2_ll
> 3) {
1601 unallocated_encoding(s
);
1604 /* DCPS1, DCPS2, DCPS3 */
1605 unsupported_encoding(s
, insn
);
1608 unallocated_encoding(s
);
1613 /* C3.2.7 Unconditional branch (register)
1614 * 31 25 24 21 20 16 15 10 9 5 4 0
1615 * +---------------+-------+-------+-------+------+-------+
1616 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1617 * +---------------+-------+-------+-------+------+-------+
1619 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1621 unsigned int opc
, op2
, op3
, rn
, op4
;
1623 opc
= extract32(insn
, 21, 4);
1624 op2
= extract32(insn
, 16, 5);
1625 op3
= extract32(insn
, 10, 6);
1626 rn
= extract32(insn
, 5, 5);
1627 op4
= extract32(insn
, 0, 5);
1629 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1630 unallocated_encoding(s
);
1637 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1640 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1641 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1644 if (s
->current_el
== 0) {
1645 unallocated_encoding(s
);
1648 gen_helper_exception_return(cpu_env
);
1649 s
->is_jmp
= DISAS_JUMP
;
1653 unallocated_encoding(s
);
1655 unsupported_encoding(s
, insn
);
1659 unallocated_encoding(s
);
1663 s
->is_jmp
= DISAS_JUMP
;
1666 /* C3.2 Branches, exception generating and system instructions */
1667 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1669 switch (extract32(insn
, 25, 7)) {
1670 case 0x0a: case 0x0b:
1671 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1672 disas_uncond_b_imm(s
, insn
);
1674 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1675 disas_comp_b_imm(s
, insn
);
1677 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1678 disas_test_b_imm(s
, insn
);
1680 case 0x2a: /* Conditional branch (immediate) */
1681 disas_cond_b_imm(s
, insn
);
1683 case 0x6a: /* Exception generation / System */
1684 if (insn
& (1 << 24)) {
1685 disas_system(s
, insn
);
1690 case 0x6b: /* Unconditional branch (register) */
1691 disas_uncond_b_reg(s
, insn
);
1694 unallocated_encoding(s
);
1700 * Load/Store exclusive instructions are implemented by remembering
1701 * the value/address loaded, and seeing if these are the same
1702 * when the store is performed. This is not actually the architecturally
1703 * mandated semantics, but it works for typical guest code sequences
1704 * and avoids having to monitor regular stores.
1706 * In system emulation mode only one CPU will be running at once, so
1707 * this sequence is effectively atomic. In user emulation mode we
1708 * throw an exception and handle the atomic operation elsewhere.
1710 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1711 TCGv_i64 addr
, int size
, bool is_pair
)
1713 TCGv_i64 tmp
= tcg_temp_new_i64();
1714 TCGMemOp memop
= s
->be_data
+ size
;
1716 g_assert(size
<= 3);
1717 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1720 TCGv_i64 addr2
= tcg_temp_new_i64();
1721 TCGv_i64 hitmp
= tcg_temp_new_i64();
1723 g_assert(size
>= 2);
1724 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1725 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1726 tcg_temp_free_i64(addr2
);
1727 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1728 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1729 tcg_temp_free_i64(hitmp
);
1732 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1733 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1735 tcg_temp_free_i64(tmp
);
1736 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1739 #ifdef CONFIG_USER_ONLY
1740 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1741 TCGv_i64 addr
, int size
, int is_pair
)
1743 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1744 tcg_gen_movi_i32(cpu_exclusive_info
,
1745 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1746 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1749 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1750 TCGv_i64 inaddr
, int size
, int is_pair
)
1752 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1753 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1756 * [addr + datasize] = {Rt2};
1762 * env->exclusive_addr = -1;
1764 TCGLabel
*fail_label
= gen_new_label();
1765 TCGLabel
*done_label
= gen_new_label();
1766 TCGv_i64 addr
= tcg_temp_local_new_i64();
1769 /* Copy input into a local temp so it is not trashed when the
1770 * basic block ends at the branch insn.
1772 tcg_gen_mov_i64(addr
, inaddr
);
1773 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1775 tmp
= tcg_temp_new_i64();
1776 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), s
->be_data
+ size
);
1777 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1778 tcg_temp_free_i64(tmp
);
1781 TCGv_i64 addrhi
= tcg_temp_new_i64();
1782 TCGv_i64 tmphi
= tcg_temp_new_i64();
1784 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1785 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
),
1787 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1789 tcg_temp_free_i64(tmphi
);
1790 tcg_temp_free_i64(addrhi
);
1793 /* We seem to still have the exclusive monitor, so do the store */
1794 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
),
1797 TCGv_i64 addrhi
= tcg_temp_new_i64();
1799 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1800 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1801 get_mem_index(s
), s
->be_data
+ size
);
1802 tcg_temp_free_i64(addrhi
);
1805 tcg_temp_free_i64(addr
);
1807 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1808 tcg_gen_br(done_label
);
1809 gen_set_label(fail_label
);
1810 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1811 gen_set_label(done_label
);
1812 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1817 /* C3.3.6 Load/store exclusive
1819 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1820 * +-----+-------------+----+---+----+------+----+-------+------+------+
1821 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1822 * +-----+-------------+----+---+----+------+----+-------+------+------+
1824 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1825 * L: 0 -> store, 1 -> load
1826 * o2: 0 -> exclusive, 1 -> not
1827 * o1: 0 -> single register, 1 -> register pair
1828 * o0: 1 -> load-acquire/store-release, 0 -> not
1830 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1832 int rt
= extract32(insn
, 0, 5);
1833 int rn
= extract32(insn
, 5, 5);
1834 int rt2
= extract32(insn
, 10, 5);
1835 int is_lasr
= extract32(insn
, 15, 1);
1836 int rs
= extract32(insn
, 16, 5);
1837 int is_pair
= extract32(insn
, 21, 1);
1838 int is_store
= !extract32(insn
, 22, 1);
1839 int is_excl
= !extract32(insn
, 23, 1);
1840 int size
= extract32(insn
, 30, 2);
1843 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1844 (!is_excl
&& is_pair
) ||
1845 (is_pair
&& size
< 2)) {
1846 unallocated_encoding(s
);
1851 gen_check_sp_alignment(s
);
1853 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1855 /* Note that since TCG is single threaded load-acquire/store-release
1856 * semantics require no extra if (is_lasr) { ... } handling.
1862 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1864 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1867 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1869 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1871 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1877 * C3.3.5 Load register (literal)
1879 * 31 30 29 27 26 25 24 23 5 4 0
1880 * +-----+-------+---+-----+-------------------+-------+
1881 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1882 * +-----+-------+---+-----+-------------------+-------+
1884 * V: 1 -> vector (simd/fp)
1885 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1886 * 10-> 32 bit signed, 11 -> prefetch
1887 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1889 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1891 int rt
= extract32(insn
, 0, 5);
1892 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1893 bool is_vector
= extract32(insn
, 26, 1);
1894 int opc
= extract32(insn
, 30, 2);
1895 bool is_signed
= false;
1897 TCGv_i64 tcg_rt
, tcg_addr
;
1901 unallocated_encoding(s
);
1905 if (!fp_access_check(s
)) {
1910 /* PRFM (literal) : prefetch */
1913 size
= 2 + extract32(opc
, 0, 1);
1914 is_signed
= extract32(opc
, 1, 1);
1917 tcg_rt
= cpu_reg(s
, rt
);
1919 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1921 do_fp_ld(s
, rt
, tcg_addr
, size
);
1923 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1925 tcg_temp_free_i64(tcg_addr
);
1929 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1930 * C5.6.81 LDP (Load Pair - non vector)
1931 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1932 * C5.6.176 STNP (Store Pair - non-temporal hint)
1933 * C5.6.177 STP (Store Pair - non vector)
1934 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1935 * C6.3.165 LDP (Load Pair of SIMD&FP)
1936 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1937 * C6.3.284 STP (Store Pair of SIMD&FP)
1939 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1940 * +-----+-------+---+---+-------+---+-----------------------------+
1941 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1942 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1944 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1946 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1947 * V: 0 -> GPR, 1 -> Vector
1948 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1949 * 10 -> signed offset, 11 -> pre-index
1950 * L: 0 -> Store 1 -> Load
1952 * Rt, Rt2 = GPR or SIMD registers to be stored
1953 * Rn = general purpose register containing address
1954 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1956 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1958 int rt
= extract32(insn
, 0, 5);
1959 int rn
= extract32(insn
, 5, 5);
1960 int rt2
= extract32(insn
, 10, 5);
1961 uint64_t offset
= sextract64(insn
, 15, 7);
1962 int index
= extract32(insn
, 23, 2);
1963 bool is_vector
= extract32(insn
, 26, 1);
1964 bool is_load
= extract32(insn
, 22, 1);
1965 int opc
= extract32(insn
, 30, 2);
1967 bool is_signed
= false;
1968 bool postindex
= false;
1971 TCGv_i64 tcg_addr
; /* calculated address */
1975 unallocated_encoding(s
);
1982 size
= 2 + extract32(opc
, 1, 1);
1983 is_signed
= extract32(opc
, 0, 1);
1984 if (!is_load
&& is_signed
) {
1985 unallocated_encoding(s
);
1991 case 1: /* post-index */
1996 /* signed offset with "non-temporal" hint. Since we don't emulate
1997 * caches we don't care about hints to the cache system about
1998 * data access patterns, and handle this identically to plain
2002 /* There is no non-temporal-hint version of LDPSW */
2003 unallocated_encoding(s
);
2008 case 2: /* signed offset, rn not updated */
2011 case 3: /* pre-index */
2017 if (is_vector
&& !fp_access_check(s
)) {
2024 gen_check_sp_alignment(s
);
2027 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2030 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2035 do_fp_ld(s
, rt
, tcg_addr
, size
);
2037 do_fp_st(s
, rt
, tcg_addr
, size
);
2040 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2042 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
2044 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2047 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2050 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2052 do_fp_st(s
, rt2
, tcg_addr
, size
);
2055 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2057 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
2059 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
2065 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2067 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2069 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2074 * C3.3.8 Load/store (immediate post-indexed)
2075 * C3.3.9 Load/store (immediate pre-indexed)
2076 * C3.3.12 Load/store (unscaled immediate)
2078 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2079 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2080 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2081 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2083 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2085 * V = 0 -> non-vector
2086 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2087 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2089 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2095 int rn
= extract32(insn
, 5, 5);
2096 int imm9
= sextract32(insn
, 12, 9);
2097 int idx
= extract32(insn
, 10, 2);
2098 bool is_signed
= false;
2099 bool is_store
= false;
2100 bool is_extended
= false;
2101 bool is_unpriv
= (idx
== 2);
2108 size
|= (opc
& 2) << 1;
2109 if (size
> 4 || is_unpriv
) {
2110 unallocated_encoding(s
);
2113 is_store
= ((opc
& 1) == 0);
2114 if (!fp_access_check(s
)) {
2118 if (size
== 3 && opc
== 2) {
2119 /* PRFM - prefetch */
2121 unallocated_encoding(s
);
2126 if (opc
== 3 && size
> 1) {
2127 unallocated_encoding(s
);
2130 is_store
= (opc
== 0);
2131 is_signed
= extract32(opc
, 1, 1);
2132 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2152 gen_check_sp_alignment(s
);
2154 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2157 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2162 do_fp_st(s
, rt
, tcg_addr
, size
);
2164 do_fp_ld(s
, rt
, tcg_addr
, size
);
2167 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2168 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2171 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2173 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2174 is_signed
, is_extended
, memidx
);
2179 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2181 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2183 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2188 * C3.3.10 Load/store (register offset)
2190 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2191 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2192 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2193 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2196 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2197 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2199 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2200 * opc<0>: 0 -> store, 1 -> load
2201 * V: 1 -> vector/simd
2202 * opt: extend encoding (see DecodeRegExtend)
2203 * S: if S=1 then scale (essentially index by sizeof(size))
2204 * Rt: register to transfer into/out of
2205 * Rn: address register or SP for base
2206 * Rm: offset register or ZR for offset
2208 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2214 int rn
= extract32(insn
, 5, 5);
2215 int shift
= extract32(insn
, 12, 1);
2216 int rm
= extract32(insn
, 16, 5);
2217 int opt
= extract32(insn
, 13, 3);
2218 bool is_signed
= false;
2219 bool is_store
= false;
2220 bool is_extended
= false;
2225 if (extract32(opt
, 1, 1) == 0) {
2226 unallocated_encoding(s
);
2231 size
|= (opc
& 2) << 1;
2233 unallocated_encoding(s
);
2236 is_store
= !extract32(opc
, 0, 1);
2237 if (!fp_access_check(s
)) {
2241 if (size
== 3 && opc
== 2) {
2242 /* PRFM - prefetch */
2245 if (opc
== 3 && size
> 1) {
2246 unallocated_encoding(s
);
2249 is_store
= (opc
== 0);
2250 is_signed
= extract32(opc
, 1, 1);
2251 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2255 gen_check_sp_alignment(s
);
2257 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2259 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2260 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2262 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2266 do_fp_st(s
, rt
, tcg_addr
, size
);
2268 do_fp_ld(s
, rt
, tcg_addr
, size
);
2271 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2273 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2275 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2281 * C3.3.13 Load/store (unsigned immediate)
2283 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2284 * +----+-------+---+-----+-----+------------+-------+------+
2285 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2286 * +----+-------+---+-----+-----+------------+-------+------+
2289 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2290 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2292 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2293 * opc<0>: 0 -> store, 1 -> load
2294 * Rn: base address register (inc SP)
2295 * Rt: target register
2297 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2303 int rn
= extract32(insn
, 5, 5);
2304 unsigned int imm12
= extract32(insn
, 10, 12);
2305 unsigned int offset
;
2310 bool is_signed
= false;
2311 bool is_extended
= false;
2314 size
|= (opc
& 2) << 1;
2316 unallocated_encoding(s
);
2319 is_store
= !extract32(opc
, 0, 1);
2320 if (!fp_access_check(s
)) {
2324 if (size
== 3 && opc
== 2) {
2325 /* PRFM - prefetch */
2328 if (opc
== 3 && size
> 1) {
2329 unallocated_encoding(s
);
2332 is_store
= (opc
== 0);
2333 is_signed
= extract32(opc
, 1, 1);
2334 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2338 gen_check_sp_alignment(s
);
2340 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2341 offset
= imm12
<< size
;
2342 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2346 do_fp_st(s
, rt
, tcg_addr
, size
);
2348 do_fp_ld(s
, rt
, tcg_addr
, size
);
2351 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2353 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2355 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2360 /* Load/store register (all forms) */
2361 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2363 int rt
= extract32(insn
, 0, 5);
2364 int opc
= extract32(insn
, 22, 2);
2365 bool is_vector
= extract32(insn
, 26, 1);
2366 int size
= extract32(insn
, 30, 2);
2368 switch (extract32(insn
, 24, 2)) {
2370 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2371 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2373 /* Load/store register (unscaled immediate)
2374 * Load/store immediate pre/post-indexed
2375 * Load/store register unprivileged
2377 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2381 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2384 unallocated_encoding(s
);
2389 /* C3.3.1 AdvSIMD load/store multiple structures
2391 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2392 * +---+---+---------------+---+-------------+--------+------+------+------+
2393 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2394 * +---+---+---------------+---+-------------+--------+------+------+------+
2396 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2398 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2399 * +---+---+---------------+---+---+---------+--------+------+------+------+
2400 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2401 * +---+---+---------------+---+---+---------+--------+------+------+------+
2403 * Rt: first (or only) SIMD&FP register to be transferred
2404 * Rn: base address or SP
2405 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2407 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2409 int rt
= extract32(insn
, 0, 5);
2410 int rn
= extract32(insn
, 5, 5);
2411 int size
= extract32(insn
, 10, 2);
2412 int opcode
= extract32(insn
, 12, 4);
2413 bool is_store
= !extract32(insn
, 22, 1);
2414 bool is_postidx
= extract32(insn
, 23, 1);
2415 bool is_q
= extract32(insn
, 30, 1);
2416 TCGv_i64 tcg_addr
, tcg_rn
;
2418 int ebytes
= 1 << size
;
2419 int elements
= (is_q
? 128 : 64) / (8 << size
);
2420 int rpt
; /* num iterations */
2421 int selem
; /* structure elements */
2424 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2425 unallocated_encoding(s
);
2429 /* From the shared decode logic */
2460 unallocated_encoding(s
);
2464 if (size
== 3 && !is_q
&& selem
!= 1) {
2466 unallocated_encoding(s
);
2470 if (!fp_access_check(s
)) {
2475 gen_check_sp_alignment(s
);
2478 tcg_rn
= cpu_reg_sp(s
, rn
);
2479 tcg_addr
= tcg_temp_new_i64();
2480 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2482 for (r
= 0; r
< rpt
; r
++) {
2484 for (e
= 0; e
< elements
; e
++) {
2485 int tt
= (rt
+ r
) % 32;
2487 for (xs
= 0; xs
< selem
; xs
++) {
2489 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2491 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2493 /* For non-quad operations, setting a slice of the low
2494 * 64 bits of the register clears the high 64 bits (in
2495 * the ARM ARM pseudocode this is implicit in the fact
2496 * that 'rval' is a 64 bit wide variable). We optimize
2497 * by noticing that we only need to do this the first
2498 * time we touch a register.
2500 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2501 clear_vec_high(s
, tt
);
2504 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2511 int rm
= extract32(insn
, 16, 5);
2513 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2515 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2518 tcg_temp_free_i64(tcg_addr
);
2521 /* C3.3.3 AdvSIMD load/store single structure
2523 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2524 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2525 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2526 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2528 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2530 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2531 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2532 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2533 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2535 * Rt: first (or only) SIMD&FP register to be transferred
2536 * Rn: base address or SP
2537 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2538 * index = encoded in Q:S:size dependent on size
2540 * lane_size = encoded in R, opc
2541 * transfer width = encoded in opc, S, size
2543 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2545 int rt
= extract32(insn
, 0, 5);
2546 int rn
= extract32(insn
, 5, 5);
2547 int size
= extract32(insn
, 10, 2);
2548 int S
= extract32(insn
, 12, 1);
2549 int opc
= extract32(insn
, 13, 3);
2550 int R
= extract32(insn
, 21, 1);
2551 int is_load
= extract32(insn
, 22, 1);
2552 int is_postidx
= extract32(insn
, 23, 1);
2553 int is_q
= extract32(insn
, 30, 1);
2555 int scale
= extract32(opc
, 1, 2);
2556 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2557 bool replicate
= false;
2558 int index
= is_q
<< 3 | S
<< 2 | size
;
2560 TCGv_i64 tcg_addr
, tcg_rn
;
2564 if (!is_load
|| S
) {
2565 unallocated_encoding(s
);
2574 if (extract32(size
, 0, 1)) {
2575 unallocated_encoding(s
);
2581 if (extract32(size
, 1, 1)) {
2582 unallocated_encoding(s
);
2585 if (!extract32(size
, 0, 1)) {
2589 unallocated_encoding(s
);
2597 g_assert_not_reached();
2600 if (!fp_access_check(s
)) {
2604 ebytes
= 1 << scale
;
2607 gen_check_sp_alignment(s
);
2610 tcg_rn
= cpu_reg_sp(s
, rn
);
2611 tcg_addr
= tcg_temp_new_i64();
2612 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2614 for (xs
= 0; xs
< selem
; xs
++) {
2616 /* Load and replicate to all elements */
2618 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2620 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2621 get_mem_index(s
), s
->be_data
+ scale
);
2624 mulconst
= 0x0101010101010101ULL
;
2627 mulconst
= 0x0001000100010001ULL
;
2630 mulconst
= 0x0000000100000001ULL
;
2636 g_assert_not_reached();
2639 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2641 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2643 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2645 clear_vec_high(s
, rt
);
2647 tcg_temp_free_i64(tcg_tmp
);
2649 /* Load/store one element per register */
2651 do_vec_ld(s
, rt
, index
, tcg_addr
, s
->be_data
+ scale
);
2653 do_vec_st(s
, rt
, index
, tcg_addr
, s
->be_data
+ scale
);
2656 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2661 int rm
= extract32(insn
, 16, 5);
2663 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2665 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2668 tcg_temp_free_i64(tcg_addr
);
2671 /* C3.3 Loads and stores */
2672 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2674 switch (extract32(insn
, 24, 6)) {
2675 case 0x08: /* Load/store exclusive */
2676 disas_ldst_excl(s
, insn
);
2678 case 0x18: case 0x1c: /* Load register (literal) */
2679 disas_ld_lit(s
, insn
);
2681 case 0x28: case 0x29:
2682 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2683 disas_ldst_pair(s
, insn
);
2685 case 0x38: case 0x39:
2686 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2687 disas_ldst_reg(s
, insn
);
2689 case 0x0c: /* AdvSIMD load/store multiple structures */
2690 disas_ldst_multiple_struct(s
, insn
);
2692 case 0x0d: /* AdvSIMD load/store single structure */
2693 disas_ldst_single_struct(s
, insn
);
2696 unallocated_encoding(s
);
2701 /* C3.4.6 PC-rel. addressing
2702 * 31 30 29 28 24 23 5 4 0
2703 * +----+-------+-----------+-------------------+------+
2704 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2705 * +----+-------+-----------+-------------------+------+
2707 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2709 unsigned int page
, rd
;
2713 page
= extract32(insn
, 31, 1);
2714 /* SignExtend(immhi:immlo) -> offset */
2715 offset
= sextract64(insn
, 5, 19);
2716 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2717 rd
= extract32(insn
, 0, 5);
2721 /* ADRP (page based) */
2726 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2730 * C3.4.1 Add/subtract (immediate)
2732 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2733 * +--+--+--+-----------+-----+-------------+-----+-----+
2734 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2735 * +--+--+--+-----------+-----+-------------+-----+-----+
2737 * sf: 0 -> 32bit, 1 -> 64bit
2738 * op: 0 -> add , 1 -> sub
2740 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2742 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2744 int rd
= extract32(insn
, 0, 5);
2745 int rn
= extract32(insn
, 5, 5);
2746 uint64_t imm
= extract32(insn
, 10, 12);
2747 int shift
= extract32(insn
, 22, 2);
2748 bool setflags
= extract32(insn
, 29, 1);
2749 bool sub_op
= extract32(insn
, 30, 1);
2750 bool is_64bit
= extract32(insn
, 31, 1);
2752 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2753 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2754 TCGv_i64 tcg_result
;
2763 unallocated_encoding(s
);
2767 tcg_result
= tcg_temp_new_i64();
2770 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2772 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2775 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2777 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2779 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2781 tcg_temp_free_i64(tcg_imm
);
2785 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2787 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2790 tcg_temp_free_i64(tcg_result
);
2793 /* The input should be a value in the bottom e bits (with higher
2794 * bits zero); returns that value replicated into every element
2795 * of size e in a 64 bit integer.
2797 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2807 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2808 static inline uint64_t bitmask64(unsigned int length
)
2810 assert(length
> 0 && length
<= 64);
2811 return ~0ULL >> (64 - length
);
2814 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2815 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2816 * value (ie should cause a guest UNDEF exception), and true if they are
2817 * valid, in which case the decoded bit pattern is written to result.
2819 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2820 unsigned int imms
, unsigned int immr
)
2823 unsigned e
, levels
, s
, r
;
2826 assert(immn
< 2 && imms
< 64 && immr
< 64);
2828 /* The bit patterns we create here are 64 bit patterns which
2829 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2830 * 64 bits each. Each element contains the same value: a run
2831 * of between 1 and e-1 non-zero bits, rotated within the
2832 * element by between 0 and e-1 bits.
2834 * The element size and run length are encoded into immn (1 bit)
2835 * and imms (6 bits) as follows:
2836 * 64 bit elements: immn = 1, imms = <length of run - 1>
2837 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2838 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2839 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2840 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2841 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2842 * Notice that immn = 0, imms = 11111x is the only combination
2843 * not covered by one of the above options; this is reserved.
2844 * Further, <length of run - 1> all-ones is a reserved pattern.
2846 * In all cases the rotation is by immr % e (and immr is 6 bits).
2849 /* First determine the element size */
2850 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2852 /* This is the immn == 0, imms == 0x11111x case */
2862 /* <length of run - 1> mustn't be all-ones. */
2866 /* Create the value of one element: s+1 set bits rotated
2867 * by r within the element (which is e bits wide)...
2869 mask
= bitmask64(s
+ 1);
2871 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2872 mask
&= bitmask64(e
);
2874 /* ...then replicate the element over the whole 64 bit value */
2875 mask
= bitfield_replicate(mask
, e
);
2880 /* C3.4.4 Logical (immediate)
2881 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2882 * +----+-----+-------------+---+------+------+------+------+
2883 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2884 * +----+-----+-------------+---+------+------+------+------+
2886 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2888 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2889 TCGv_i64 tcg_rd
, tcg_rn
;
2891 bool is_and
= false;
2893 sf
= extract32(insn
, 31, 1);
2894 opc
= extract32(insn
, 29, 2);
2895 is_n
= extract32(insn
, 22, 1);
2896 immr
= extract32(insn
, 16, 6);
2897 imms
= extract32(insn
, 10, 6);
2898 rn
= extract32(insn
, 5, 5);
2899 rd
= extract32(insn
, 0, 5);
2902 unallocated_encoding(s
);
2906 if (opc
== 0x3) { /* ANDS */
2907 tcg_rd
= cpu_reg(s
, rd
);
2909 tcg_rd
= cpu_reg_sp(s
, rd
);
2911 tcg_rn
= cpu_reg(s
, rn
);
2913 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2914 /* some immediate field values are reserved */
2915 unallocated_encoding(s
);
2920 wmask
&= 0xffffffff;
2924 case 0x3: /* ANDS */
2926 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2930 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2933 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2936 assert(FALSE
); /* must handle all above */
2940 if (!sf
&& !is_and
) {
2941 /* zero extend final result; we know we can skip this for AND
2942 * since the immediate had the high 32 bits clear.
2944 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2947 if (opc
== 3) { /* ANDS */
2948 gen_logic_CC(sf
, tcg_rd
);
2953 * C3.4.5 Move wide (immediate)
2955 * 31 30 29 28 23 22 21 20 5 4 0
2956 * +--+-----+-------------+-----+----------------+------+
2957 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2958 * +--+-----+-------------+-----+----------------+------+
2960 * sf: 0 -> 32 bit, 1 -> 64 bit
2961 * opc: 00 -> N, 10 -> Z, 11 -> K
2962 * hw: shift/16 (0,16, and sf only 32, 48)
2964 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2966 int rd
= extract32(insn
, 0, 5);
2967 uint64_t imm
= extract32(insn
, 5, 16);
2968 int sf
= extract32(insn
, 31, 1);
2969 int opc
= extract32(insn
, 29, 2);
2970 int pos
= extract32(insn
, 21, 2) << 4;
2971 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2974 if (!sf
&& (pos
>= 32)) {
2975 unallocated_encoding(s
);
2989 tcg_gen_movi_i64(tcg_rd
, imm
);
2992 tcg_imm
= tcg_const_i64(imm
);
2993 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2994 tcg_temp_free_i64(tcg_imm
);
2996 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3000 unallocated_encoding(s
);
3006 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3007 * +----+-----+-------------+---+------+------+------+------+
3008 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3009 * +----+-----+-------------+---+------+------+------+------+
3011 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3013 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3014 TCGv_i64 tcg_rd
, tcg_tmp
;
3016 sf
= extract32(insn
, 31, 1);
3017 opc
= extract32(insn
, 29, 2);
3018 n
= extract32(insn
, 22, 1);
3019 ri
= extract32(insn
, 16, 6);
3020 si
= extract32(insn
, 10, 6);
3021 rn
= extract32(insn
, 5, 5);
3022 rd
= extract32(insn
, 0, 5);
3023 bitsize
= sf
? 64 : 32;
3025 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3026 unallocated_encoding(s
);
3030 tcg_rd
= cpu_reg(s
, rd
);
3032 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3033 to be smaller than bitsize, we'll never reference data outside the
3034 low 32-bits anyway. */
3035 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3037 /* Recognize the common aliases. */
3038 if (opc
== 0) { /* SBFM */
3040 if (si
== 7) { /* SXTB */
3041 tcg_gen_ext8s_i64(tcg_rd
, tcg_tmp
);
3043 } else if (si
== 15) { /* SXTH */
3044 tcg_gen_ext16s_i64(tcg_rd
, tcg_tmp
);
3046 } else if (si
== 31) { /* SXTW */
3047 tcg_gen_ext32s_i64(tcg_rd
, tcg_tmp
);
3051 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* ASR */
3053 tcg_gen_ext32s_i64(tcg_tmp
, tcg_tmp
);
3055 tcg_gen_sari_i64(tcg_rd
, tcg_tmp
, ri
);
3058 } else if (opc
== 2) { /* UBFM */
3059 if (ri
== 0) { /* UXTB, UXTH, plus non-canonical AND */
3060 tcg_gen_andi_i64(tcg_rd
, tcg_tmp
, bitmask64(si
+ 1));
3063 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* LSR */
3065 tcg_gen_ext32u_i64(tcg_tmp
, tcg_tmp
);
3067 tcg_gen_shri_i64(tcg_rd
, tcg_tmp
, ri
);
3070 if (si
+ 1 == ri
&& si
!= bitsize
- 1) { /* LSL */
3071 int shift
= bitsize
- 1 - si
;
3072 tcg_gen_shli_i64(tcg_rd
, tcg_tmp
, shift
);
3077 if (opc
!= 1) { /* SBFM or UBFM */
3078 tcg_gen_movi_i64(tcg_rd
, 0);
3081 /* do the bit move operation */
3083 /* Wd<s-r:0> = Wn<s:r> */
3084 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3086 len
= (si
- ri
) + 1;
3088 /* Wd<32+s-r,32-r> = Wn<s:0> */
3093 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3095 if (opc
== 0) { /* SBFM - sign extend the destination field */
3096 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3097 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3101 if (!sf
) { /* zero extend final result */
3102 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3107 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3108 * +----+------+-------------+---+----+------+--------+------+------+
3109 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3110 * +----+------+-------------+---+----+------+--------+------+------+
3112 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3114 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3116 sf
= extract32(insn
, 31, 1);
3117 n
= extract32(insn
, 22, 1);
3118 rm
= extract32(insn
, 16, 5);
3119 imm
= extract32(insn
, 10, 6);
3120 rn
= extract32(insn
, 5, 5);
3121 rd
= extract32(insn
, 0, 5);
3122 op21
= extract32(insn
, 29, 2);
3123 op0
= extract32(insn
, 21, 1);
3124 bitsize
= sf
? 64 : 32;
3126 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3127 unallocated_encoding(s
);
3129 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3131 tcg_rd
= cpu_reg(s
, rd
);
3133 if (unlikely(imm
== 0)) {
3134 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3135 * so an extract from bit 0 is a special case.
3138 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3140 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3142 } else if (rm
== rn
) { /* ROR */
3143 tcg_rm
= cpu_reg(s
, rm
);
3145 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3147 TCGv_i32 tmp
= tcg_temp_new_i32();
3148 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3149 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3150 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3151 tcg_temp_free_i32(tmp
);
3154 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3155 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3156 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3157 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3158 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3160 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3166 /* C3.4 Data processing - immediate */
3167 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3169 switch (extract32(insn
, 23, 6)) {
3170 case 0x20: case 0x21: /* PC-rel. addressing */
3171 disas_pc_rel_adr(s
, insn
);
3173 case 0x22: case 0x23: /* Add/subtract (immediate) */
3174 disas_add_sub_imm(s
, insn
);
3176 case 0x24: /* Logical (immediate) */
3177 disas_logic_imm(s
, insn
);
3179 case 0x25: /* Move wide (immediate) */
3180 disas_movw_imm(s
, insn
);
3182 case 0x26: /* Bitfield */
3183 disas_bitfield(s
, insn
);
3185 case 0x27: /* Extract */
3186 disas_extract(s
, insn
);
3189 unallocated_encoding(s
);
3194 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3195 * Note that it is the caller's responsibility to ensure that the
3196 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3197 * mandated semantics for out of range shifts.
3199 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3200 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3202 switch (shift_type
) {
3203 case A64_SHIFT_TYPE_LSL
:
3204 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3206 case A64_SHIFT_TYPE_LSR
:
3207 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3209 case A64_SHIFT_TYPE_ASR
:
3211 tcg_gen_ext32s_i64(dst
, src
);
3213 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3215 case A64_SHIFT_TYPE_ROR
:
3217 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3220 t0
= tcg_temp_new_i32();
3221 t1
= tcg_temp_new_i32();
3222 tcg_gen_extrl_i64_i32(t0
, src
);
3223 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3224 tcg_gen_rotr_i32(t0
, t0
, t1
);
3225 tcg_gen_extu_i32_i64(dst
, t0
);
3226 tcg_temp_free_i32(t0
);
3227 tcg_temp_free_i32(t1
);
3231 assert(FALSE
); /* all shift types should be handled */
3235 if (!sf
) { /* zero extend final result */
3236 tcg_gen_ext32u_i64(dst
, dst
);
3240 /* Shift a TCGv src by immediate, put result in dst.
3241 * The shift amount must be in range (this should always be true as the
3242 * relevant instructions will UNDEF on bad shift immediates).
3244 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3245 enum a64_shift_type shift_type
, unsigned int shift_i
)
3247 assert(shift_i
< (sf
? 64 : 32));
3250 tcg_gen_mov_i64(dst
, src
);
3252 TCGv_i64 shift_const
;
3254 shift_const
= tcg_const_i64(shift_i
);
3255 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3256 tcg_temp_free_i64(shift_const
);
3260 /* C3.5.10 Logical (shifted register)
3261 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3262 * +----+-----+-----------+-------+---+------+--------+------+------+
3263 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3264 * +----+-----+-----------+-------+---+------+--------+------+------+
3266 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3268 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3269 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3271 sf
= extract32(insn
, 31, 1);
3272 opc
= extract32(insn
, 29, 2);
3273 shift_type
= extract32(insn
, 22, 2);
3274 invert
= extract32(insn
, 21, 1);
3275 rm
= extract32(insn
, 16, 5);
3276 shift_amount
= extract32(insn
, 10, 6);
3277 rn
= extract32(insn
, 5, 5);
3278 rd
= extract32(insn
, 0, 5);
3280 if (!sf
&& (shift_amount
& (1 << 5))) {
3281 unallocated_encoding(s
);
3285 tcg_rd
= cpu_reg(s
, rd
);
3287 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3288 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3289 * register-register MOV and MVN, so it is worth special casing.
3291 tcg_rm
= cpu_reg(s
, rm
);
3293 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3295 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3299 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3301 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3307 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3310 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3313 tcg_rn
= cpu_reg(s
, rn
);
3315 switch (opc
| (invert
<< 2)) {
3318 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3321 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3324 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3328 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3331 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3334 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3342 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3346 gen_logic_CC(sf
, tcg_rd
);
3351 * C3.5.1 Add/subtract (extended register)
3353 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3354 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3355 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3356 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3358 * sf: 0 -> 32bit, 1 -> 64bit
3359 * op: 0 -> add , 1 -> sub
3362 * option: extension type (see DecodeRegExtend)
3363 * imm3: optional shift to Rm
3365 * Rd = Rn + LSL(extend(Rm), amount)
3367 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3369 int rd
= extract32(insn
, 0, 5);
3370 int rn
= extract32(insn
, 5, 5);
3371 int imm3
= extract32(insn
, 10, 3);
3372 int option
= extract32(insn
, 13, 3);
3373 int rm
= extract32(insn
, 16, 5);
3374 bool setflags
= extract32(insn
, 29, 1);
3375 bool sub_op
= extract32(insn
, 30, 1);
3376 bool sf
= extract32(insn
, 31, 1);
3378 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3380 TCGv_i64 tcg_result
;
3383 unallocated_encoding(s
);
3387 /* non-flag setting ops may use SP */
3389 tcg_rd
= cpu_reg_sp(s
, rd
);
3391 tcg_rd
= cpu_reg(s
, rd
);
3393 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3395 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3396 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3398 tcg_result
= tcg_temp_new_i64();
3402 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3404 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3408 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3410 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3415 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3417 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3420 tcg_temp_free_i64(tcg_result
);
3424 * C3.5.2 Add/subtract (shifted register)
3426 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3427 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3428 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3429 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3431 * sf: 0 -> 32bit, 1 -> 64bit
3432 * op: 0 -> add , 1 -> sub
3434 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3435 * imm6: Shift amount to apply to Rm before the add/sub
3437 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3439 int rd
= extract32(insn
, 0, 5);
3440 int rn
= extract32(insn
, 5, 5);
3441 int imm6
= extract32(insn
, 10, 6);
3442 int rm
= extract32(insn
, 16, 5);
3443 int shift_type
= extract32(insn
, 22, 2);
3444 bool setflags
= extract32(insn
, 29, 1);
3445 bool sub_op
= extract32(insn
, 30, 1);
3446 bool sf
= extract32(insn
, 31, 1);
3448 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3449 TCGv_i64 tcg_rn
, tcg_rm
;
3450 TCGv_i64 tcg_result
;
3452 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3453 unallocated_encoding(s
);
3457 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3458 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3460 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3462 tcg_result
= tcg_temp_new_i64();
3466 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3468 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3472 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3474 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3479 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3481 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3484 tcg_temp_free_i64(tcg_result
);
3487 /* C3.5.9 Data-processing (3 source)
3489 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3490 +--+------+-----------+------+------+----+------+------+------+
3491 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3492 +--+------+-----------+------+------+----+------+------+------+
3495 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3497 int rd
= extract32(insn
, 0, 5);
3498 int rn
= extract32(insn
, 5, 5);
3499 int ra
= extract32(insn
, 10, 5);
3500 int rm
= extract32(insn
, 16, 5);
3501 int op_id
= (extract32(insn
, 29, 3) << 4) |
3502 (extract32(insn
, 21, 3) << 1) |
3503 extract32(insn
, 15, 1);
3504 bool sf
= extract32(insn
, 31, 1);
3505 bool is_sub
= extract32(op_id
, 0, 1);
3506 bool is_high
= extract32(op_id
, 2, 1);
3507 bool is_signed
= false;
3512 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3514 case 0x42: /* SMADDL */
3515 case 0x43: /* SMSUBL */
3516 case 0x44: /* SMULH */
3519 case 0x0: /* MADD (32bit) */
3520 case 0x1: /* MSUB (32bit) */
3521 case 0x40: /* MADD (64bit) */
3522 case 0x41: /* MSUB (64bit) */
3523 case 0x4a: /* UMADDL */
3524 case 0x4b: /* UMSUBL */
3525 case 0x4c: /* UMULH */
3528 unallocated_encoding(s
);
3533 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3534 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3535 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3536 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3539 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3541 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3544 tcg_temp_free_i64(low_bits
);
3548 tcg_op1
= tcg_temp_new_i64();
3549 tcg_op2
= tcg_temp_new_i64();
3550 tcg_tmp
= tcg_temp_new_i64();
3553 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3554 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3557 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3558 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3560 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3561 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3565 if (ra
== 31 && !is_sub
) {
3566 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3567 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3569 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3571 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3573 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3578 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3581 tcg_temp_free_i64(tcg_op1
);
3582 tcg_temp_free_i64(tcg_op2
);
3583 tcg_temp_free_i64(tcg_tmp
);
3586 /* C3.5.3 - Add/subtract (with carry)
3587 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3588 * +--+--+--+------------------------+------+---------+------+-----+
3589 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3590 * +--+--+--+------------------------+------+---------+------+-----+
3594 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3596 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3597 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3599 if (extract32(insn
, 10, 6) != 0) {
3600 unallocated_encoding(s
);
3604 sf
= extract32(insn
, 31, 1);
3605 op
= extract32(insn
, 30, 1);
3606 setflags
= extract32(insn
, 29, 1);
3607 rm
= extract32(insn
, 16, 5);
3608 rn
= extract32(insn
, 5, 5);
3609 rd
= extract32(insn
, 0, 5);
3611 tcg_rd
= cpu_reg(s
, rd
);
3612 tcg_rn
= cpu_reg(s
, rn
);
3615 tcg_y
= new_tmp_a64(s
);
3616 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3618 tcg_y
= cpu_reg(s
, rm
);
3622 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3624 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3628 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3629 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3630 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3631 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3632 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3635 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3637 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3638 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3639 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3642 if (!extract32(insn
, 29, 1)) {
3643 unallocated_encoding(s
);
3646 if (insn
& (1 << 10 | 1 << 4)) {
3647 unallocated_encoding(s
);
3650 sf
= extract32(insn
, 31, 1);
3651 op
= extract32(insn
, 30, 1);
3652 is_imm
= extract32(insn
, 11, 1);
3653 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3654 cond
= extract32(insn
, 12, 4);
3655 rn
= extract32(insn
, 5, 5);
3656 nzcv
= extract32(insn
, 0, 4);
3658 /* Set T0 = !COND. */
3659 tcg_t0
= tcg_temp_new_i32();
3660 arm_test_cc(&c
, cond
);
3661 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3664 /* Load the arguments for the new comparison. */
3666 tcg_y
= new_tmp_a64(s
);
3667 tcg_gen_movi_i64(tcg_y
, y
);
3669 tcg_y
= cpu_reg(s
, y
);
3671 tcg_rn
= cpu_reg(s
, rn
);
3673 /* Set the flags for the new comparison. */
3674 tcg_tmp
= tcg_temp_new_i64();
3676 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3678 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3680 tcg_temp_free_i64(tcg_tmp
);
3682 /* If COND was false, force the flags to #nzcv. Compute two masks
3683 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3684 * For tcg hosts that support ANDC, we can make do with just T1.
3685 * In either case, allow the tcg optimizer to delete any unused mask.
3687 tcg_t1
= tcg_temp_new_i32();
3688 tcg_t2
= tcg_temp_new_i32();
3689 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3690 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3692 if (nzcv
& 8) { /* N */
3693 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3695 if (TCG_TARGET_HAS_andc_i32
) {
3696 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3698 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3701 if (nzcv
& 4) { /* Z */
3702 if (TCG_TARGET_HAS_andc_i32
) {
3703 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3705 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3708 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3710 if (nzcv
& 2) { /* C */
3711 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3713 if (TCG_TARGET_HAS_andc_i32
) {
3714 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3716 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3719 if (nzcv
& 1) { /* V */
3720 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3722 if (TCG_TARGET_HAS_andc_i32
) {
3723 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3725 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3728 tcg_temp_free_i32(tcg_t0
);
3729 tcg_temp_free_i32(tcg_t1
);
3730 tcg_temp_free_i32(tcg_t2
);
3733 /* C3.5.6 Conditional select
3734 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3735 * +----+----+---+-----------------+------+------+-----+------+------+
3736 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3737 * +----+----+---+-----------------+------+------+-----+------+------+
3739 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3741 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3742 TCGv_i64 tcg_rd
, zero
;
3745 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3746 /* S == 1 or op2<1> == 1 */
3747 unallocated_encoding(s
);
3750 sf
= extract32(insn
, 31, 1);
3751 else_inv
= extract32(insn
, 30, 1);
3752 rm
= extract32(insn
, 16, 5);
3753 cond
= extract32(insn
, 12, 4);
3754 else_inc
= extract32(insn
, 10, 1);
3755 rn
= extract32(insn
, 5, 5);
3756 rd
= extract32(insn
, 0, 5);
3758 tcg_rd
= cpu_reg(s
, rd
);
3760 a64_test_cc(&c
, cond
);
3761 zero
= tcg_const_i64(0);
3763 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3765 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3767 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3770 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3771 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3772 if (else_inv
&& else_inc
) {
3773 tcg_gen_neg_i64(t_false
, t_false
);
3774 } else if (else_inv
) {
3775 tcg_gen_not_i64(t_false
, t_false
);
3776 } else if (else_inc
) {
3777 tcg_gen_addi_i64(t_false
, t_false
, 1);
3779 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3782 tcg_temp_free_i64(zero
);
3786 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3790 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3791 unsigned int rn
, unsigned int rd
)
3793 TCGv_i64 tcg_rd
, tcg_rn
;
3794 tcg_rd
= cpu_reg(s
, rd
);
3795 tcg_rn
= cpu_reg(s
, rn
);
3798 gen_helper_clz64(tcg_rd
, tcg_rn
);
3800 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3801 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3802 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3803 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3804 tcg_temp_free_i32(tcg_tmp32
);
3808 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3809 unsigned int rn
, unsigned int rd
)
3811 TCGv_i64 tcg_rd
, tcg_rn
;
3812 tcg_rd
= cpu_reg(s
, rd
);
3813 tcg_rn
= cpu_reg(s
, rn
);
3816 gen_helper_cls64(tcg_rd
, tcg_rn
);
3818 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3819 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3820 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3821 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3822 tcg_temp_free_i32(tcg_tmp32
);
3826 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3827 unsigned int rn
, unsigned int rd
)
3829 TCGv_i64 tcg_rd
, tcg_rn
;
3830 tcg_rd
= cpu_reg(s
, rd
);
3831 tcg_rn
= cpu_reg(s
, rn
);
3834 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3836 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3837 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3838 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3839 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3840 tcg_temp_free_i32(tcg_tmp32
);
3844 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3845 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3846 unsigned int rn
, unsigned int rd
)
3849 unallocated_encoding(s
);
3852 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3855 /* C5.6.149 REV with sf==0, opcode==2
3856 * C5.6.151 REV32 (sf==1, opcode==2)
3858 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3859 unsigned int rn
, unsigned int rd
)
3861 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3864 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3865 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3867 /* bswap32_i64 requires zero high word */
3868 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3869 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3870 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3871 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3872 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3874 tcg_temp_free_i64(tcg_tmp
);
3876 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3877 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3881 /* C5.6.150 REV16 (opcode==1) */
3882 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3883 unsigned int rn
, unsigned int rd
)
3885 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3886 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3887 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3889 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3890 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3892 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3893 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3894 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3895 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3898 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3899 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3900 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3901 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3903 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3904 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3905 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3908 tcg_temp_free_i64(tcg_tmp
);
3911 /* C3.5.7 Data-processing (1 source)
3912 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3913 * +----+---+---+-----------------+---------+--------+------+------+
3914 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3915 * +----+---+---+-----------------+---------+--------+------+------+
3917 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3919 unsigned int sf
, opcode
, rn
, rd
;
3921 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3922 unallocated_encoding(s
);
3926 sf
= extract32(insn
, 31, 1);
3927 opcode
= extract32(insn
, 10, 6);
3928 rn
= extract32(insn
, 5, 5);
3929 rd
= extract32(insn
, 0, 5);
3933 handle_rbit(s
, sf
, rn
, rd
);
3936 handle_rev16(s
, sf
, rn
, rd
);
3939 handle_rev32(s
, sf
, rn
, rd
);
3942 handle_rev64(s
, sf
, rn
, rd
);
3945 handle_clz(s
, sf
, rn
, rd
);
3948 handle_cls(s
, sf
, rn
, rd
);
3953 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3954 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3956 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3957 tcg_rd
= cpu_reg(s
, rd
);
3959 if (!sf
&& is_signed
) {
3960 tcg_n
= new_tmp_a64(s
);
3961 tcg_m
= new_tmp_a64(s
);
3962 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3963 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3965 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3966 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3970 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3972 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3975 if (!sf
) { /* zero extend final result */
3976 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3980 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3981 static void handle_shift_reg(DisasContext
*s
,
3982 enum a64_shift_type shift_type
, unsigned int sf
,
3983 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3985 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3986 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3987 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3989 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3990 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3991 tcg_temp_free_i64(tcg_shift
);
3994 /* CRC32[BHWX], CRC32C[BHWX] */
3995 static void handle_crc32(DisasContext
*s
,
3996 unsigned int sf
, unsigned int sz
, bool crc32c
,
3997 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3999 TCGv_i64 tcg_acc
, tcg_val
;
4002 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4003 || (sf
== 1 && sz
!= 3)
4004 || (sf
== 0 && sz
== 3)) {
4005 unallocated_encoding(s
);
4010 tcg_val
= cpu_reg(s
, rm
);
4024 g_assert_not_reached();
4026 tcg_val
= new_tmp_a64(s
);
4027 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4030 tcg_acc
= cpu_reg(s
, rn
);
4031 tcg_bytes
= tcg_const_i32(1 << sz
);
4034 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4036 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4039 tcg_temp_free_i32(tcg_bytes
);
4042 /* C3.5.8 Data-processing (2 source)
4043 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4044 * +----+---+---+-----------------+------+--------+------+------+
4045 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4046 * +----+---+---+-----------------+------+--------+------+------+
4048 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4050 unsigned int sf
, rm
, opcode
, rn
, rd
;
4051 sf
= extract32(insn
, 31, 1);
4052 rm
= extract32(insn
, 16, 5);
4053 opcode
= extract32(insn
, 10, 6);
4054 rn
= extract32(insn
, 5, 5);
4055 rd
= extract32(insn
, 0, 5);
4057 if (extract32(insn
, 29, 1)) {
4058 unallocated_encoding(s
);
4064 handle_div(s
, false, sf
, rm
, rn
, rd
);
4067 handle_div(s
, true, sf
, rm
, rn
, rd
);
4070 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4073 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4076 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4079 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4088 case 23: /* CRC32 */
4090 int sz
= extract32(opcode
, 0, 2);
4091 bool crc32c
= extract32(opcode
, 2, 1);
4092 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4096 unallocated_encoding(s
);
4101 /* C3.5 Data processing - register */
4102 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4104 switch (extract32(insn
, 24, 5)) {
4105 case 0x0a: /* Logical (shifted register) */
4106 disas_logic_reg(s
, insn
);
4108 case 0x0b: /* Add/subtract */
4109 if (insn
& (1 << 21)) { /* (extended register) */
4110 disas_add_sub_ext_reg(s
, insn
);
4112 disas_add_sub_reg(s
, insn
);
4115 case 0x1b: /* Data-processing (3 source) */
4116 disas_data_proc_3src(s
, insn
);
4119 switch (extract32(insn
, 21, 3)) {
4120 case 0x0: /* Add/subtract (with carry) */
4121 disas_adc_sbc(s
, insn
);
4123 case 0x2: /* Conditional compare */
4124 disas_cc(s
, insn
); /* both imm and reg forms */
4126 case 0x4: /* Conditional select */
4127 disas_cond_select(s
, insn
);
4129 case 0x6: /* Data-processing */
4130 if (insn
& (1 << 30)) { /* (1 source) */
4131 disas_data_proc_1src(s
, insn
);
4132 } else { /* (2 source) */
4133 disas_data_proc_2src(s
, insn
);
4137 unallocated_encoding(s
);
4142 unallocated_encoding(s
);
4147 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4148 unsigned int rn
, unsigned int rm
,
4149 bool cmp_with_zero
, bool signal_all_nans
)
4151 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4152 TCGv_ptr fpst
= get_fpstatus_ptr();
4155 TCGv_i64 tcg_vn
, tcg_vm
;
4157 tcg_vn
= read_fp_dreg(s
, rn
);
4158 if (cmp_with_zero
) {
4159 tcg_vm
= tcg_const_i64(0);
4161 tcg_vm
= read_fp_dreg(s
, rm
);
4163 if (signal_all_nans
) {
4164 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4166 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4168 tcg_temp_free_i64(tcg_vn
);
4169 tcg_temp_free_i64(tcg_vm
);
4171 TCGv_i32 tcg_vn
, tcg_vm
;
4173 tcg_vn
= read_fp_sreg(s
, rn
);
4174 if (cmp_with_zero
) {
4175 tcg_vm
= tcg_const_i32(0);
4177 tcg_vm
= read_fp_sreg(s
, rm
);
4179 if (signal_all_nans
) {
4180 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4182 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4184 tcg_temp_free_i32(tcg_vn
);
4185 tcg_temp_free_i32(tcg_vm
);
4188 tcg_temp_free_ptr(fpst
);
4190 gen_set_nzcv(tcg_flags
);
4192 tcg_temp_free_i64(tcg_flags
);
4195 /* C3.6.22 Floating point compare
4196 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4197 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4198 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4199 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4201 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4203 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4205 mos
= extract32(insn
, 29, 3);
4206 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4207 rm
= extract32(insn
, 16, 5);
4208 op
= extract32(insn
, 14, 2);
4209 rn
= extract32(insn
, 5, 5);
4210 opc
= extract32(insn
, 3, 2);
4211 op2r
= extract32(insn
, 0, 3);
4213 if (mos
|| op
|| op2r
|| type
> 1) {
4214 unallocated_encoding(s
);
4218 if (!fp_access_check(s
)) {
4222 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4225 /* C3.6.23 Floating point conditional compare
4226 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4227 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4228 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4229 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4231 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4233 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4235 TCGLabel
*label_continue
= NULL
;
4237 mos
= extract32(insn
, 29, 3);
4238 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4239 rm
= extract32(insn
, 16, 5);
4240 cond
= extract32(insn
, 12, 4);
4241 rn
= extract32(insn
, 5, 5);
4242 op
= extract32(insn
, 4, 1);
4243 nzcv
= extract32(insn
, 0, 4);
4245 if (mos
|| type
> 1) {
4246 unallocated_encoding(s
);
4250 if (!fp_access_check(s
)) {
4254 if (cond
< 0x0e) { /* not always */
4255 TCGLabel
*label_match
= gen_new_label();
4256 label_continue
= gen_new_label();
4257 arm_gen_test_cc(cond
, label_match
);
4259 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4260 gen_set_nzcv(tcg_flags
);
4261 tcg_temp_free_i64(tcg_flags
);
4262 tcg_gen_br(label_continue
);
4263 gen_set_label(label_match
);
4266 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4269 gen_set_label(label_continue
);
4273 /* C3.6.24 Floating point conditional select
4274 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4275 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4276 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4277 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4279 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4281 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4282 TCGv_i64 t_true
, t_false
, t_zero
;
4285 mos
= extract32(insn
, 29, 3);
4286 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4287 rm
= extract32(insn
, 16, 5);
4288 cond
= extract32(insn
, 12, 4);
4289 rn
= extract32(insn
, 5, 5);
4290 rd
= extract32(insn
, 0, 5);
4292 if (mos
|| type
> 1) {
4293 unallocated_encoding(s
);
4297 if (!fp_access_check(s
)) {
4301 /* Zero extend sreg inputs to 64 bits now. */
4302 t_true
= tcg_temp_new_i64();
4303 t_false
= tcg_temp_new_i64();
4304 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4305 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4307 a64_test_cc(&c
, cond
);
4308 t_zero
= tcg_const_i64(0);
4309 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4310 tcg_temp_free_i64(t_zero
);
4311 tcg_temp_free_i64(t_false
);
4314 /* Note that sregs write back zeros to the high bits,
4315 and we've already done the zero-extension. */
4316 write_fp_dreg(s
, rd
, t_true
);
4317 tcg_temp_free_i64(t_true
);
4320 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4321 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4327 fpst
= get_fpstatus_ptr();
4328 tcg_op
= read_fp_sreg(s
, rn
);
4329 tcg_res
= tcg_temp_new_i32();
4332 case 0x0: /* FMOV */
4333 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4335 case 0x1: /* FABS */
4336 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4338 case 0x2: /* FNEG */
4339 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4341 case 0x3: /* FSQRT */
4342 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4344 case 0x8: /* FRINTN */
4345 case 0x9: /* FRINTP */
4346 case 0xa: /* FRINTM */
4347 case 0xb: /* FRINTZ */
4348 case 0xc: /* FRINTA */
4350 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4352 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4353 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4355 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4356 tcg_temp_free_i32(tcg_rmode
);
4359 case 0xe: /* FRINTX */
4360 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4362 case 0xf: /* FRINTI */
4363 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4369 write_fp_sreg(s
, rd
, tcg_res
);
4371 tcg_temp_free_ptr(fpst
);
4372 tcg_temp_free_i32(tcg_op
);
4373 tcg_temp_free_i32(tcg_res
);
4376 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4377 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4383 fpst
= get_fpstatus_ptr();
4384 tcg_op
= read_fp_dreg(s
, rn
);
4385 tcg_res
= tcg_temp_new_i64();
4388 case 0x0: /* FMOV */
4389 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4391 case 0x1: /* FABS */
4392 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4394 case 0x2: /* FNEG */
4395 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4397 case 0x3: /* FSQRT */
4398 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4400 case 0x8: /* FRINTN */
4401 case 0x9: /* FRINTP */
4402 case 0xa: /* FRINTM */
4403 case 0xb: /* FRINTZ */
4404 case 0xc: /* FRINTA */
4406 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4408 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4409 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4411 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4412 tcg_temp_free_i32(tcg_rmode
);
4415 case 0xe: /* FRINTX */
4416 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4418 case 0xf: /* FRINTI */
4419 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4425 write_fp_dreg(s
, rd
, tcg_res
);
4427 tcg_temp_free_ptr(fpst
);
4428 tcg_temp_free_i64(tcg_op
);
4429 tcg_temp_free_i64(tcg_res
);
4432 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4433 int rd
, int rn
, int dtype
, int ntype
)
4438 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4440 /* Single to double */
4441 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4442 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4443 write_fp_dreg(s
, rd
, tcg_rd
);
4444 tcg_temp_free_i64(tcg_rd
);
4446 /* Single to half */
4447 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4448 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4449 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4450 write_fp_sreg(s
, rd
, tcg_rd
);
4451 tcg_temp_free_i32(tcg_rd
);
4453 tcg_temp_free_i32(tcg_rn
);
4458 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4459 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4461 /* Double to single */
4462 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4464 /* Double to half */
4465 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4466 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4468 write_fp_sreg(s
, rd
, tcg_rd
);
4469 tcg_temp_free_i32(tcg_rd
);
4470 tcg_temp_free_i64(tcg_rn
);
4475 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4476 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4478 /* Half to single */
4479 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4480 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4481 write_fp_sreg(s
, rd
, tcg_rd
);
4482 tcg_temp_free_i32(tcg_rd
);
4484 /* Half to double */
4485 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4486 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4487 write_fp_dreg(s
, rd
, tcg_rd
);
4488 tcg_temp_free_i64(tcg_rd
);
4490 tcg_temp_free_i32(tcg_rn
);
4498 /* C3.6.25 Floating point data-processing (1 source)
4499 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4500 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4501 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4502 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4504 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4506 int type
= extract32(insn
, 22, 2);
4507 int opcode
= extract32(insn
, 15, 6);
4508 int rn
= extract32(insn
, 5, 5);
4509 int rd
= extract32(insn
, 0, 5);
4512 case 0x4: case 0x5: case 0x7:
4514 /* FCVT between half, single and double precision */
4515 int dtype
= extract32(opcode
, 0, 2);
4516 if (type
== 2 || dtype
== type
) {
4517 unallocated_encoding(s
);
4520 if (!fp_access_check(s
)) {
4524 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4530 /* 32-to-32 and 64-to-64 ops */
4533 if (!fp_access_check(s
)) {
4537 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4540 if (!fp_access_check(s
)) {
4544 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4547 unallocated_encoding(s
);
4551 unallocated_encoding(s
);
4556 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4557 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4558 int rd
, int rn
, int rm
)
4565 tcg_res
= tcg_temp_new_i32();
4566 fpst
= get_fpstatus_ptr();
4567 tcg_op1
= read_fp_sreg(s
, rn
);
4568 tcg_op2
= read_fp_sreg(s
, rm
);
4571 case 0x0: /* FMUL */
4572 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4574 case 0x1: /* FDIV */
4575 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4577 case 0x2: /* FADD */
4578 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4580 case 0x3: /* FSUB */
4581 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4583 case 0x4: /* FMAX */
4584 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4586 case 0x5: /* FMIN */
4587 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4589 case 0x6: /* FMAXNM */
4590 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4592 case 0x7: /* FMINNM */
4593 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4595 case 0x8: /* FNMUL */
4596 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4597 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4601 write_fp_sreg(s
, rd
, tcg_res
);
4603 tcg_temp_free_ptr(fpst
);
4604 tcg_temp_free_i32(tcg_op1
);
4605 tcg_temp_free_i32(tcg_op2
);
4606 tcg_temp_free_i32(tcg_res
);
4609 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4610 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4611 int rd
, int rn
, int rm
)
4618 tcg_res
= tcg_temp_new_i64();
4619 fpst
= get_fpstatus_ptr();
4620 tcg_op1
= read_fp_dreg(s
, rn
);
4621 tcg_op2
= read_fp_dreg(s
, rm
);
4624 case 0x0: /* FMUL */
4625 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4627 case 0x1: /* FDIV */
4628 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4630 case 0x2: /* FADD */
4631 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4633 case 0x3: /* FSUB */
4634 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4636 case 0x4: /* FMAX */
4637 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4639 case 0x5: /* FMIN */
4640 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4642 case 0x6: /* FMAXNM */
4643 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4645 case 0x7: /* FMINNM */
4646 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4648 case 0x8: /* FNMUL */
4649 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4650 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4654 write_fp_dreg(s
, rd
, tcg_res
);
4656 tcg_temp_free_ptr(fpst
);
4657 tcg_temp_free_i64(tcg_op1
);
4658 tcg_temp_free_i64(tcg_op2
);
4659 tcg_temp_free_i64(tcg_res
);
4662 /* C3.6.26 Floating point data-processing (2 source)
4663 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4664 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4665 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4666 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4668 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4670 int type
= extract32(insn
, 22, 2);
4671 int rd
= extract32(insn
, 0, 5);
4672 int rn
= extract32(insn
, 5, 5);
4673 int rm
= extract32(insn
, 16, 5);
4674 int opcode
= extract32(insn
, 12, 4);
4677 unallocated_encoding(s
);
4683 if (!fp_access_check(s
)) {
4686 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4689 if (!fp_access_check(s
)) {
4692 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4695 unallocated_encoding(s
);
4699 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4700 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4701 int rd
, int rn
, int rm
, int ra
)
4703 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4704 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4705 TCGv_ptr fpst
= get_fpstatus_ptr();
4707 tcg_op1
= read_fp_sreg(s
, rn
);
4708 tcg_op2
= read_fp_sreg(s
, rm
);
4709 tcg_op3
= read_fp_sreg(s
, ra
);
4711 /* These are fused multiply-add, and must be done as one
4712 * floating point operation with no rounding between the
4713 * multiplication and addition steps.
4714 * NB that doing the negations here as separate steps is
4715 * correct : an input NaN should come out with its sign bit
4716 * flipped if it is a negated-input.
4719 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4723 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4726 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4728 write_fp_sreg(s
, rd
, tcg_res
);
4730 tcg_temp_free_ptr(fpst
);
4731 tcg_temp_free_i32(tcg_op1
);
4732 tcg_temp_free_i32(tcg_op2
);
4733 tcg_temp_free_i32(tcg_op3
);
4734 tcg_temp_free_i32(tcg_res
);
4737 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4738 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4739 int rd
, int rn
, int rm
, int ra
)
4741 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4742 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4743 TCGv_ptr fpst
= get_fpstatus_ptr();
4745 tcg_op1
= read_fp_dreg(s
, rn
);
4746 tcg_op2
= read_fp_dreg(s
, rm
);
4747 tcg_op3
= read_fp_dreg(s
, ra
);
4749 /* These are fused multiply-add, and must be done as one
4750 * floating point operation with no rounding between the
4751 * multiplication and addition steps.
4752 * NB that doing the negations here as separate steps is
4753 * correct : an input NaN should come out with its sign bit
4754 * flipped if it is a negated-input.
4757 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4761 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4764 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4766 write_fp_dreg(s
, rd
, tcg_res
);
4768 tcg_temp_free_ptr(fpst
);
4769 tcg_temp_free_i64(tcg_op1
);
4770 tcg_temp_free_i64(tcg_op2
);
4771 tcg_temp_free_i64(tcg_op3
);
4772 tcg_temp_free_i64(tcg_res
);
4775 /* C3.6.27 Floating point data-processing (3 source)
4776 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4777 * +---+---+---+-----------+------+----+------+----+------+------+------+
4778 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4779 * +---+---+---+-----------+------+----+------+----+------+------+------+
4781 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4783 int type
= extract32(insn
, 22, 2);
4784 int rd
= extract32(insn
, 0, 5);
4785 int rn
= extract32(insn
, 5, 5);
4786 int ra
= extract32(insn
, 10, 5);
4787 int rm
= extract32(insn
, 16, 5);
4788 bool o0
= extract32(insn
, 15, 1);
4789 bool o1
= extract32(insn
, 21, 1);
4793 if (!fp_access_check(s
)) {
4796 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4799 if (!fp_access_check(s
)) {
4802 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4805 unallocated_encoding(s
);
4809 /* C3.6.28 Floating point immediate
4810 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4811 * +---+---+---+-----------+------+---+------------+-------+------+------+
4812 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4813 * +---+---+---+-----------+------+---+------------+-------+------+------+
4815 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4817 int rd
= extract32(insn
, 0, 5);
4818 int imm8
= extract32(insn
, 13, 8);
4819 int is_double
= extract32(insn
, 22, 2);
4823 if (is_double
> 1) {
4824 unallocated_encoding(s
);
4828 if (!fp_access_check(s
)) {
4832 /* The imm8 encodes the sign bit, enough bits to represent
4833 * an exponent in the range 01....1xx to 10....0xx,
4834 * and the most significant 4 bits of the mantissa; see
4835 * VFPExpandImm() in the v8 ARM ARM.
4838 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4839 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4840 extract32(imm8
, 0, 6);
4843 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4844 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4845 (extract32(imm8
, 0, 6) << 3);
4849 tcg_res
= tcg_const_i64(imm
);
4850 write_fp_dreg(s
, rd
, tcg_res
);
4851 tcg_temp_free_i64(tcg_res
);
4854 /* Handle floating point <=> fixed point conversions. Note that we can
4855 * also deal with fp <=> integer conversions as a special case (scale == 64)
4856 * OPTME: consider handling that special case specially or at least skipping
4857 * the call to scalbn in the helpers for zero shifts.
4859 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4860 bool itof
, int rmode
, int scale
, int sf
, int type
)
4862 bool is_signed
= !(opcode
& 1);
4863 bool is_double
= type
;
4864 TCGv_ptr tcg_fpstatus
;
4867 tcg_fpstatus
= get_fpstatus_ptr();
4869 tcg_shift
= tcg_const_i32(64 - scale
);
4872 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4874 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4877 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4879 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4882 tcg_int
= tcg_extend
;
4886 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4888 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4889 tcg_shift
, tcg_fpstatus
);
4891 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4892 tcg_shift
, tcg_fpstatus
);
4894 write_fp_dreg(s
, rd
, tcg_double
);
4895 tcg_temp_free_i64(tcg_double
);
4897 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4899 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4900 tcg_shift
, tcg_fpstatus
);
4902 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4903 tcg_shift
, tcg_fpstatus
);
4905 write_fp_sreg(s
, rd
, tcg_single
);
4906 tcg_temp_free_i32(tcg_single
);
4909 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4912 if (extract32(opcode
, 2, 1)) {
4913 /* There are too many rounding modes to all fit into rmode,
4914 * so FCVTA[US] is a special case.
4916 rmode
= FPROUNDING_TIEAWAY
;
4919 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4921 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4924 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4927 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4928 tcg_shift
, tcg_fpstatus
);
4930 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4931 tcg_shift
, tcg_fpstatus
);
4935 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4936 tcg_shift
, tcg_fpstatus
);
4938 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4939 tcg_shift
, tcg_fpstatus
);
4942 tcg_temp_free_i64(tcg_double
);
4944 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4947 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4948 tcg_shift
, tcg_fpstatus
);
4950 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4951 tcg_shift
, tcg_fpstatus
);
4954 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4956 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4957 tcg_shift
, tcg_fpstatus
);
4959 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4960 tcg_shift
, tcg_fpstatus
);
4962 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4963 tcg_temp_free_i32(tcg_dest
);
4965 tcg_temp_free_i32(tcg_single
);
4968 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4969 tcg_temp_free_i32(tcg_rmode
);
4972 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4976 tcg_temp_free_ptr(tcg_fpstatus
);
4977 tcg_temp_free_i32(tcg_shift
);
4980 /* C3.6.29 Floating point <-> fixed point conversions
4981 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4982 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4983 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4984 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4986 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4988 int rd
= extract32(insn
, 0, 5);
4989 int rn
= extract32(insn
, 5, 5);
4990 int scale
= extract32(insn
, 10, 6);
4991 int opcode
= extract32(insn
, 16, 3);
4992 int rmode
= extract32(insn
, 19, 2);
4993 int type
= extract32(insn
, 22, 2);
4994 bool sbit
= extract32(insn
, 29, 1);
4995 bool sf
= extract32(insn
, 31, 1);
4998 if (sbit
|| (type
> 1)
4999 || (!sf
&& scale
< 32)) {
5000 unallocated_encoding(s
);
5004 switch ((rmode
<< 3) | opcode
) {
5005 case 0x2: /* SCVTF */
5006 case 0x3: /* UCVTF */
5009 case 0x18: /* FCVTZS */
5010 case 0x19: /* FCVTZU */
5014 unallocated_encoding(s
);
5018 if (!fp_access_check(s
)) {
5022 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5025 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5027 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5028 * without conversion.
5032 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5038 TCGv_i64 tmp
= tcg_temp_new_i64();
5039 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5040 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5041 tcg_gen_movi_i64(tmp
, 0);
5042 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5043 tcg_temp_free_i64(tmp
);
5049 TCGv_i64 tmp
= tcg_const_i64(0);
5050 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5051 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5052 tcg_temp_free_i64(tmp
);
5056 /* 64 bit to top half. */
5057 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5061 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5066 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5070 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5073 /* 64 bits from top half */
5074 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5080 /* C3.6.30 Floating point <-> integer conversions
5081 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5082 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5083 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5084 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5086 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5088 int rd
= extract32(insn
, 0, 5);
5089 int rn
= extract32(insn
, 5, 5);
5090 int opcode
= extract32(insn
, 16, 3);
5091 int rmode
= extract32(insn
, 19, 2);
5092 int type
= extract32(insn
, 22, 2);
5093 bool sbit
= extract32(insn
, 29, 1);
5094 bool sf
= extract32(insn
, 31, 1);
5097 unallocated_encoding(s
);
5103 bool itof
= opcode
& 1;
5106 unallocated_encoding(s
);
5110 switch (sf
<< 3 | type
<< 1 | rmode
) {
5111 case 0x0: /* 32 bit */
5112 case 0xa: /* 64 bit */
5113 case 0xd: /* 64 bit to top half of quad */
5116 /* all other sf/type/rmode combinations are invalid */
5117 unallocated_encoding(s
);
5121 if (!fp_access_check(s
)) {
5124 handle_fmov(s
, rd
, rn
, type
, itof
);
5126 /* actual FP conversions */
5127 bool itof
= extract32(opcode
, 1, 1);
5129 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5130 unallocated_encoding(s
);
5134 if (!fp_access_check(s
)) {
5137 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5141 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5142 * 31 30 29 28 25 24 0
5143 * +---+---+---+---------+-----------------------------+
5144 * | | 0 | | 1 1 1 1 | |
5145 * +---+---+---+---------+-----------------------------+
5147 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5149 if (extract32(insn
, 24, 1)) {
5150 /* Floating point data-processing (3 source) */
5151 disas_fp_3src(s
, insn
);
5152 } else if (extract32(insn
, 21, 1) == 0) {
5153 /* Floating point to fixed point conversions */
5154 disas_fp_fixed_conv(s
, insn
);
5156 switch (extract32(insn
, 10, 2)) {
5158 /* Floating point conditional compare */
5159 disas_fp_ccomp(s
, insn
);
5162 /* Floating point data-processing (2 source) */
5163 disas_fp_2src(s
, insn
);
5166 /* Floating point conditional select */
5167 disas_fp_csel(s
, insn
);
5170 switch (ctz32(extract32(insn
, 12, 4))) {
5171 case 0: /* [15:12] == xxx1 */
5172 /* Floating point immediate */
5173 disas_fp_imm(s
, insn
);
5175 case 1: /* [15:12] == xx10 */
5176 /* Floating point compare */
5177 disas_fp_compare(s
, insn
);
5179 case 2: /* [15:12] == x100 */
5180 /* Floating point data-processing (1 source) */
5181 disas_fp_1src(s
, insn
);
5183 case 3: /* [15:12] == 1000 */
5184 unallocated_encoding(s
);
5186 default: /* [15:12] == 0000 */
5187 /* Floating point <-> integer conversions */
5188 disas_fp_int_conv(s
, insn
);
5196 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5199 /* Extract 64 bits from the middle of two concatenated 64 bit
5200 * vector register slices left:right. The extracted bits start
5201 * at 'pos' bits into the right (least significant) side.
5202 * We return the result in tcg_right, and guarantee not to
5205 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5206 assert(pos
> 0 && pos
< 64);
5208 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5209 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5210 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5212 tcg_temp_free_i64(tcg_tmp
);
5216 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5217 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5218 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5219 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5221 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5223 int is_q
= extract32(insn
, 30, 1);
5224 int op2
= extract32(insn
, 22, 2);
5225 int imm4
= extract32(insn
, 11, 4);
5226 int rm
= extract32(insn
, 16, 5);
5227 int rn
= extract32(insn
, 5, 5);
5228 int rd
= extract32(insn
, 0, 5);
5229 int pos
= imm4
<< 3;
5230 TCGv_i64 tcg_resl
, tcg_resh
;
5232 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5233 unallocated_encoding(s
);
5237 if (!fp_access_check(s
)) {
5241 tcg_resh
= tcg_temp_new_i64();
5242 tcg_resl
= tcg_temp_new_i64();
5244 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5245 * either extracting 128 bits from a 128:128 concatenation, or
5246 * extracting 64 bits from a 64:64 concatenation.
5249 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5251 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5252 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5254 tcg_gen_movi_i64(tcg_resh
, 0);
5261 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5262 EltPosns
*elt
= eltposns
;
5269 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5271 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5274 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5275 tcg_hh
= tcg_temp_new_i64();
5276 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5277 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5278 tcg_temp_free_i64(tcg_hh
);
5282 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5283 tcg_temp_free_i64(tcg_resl
);
5284 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5285 tcg_temp_free_i64(tcg_resh
);
5289 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5290 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5291 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5292 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5294 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5296 int op2
= extract32(insn
, 22, 2);
5297 int is_q
= extract32(insn
, 30, 1);
5298 int rm
= extract32(insn
, 16, 5);
5299 int rn
= extract32(insn
, 5, 5);
5300 int rd
= extract32(insn
, 0, 5);
5301 int is_tblx
= extract32(insn
, 12, 1);
5302 int len
= extract32(insn
, 13, 2);
5303 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5304 TCGv_i32 tcg_regno
, tcg_numregs
;
5307 unallocated_encoding(s
);
5311 if (!fp_access_check(s
)) {
5315 /* This does a table lookup: for every byte element in the input
5316 * we index into a table formed from up to four vector registers,
5317 * and then the output is the result of the lookups. Our helper
5318 * function does the lookup operation for a single 64 bit part of
5321 tcg_resl
= tcg_temp_new_i64();
5322 tcg_resh
= tcg_temp_new_i64();
5325 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5327 tcg_gen_movi_i64(tcg_resl
, 0);
5329 if (is_tblx
&& is_q
) {
5330 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5332 tcg_gen_movi_i64(tcg_resh
, 0);
5335 tcg_idx
= tcg_temp_new_i64();
5336 tcg_regno
= tcg_const_i32(rn
);
5337 tcg_numregs
= tcg_const_i32(len
+ 1);
5338 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5339 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5340 tcg_regno
, tcg_numregs
);
5342 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5343 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5344 tcg_regno
, tcg_numregs
);
5346 tcg_temp_free_i64(tcg_idx
);
5347 tcg_temp_free_i32(tcg_regno
);
5348 tcg_temp_free_i32(tcg_numregs
);
5350 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5351 tcg_temp_free_i64(tcg_resl
);
5352 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5353 tcg_temp_free_i64(tcg_resh
);
5356 /* C3.6.3 ZIP/UZP/TRN
5357 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5358 * +---+---+-------------+------+---+------+---+------------------+------+
5359 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5360 * +---+---+-------------+------+---+------+---+------------------+------+
5362 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5364 int rd
= extract32(insn
, 0, 5);
5365 int rn
= extract32(insn
, 5, 5);
5366 int rm
= extract32(insn
, 16, 5);
5367 int size
= extract32(insn
, 22, 2);
5368 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5369 * bit 2 indicates 1 vs 2 variant of the insn.
5371 int opcode
= extract32(insn
, 12, 2);
5372 bool part
= extract32(insn
, 14, 1);
5373 bool is_q
= extract32(insn
, 30, 1);
5374 int esize
= 8 << size
;
5376 int datasize
= is_q
? 128 : 64;
5377 int elements
= datasize
/ esize
;
5378 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5380 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5381 unallocated_encoding(s
);
5385 if (!fp_access_check(s
)) {
5389 tcg_resl
= tcg_const_i64(0);
5390 tcg_resh
= tcg_const_i64(0);
5391 tcg_res
= tcg_temp_new_i64();
5393 for (i
= 0; i
< elements
; i
++) {
5395 case 1: /* UZP1/2 */
5397 int midpoint
= elements
/ 2;
5399 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5401 read_vec_element(s
, tcg_res
, rm
,
5402 2 * (i
- midpoint
) + part
, size
);
5406 case 2: /* TRN1/2 */
5408 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5410 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5413 case 3: /* ZIP1/2 */
5415 int base
= part
* elements
/ 2;
5417 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5419 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5424 g_assert_not_reached();
5429 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5430 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5432 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5433 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5437 tcg_temp_free_i64(tcg_res
);
5439 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5440 tcg_temp_free_i64(tcg_resl
);
5441 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5442 tcg_temp_free_i64(tcg_resh
);
5445 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5446 int opc
, bool is_min
, TCGv_ptr fpst
)
5448 /* Helper function for disas_simd_across_lanes: do a single precision
5449 * min/max operation on the specified two inputs,
5450 * and return the result in tcg_elt1.
5454 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5456 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5461 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5463 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5468 /* C3.6.4 AdvSIMD across lanes
5469 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5470 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5471 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5472 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5474 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5476 int rd
= extract32(insn
, 0, 5);
5477 int rn
= extract32(insn
, 5, 5);
5478 int size
= extract32(insn
, 22, 2);
5479 int opcode
= extract32(insn
, 12, 5);
5480 bool is_q
= extract32(insn
, 30, 1);
5481 bool is_u
= extract32(insn
, 29, 1);
5483 bool is_min
= false;
5487 TCGv_i64 tcg_res
, tcg_elt
;
5490 case 0x1b: /* ADDV */
5492 unallocated_encoding(s
);
5496 case 0x3: /* SADDLV, UADDLV */
5497 case 0xa: /* SMAXV, UMAXV */
5498 case 0x1a: /* SMINV, UMINV */
5499 if (size
== 3 || (size
== 2 && !is_q
)) {
5500 unallocated_encoding(s
);
5504 case 0xc: /* FMAXNMV, FMINNMV */
5505 case 0xf: /* FMAXV, FMINV */
5506 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5507 unallocated_encoding(s
);
5510 /* Bit 1 of size field encodes min vs max, and actual size is always
5511 * 32 bits: adjust the size variable so following code can rely on it
5513 is_min
= extract32(size
, 1, 1);
5518 unallocated_encoding(s
);
5522 if (!fp_access_check(s
)) {
5527 elements
= (is_q
? 128 : 64) / esize
;
5529 tcg_res
= tcg_temp_new_i64();
5530 tcg_elt
= tcg_temp_new_i64();
5532 /* These instructions operate across all lanes of a vector
5533 * to produce a single result. We can guarantee that a 64
5534 * bit intermediate is sufficient:
5535 * + for [US]ADDLV the maximum element size is 32 bits, and
5536 * the result type is 64 bits
5537 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5538 * same as the element size, which is 32 bits at most
5539 * For the integer operations we can choose to work at 64
5540 * or 32 bits and truncate at the end; for simplicity
5541 * we use 64 bits always. The floating point
5542 * ops do require 32 bit intermediates, though.
5545 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5547 for (i
= 1; i
< elements
; i
++) {
5548 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5551 case 0x03: /* SADDLV / UADDLV */
5552 case 0x1b: /* ADDV */
5553 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5555 case 0x0a: /* SMAXV / UMAXV */
5556 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5558 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5560 case 0x1a: /* SMINV / UMINV */
5561 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5563 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5567 g_assert_not_reached();
5572 /* Floating point ops which work on 32 bit (single) intermediates.
5573 * Note that correct NaN propagation requires that we do these
5574 * operations in exactly the order specified by the pseudocode.
5576 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5577 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5578 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5579 TCGv_ptr fpst
= get_fpstatus_ptr();
5581 assert(esize
== 32);
5582 assert(elements
== 4);
5584 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5585 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5586 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5587 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5589 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5591 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5592 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5593 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5594 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5596 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5598 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5600 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5601 tcg_temp_free_i32(tcg_elt1
);
5602 tcg_temp_free_i32(tcg_elt2
);
5603 tcg_temp_free_i32(tcg_elt3
);
5604 tcg_temp_free_ptr(fpst
);
5607 tcg_temp_free_i64(tcg_elt
);
5609 /* Now truncate the result to the width required for the final output */
5610 if (opcode
== 0x03) {
5611 /* SADDLV, UADDLV: result is 2*esize */
5617 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5620 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5623 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5628 g_assert_not_reached();
5631 write_fp_dreg(s
, rd
, tcg_res
);
5632 tcg_temp_free_i64(tcg_res
);
5635 /* C6.3.31 DUP (Element, Vector)
5637 * 31 30 29 21 20 16 15 10 9 5 4 0
5638 * +---+---+-------------------+--------+-------------+------+------+
5639 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5640 * +---+---+-------------------+--------+-------------+------+------+
5642 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5644 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5647 int size
= ctz32(imm5
);
5648 int esize
= 8 << size
;
5649 int elements
= (is_q
? 128 : 64) / esize
;
5653 if (size
> 3 || (size
== 3 && !is_q
)) {
5654 unallocated_encoding(s
);
5658 if (!fp_access_check(s
)) {
5662 index
= imm5
>> (size
+ 1);
5664 tmp
= tcg_temp_new_i64();
5665 read_vec_element(s
, tmp
, rn
, index
, size
);
5667 for (i
= 0; i
< elements
; i
++) {
5668 write_vec_element(s
, tmp
, rd
, i
, size
);
5672 clear_vec_high(s
, rd
);
5675 tcg_temp_free_i64(tmp
);
5678 /* C6.3.31 DUP (element, scalar)
5679 * 31 21 20 16 15 10 9 5 4 0
5680 * +-----------------------+--------+-------------+------+------+
5681 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5682 * +-----------------------+--------+-------------+------+------+
5684 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5687 int size
= ctz32(imm5
);
5692 unallocated_encoding(s
);
5696 if (!fp_access_check(s
)) {
5700 index
= imm5
>> (size
+ 1);
5702 /* This instruction just extracts the specified element and
5703 * zero-extends it into the bottom of the destination register.
5705 tmp
= tcg_temp_new_i64();
5706 read_vec_element(s
, tmp
, rn
, index
, size
);
5707 write_fp_dreg(s
, rd
, tmp
);
5708 tcg_temp_free_i64(tmp
);
5711 /* C6.3.32 DUP (General)
5713 * 31 30 29 21 20 16 15 10 9 5 4 0
5714 * +---+---+-------------------+--------+-------------+------+------+
5715 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5716 * +---+---+-------------------+--------+-------------+------+------+
5718 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5720 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5723 int size
= ctz32(imm5
);
5724 int esize
= 8 << size
;
5725 int elements
= (is_q
? 128 : 64)/esize
;
5728 if (size
> 3 || ((size
== 3) && !is_q
)) {
5729 unallocated_encoding(s
);
5733 if (!fp_access_check(s
)) {
5737 for (i
= 0; i
< elements
; i
++) {
5738 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5741 clear_vec_high(s
, rd
);
5745 /* C6.3.150 INS (Element)
5747 * 31 21 20 16 15 14 11 10 9 5 4 0
5748 * +-----------------------+--------+------------+---+------+------+
5749 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5750 * +-----------------------+--------+------------+---+------+------+
5752 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5753 * index: encoded in imm5<4:size+1>
5755 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5758 int size
= ctz32(imm5
);
5759 int src_index
, dst_index
;
5763 unallocated_encoding(s
);
5767 if (!fp_access_check(s
)) {
5771 dst_index
= extract32(imm5
, 1+size
, 5);
5772 src_index
= extract32(imm4
, size
, 4);
5774 tmp
= tcg_temp_new_i64();
5776 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5777 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5779 tcg_temp_free_i64(tmp
);
5783 /* C6.3.151 INS (General)
5785 * 31 21 20 16 15 10 9 5 4 0
5786 * +-----------------------+--------+-------------+------+------+
5787 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5788 * +-----------------------+--------+-------------+------+------+
5790 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5791 * index: encoded in imm5<4:size+1>
5793 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5795 int size
= ctz32(imm5
);
5799 unallocated_encoding(s
);
5803 if (!fp_access_check(s
)) {
5807 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5808 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5812 * C6.3.321 UMOV (General)
5813 * C6.3.237 SMOV (General)
5815 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5816 * +---+---+-------------------+--------+-------------+------+------+
5817 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5818 * +---+---+-------------------+--------+-------------+------+------+
5820 * U: unsigned when set
5821 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5823 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5824 int rn
, int rd
, int imm5
)
5826 int size
= ctz32(imm5
);
5830 /* Check for UnallocatedEncodings */
5832 if (size
> 2 || (size
== 2 && !is_q
)) {
5833 unallocated_encoding(s
);
5838 || (size
< 3 && is_q
)
5839 || (size
== 3 && !is_q
)) {
5840 unallocated_encoding(s
);
5845 if (!fp_access_check(s
)) {
5849 element
= extract32(imm5
, 1+size
, 4);
5851 tcg_rd
= cpu_reg(s
, rd
);
5852 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5853 if (is_signed
&& !is_q
) {
5854 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5858 /* C3.6.5 AdvSIMD copy
5859 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5860 * +---+---+----+-----------------+------+---+------+---+------+------+
5861 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5862 * +---+---+----+-----------------+------+---+------+---+------+------+
5864 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5866 int rd
= extract32(insn
, 0, 5);
5867 int rn
= extract32(insn
, 5, 5);
5868 int imm4
= extract32(insn
, 11, 4);
5869 int op
= extract32(insn
, 29, 1);
5870 int is_q
= extract32(insn
, 30, 1);
5871 int imm5
= extract32(insn
, 16, 5);
5876 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5878 unallocated_encoding(s
);
5883 /* DUP (element - vector) */
5884 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5888 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5893 handle_simd_insg(s
, rd
, rn
, imm5
);
5895 unallocated_encoding(s
);
5900 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5901 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5904 unallocated_encoding(s
);
5910 /* C3.6.6 AdvSIMD modified immediate
5911 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5912 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5913 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5914 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5916 * There are a number of operations that can be carried out here:
5917 * MOVI - move (shifted) imm into register
5918 * MVNI - move inverted (shifted) imm into register
5919 * ORR - bitwise OR of (shifted) imm with register
5920 * BIC - bitwise clear of (shifted) imm with register
5922 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5924 int rd
= extract32(insn
, 0, 5);
5925 int cmode
= extract32(insn
, 12, 4);
5926 int cmode_3_1
= extract32(cmode
, 1, 3);
5927 int cmode_0
= extract32(cmode
, 0, 1);
5928 int o2
= extract32(insn
, 11, 1);
5929 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5930 bool is_neg
= extract32(insn
, 29, 1);
5931 bool is_q
= extract32(insn
, 30, 1);
5933 TCGv_i64 tcg_rd
, tcg_imm
;
5936 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5937 unallocated_encoding(s
);
5941 if (!fp_access_check(s
)) {
5945 /* See AdvSIMDExpandImm() in ARM ARM */
5946 switch (cmode_3_1
) {
5947 case 0: /* Replicate(Zeros(24):imm8, 2) */
5948 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5949 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5950 case 3: /* Replicate(imm8:Zeros(24), 2) */
5952 int shift
= cmode_3_1
* 8;
5953 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5956 case 4: /* Replicate(Zeros(8):imm8, 4) */
5957 case 5: /* Replicate(imm8:Zeros(8), 4) */
5959 int shift
= (cmode_3_1
& 0x1) * 8;
5960 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5965 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5966 imm
= (abcdefgh
<< 16) | 0xffff;
5968 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5969 imm
= (abcdefgh
<< 8) | 0xff;
5971 imm
= bitfield_replicate(imm
, 32);
5974 if (!cmode_0
&& !is_neg
) {
5975 imm
= bitfield_replicate(abcdefgh
, 8);
5976 } else if (!cmode_0
&& is_neg
) {
5979 for (i
= 0; i
< 8; i
++) {
5980 if ((abcdefgh
) & (1 << i
)) {
5981 imm
|= 0xffULL
<< (i
* 8);
5984 } else if (cmode_0
) {
5986 imm
= (abcdefgh
& 0x3f) << 48;
5987 if (abcdefgh
& 0x80) {
5988 imm
|= 0x8000000000000000ULL
;
5990 if (abcdefgh
& 0x40) {
5991 imm
|= 0x3fc0000000000000ULL
;
5993 imm
|= 0x4000000000000000ULL
;
5996 imm
= (abcdefgh
& 0x3f) << 19;
5997 if (abcdefgh
& 0x80) {
6000 if (abcdefgh
& 0x40) {
6011 if (cmode_3_1
!= 7 && is_neg
) {
6015 tcg_imm
= tcg_const_i64(imm
);
6016 tcg_rd
= new_tmp_a64(s
);
6018 for (i
= 0; i
< 2; i
++) {
6019 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6021 if (i
== 1 && !is_q
) {
6022 /* non-quad ops clear high half of vector */
6023 tcg_gen_movi_i64(tcg_rd
, 0);
6024 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6025 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6028 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6031 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6035 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6037 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6040 tcg_temp_free_i64(tcg_imm
);
6043 /* C3.6.7 AdvSIMD scalar copy
6044 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6045 * +-----+----+-----------------+------+---+------+---+------+------+
6046 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6047 * +-----+----+-----------------+------+---+------+---+------+------+
6049 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6051 int rd
= extract32(insn
, 0, 5);
6052 int rn
= extract32(insn
, 5, 5);
6053 int imm4
= extract32(insn
, 11, 4);
6054 int imm5
= extract32(insn
, 16, 5);
6055 int op
= extract32(insn
, 29, 1);
6057 if (op
!= 0 || imm4
!= 0) {
6058 unallocated_encoding(s
);
6062 /* DUP (element, scalar) */
6063 handle_simd_dupes(s
, rd
, rn
, imm5
);
6066 /* C3.6.8 AdvSIMD scalar pairwise
6067 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6068 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6069 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6070 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6072 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6074 int u
= extract32(insn
, 29, 1);
6075 int size
= extract32(insn
, 22, 2);
6076 int opcode
= extract32(insn
, 12, 5);
6077 int rn
= extract32(insn
, 5, 5);
6078 int rd
= extract32(insn
, 0, 5);
6081 /* For some ops (the FP ones), size[1] is part of the encoding.
6082 * For ADDP strictly it is not but size[1] is always 1 for valid
6085 opcode
|= (extract32(size
, 1, 1) << 5);
6088 case 0x3b: /* ADDP */
6089 if (u
|| size
!= 3) {
6090 unallocated_encoding(s
);
6093 if (!fp_access_check(s
)) {
6097 TCGV_UNUSED_PTR(fpst
);
6099 case 0xc: /* FMAXNMP */
6100 case 0xd: /* FADDP */
6101 case 0xf: /* FMAXP */
6102 case 0x2c: /* FMINNMP */
6103 case 0x2f: /* FMINP */
6104 /* FP op, size[0] is 32 or 64 bit */
6106 unallocated_encoding(s
);
6109 if (!fp_access_check(s
)) {
6113 size
= extract32(size
, 0, 1) ? 3 : 2;
6114 fpst
= get_fpstatus_ptr();
6117 unallocated_encoding(s
);
6122 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6123 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6124 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6126 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6127 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6130 case 0x3b: /* ADDP */
6131 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6133 case 0xc: /* FMAXNMP */
6134 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6136 case 0xd: /* FADDP */
6137 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6139 case 0xf: /* FMAXP */
6140 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6142 case 0x2c: /* FMINNMP */
6143 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6145 case 0x2f: /* FMINP */
6146 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6149 g_assert_not_reached();
6152 write_fp_dreg(s
, rd
, tcg_res
);
6154 tcg_temp_free_i64(tcg_op1
);
6155 tcg_temp_free_i64(tcg_op2
);
6156 tcg_temp_free_i64(tcg_res
);
6158 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6159 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6160 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6162 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6163 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6166 case 0xc: /* FMAXNMP */
6167 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6169 case 0xd: /* FADDP */
6170 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6172 case 0xf: /* FMAXP */
6173 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6175 case 0x2c: /* FMINNMP */
6176 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6178 case 0x2f: /* FMINP */
6179 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6182 g_assert_not_reached();
6185 write_fp_sreg(s
, rd
, tcg_res
);
6187 tcg_temp_free_i32(tcg_op1
);
6188 tcg_temp_free_i32(tcg_op2
);
6189 tcg_temp_free_i32(tcg_res
);
6192 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6193 tcg_temp_free_ptr(fpst
);
6198 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6200 * This code is handles the common shifting code and is used by both
6201 * the vector and scalar code.
6203 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6204 TCGv_i64 tcg_rnd
, bool accumulate
,
6205 bool is_u
, int size
, int shift
)
6207 bool extended_result
= false;
6208 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6210 TCGv_i64 tcg_src_hi
;
6212 if (round
&& size
== 3) {
6213 extended_result
= true;
6214 ext_lshift
= 64 - shift
;
6215 tcg_src_hi
= tcg_temp_new_i64();
6216 } else if (shift
== 64) {
6217 if (!accumulate
&& is_u
) {
6218 /* result is zero */
6219 tcg_gen_movi_i64(tcg_res
, 0);
6224 /* Deal with the rounding step */
6226 if (extended_result
) {
6227 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6229 /* take care of sign extending tcg_res */
6230 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6231 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6232 tcg_src
, tcg_src_hi
,
6235 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6239 tcg_temp_free_i64(tcg_zero
);
6241 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6245 /* Now do the shift right */
6246 if (round
&& extended_result
) {
6247 /* extended case, >64 bit precision required */
6248 if (ext_lshift
== 0) {
6249 /* special case, only high bits matter */
6250 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6252 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6253 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6254 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6259 /* essentially shifting in 64 zeros */
6260 tcg_gen_movi_i64(tcg_src
, 0);
6262 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6266 /* effectively extending the sign-bit */
6267 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6269 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6275 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6277 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6280 if (extended_result
) {
6281 tcg_temp_free_i64(tcg_src_hi
);
6285 /* Common SHL/SLI - Shift left with an optional insert */
6286 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6287 bool insert
, int shift
)
6289 if (insert
) { /* SLI */
6290 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6292 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6296 /* SRI: shift right with insert */
6297 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6298 int size
, int shift
)
6300 int esize
= 8 << size
;
6302 /* shift count same as element size is valid but does nothing;
6303 * special case to avoid potential shift by 64.
6305 if (shift
!= esize
) {
6306 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6307 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6311 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6312 static void handle_scalar_simd_shri(DisasContext
*s
,
6313 bool is_u
, int immh
, int immb
,
6314 int opcode
, int rn
, int rd
)
6317 int immhb
= immh
<< 3 | immb
;
6318 int shift
= 2 * (8 << size
) - immhb
;
6319 bool accumulate
= false;
6321 bool insert
= false;
6326 if (!extract32(immh
, 3, 1)) {
6327 unallocated_encoding(s
);
6331 if (!fp_access_check(s
)) {
6336 case 0x02: /* SSRA / USRA (accumulate) */
6339 case 0x04: /* SRSHR / URSHR (rounding) */
6342 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6343 accumulate
= round
= true;
6345 case 0x08: /* SRI */
6351 uint64_t round_const
= 1ULL << (shift
- 1);
6352 tcg_round
= tcg_const_i64(round_const
);
6354 TCGV_UNUSED_I64(tcg_round
);
6357 tcg_rn
= read_fp_dreg(s
, rn
);
6358 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6361 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6363 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6364 accumulate
, is_u
, size
, shift
);
6367 write_fp_dreg(s
, rd
, tcg_rd
);
6369 tcg_temp_free_i64(tcg_rn
);
6370 tcg_temp_free_i64(tcg_rd
);
6372 tcg_temp_free_i64(tcg_round
);
6376 /* SHL/SLI - Scalar shift left */
6377 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6378 int immh
, int immb
, int opcode
,
6381 int size
= 32 - clz32(immh
) - 1;
6382 int immhb
= immh
<< 3 | immb
;
6383 int shift
= immhb
- (8 << size
);
6384 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6385 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6387 if (!extract32(immh
, 3, 1)) {
6388 unallocated_encoding(s
);
6392 if (!fp_access_check(s
)) {
6396 tcg_rn
= read_fp_dreg(s
, rn
);
6397 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6399 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6401 write_fp_dreg(s
, rd
, tcg_rd
);
6403 tcg_temp_free_i64(tcg_rn
);
6404 tcg_temp_free_i64(tcg_rd
);
6407 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6408 * (signed/unsigned) narrowing */
6409 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6410 bool is_u_shift
, bool is_u_narrow
,
6411 int immh
, int immb
, int opcode
,
6414 int immhb
= immh
<< 3 | immb
;
6415 int size
= 32 - clz32(immh
) - 1;
6416 int esize
= 8 << size
;
6417 int shift
= (2 * esize
) - immhb
;
6418 int elements
= is_scalar
? 1 : (64 / esize
);
6419 bool round
= extract32(opcode
, 0, 1);
6420 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6421 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6422 TCGv_i32 tcg_rd_narrowed
;
6425 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6426 { gen_helper_neon_narrow_sat_s8
,
6427 gen_helper_neon_unarrow_sat8
},
6428 { gen_helper_neon_narrow_sat_s16
,
6429 gen_helper_neon_unarrow_sat16
},
6430 { gen_helper_neon_narrow_sat_s32
,
6431 gen_helper_neon_unarrow_sat32
},
6434 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6435 gen_helper_neon_narrow_sat_u8
,
6436 gen_helper_neon_narrow_sat_u16
,
6437 gen_helper_neon_narrow_sat_u32
,
6440 NeonGenNarrowEnvFn
*narrowfn
;
6446 if (extract32(immh
, 3, 1)) {
6447 unallocated_encoding(s
);
6451 if (!fp_access_check(s
)) {
6456 narrowfn
= unsigned_narrow_fns
[size
];
6458 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6461 tcg_rn
= tcg_temp_new_i64();
6462 tcg_rd
= tcg_temp_new_i64();
6463 tcg_rd_narrowed
= tcg_temp_new_i32();
6464 tcg_final
= tcg_const_i64(0);
6467 uint64_t round_const
= 1ULL << (shift
- 1);
6468 tcg_round
= tcg_const_i64(round_const
);
6470 TCGV_UNUSED_I64(tcg_round
);
6473 for (i
= 0; i
< elements
; i
++) {
6474 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6475 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6476 false, is_u_shift
, size
+1, shift
);
6477 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6478 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6479 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6483 clear_vec_high(s
, rd
);
6484 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6486 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6490 tcg_temp_free_i64(tcg_round
);
6492 tcg_temp_free_i64(tcg_rn
);
6493 tcg_temp_free_i64(tcg_rd
);
6494 tcg_temp_free_i32(tcg_rd_narrowed
);
6495 tcg_temp_free_i64(tcg_final
);
6499 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6500 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6501 bool src_unsigned
, bool dst_unsigned
,
6502 int immh
, int immb
, int rn
, int rd
)
6504 int immhb
= immh
<< 3 | immb
;
6505 int size
= 32 - clz32(immh
) - 1;
6506 int shift
= immhb
- (8 << size
);
6510 assert(!(scalar
&& is_q
));
6513 if (!is_q
&& extract32(immh
, 3, 1)) {
6514 unallocated_encoding(s
);
6518 /* Since we use the variable-shift helpers we must
6519 * replicate the shift count into each element of
6520 * the tcg_shift value.
6524 shift
|= shift
<< 8;
6527 shift
|= shift
<< 16;
6533 g_assert_not_reached();
6537 if (!fp_access_check(s
)) {
6542 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6543 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6544 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6545 { NULL
, gen_helper_neon_qshl_u64
},
6547 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6548 int maxpass
= is_q
? 2 : 1;
6550 for (pass
= 0; pass
< maxpass
; pass
++) {
6551 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6553 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6554 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6555 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6557 tcg_temp_free_i64(tcg_op
);
6559 tcg_temp_free_i64(tcg_shift
);
6562 clear_vec_high(s
, rd
);
6565 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6566 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6568 { gen_helper_neon_qshl_s8
,
6569 gen_helper_neon_qshl_s16
,
6570 gen_helper_neon_qshl_s32
},
6571 { gen_helper_neon_qshlu_s8
,
6572 gen_helper_neon_qshlu_s16
,
6573 gen_helper_neon_qshlu_s32
}
6575 { NULL
, NULL
, NULL
},
6576 { gen_helper_neon_qshl_u8
,
6577 gen_helper_neon_qshl_u16
,
6578 gen_helper_neon_qshl_u32
}
6581 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6582 TCGMemOp memop
= scalar
? size
: MO_32
;
6583 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6585 for (pass
= 0; pass
< maxpass
; pass
++) {
6586 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6588 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6589 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6593 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6596 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6601 g_assert_not_reached();
6603 write_fp_sreg(s
, rd
, tcg_op
);
6605 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6608 tcg_temp_free_i32(tcg_op
);
6610 tcg_temp_free_i32(tcg_shift
);
6612 if (!is_q
&& !scalar
) {
6613 clear_vec_high(s
, rd
);
6618 /* Common vector code for handling integer to FP conversion */
6619 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6620 int elements
, int is_signed
,
6621 int fracbits
, int size
)
6623 bool is_double
= size
== 3 ? true : false;
6624 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6625 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6626 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6627 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6630 for (pass
= 0; pass
< elements
; pass
++) {
6631 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6634 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6636 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6637 tcg_shift
, tcg_fpst
);
6639 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6640 tcg_shift
, tcg_fpst
);
6642 if (elements
== 1) {
6643 write_fp_dreg(s
, rd
, tcg_double
);
6645 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6647 tcg_temp_free_i64(tcg_double
);
6649 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6651 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6652 tcg_shift
, tcg_fpst
);
6654 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6655 tcg_shift
, tcg_fpst
);
6657 if (elements
== 1) {
6658 write_fp_sreg(s
, rd
, tcg_single
);
6660 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6662 tcg_temp_free_i32(tcg_single
);
6666 if (!is_double
&& elements
== 2) {
6667 clear_vec_high(s
, rd
);
6670 tcg_temp_free_i64(tcg_int
);
6671 tcg_temp_free_ptr(tcg_fpst
);
6672 tcg_temp_free_i32(tcg_shift
);
6675 /* UCVTF/SCVTF - Integer to FP conversion */
6676 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6677 bool is_q
, bool is_u
,
6678 int immh
, int immb
, int opcode
,
6681 bool is_double
= extract32(immh
, 3, 1);
6682 int size
= is_double
? MO_64
: MO_32
;
6684 int immhb
= immh
<< 3 | immb
;
6685 int fracbits
= (is_double
? 128 : 64) - immhb
;
6687 if (!extract32(immh
, 2, 2)) {
6688 unallocated_encoding(s
);
6695 elements
= is_double
? 2 : is_q
? 4 : 2;
6696 if (is_double
&& !is_q
) {
6697 unallocated_encoding(s
);
6702 if (!fp_access_check(s
)) {
6706 /* immh == 0 would be a failure of the decode logic */
6709 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6712 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6713 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6714 bool is_q
, bool is_u
,
6715 int immh
, int immb
, int rn
, int rd
)
6717 bool is_double
= extract32(immh
, 3, 1);
6718 int immhb
= immh
<< 3 | immb
;
6719 int fracbits
= (is_double
? 128 : 64) - immhb
;
6721 TCGv_ptr tcg_fpstatus
;
6722 TCGv_i32 tcg_rmode
, tcg_shift
;
6724 if (!extract32(immh
, 2, 2)) {
6725 unallocated_encoding(s
);
6729 if (!is_scalar
&& !is_q
&& is_double
) {
6730 unallocated_encoding(s
);
6734 if (!fp_access_check(s
)) {
6738 assert(!(is_scalar
&& is_q
));
6740 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6741 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6742 tcg_fpstatus
= get_fpstatus_ptr();
6743 tcg_shift
= tcg_const_i32(fracbits
);
6746 int maxpass
= is_scalar
? 1 : 2;
6748 for (pass
= 0; pass
< maxpass
; pass
++) {
6749 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6751 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6753 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6755 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6757 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6758 tcg_temp_free_i64(tcg_op
);
6761 clear_vec_high(s
, rd
);
6764 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6765 for (pass
= 0; pass
< maxpass
; pass
++) {
6766 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6768 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6770 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6772 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6775 write_fp_sreg(s
, rd
, tcg_op
);
6777 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6779 tcg_temp_free_i32(tcg_op
);
6781 if (!is_q
&& !is_scalar
) {
6782 clear_vec_high(s
, rd
);
6786 tcg_temp_free_ptr(tcg_fpstatus
);
6787 tcg_temp_free_i32(tcg_shift
);
6788 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6789 tcg_temp_free_i32(tcg_rmode
);
6792 /* C3.6.9 AdvSIMD scalar shift by immediate
6793 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6794 * +-----+---+-------------+------+------+--------+---+------+------+
6795 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6796 * +-----+---+-------------+------+------+--------+---+------+------+
6798 * This is the scalar version so it works on a fixed sized registers
6800 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6802 int rd
= extract32(insn
, 0, 5);
6803 int rn
= extract32(insn
, 5, 5);
6804 int opcode
= extract32(insn
, 11, 5);
6805 int immb
= extract32(insn
, 16, 3);
6806 int immh
= extract32(insn
, 19, 4);
6807 bool is_u
= extract32(insn
, 29, 1);
6810 unallocated_encoding(s
);
6815 case 0x08: /* SRI */
6817 unallocated_encoding(s
);
6821 case 0x00: /* SSHR / USHR */
6822 case 0x02: /* SSRA / USRA */
6823 case 0x04: /* SRSHR / URSHR */
6824 case 0x06: /* SRSRA / URSRA */
6825 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6827 case 0x0a: /* SHL / SLI */
6828 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6830 case 0x1c: /* SCVTF, UCVTF */
6831 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6834 case 0x10: /* SQSHRUN, SQSHRUN2 */
6835 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6837 unallocated_encoding(s
);
6840 handle_vec_simd_sqshrn(s
, true, false, false, true,
6841 immh
, immb
, opcode
, rn
, rd
);
6843 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6844 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6845 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6846 immh
, immb
, opcode
, rn
, rd
);
6848 case 0xc: /* SQSHLU */
6850 unallocated_encoding(s
);
6853 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6855 case 0xe: /* SQSHL, UQSHL */
6856 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6858 case 0x1f: /* FCVTZS, FCVTZU */
6859 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6862 unallocated_encoding(s
);
6867 /* C3.6.10 AdvSIMD scalar three different
6868 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6869 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6870 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6871 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6873 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6875 bool is_u
= extract32(insn
, 29, 1);
6876 int size
= extract32(insn
, 22, 2);
6877 int opcode
= extract32(insn
, 12, 4);
6878 int rm
= extract32(insn
, 16, 5);
6879 int rn
= extract32(insn
, 5, 5);
6880 int rd
= extract32(insn
, 0, 5);
6883 unallocated_encoding(s
);
6888 case 0x9: /* SQDMLAL, SQDMLAL2 */
6889 case 0xb: /* SQDMLSL, SQDMLSL2 */
6890 case 0xd: /* SQDMULL, SQDMULL2 */
6891 if (size
== 0 || size
== 3) {
6892 unallocated_encoding(s
);
6897 unallocated_encoding(s
);
6901 if (!fp_access_check(s
)) {
6906 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6907 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6908 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6910 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6911 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6913 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6914 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6917 case 0xd: /* SQDMULL, SQDMULL2 */
6919 case 0xb: /* SQDMLSL, SQDMLSL2 */
6920 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6922 case 0x9: /* SQDMLAL, SQDMLAL2 */
6923 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6924 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6928 g_assert_not_reached();
6931 write_fp_dreg(s
, rd
, tcg_res
);
6933 tcg_temp_free_i64(tcg_op1
);
6934 tcg_temp_free_i64(tcg_op2
);
6935 tcg_temp_free_i64(tcg_res
);
6937 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6938 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6939 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6941 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6942 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6944 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6945 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6948 case 0xd: /* SQDMULL, SQDMULL2 */
6950 case 0xb: /* SQDMLSL, SQDMLSL2 */
6951 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6953 case 0x9: /* SQDMLAL, SQDMLAL2 */
6955 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6956 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6957 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6959 tcg_temp_free_i64(tcg_op3
);
6963 g_assert_not_reached();
6966 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6967 write_fp_dreg(s
, rd
, tcg_res
);
6969 tcg_temp_free_i32(tcg_op1
);
6970 tcg_temp_free_i32(tcg_op2
);
6971 tcg_temp_free_i64(tcg_res
);
6975 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6976 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6978 /* Handle 64x64->64 opcodes which are shared between the scalar
6979 * and vector 3-same groups. We cover every opcode where size == 3
6980 * is valid in either the three-reg-same (integer, not pairwise)
6981 * or scalar-three-reg-same groups. (Some opcodes are not yet
6987 case 0x1: /* SQADD */
6989 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6991 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6994 case 0x5: /* SQSUB */
6996 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6998 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7001 case 0x6: /* CMGT, CMHI */
7002 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7003 * We implement this using setcond (test) and then negating.
7005 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7007 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7008 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7010 case 0x7: /* CMGE, CMHS */
7011 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7013 case 0x11: /* CMTST, CMEQ */
7018 /* CMTST : test is "if (X & Y != 0)". */
7019 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7020 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7021 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7023 case 0x8: /* SSHL, USHL */
7025 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7027 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7030 case 0x9: /* SQSHL, UQSHL */
7032 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7034 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7037 case 0xa: /* SRSHL, URSHL */
7039 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7041 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7044 case 0xb: /* SQRSHL, UQRSHL */
7046 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7048 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7051 case 0x10: /* ADD, SUB */
7053 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7055 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7059 g_assert_not_reached();
7063 /* Handle the 3-same-operands float operations; shared by the scalar
7064 * and vector encodings. The caller must filter out any encodings
7065 * not allocated for the encoding it is dealing with.
7067 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7068 int fpopcode
, int rd
, int rn
, int rm
)
7071 TCGv_ptr fpst
= get_fpstatus_ptr();
7073 for (pass
= 0; pass
< elements
; pass
++) {
7076 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7077 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7078 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7080 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7081 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7084 case 0x39: /* FMLS */
7085 /* As usual for ARM, separate negation for fused multiply-add */
7086 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7088 case 0x19: /* FMLA */
7089 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7090 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7093 case 0x18: /* FMAXNM */
7094 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7096 case 0x1a: /* FADD */
7097 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7099 case 0x1b: /* FMULX */
7100 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7102 case 0x1c: /* FCMEQ */
7103 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7105 case 0x1e: /* FMAX */
7106 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7108 case 0x1f: /* FRECPS */
7109 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7111 case 0x38: /* FMINNM */
7112 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7114 case 0x3a: /* FSUB */
7115 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7117 case 0x3e: /* FMIN */
7118 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7120 case 0x3f: /* FRSQRTS */
7121 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7123 case 0x5b: /* FMUL */
7124 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7126 case 0x5c: /* FCMGE */
7127 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7129 case 0x5d: /* FACGE */
7130 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7132 case 0x5f: /* FDIV */
7133 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7135 case 0x7a: /* FABD */
7136 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7137 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7139 case 0x7c: /* FCMGT */
7140 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7142 case 0x7d: /* FACGT */
7143 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7146 g_assert_not_reached();
7149 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7151 tcg_temp_free_i64(tcg_res
);
7152 tcg_temp_free_i64(tcg_op1
);
7153 tcg_temp_free_i64(tcg_op2
);
7156 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7157 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7158 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7160 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7161 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7164 case 0x39: /* FMLS */
7165 /* As usual for ARM, separate negation for fused multiply-add */
7166 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7168 case 0x19: /* FMLA */
7169 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7170 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7173 case 0x1a: /* FADD */
7174 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7176 case 0x1b: /* FMULX */
7177 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7179 case 0x1c: /* FCMEQ */
7180 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7182 case 0x1e: /* FMAX */
7183 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7185 case 0x1f: /* FRECPS */
7186 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7188 case 0x18: /* FMAXNM */
7189 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7191 case 0x38: /* FMINNM */
7192 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7194 case 0x3a: /* FSUB */
7195 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7197 case 0x3e: /* FMIN */
7198 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7200 case 0x3f: /* FRSQRTS */
7201 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7203 case 0x5b: /* FMUL */
7204 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7206 case 0x5c: /* FCMGE */
7207 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7209 case 0x5d: /* FACGE */
7210 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7212 case 0x5f: /* FDIV */
7213 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7215 case 0x7a: /* FABD */
7216 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7217 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7219 case 0x7c: /* FCMGT */
7220 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7222 case 0x7d: /* FACGT */
7223 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7226 g_assert_not_reached();
7229 if (elements
== 1) {
7230 /* scalar single so clear high part */
7231 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7233 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7234 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7235 tcg_temp_free_i64(tcg_tmp
);
7237 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7240 tcg_temp_free_i32(tcg_res
);
7241 tcg_temp_free_i32(tcg_op1
);
7242 tcg_temp_free_i32(tcg_op2
);
7246 tcg_temp_free_ptr(fpst
);
7248 if ((elements
<< size
) < 4) {
7249 /* scalar, or non-quad vector op */
7250 clear_vec_high(s
, rd
);
7254 /* C3.6.11 AdvSIMD scalar three same
7255 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7256 * +-----+---+-----------+------+---+------+--------+---+------+------+
7257 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7258 * +-----+---+-----------+------+---+------+--------+---+------+------+
7260 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7262 int rd
= extract32(insn
, 0, 5);
7263 int rn
= extract32(insn
, 5, 5);
7264 int opcode
= extract32(insn
, 11, 5);
7265 int rm
= extract32(insn
, 16, 5);
7266 int size
= extract32(insn
, 22, 2);
7267 bool u
= extract32(insn
, 29, 1);
7270 if (opcode
>= 0x18) {
7271 /* Floating point: U, size[1] and opcode indicate operation */
7272 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7274 case 0x1b: /* FMULX */
7275 case 0x1f: /* FRECPS */
7276 case 0x3f: /* FRSQRTS */
7277 case 0x5d: /* FACGE */
7278 case 0x7d: /* FACGT */
7279 case 0x1c: /* FCMEQ */
7280 case 0x5c: /* FCMGE */
7281 case 0x7c: /* FCMGT */
7282 case 0x7a: /* FABD */
7285 unallocated_encoding(s
);
7289 if (!fp_access_check(s
)) {
7293 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7298 case 0x1: /* SQADD, UQADD */
7299 case 0x5: /* SQSUB, UQSUB */
7300 case 0x9: /* SQSHL, UQSHL */
7301 case 0xb: /* SQRSHL, UQRSHL */
7303 case 0x8: /* SSHL, USHL */
7304 case 0xa: /* SRSHL, URSHL */
7305 case 0x6: /* CMGT, CMHI */
7306 case 0x7: /* CMGE, CMHS */
7307 case 0x11: /* CMTST, CMEQ */
7308 case 0x10: /* ADD, SUB (vector) */
7310 unallocated_encoding(s
);
7314 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7315 if (size
!= 1 && size
!= 2) {
7316 unallocated_encoding(s
);
7321 unallocated_encoding(s
);
7325 if (!fp_access_check(s
)) {
7329 tcg_rd
= tcg_temp_new_i64();
7332 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7333 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7335 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7336 tcg_temp_free_i64(tcg_rn
);
7337 tcg_temp_free_i64(tcg_rm
);
7339 /* Do a single operation on the lowest element in the vector.
7340 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7341 * no side effects for all these operations.
7342 * OPTME: special-purpose helpers would avoid doing some
7343 * unnecessary work in the helper for the 8 and 16 bit cases.
7345 NeonGenTwoOpEnvFn
*genenvfn
;
7346 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7347 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7348 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7350 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7351 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7354 case 0x1: /* SQADD, UQADD */
7356 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7357 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7358 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7359 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7361 genenvfn
= fns
[size
][u
];
7364 case 0x5: /* SQSUB, UQSUB */
7366 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7367 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7368 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7369 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7371 genenvfn
= fns
[size
][u
];
7374 case 0x9: /* SQSHL, UQSHL */
7376 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7377 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7378 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7379 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7381 genenvfn
= fns
[size
][u
];
7384 case 0xb: /* SQRSHL, UQRSHL */
7386 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7387 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7388 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7389 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7391 genenvfn
= fns
[size
][u
];
7394 case 0x16: /* SQDMULH, SQRDMULH */
7396 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7397 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7398 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7400 assert(size
== 1 || size
== 2);
7401 genenvfn
= fns
[size
- 1][u
];
7405 g_assert_not_reached();
7408 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7409 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7410 tcg_temp_free_i32(tcg_rd32
);
7411 tcg_temp_free_i32(tcg_rn
);
7412 tcg_temp_free_i32(tcg_rm
);
7415 write_fp_dreg(s
, rd
, tcg_rd
);
7417 tcg_temp_free_i64(tcg_rd
);
7420 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7421 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7422 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7424 /* Handle 64->64 opcodes which are shared between the scalar and
7425 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7426 * is valid in either group and also the double-precision fp ops.
7427 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7433 case 0x4: /* CLS, CLZ */
7435 gen_helper_clz64(tcg_rd
, tcg_rn
);
7437 gen_helper_cls64(tcg_rd
, tcg_rn
);
7441 /* This opcode is shared with CNT and RBIT but we have earlier
7442 * enforced that size == 3 if and only if this is the NOT insn.
7444 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7446 case 0x7: /* SQABS, SQNEG */
7448 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7450 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7453 case 0xa: /* CMLT */
7454 /* 64 bit integer comparison against zero, result is
7455 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7460 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7461 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7463 case 0x8: /* CMGT, CMGE */
7464 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7466 case 0x9: /* CMEQ, CMLE */
7467 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7469 case 0xb: /* ABS, NEG */
7471 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7473 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7474 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7475 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7477 tcg_temp_free_i64(tcg_zero
);
7480 case 0x2f: /* FABS */
7481 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7483 case 0x6f: /* FNEG */
7484 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7486 case 0x7f: /* FSQRT */
7487 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7489 case 0x1a: /* FCVTNS */
7490 case 0x1b: /* FCVTMS */
7491 case 0x1c: /* FCVTAS */
7492 case 0x3a: /* FCVTPS */
7493 case 0x3b: /* FCVTZS */
7495 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7496 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7497 tcg_temp_free_i32(tcg_shift
);
7500 case 0x5a: /* FCVTNU */
7501 case 0x5b: /* FCVTMU */
7502 case 0x5c: /* FCVTAU */
7503 case 0x7a: /* FCVTPU */
7504 case 0x7b: /* FCVTZU */
7506 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7507 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7508 tcg_temp_free_i32(tcg_shift
);
7511 case 0x18: /* FRINTN */
7512 case 0x19: /* FRINTM */
7513 case 0x38: /* FRINTP */
7514 case 0x39: /* FRINTZ */
7515 case 0x58: /* FRINTA */
7516 case 0x79: /* FRINTI */
7517 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7519 case 0x59: /* FRINTX */
7520 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7523 g_assert_not_reached();
7527 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7528 bool is_scalar
, bool is_u
, bool is_q
,
7529 int size
, int rn
, int rd
)
7531 bool is_double
= (size
== 3);
7534 if (!fp_access_check(s
)) {
7538 fpst
= get_fpstatus_ptr();
7541 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7542 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7543 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7544 NeonGenTwoDoubleOPFn
*genfn
;
7549 case 0x2e: /* FCMLT (zero) */
7552 case 0x2c: /* FCMGT (zero) */
7553 genfn
= gen_helper_neon_cgt_f64
;
7555 case 0x2d: /* FCMEQ (zero) */
7556 genfn
= gen_helper_neon_ceq_f64
;
7558 case 0x6d: /* FCMLE (zero) */
7561 case 0x6c: /* FCMGE (zero) */
7562 genfn
= gen_helper_neon_cge_f64
;
7565 g_assert_not_reached();
7568 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7569 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7571 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7573 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7575 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7578 clear_vec_high(s
, rd
);
7581 tcg_temp_free_i64(tcg_res
);
7582 tcg_temp_free_i64(tcg_zero
);
7583 tcg_temp_free_i64(tcg_op
);
7585 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7586 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7587 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7588 NeonGenTwoSingleOPFn
*genfn
;
7590 int pass
, maxpasses
;
7593 case 0x2e: /* FCMLT (zero) */
7596 case 0x2c: /* FCMGT (zero) */
7597 genfn
= gen_helper_neon_cgt_f32
;
7599 case 0x2d: /* FCMEQ (zero) */
7600 genfn
= gen_helper_neon_ceq_f32
;
7602 case 0x6d: /* FCMLE (zero) */
7605 case 0x6c: /* FCMGE (zero) */
7606 genfn
= gen_helper_neon_cge_f32
;
7609 g_assert_not_reached();
7615 maxpasses
= is_q
? 4 : 2;
7618 for (pass
= 0; pass
< maxpasses
; pass
++) {
7619 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7621 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7623 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7626 write_fp_sreg(s
, rd
, tcg_res
);
7628 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7631 tcg_temp_free_i32(tcg_res
);
7632 tcg_temp_free_i32(tcg_zero
);
7633 tcg_temp_free_i32(tcg_op
);
7634 if (!is_q
&& !is_scalar
) {
7635 clear_vec_high(s
, rd
);
7639 tcg_temp_free_ptr(fpst
);
7642 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7643 bool is_scalar
, bool is_u
, bool is_q
,
7644 int size
, int rn
, int rd
)
7646 bool is_double
= (size
== 3);
7647 TCGv_ptr fpst
= get_fpstatus_ptr();
7650 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7651 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7654 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7655 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7657 case 0x3d: /* FRECPE */
7658 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7660 case 0x3f: /* FRECPX */
7661 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7663 case 0x7d: /* FRSQRTE */
7664 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7667 g_assert_not_reached();
7669 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7672 clear_vec_high(s
, rd
);
7675 tcg_temp_free_i64(tcg_res
);
7676 tcg_temp_free_i64(tcg_op
);
7678 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7679 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7680 int pass
, maxpasses
;
7685 maxpasses
= is_q
? 4 : 2;
7688 for (pass
= 0; pass
< maxpasses
; pass
++) {
7689 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7692 case 0x3c: /* URECPE */
7693 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7695 case 0x3d: /* FRECPE */
7696 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7698 case 0x3f: /* FRECPX */
7699 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7701 case 0x7d: /* FRSQRTE */
7702 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7705 g_assert_not_reached();
7709 write_fp_sreg(s
, rd
, tcg_res
);
7711 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7714 tcg_temp_free_i32(tcg_res
);
7715 tcg_temp_free_i32(tcg_op
);
7716 if (!is_q
&& !is_scalar
) {
7717 clear_vec_high(s
, rd
);
7720 tcg_temp_free_ptr(fpst
);
7723 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7724 int opcode
, bool u
, bool is_q
,
7725 int size
, int rn
, int rd
)
7727 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7728 * in the source becomes a size element in the destination).
7731 TCGv_i32 tcg_res
[2];
7732 int destelt
= is_q
? 2 : 0;
7733 int passes
= scalar
? 1 : 2;
7736 tcg_res
[1] = tcg_const_i32(0);
7739 for (pass
= 0; pass
< passes
; pass
++) {
7740 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7741 NeonGenNarrowFn
*genfn
= NULL
;
7742 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7745 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7747 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7749 tcg_res
[pass
] = tcg_temp_new_i32();
7752 case 0x12: /* XTN, SQXTUN */
7754 static NeonGenNarrowFn
* const xtnfns
[3] = {
7755 gen_helper_neon_narrow_u8
,
7756 gen_helper_neon_narrow_u16
,
7757 tcg_gen_extrl_i64_i32
,
7759 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7760 gen_helper_neon_unarrow_sat8
,
7761 gen_helper_neon_unarrow_sat16
,
7762 gen_helper_neon_unarrow_sat32
,
7765 genenvfn
= sqxtunfns
[size
];
7767 genfn
= xtnfns
[size
];
7771 case 0x14: /* SQXTN, UQXTN */
7773 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7774 { gen_helper_neon_narrow_sat_s8
,
7775 gen_helper_neon_narrow_sat_u8
},
7776 { gen_helper_neon_narrow_sat_s16
,
7777 gen_helper_neon_narrow_sat_u16
},
7778 { gen_helper_neon_narrow_sat_s32
,
7779 gen_helper_neon_narrow_sat_u32
},
7781 genenvfn
= fns
[size
][u
];
7784 case 0x16: /* FCVTN, FCVTN2 */
7785 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7787 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7789 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7790 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7791 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7792 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7793 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7794 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7795 tcg_temp_free_i32(tcg_lo
);
7796 tcg_temp_free_i32(tcg_hi
);
7799 case 0x56: /* FCVTXN, FCVTXN2 */
7800 /* 64 bit to 32 bit float conversion
7801 * with von Neumann rounding (round to odd)
7804 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7807 g_assert_not_reached();
7811 genfn(tcg_res
[pass
], tcg_op
);
7812 } else if (genenvfn
) {
7813 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7816 tcg_temp_free_i64(tcg_op
);
7819 for (pass
= 0; pass
< 2; pass
++) {
7820 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7821 tcg_temp_free_i32(tcg_res
[pass
]);
7824 clear_vec_high(s
, rd
);
7828 /* Remaining saturating accumulating ops */
7829 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7830 bool is_q
, int size
, int rn
, int rd
)
7832 bool is_double
= (size
== 3);
7835 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7836 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7839 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7840 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7841 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7843 if (is_u
) { /* USQADD */
7844 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7845 } else { /* SUQADD */
7846 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7848 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7851 clear_vec_high(s
, rd
);
7854 tcg_temp_free_i64(tcg_rd
);
7855 tcg_temp_free_i64(tcg_rn
);
7857 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7858 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7859 int pass
, maxpasses
;
7864 maxpasses
= is_q
? 4 : 2;
7867 for (pass
= 0; pass
< maxpasses
; pass
++) {
7869 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7870 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7872 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7873 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7876 if (is_u
) { /* USQADD */
7879 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7882 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7885 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7888 g_assert_not_reached();
7890 } else { /* SUQADD */
7893 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7896 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7899 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7902 g_assert_not_reached();
7907 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7908 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7909 tcg_temp_free_i64(tcg_zero
);
7911 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7915 clear_vec_high(s
, rd
);
7918 tcg_temp_free_i32(tcg_rd
);
7919 tcg_temp_free_i32(tcg_rn
);
7923 /* C3.6.12 AdvSIMD scalar two reg misc
7924 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7925 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7926 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7927 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7929 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7931 int rd
= extract32(insn
, 0, 5);
7932 int rn
= extract32(insn
, 5, 5);
7933 int opcode
= extract32(insn
, 12, 5);
7934 int size
= extract32(insn
, 22, 2);
7935 bool u
= extract32(insn
, 29, 1);
7936 bool is_fcvt
= false;
7939 TCGv_ptr tcg_fpstatus
;
7942 case 0x3: /* USQADD / SUQADD*/
7943 if (!fp_access_check(s
)) {
7946 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7948 case 0x7: /* SQABS / SQNEG */
7950 case 0xa: /* CMLT */
7952 unallocated_encoding(s
);
7956 case 0x8: /* CMGT, CMGE */
7957 case 0x9: /* CMEQ, CMLE */
7958 case 0xb: /* ABS, NEG */
7960 unallocated_encoding(s
);
7964 case 0x12: /* SQXTUN */
7966 unallocated_encoding(s
);
7970 case 0x14: /* SQXTN, UQXTN */
7972 unallocated_encoding(s
);
7975 if (!fp_access_check(s
)) {
7978 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7983 /* Floating point: U, size[1] and opcode indicate operation;
7984 * size[0] indicates single or double precision.
7986 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7987 size
= extract32(size
, 0, 1) ? 3 : 2;
7989 case 0x2c: /* FCMGT (zero) */
7990 case 0x2d: /* FCMEQ (zero) */
7991 case 0x2e: /* FCMLT (zero) */
7992 case 0x6c: /* FCMGE (zero) */
7993 case 0x6d: /* FCMLE (zero) */
7994 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7996 case 0x1d: /* SCVTF */
7997 case 0x5d: /* UCVTF */
7999 bool is_signed
= (opcode
== 0x1d);
8000 if (!fp_access_check(s
)) {
8003 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8006 case 0x3d: /* FRECPE */
8007 case 0x3f: /* FRECPX */
8008 case 0x7d: /* FRSQRTE */
8009 if (!fp_access_check(s
)) {
8012 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8014 case 0x1a: /* FCVTNS */
8015 case 0x1b: /* FCVTMS */
8016 case 0x3a: /* FCVTPS */
8017 case 0x3b: /* FCVTZS */
8018 case 0x5a: /* FCVTNU */
8019 case 0x5b: /* FCVTMU */
8020 case 0x7a: /* FCVTPU */
8021 case 0x7b: /* FCVTZU */
8023 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8025 case 0x1c: /* FCVTAS */
8026 case 0x5c: /* FCVTAU */
8027 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8029 rmode
= FPROUNDING_TIEAWAY
;
8031 case 0x56: /* FCVTXN, FCVTXN2 */
8033 unallocated_encoding(s
);
8036 if (!fp_access_check(s
)) {
8039 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8042 unallocated_encoding(s
);
8047 unallocated_encoding(s
);
8051 if (!fp_access_check(s
)) {
8056 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8057 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8058 tcg_fpstatus
= get_fpstatus_ptr();
8060 TCGV_UNUSED_I32(tcg_rmode
);
8061 TCGV_UNUSED_PTR(tcg_fpstatus
);
8065 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8066 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8068 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8069 write_fp_dreg(s
, rd
, tcg_rd
);
8070 tcg_temp_free_i64(tcg_rd
);
8071 tcg_temp_free_i64(tcg_rn
);
8073 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8074 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8076 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8079 case 0x7: /* SQABS, SQNEG */
8081 NeonGenOneOpEnvFn
*genfn
;
8082 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8083 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8084 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8085 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8087 genfn
= fns
[size
][u
];
8088 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8091 case 0x1a: /* FCVTNS */
8092 case 0x1b: /* FCVTMS */
8093 case 0x1c: /* FCVTAS */
8094 case 0x3a: /* FCVTPS */
8095 case 0x3b: /* FCVTZS */
8097 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8098 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8099 tcg_temp_free_i32(tcg_shift
);
8102 case 0x5a: /* FCVTNU */
8103 case 0x5b: /* FCVTMU */
8104 case 0x5c: /* FCVTAU */
8105 case 0x7a: /* FCVTPU */
8106 case 0x7b: /* FCVTZU */
8108 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8109 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8110 tcg_temp_free_i32(tcg_shift
);
8114 g_assert_not_reached();
8117 write_fp_sreg(s
, rd
, tcg_rd
);
8118 tcg_temp_free_i32(tcg_rd
);
8119 tcg_temp_free_i32(tcg_rn
);
8123 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8124 tcg_temp_free_i32(tcg_rmode
);
8125 tcg_temp_free_ptr(tcg_fpstatus
);
8129 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8130 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8131 int immh
, int immb
, int opcode
, int rn
, int rd
)
8133 int size
= 32 - clz32(immh
) - 1;
8134 int immhb
= immh
<< 3 | immb
;
8135 int shift
= 2 * (8 << size
) - immhb
;
8136 bool accumulate
= false;
8138 bool insert
= false;
8139 int dsize
= is_q
? 128 : 64;
8140 int esize
= 8 << size
;
8141 int elements
= dsize
/esize
;
8142 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8143 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8144 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8148 if (extract32(immh
, 3, 1) && !is_q
) {
8149 unallocated_encoding(s
);
8153 if (size
> 3 && !is_q
) {
8154 unallocated_encoding(s
);
8158 if (!fp_access_check(s
)) {
8163 case 0x02: /* SSRA / USRA (accumulate) */
8166 case 0x04: /* SRSHR / URSHR (rounding) */
8169 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8170 accumulate
= round
= true;
8172 case 0x08: /* SRI */
8178 uint64_t round_const
= 1ULL << (shift
- 1);
8179 tcg_round
= tcg_const_i64(round_const
);
8181 TCGV_UNUSED_I64(tcg_round
);
8184 for (i
= 0; i
< elements
; i
++) {
8185 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8186 if (accumulate
|| insert
) {
8187 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8191 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8193 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8194 accumulate
, is_u
, size
, shift
);
8197 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8201 clear_vec_high(s
, rd
);
8205 tcg_temp_free_i64(tcg_round
);
8209 /* SHL/SLI - Vector shift left */
8210 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8211 int immh
, int immb
, int opcode
, int rn
, int rd
)
8213 int size
= 32 - clz32(immh
) - 1;
8214 int immhb
= immh
<< 3 | immb
;
8215 int shift
= immhb
- (8 << size
);
8216 int dsize
= is_q
? 128 : 64;
8217 int esize
= 8 << size
;
8218 int elements
= dsize
/esize
;
8219 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8220 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8223 if (extract32(immh
, 3, 1) && !is_q
) {
8224 unallocated_encoding(s
);
8228 if (size
> 3 && !is_q
) {
8229 unallocated_encoding(s
);
8233 if (!fp_access_check(s
)) {
8237 for (i
= 0; i
< elements
; i
++) {
8238 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8240 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8243 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8245 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8249 clear_vec_high(s
, rd
);
8253 /* USHLL/SHLL - Vector shift left with widening */
8254 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8255 int immh
, int immb
, int opcode
, int rn
, int rd
)
8257 int size
= 32 - clz32(immh
) - 1;
8258 int immhb
= immh
<< 3 | immb
;
8259 int shift
= immhb
- (8 << size
);
8261 int esize
= 8 << size
;
8262 int elements
= dsize
/esize
;
8263 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8264 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8268 unallocated_encoding(s
);
8272 if (!fp_access_check(s
)) {
8276 /* For the LL variants the store is larger than the load,
8277 * so if rd == rn we would overwrite parts of our input.
8278 * So load everything right now and use shifts in the main loop.
8280 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8282 for (i
= 0; i
< elements
; i
++) {
8283 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8284 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8285 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8286 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8290 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8291 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8292 int immh
, int immb
, int opcode
, int rn
, int rd
)
8294 int immhb
= immh
<< 3 | immb
;
8295 int size
= 32 - clz32(immh
) - 1;
8297 int esize
= 8 << size
;
8298 int elements
= dsize
/esize
;
8299 int shift
= (2 * esize
) - immhb
;
8300 bool round
= extract32(opcode
, 0, 1);
8301 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8305 if (extract32(immh
, 3, 1)) {
8306 unallocated_encoding(s
);
8310 if (!fp_access_check(s
)) {
8314 tcg_rn
= tcg_temp_new_i64();
8315 tcg_rd
= tcg_temp_new_i64();
8316 tcg_final
= tcg_temp_new_i64();
8317 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8320 uint64_t round_const
= 1ULL << (shift
- 1);
8321 tcg_round
= tcg_const_i64(round_const
);
8323 TCGV_UNUSED_I64(tcg_round
);
8326 for (i
= 0; i
< elements
; i
++) {
8327 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8328 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8329 false, true, size
+1, shift
);
8331 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8335 clear_vec_high(s
, rd
);
8336 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8338 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8342 tcg_temp_free_i64(tcg_round
);
8344 tcg_temp_free_i64(tcg_rn
);
8345 tcg_temp_free_i64(tcg_rd
);
8346 tcg_temp_free_i64(tcg_final
);
8351 /* C3.6.14 AdvSIMD shift by immediate
8352 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8353 * +---+---+---+-------------+------+------+--------+---+------+------+
8354 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8355 * +---+---+---+-------------+------+------+--------+---+------+------+
8357 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8359 int rd
= extract32(insn
, 0, 5);
8360 int rn
= extract32(insn
, 5, 5);
8361 int opcode
= extract32(insn
, 11, 5);
8362 int immb
= extract32(insn
, 16, 3);
8363 int immh
= extract32(insn
, 19, 4);
8364 bool is_u
= extract32(insn
, 29, 1);
8365 bool is_q
= extract32(insn
, 30, 1);
8368 case 0x08: /* SRI */
8370 unallocated_encoding(s
);
8374 case 0x00: /* SSHR / USHR */
8375 case 0x02: /* SSRA / USRA (accumulate) */
8376 case 0x04: /* SRSHR / URSHR (rounding) */
8377 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8378 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8380 case 0x0a: /* SHL / SLI */
8381 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8383 case 0x10: /* SHRN */
8384 case 0x11: /* RSHRN / SQRSHRUN */
8386 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8389 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8392 case 0x12: /* SQSHRN / UQSHRN */
8393 case 0x13: /* SQRSHRN / UQRSHRN */
8394 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8397 case 0x14: /* SSHLL / USHLL */
8398 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8400 case 0x1c: /* SCVTF / UCVTF */
8401 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8404 case 0xc: /* SQSHLU */
8406 unallocated_encoding(s
);
8409 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8411 case 0xe: /* SQSHL, UQSHL */
8412 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8414 case 0x1f: /* FCVTZS/ FCVTZU */
8415 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8418 unallocated_encoding(s
);
8423 /* Generate code to do a "long" addition or subtraction, ie one done in
8424 * TCGv_i64 on vector lanes twice the width specified by size.
8426 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8427 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8429 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8430 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8431 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8432 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8434 NeonGenTwo64OpFn
*genfn
;
8437 genfn
= fns
[size
][is_sub
];
8438 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8441 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8442 int opcode
, int rd
, int rn
, int rm
)
8444 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8445 TCGv_i64 tcg_res
[2];
8448 tcg_res
[0] = tcg_temp_new_i64();
8449 tcg_res
[1] = tcg_temp_new_i64();
8451 /* Does this op do an adding accumulate, a subtracting accumulate,
8452 * or no accumulate at all?
8470 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8471 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8474 /* size == 2 means two 32x32->64 operations; this is worth special
8475 * casing because we can generally handle it inline.
8478 for (pass
= 0; pass
< 2; pass
++) {
8479 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8480 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8481 TCGv_i64 tcg_passres
;
8482 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8484 int elt
= pass
+ is_q
* 2;
8486 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8487 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8490 tcg_passres
= tcg_res
[pass
];
8492 tcg_passres
= tcg_temp_new_i64();
8496 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8497 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8499 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8500 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8502 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8503 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8505 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8506 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8508 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8509 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8510 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8512 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8513 tcg_temp_free_i64(tcg_tmp1
);
8514 tcg_temp_free_i64(tcg_tmp2
);
8517 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8518 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8519 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8520 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8522 case 9: /* SQDMLAL, SQDMLAL2 */
8523 case 11: /* SQDMLSL, SQDMLSL2 */
8524 case 13: /* SQDMULL, SQDMULL2 */
8525 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8526 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8527 tcg_passres
, tcg_passres
);
8530 g_assert_not_reached();
8533 if (opcode
== 9 || opcode
== 11) {
8534 /* saturating accumulate ops */
8536 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8538 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8539 tcg_res
[pass
], tcg_passres
);
8540 } else if (accop
> 0) {
8541 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8542 } else if (accop
< 0) {
8543 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8547 tcg_temp_free_i64(tcg_passres
);
8550 tcg_temp_free_i64(tcg_op1
);
8551 tcg_temp_free_i64(tcg_op2
);
8554 /* size 0 or 1, generally helper functions */
8555 for (pass
= 0; pass
< 2; pass
++) {
8556 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8557 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8558 TCGv_i64 tcg_passres
;
8559 int elt
= pass
+ is_q
* 2;
8561 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8562 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8565 tcg_passres
= tcg_res
[pass
];
8567 tcg_passres
= tcg_temp_new_i64();
8571 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8572 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8574 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8575 static NeonGenWidenFn
* const widenfns
[2][2] = {
8576 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8577 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8579 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8581 widenfn(tcg_op2_64
, tcg_op2
);
8582 widenfn(tcg_passres
, tcg_op1
);
8583 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8584 tcg_passres
, tcg_op2_64
);
8585 tcg_temp_free_i64(tcg_op2_64
);
8588 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8589 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8592 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8594 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8598 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8600 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8604 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8605 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8606 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8609 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8611 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8615 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8617 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8621 case 9: /* SQDMLAL, SQDMLAL2 */
8622 case 11: /* SQDMLSL, SQDMLSL2 */
8623 case 13: /* SQDMULL, SQDMULL2 */
8625 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8626 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8627 tcg_passres
, tcg_passres
);
8629 case 14: /* PMULL */
8631 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8634 g_assert_not_reached();
8636 tcg_temp_free_i32(tcg_op1
);
8637 tcg_temp_free_i32(tcg_op2
);
8640 if (opcode
== 9 || opcode
== 11) {
8641 /* saturating accumulate ops */
8643 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8645 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8649 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8650 tcg_res
[pass
], tcg_passres
);
8652 tcg_temp_free_i64(tcg_passres
);
8657 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8658 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8659 tcg_temp_free_i64(tcg_res
[0]);
8660 tcg_temp_free_i64(tcg_res
[1]);
8663 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8664 int opcode
, int rd
, int rn
, int rm
)
8666 TCGv_i64 tcg_res
[2];
8667 int part
= is_q
? 2 : 0;
8670 for (pass
= 0; pass
< 2; pass
++) {
8671 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8672 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8673 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8674 static NeonGenWidenFn
* const widenfns
[3][2] = {
8675 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8676 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8677 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8679 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8681 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8682 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8683 widenfn(tcg_op2_wide
, tcg_op2
);
8684 tcg_temp_free_i32(tcg_op2
);
8685 tcg_res
[pass
] = tcg_temp_new_i64();
8686 gen_neon_addl(size
, (opcode
== 3),
8687 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8688 tcg_temp_free_i64(tcg_op1
);
8689 tcg_temp_free_i64(tcg_op2_wide
);
8692 for (pass
= 0; pass
< 2; pass
++) {
8693 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8694 tcg_temp_free_i64(tcg_res
[pass
]);
8698 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8700 tcg_gen_addi_i64(in
, in
, 1U << 31);
8701 tcg_gen_extrh_i64_i32(res
, in
);
8704 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8705 int opcode
, int rd
, int rn
, int rm
)
8707 TCGv_i32 tcg_res
[2];
8708 int part
= is_q
? 2 : 0;
8711 for (pass
= 0; pass
< 2; pass
++) {
8712 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8713 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8714 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8715 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8716 { gen_helper_neon_narrow_high_u8
,
8717 gen_helper_neon_narrow_round_high_u8
},
8718 { gen_helper_neon_narrow_high_u16
,
8719 gen_helper_neon_narrow_round_high_u16
},
8720 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8722 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8724 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8725 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8727 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8729 tcg_temp_free_i64(tcg_op1
);
8730 tcg_temp_free_i64(tcg_op2
);
8732 tcg_res
[pass
] = tcg_temp_new_i32();
8733 gennarrow(tcg_res
[pass
], tcg_wideres
);
8734 tcg_temp_free_i64(tcg_wideres
);
8737 for (pass
= 0; pass
< 2; pass
++) {
8738 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8739 tcg_temp_free_i32(tcg_res
[pass
]);
8742 clear_vec_high(s
, rd
);
8746 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8748 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8749 * is the only three-reg-diff instruction which produces a
8750 * 128-bit wide result from a single operation. However since
8751 * it's possible to calculate the two halves more or less
8752 * separately we just use two helper calls.
8754 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8755 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8756 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8758 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8759 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8760 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8761 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8762 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8763 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8765 tcg_temp_free_i64(tcg_op1
);
8766 tcg_temp_free_i64(tcg_op2
);
8767 tcg_temp_free_i64(tcg_res
);
8770 /* C3.6.15 AdvSIMD three different
8771 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8772 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8773 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8774 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8776 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8778 /* Instructions in this group fall into three basic classes
8779 * (in each case with the operation working on each element in
8780 * the input vectors):
8781 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8783 * (2) wide 64 x 128 -> 128
8784 * (3) narrowing 128 x 128 -> 64
8785 * Here we do initial decode, catch unallocated cases and
8786 * dispatch to separate functions for each class.
8788 int is_q
= extract32(insn
, 30, 1);
8789 int is_u
= extract32(insn
, 29, 1);
8790 int size
= extract32(insn
, 22, 2);
8791 int opcode
= extract32(insn
, 12, 4);
8792 int rm
= extract32(insn
, 16, 5);
8793 int rn
= extract32(insn
, 5, 5);
8794 int rd
= extract32(insn
, 0, 5);
8797 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8798 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8799 /* 64 x 128 -> 128 */
8801 unallocated_encoding(s
);
8804 if (!fp_access_check(s
)) {
8807 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8809 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8810 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8811 /* 128 x 128 -> 64 */
8813 unallocated_encoding(s
);
8816 if (!fp_access_check(s
)) {
8819 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8821 case 14: /* PMULL, PMULL2 */
8822 if (is_u
|| size
== 1 || size
== 2) {
8823 unallocated_encoding(s
);
8827 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8828 unallocated_encoding(s
);
8831 if (!fp_access_check(s
)) {
8834 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8838 case 9: /* SQDMLAL, SQDMLAL2 */
8839 case 11: /* SQDMLSL, SQDMLSL2 */
8840 case 13: /* SQDMULL, SQDMULL2 */
8841 if (is_u
|| size
== 0) {
8842 unallocated_encoding(s
);
8846 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8847 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8848 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8849 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8850 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8851 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8852 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8853 /* 64 x 64 -> 128 */
8855 unallocated_encoding(s
);
8859 if (!fp_access_check(s
)) {
8863 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8866 /* opcode 15 not allocated */
8867 unallocated_encoding(s
);
8872 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8873 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8875 int rd
= extract32(insn
, 0, 5);
8876 int rn
= extract32(insn
, 5, 5);
8877 int rm
= extract32(insn
, 16, 5);
8878 int size
= extract32(insn
, 22, 2);
8879 bool is_u
= extract32(insn
, 29, 1);
8880 bool is_q
= extract32(insn
, 30, 1);
8881 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8884 if (!fp_access_check(s
)) {
8888 tcg_op1
= tcg_temp_new_i64();
8889 tcg_op2
= tcg_temp_new_i64();
8890 tcg_res
[0] = tcg_temp_new_i64();
8891 tcg_res
[1] = tcg_temp_new_i64();
8893 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8894 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8895 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8900 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8903 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8906 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8909 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8914 /* B* ops need res loaded to operate on */
8915 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8920 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8922 case 1: /* BSL bitwise select */
8923 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8924 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8925 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8927 case 2: /* BIT, bitwise insert if true */
8928 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8929 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8930 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8932 case 3: /* BIF, bitwise insert if false */
8933 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8934 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8935 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8941 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8943 tcg_gen_movi_i64(tcg_res
[1], 0);
8945 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8947 tcg_temp_free_i64(tcg_op1
);
8948 tcg_temp_free_i64(tcg_op2
);
8949 tcg_temp_free_i64(tcg_res
[0]);
8950 tcg_temp_free_i64(tcg_res
[1]);
8953 /* Helper functions for 32 bit comparisons */
8954 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8956 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8959 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8961 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8964 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8966 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8969 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8971 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8974 /* Pairwise op subgroup of C3.6.16.
8976 * This is called directly or via the handle_3same_float for float pairwise
8977 * operations where the opcode and size are calculated differently.
8979 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8980 int size
, int rn
, int rm
, int rd
)
8985 /* Floating point operations need fpst */
8986 if (opcode
>= 0x58) {
8987 fpst
= get_fpstatus_ptr();
8989 TCGV_UNUSED_PTR(fpst
);
8992 if (!fp_access_check(s
)) {
8996 /* These operations work on the concatenated rm:rn, with each pair of
8997 * adjacent elements being operated on to produce an element in the result.
9000 TCGv_i64 tcg_res
[2];
9002 for (pass
= 0; pass
< 2; pass
++) {
9003 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9004 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9005 int passreg
= (pass
== 0) ? rn
: rm
;
9007 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9008 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9009 tcg_res
[pass
] = tcg_temp_new_i64();
9012 case 0x17: /* ADDP */
9013 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9015 case 0x58: /* FMAXNMP */
9016 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9018 case 0x5a: /* FADDP */
9019 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9021 case 0x5e: /* FMAXP */
9022 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9024 case 0x78: /* FMINNMP */
9025 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9027 case 0x7e: /* FMINP */
9028 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9031 g_assert_not_reached();
9034 tcg_temp_free_i64(tcg_op1
);
9035 tcg_temp_free_i64(tcg_op2
);
9038 for (pass
= 0; pass
< 2; pass
++) {
9039 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9040 tcg_temp_free_i64(tcg_res
[pass
]);
9043 int maxpass
= is_q
? 4 : 2;
9044 TCGv_i32 tcg_res
[4];
9046 for (pass
= 0; pass
< maxpass
; pass
++) {
9047 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9048 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9049 NeonGenTwoOpFn
*genfn
= NULL
;
9050 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9051 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9053 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9054 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9055 tcg_res
[pass
] = tcg_temp_new_i32();
9058 case 0x17: /* ADDP */
9060 static NeonGenTwoOpFn
* const fns
[3] = {
9061 gen_helper_neon_padd_u8
,
9062 gen_helper_neon_padd_u16
,
9068 case 0x14: /* SMAXP, UMAXP */
9070 static NeonGenTwoOpFn
* const fns
[3][2] = {
9071 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9072 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9073 { gen_max_s32
, gen_max_u32
},
9075 genfn
= fns
[size
][u
];
9078 case 0x15: /* SMINP, UMINP */
9080 static NeonGenTwoOpFn
* const fns
[3][2] = {
9081 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9082 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9083 { gen_min_s32
, gen_min_u32
},
9085 genfn
= fns
[size
][u
];
9088 /* The FP operations are all on single floats (32 bit) */
9089 case 0x58: /* FMAXNMP */
9090 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9092 case 0x5a: /* FADDP */
9093 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9095 case 0x5e: /* FMAXP */
9096 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9098 case 0x78: /* FMINNMP */
9099 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9101 case 0x7e: /* FMINP */
9102 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9105 g_assert_not_reached();
9108 /* FP ops called directly, otherwise call now */
9110 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9113 tcg_temp_free_i32(tcg_op1
);
9114 tcg_temp_free_i32(tcg_op2
);
9117 for (pass
= 0; pass
< maxpass
; pass
++) {
9118 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9119 tcg_temp_free_i32(tcg_res
[pass
]);
9122 clear_vec_high(s
, rd
);
9126 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9127 tcg_temp_free_ptr(fpst
);
9131 /* Floating point op subgroup of C3.6.16. */
9132 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9134 /* For floating point ops, the U, size[1] and opcode bits
9135 * together indicate the operation. size[0] indicates single
9138 int fpopcode
= extract32(insn
, 11, 5)
9139 | (extract32(insn
, 23, 1) << 5)
9140 | (extract32(insn
, 29, 1) << 6);
9141 int is_q
= extract32(insn
, 30, 1);
9142 int size
= extract32(insn
, 22, 1);
9143 int rm
= extract32(insn
, 16, 5);
9144 int rn
= extract32(insn
, 5, 5);
9145 int rd
= extract32(insn
, 0, 5);
9147 int datasize
= is_q
? 128 : 64;
9148 int esize
= 32 << size
;
9149 int elements
= datasize
/ esize
;
9151 if (size
== 1 && !is_q
) {
9152 unallocated_encoding(s
);
9157 case 0x58: /* FMAXNMP */
9158 case 0x5a: /* FADDP */
9159 case 0x5e: /* FMAXP */
9160 case 0x78: /* FMINNMP */
9161 case 0x7e: /* FMINP */
9162 if (size
&& !is_q
) {
9163 unallocated_encoding(s
);
9166 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9169 case 0x1b: /* FMULX */
9170 case 0x1f: /* FRECPS */
9171 case 0x3f: /* FRSQRTS */
9172 case 0x5d: /* FACGE */
9173 case 0x7d: /* FACGT */
9174 case 0x19: /* FMLA */
9175 case 0x39: /* FMLS */
9176 case 0x18: /* FMAXNM */
9177 case 0x1a: /* FADD */
9178 case 0x1c: /* FCMEQ */
9179 case 0x1e: /* FMAX */
9180 case 0x38: /* FMINNM */
9181 case 0x3a: /* FSUB */
9182 case 0x3e: /* FMIN */
9183 case 0x5b: /* FMUL */
9184 case 0x5c: /* FCMGE */
9185 case 0x5f: /* FDIV */
9186 case 0x7a: /* FABD */
9187 case 0x7c: /* FCMGT */
9188 if (!fp_access_check(s
)) {
9192 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9195 unallocated_encoding(s
);
9200 /* Integer op subgroup of C3.6.16. */
9201 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9203 int is_q
= extract32(insn
, 30, 1);
9204 int u
= extract32(insn
, 29, 1);
9205 int size
= extract32(insn
, 22, 2);
9206 int opcode
= extract32(insn
, 11, 5);
9207 int rm
= extract32(insn
, 16, 5);
9208 int rn
= extract32(insn
, 5, 5);
9209 int rd
= extract32(insn
, 0, 5);
9213 case 0x13: /* MUL, PMUL */
9214 if (u
&& size
!= 0) {
9215 unallocated_encoding(s
);
9219 case 0x0: /* SHADD, UHADD */
9220 case 0x2: /* SRHADD, URHADD */
9221 case 0x4: /* SHSUB, UHSUB */
9222 case 0xc: /* SMAX, UMAX */
9223 case 0xd: /* SMIN, UMIN */
9224 case 0xe: /* SABD, UABD */
9225 case 0xf: /* SABA, UABA */
9226 case 0x12: /* MLA, MLS */
9228 unallocated_encoding(s
);
9232 case 0x16: /* SQDMULH, SQRDMULH */
9233 if (size
== 0 || size
== 3) {
9234 unallocated_encoding(s
);
9239 if (size
== 3 && !is_q
) {
9240 unallocated_encoding(s
);
9246 if (!fp_access_check(s
)) {
9252 for (pass
= 0; pass
< 2; pass
++) {
9253 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9254 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9255 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9257 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9258 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9260 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9262 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9264 tcg_temp_free_i64(tcg_res
);
9265 tcg_temp_free_i64(tcg_op1
);
9266 tcg_temp_free_i64(tcg_op2
);
9269 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9270 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9271 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9272 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9273 NeonGenTwoOpFn
*genfn
= NULL
;
9274 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9276 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9277 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9280 case 0x0: /* SHADD, UHADD */
9282 static NeonGenTwoOpFn
* const fns
[3][2] = {
9283 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9284 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9285 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9287 genfn
= fns
[size
][u
];
9290 case 0x1: /* SQADD, UQADD */
9292 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9293 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9294 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9295 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9297 genenvfn
= fns
[size
][u
];
9300 case 0x2: /* SRHADD, URHADD */
9302 static NeonGenTwoOpFn
* const fns
[3][2] = {
9303 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9304 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9305 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9307 genfn
= fns
[size
][u
];
9310 case 0x4: /* SHSUB, UHSUB */
9312 static NeonGenTwoOpFn
* const fns
[3][2] = {
9313 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9314 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9315 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9317 genfn
= fns
[size
][u
];
9320 case 0x5: /* SQSUB, UQSUB */
9322 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9323 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9324 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9325 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9327 genenvfn
= fns
[size
][u
];
9330 case 0x6: /* CMGT, CMHI */
9332 static NeonGenTwoOpFn
* const fns
[3][2] = {
9333 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9334 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9335 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9337 genfn
= fns
[size
][u
];
9340 case 0x7: /* CMGE, CMHS */
9342 static NeonGenTwoOpFn
* const fns
[3][2] = {
9343 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9344 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9345 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9347 genfn
= fns
[size
][u
];
9350 case 0x8: /* SSHL, USHL */
9352 static NeonGenTwoOpFn
* const fns
[3][2] = {
9353 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9354 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9355 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9357 genfn
= fns
[size
][u
];
9360 case 0x9: /* SQSHL, UQSHL */
9362 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9363 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9364 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9365 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9367 genenvfn
= fns
[size
][u
];
9370 case 0xa: /* SRSHL, URSHL */
9372 static NeonGenTwoOpFn
* const fns
[3][2] = {
9373 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9374 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9375 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9377 genfn
= fns
[size
][u
];
9380 case 0xb: /* SQRSHL, UQRSHL */
9382 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9383 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9384 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9385 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9387 genenvfn
= fns
[size
][u
];
9390 case 0xc: /* SMAX, UMAX */
9392 static NeonGenTwoOpFn
* const fns
[3][2] = {
9393 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9394 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9395 { gen_max_s32
, gen_max_u32
},
9397 genfn
= fns
[size
][u
];
9401 case 0xd: /* SMIN, UMIN */
9403 static NeonGenTwoOpFn
* const fns
[3][2] = {
9404 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9405 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9406 { gen_min_s32
, gen_min_u32
},
9408 genfn
= fns
[size
][u
];
9411 case 0xe: /* SABD, UABD */
9412 case 0xf: /* SABA, UABA */
9414 static NeonGenTwoOpFn
* const fns
[3][2] = {
9415 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9416 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9417 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9419 genfn
= fns
[size
][u
];
9422 case 0x10: /* ADD, SUB */
9424 static NeonGenTwoOpFn
* const fns
[3][2] = {
9425 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9426 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9427 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9429 genfn
= fns
[size
][u
];
9432 case 0x11: /* CMTST, CMEQ */
9434 static NeonGenTwoOpFn
* const fns
[3][2] = {
9435 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9436 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9437 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9439 genfn
= fns
[size
][u
];
9442 case 0x13: /* MUL, PMUL */
9446 genfn
= gen_helper_neon_mul_p8
;
9449 /* fall through : MUL */
9450 case 0x12: /* MLA, MLS */
9452 static NeonGenTwoOpFn
* const fns
[3] = {
9453 gen_helper_neon_mul_u8
,
9454 gen_helper_neon_mul_u16
,
9460 case 0x16: /* SQDMULH, SQRDMULH */
9462 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9463 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9464 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9466 assert(size
== 1 || size
== 2);
9467 genenvfn
= fns
[size
- 1][u
];
9471 g_assert_not_reached();
9475 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9477 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9480 if (opcode
== 0xf || opcode
== 0x12) {
9481 /* SABA, UABA, MLA, MLS: accumulating ops */
9482 static NeonGenTwoOpFn
* const fns
[3][2] = {
9483 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9484 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9485 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9487 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9489 genfn
= fns
[size
][is_sub
];
9490 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9491 genfn(tcg_res
, tcg_op1
, tcg_res
);
9494 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9496 tcg_temp_free_i32(tcg_res
);
9497 tcg_temp_free_i32(tcg_op1
);
9498 tcg_temp_free_i32(tcg_op2
);
9503 clear_vec_high(s
, rd
);
9507 /* C3.6.16 AdvSIMD three same
9508 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9509 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9510 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9511 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9513 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9515 int opcode
= extract32(insn
, 11, 5);
9518 case 0x3: /* logic ops */
9519 disas_simd_3same_logic(s
, insn
);
9521 case 0x17: /* ADDP */
9522 case 0x14: /* SMAXP, UMAXP */
9523 case 0x15: /* SMINP, UMINP */
9525 /* Pairwise operations */
9526 int is_q
= extract32(insn
, 30, 1);
9527 int u
= extract32(insn
, 29, 1);
9528 int size
= extract32(insn
, 22, 2);
9529 int rm
= extract32(insn
, 16, 5);
9530 int rn
= extract32(insn
, 5, 5);
9531 int rd
= extract32(insn
, 0, 5);
9532 if (opcode
== 0x17) {
9533 if (u
|| (size
== 3 && !is_q
)) {
9534 unallocated_encoding(s
);
9539 unallocated_encoding(s
);
9543 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9547 /* floating point ops, sz[1] and U are part of opcode */
9548 disas_simd_3same_float(s
, insn
);
9551 disas_simd_3same_int(s
, insn
);
9556 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9557 int size
, int rn
, int rd
)
9559 /* Handle 2-reg-misc ops which are widening (so each size element
9560 * in the source becomes a 2*size element in the destination.
9561 * The only instruction like this is FCVTL.
9566 /* 32 -> 64 bit fp conversion */
9567 TCGv_i64 tcg_res
[2];
9568 int srcelt
= is_q
? 2 : 0;
9570 for (pass
= 0; pass
< 2; pass
++) {
9571 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9572 tcg_res
[pass
] = tcg_temp_new_i64();
9574 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9575 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9576 tcg_temp_free_i32(tcg_op
);
9578 for (pass
= 0; pass
< 2; pass
++) {
9579 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9580 tcg_temp_free_i64(tcg_res
[pass
]);
9583 /* 16 -> 32 bit fp conversion */
9584 int srcelt
= is_q
? 4 : 0;
9585 TCGv_i32 tcg_res
[4];
9587 for (pass
= 0; pass
< 4; pass
++) {
9588 tcg_res
[pass
] = tcg_temp_new_i32();
9590 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9591 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9594 for (pass
= 0; pass
< 4; pass
++) {
9595 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9596 tcg_temp_free_i32(tcg_res
[pass
]);
9601 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9602 bool is_q
, int size
, int rn
, int rd
)
9604 int op
= (opcode
<< 1) | u
;
9605 int opsz
= op
+ size
;
9606 int grp_size
= 3 - opsz
;
9607 int dsize
= is_q
? 128 : 64;
9611 unallocated_encoding(s
);
9615 if (!fp_access_check(s
)) {
9620 /* Special case bytes, use bswap op on each group of elements */
9621 int groups
= dsize
/ (8 << grp_size
);
9623 for (i
= 0; i
< groups
; i
++) {
9624 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9626 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9629 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9632 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9635 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9638 g_assert_not_reached();
9640 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9641 tcg_temp_free_i64(tcg_tmp
);
9644 clear_vec_high(s
, rd
);
9647 int revmask
= (1 << grp_size
) - 1;
9648 int esize
= 8 << size
;
9649 int elements
= dsize
/ esize
;
9650 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9651 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9652 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9654 for (i
= 0; i
< elements
; i
++) {
9655 int e_rev
= (i
& 0xf) ^ revmask
;
9656 int off
= e_rev
* esize
;
9657 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9659 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9660 tcg_rn
, off
- 64, esize
);
9662 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9665 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9666 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9668 tcg_temp_free_i64(tcg_rd_hi
);
9669 tcg_temp_free_i64(tcg_rd
);
9670 tcg_temp_free_i64(tcg_rn
);
9674 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9675 bool is_q
, int size
, int rn
, int rd
)
9677 /* Implement the pairwise operations from 2-misc:
9678 * SADDLP, UADDLP, SADALP, UADALP.
9679 * These all add pairs of elements in the input to produce a
9680 * double-width result element in the output (possibly accumulating).
9682 bool accum
= (opcode
== 0x6);
9683 int maxpass
= is_q
? 2 : 1;
9685 TCGv_i64 tcg_res
[2];
9688 /* 32 + 32 -> 64 op */
9689 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9691 for (pass
= 0; pass
< maxpass
; pass
++) {
9692 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9693 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9695 tcg_res
[pass
] = tcg_temp_new_i64();
9697 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9698 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9699 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9701 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9702 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9705 tcg_temp_free_i64(tcg_op1
);
9706 tcg_temp_free_i64(tcg_op2
);
9709 for (pass
= 0; pass
< maxpass
; pass
++) {
9710 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9711 NeonGenOneOpFn
*genfn
;
9712 static NeonGenOneOpFn
* const fns
[2][2] = {
9713 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9714 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9717 genfn
= fns
[size
][u
];
9719 tcg_res
[pass
] = tcg_temp_new_i64();
9721 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9722 genfn(tcg_res
[pass
], tcg_op
);
9725 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9727 gen_helper_neon_addl_u16(tcg_res
[pass
],
9728 tcg_res
[pass
], tcg_op
);
9730 gen_helper_neon_addl_u32(tcg_res
[pass
],
9731 tcg_res
[pass
], tcg_op
);
9734 tcg_temp_free_i64(tcg_op
);
9738 tcg_res
[1] = tcg_const_i64(0);
9740 for (pass
= 0; pass
< 2; pass
++) {
9741 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9742 tcg_temp_free_i64(tcg_res
[pass
]);
9746 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9748 /* Implement SHLL and SHLL2 */
9750 int part
= is_q
? 2 : 0;
9751 TCGv_i64 tcg_res
[2];
9753 for (pass
= 0; pass
< 2; pass
++) {
9754 static NeonGenWidenFn
* const widenfns
[3] = {
9755 gen_helper_neon_widen_u8
,
9756 gen_helper_neon_widen_u16
,
9757 tcg_gen_extu_i32_i64
,
9759 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9760 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9762 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9763 tcg_res
[pass
] = tcg_temp_new_i64();
9764 widenfn(tcg_res
[pass
], tcg_op
);
9765 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9767 tcg_temp_free_i32(tcg_op
);
9770 for (pass
= 0; pass
< 2; pass
++) {
9771 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9772 tcg_temp_free_i64(tcg_res
[pass
]);
9776 /* C3.6.17 AdvSIMD two reg misc
9777 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9778 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9779 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9780 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9782 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9784 int size
= extract32(insn
, 22, 2);
9785 int opcode
= extract32(insn
, 12, 5);
9786 bool u
= extract32(insn
, 29, 1);
9787 bool is_q
= extract32(insn
, 30, 1);
9788 int rn
= extract32(insn
, 5, 5);
9789 int rd
= extract32(insn
, 0, 5);
9790 bool need_fpstatus
= false;
9791 bool need_rmode
= false;
9794 TCGv_ptr tcg_fpstatus
;
9797 case 0x0: /* REV64, REV32 */
9798 case 0x1: /* REV16 */
9799 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9801 case 0x5: /* CNT, NOT, RBIT */
9802 if (u
&& size
== 0) {
9803 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9806 } else if (u
&& size
== 1) {
9809 } else if (!u
&& size
== 0) {
9813 unallocated_encoding(s
);
9815 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9816 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9818 unallocated_encoding(s
);
9821 if (!fp_access_check(s
)) {
9825 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9827 case 0x4: /* CLS, CLZ */
9829 unallocated_encoding(s
);
9833 case 0x2: /* SADDLP, UADDLP */
9834 case 0x6: /* SADALP, UADALP */
9836 unallocated_encoding(s
);
9839 if (!fp_access_check(s
)) {
9842 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9844 case 0x13: /* SHLL, SHLL2 */
9845 if (u
== 0 || size
== 3) {
9846 unallocated_encoding(s
);
9849 if (!fp_access_check(s
)) {
9852 handle_shll(s
, is_q
, size
, rn
, rd
);
9854 case 0xa: /* CMLT */
9856 unallocated_encoding(s
);
9860 case 0x8: /* CMGT, CMGE */
9861 case 0x9: /* CMEQ, CMLE */
9862 case 0xb: /* ABS, NEG */
9863 if (size
== 3 && !is_q
) {
9864 unallocated_encoding(s
);
9868 case 0x3: /* SUQADD, USQADD */
9869 if (size
== 3 && !is_q
) {
9870 unallocated_encoding(s
);
9873 if (!fp_access_check(s
)) {
9876 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9878 case 0x7: /* SQABS, SQNEG */
9879 if (size
== 3 && !is_q
) {
9880 unallocated_encoding(s
);
9888 /* Floating point: U, size[1] and opcode indicate operation;
9889 * size[0] indicates single or double precision.
9891 int is_double
= extract32(size
, 0, 1);
9892 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9893 size
= is_double
? 3 : 2;
9895 case 0x2f: /* FABS */
9896 case 0x6f: /* FNEG */
9897 if (size
== 3 && !is_q
) {
9898 unallocated_encoding(s
);
9902 case 0x1d: /* SCVTF */
9903 case 0x5d: /* UCVTF */
9905 bool is_signed
= (opcode
== 0x1d) ? true : false;
9906 int elements
= is_double
? 2 : is_q
? 4 : 2;
9907 if (is_double
&& !is_q
) {
9908 unallocated_encoding(s
);
9911 if (!fp_access_check(s
)) {
9914 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9917 case 0x2c: /* FCMGT (zero) */
9918 case 0x2d: /* FCMEQ (zero) */
9919 case 0x2e: /* FCMLT (zero) */
9920 case 0x6c: /* FCMGE (zero) */
9921 case 0x6d: /* FCMLE (zero) */
9922 if (size
== 3 && !is_q
) {
9923 unallocated_encoding(s
);
9926 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9928 case 0x7f: /* FSQRT */
9929 if (size
== 3 && !is_q
) {
9930 unallocated_encoding(s
);
9934 case 0x1a: /* FCVTNS */
9935 case 0x1b: /* FCVTMS */
9936 case 0x3a: /* FCVTPS */
9937 case 0x3b: /* FCVTZS */
9938 case 0x5a: /* FCVTNU */
9939 case 0x5b: /* FCVTMU */
9940 case 0x7a: /* FCVTPU */
9941 case 0x7b: /* FCVTZU */
9942 need_fpstatus
= true;
9944 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9945 if (size
== 3 && !is_q
) {
9946 unallocated_encoding(s
);
9950 case 0x5c: /* FCVTAU */
9951 case 0x1c: /* FCVTAS */
9952 need_fpstatus
= true;
9954 rmode
= FPROUNDING_TIEAWAY
;
9955 if (size
== 3 && !is_q
) {
9956 unallocated_encoding(s
);
9960 case 0x3c: /* URECPE */
9962 unallocated_encoding(s
);
9966 case 0x3d: /* FRECPE */
9967 case 0x7d: /* FRSQRTE */
9968 if (size
== 3 && !is_q
) {
9969 unallocated_encoding(s
);
9972 if (!fp_access_check(s
)) {
9975 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9977 case 0x56: /* FCVTXN, FCVTXN2 */
9979 unallocated_encoding(s
);
9983 case 0x16: /* FCVTN, FCVTN2 */
9984 /* handle_2misc_narrow does a 2*size -> size operation, but these
9985 * instructions encode the source size rather than dest size.
9987 if (!fp_access_check(s
)) {
9990 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9992 case 0x17: /* FCVTL, FCVTL2 */
9993 if (!fp_access_check(s
)) {
9996 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9998 case 0x18: /* FRINTN */
9999 case 0x19: /* FRINTM */
10000 case 0x38: /* FRINTP */
10001 case 0x39: /* FRINTZ */
10003 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10005 case 0x59: /* FRINTX */
10006 case 0x79: /* FRINTI */
10007 need_fpstatus
= true;
10008 if (size
== 3 && !is_q
) {
10009 unallocated_encoding(s
);
10013 case 0x58: /* FRINTA */
10015 rmode
= FPROUNDING_TIEAWAY
;
10016 need_fpstatus
= true;
10017 if (size
== 3 && !is_q
) {
10018 unallocated_encoding(s
);
10022 case 0x7c: /* URSQRTE */
10024 unallocated_encoding(s
);
10027 need_fpstatus
= true;
10030 unallocated_encoding(s
);
10036 unallocated_encoding(s
);
10040 if (!fp_access_check(s
)) {
10044 if (need_fpstatus
) {
10045 tcg_fpstatus
= get_fpstatus_ptr();
10047 TCGV_UNUSED_PTR(tcg_fpstatus
);
10050 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10051 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10053 TCGV_UNUSED_I32(tcg_rmode
);
10057 /* All 64-bit element operations can be shared with scalar 2misc */
10060 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10061 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10062 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10064 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10066 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10067 tcg_rmode
, tcg_fpstatus
);
10069 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10071 tcg_temp_free_i64(tcg_res
);
10072 tcg_temp_free_i64(tcg_op
);
10077 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10078 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10079 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10082 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10085 /* Special cases for 32 bit elements */
10087 case 0xa: /* CMLT */
10088 /* 32 bit integer comparison against zero, result is
10089 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10092 cond
= TCG_COND_LT
;
10094 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10095 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10097 case 0x8: /* CMGT, CMGE */
10098 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10100 case 0x9: /* CMEQ, CMLE */
10101 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10103 case 0x4: /* CLS */
10105 gen_helper_clz32(tcg_res
, tcg_op
);
10107 gen_helper_cls32(tcg_res
, tcg_op
);
10110 case 0x7: /* SQABS, SQNEG */
10112 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10114 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10117 case 0xb: /* ABS, NEG */
10119 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10121 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10122 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10123 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10124 tcg_zero
, tcg_op
, tcg_res
);
10125 tcg_temp_free_i32(tcg_zero
);
10128 case 0x2f: /* FABS */
10129 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10131 case 0x6f: /* FNEG */
10132 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10134 case 0x7f: /* FSQRT */
10135 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10137 case 0x1a: /* FCVTNS */
10138 case 0x1b: /* FCVTMS */
10139 case 0x1c: /* FCVTAS */
10140 case 0x3a: /* FCVTPS */
10141 case 0x3b: /* FCVTZS */
10143 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10144 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10145 tcg_shift
, tcg_fpstatus
);
10146 tcg_temp_free_i32(tcg_shift
);
10149 case 0x5a: /* FCVTNU */
10150 case 0x5b: /* FCVTMU */
10151 case 0x5c: /* FCVTAU */
10152 case 0x7a: /* FCVTPU */
10153 case 0x7b: /* FCVTZU */
10155 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10156 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10157 tcg_shift
, tcg_fpstatus
);
10158 tcg_temp_free_i32(tcg_shift
);
10161 case 0x18: /* FRINTN */
10162 case 0x19: /* FRINTM */
10163 case 0x38: /* FRINTP */
10164 case 0x39: /* FRINTZ */
10165 case 0x58: /* FRINTA */
10166 case 0x79: /* FRINTI */
10167 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10169 case 0x59: /* FRINTX */
10170 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10172 case 0x7c: /* URSQRTE */
10173 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10176 g_assert_not_reached();
10179 /* Use helpers for 8 and 16 bit elements */
10181 case 0x5: /* CNT, RBIT */
10182 /* For these two insns size is part of the opcode specifier
10183 * (handled earlier); they always operate on byte elements.
10186 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10188 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10191 case 0x7: /* SQABS, SQNEG */
10193 NeonGenOneOpEnvFn
*genfn
;
10194 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10195 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10196 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10198 genfn
= fns
[size
][u
];
10199 genfn(tcg_res
, cpu_env
, tcg_op
);
10202 case 0x8: /* CMGT, CMGE */
10203 case 0x9: /* CMEQ, CMLE */
10204 case 0xa: /* CMLT */
10206 static NeonGenTwoOpFn
* const fns
[3][2] = {
10207 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10208 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10209 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10211 NeonGenTwoOpFn
*genfn
;
10214 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10216 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10217 comp
= (opcode
- 0x8) * 2 + u
;
10218 /* ...but LE, LT are implemented as reverse GE, GT */
10219 reverse
= (comp
> 2);
10223 genfn
= fns
[comp
][size
];
10225 genfn(tcg_res
, tcg_zero
, tcg_op
);
10227 genfn(tcg_res
, tcg_op
, tcg_zero
);
10229 tcg_temp_free_i32(tcg_zero
);
10232 case 0xb: /* ABS, NEG */
10234 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10236 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10238 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10240 tcg_temp_free_i32(tcg_zero
);
10243 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10245 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10249 case 0x4: /* CLS, CLZ */
10252 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10254 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10258 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10260 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10265 g_assert_not_reached();
10269 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10271 tcg_temp_free_i32(tcg_res
);
10272 tcg_temp_free_i32(tcg_op
);
10276 clear_vec_high(s
, rd
);
10280 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10281 tcg_temp_free_i32(tcg_rmode
);
10283 if (need_fpstatus
) {
10284 tcg_temp_free_ptr(tcg_fpstatus
);
10288 /* C3.6.13 AdvSIMD scalar x indexed element
10289 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10290 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10291 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10292 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10293 * C3.6.18 AdvSIMD vector x indexed element
10294 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10295 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10296 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10297 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10299 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10301 /* This encoding has two kinds of instruction:
10302 * normal, where we perform elt x idxelt => elt for each
10303 * element in the vector
10304 * long, where we perform elt x idxelt and generate a result of
10305 * double the width of the input element
10306 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10308 bool is_scalar
= extract32(insn
, 28, 1);
10309 bool is_q
= extract32(insn
, 30, 1);
10310 bool u
= extract32(insn
, 29, 1);
10311 int size
= extract32(insn
, 22, 2);
10312 int l
= extract32(insn
, 21, 1);
10313 int m
= extract32(insn
, 20, 1);
10314 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10315 int rm
= extract32(insn
, 16, 4);
10316 int opcode
= extract32(insn
, 12, 4);
10317 int h
= extract32(insn
, 11, 1);
10318 int rn
= extract32(insn
, 5, 5);
10319 int rd
= extract32(insn
, 0, 5);
10320 bool is_long
= false;
10321 bool is_fp
= false;
10326 case 0x0: /* MLA */
10327 case 0x4: /* MLS */
10328 if (!u
|| is_scalar
) {
10329 unallocated_encoding(s
);
10333 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10334 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10335 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10337 unallocated_encoding(s
);
10342 case 0x3: /* SQDMLAL, SQDMLAL2 */
10343 case 0x7: /* SQDMLSL, SQDMLSL2 */
10344 case 0xb: /* SQDMULL, SQDMULL2 */
10347 case 0xc: /* SQDMULH */
10348 case 0xd: /* SQRDMULH */
10350 unallocated_encoding(s
);
10354 case 0x8: /* MUL */
10355 if (u
|| is_scalar
) {
10356 unallocated_encoding(s
);
10360 case 0x1: /* FMLA */
10361 case 0x5: /* FMLS */
10363 unallocated_encoding(s
);
10367 case 0x9: /* FMUL, FMULX */
10368 if (!extract32(size
, 1, 1)) {
10369 unallocated_encoding(s
);
10375 unallocated_encoding(s
);
10380 /* low bit of size indicates single/double */
10381 size
= extract32(size
, 0, 1) ? 3 : 2;
10383 index
= h
<< 1 | l
;
10386 unallocated_encoding(s
);
10395 index
= h
<< 2 | l
<< 1 | m
;
10398 index
= h
<< 1 | l
;
10402 unallocated_encoding(s
);
10407 if (!fp_access_check(s
)) {
10412 fpst
= get_fpstatus_ptr();
10414 TCGV_UNUSED_PTR(fpst
);
10418 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10421 assert(is_fp
&& is_q
&& !is_long
);
10423 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10425 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10426 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10427 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10429 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10432 case 0x5: /* FMLS */
10433 /* As usual for ARM, separate negation for fused multiply-add */
10434 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10436 case 0x1: /* FMLA */
10437 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10438 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10440 case 0x9: /* FMUL, FMULX */
10442 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10444 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10448 g_assert_not_reached();
10451 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10452 tcg_temp_free_i64(tcg_op
);
10453 tcg_temp_free_i64(tcg_res
);
10457 clear_vec_high(s
, rd
);
10460 tcg_temp_free_i64(tcg_idx
);
10461 } else if (!is_long
) {
10462 /* 32 bit floating point, or 16 or 32 bit integer.
10463 * For the 16 bit scalar case we use the usual Neon helpers and
10464 * rely on the fact that 0 op 0 == 0 with no side effects.
10466 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10467 int pass
, maxpasses
;
10472 maxpasses
= is_q
? 4 : 2;
10475 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10477 if (size
== 1 && !is_scalar
) {
10478 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10479 * the index into both halves of the 32 bit tcg_idx and then use
10480 * the usual Neon helpers.
10482 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10485 for (pass
= 0; pass
< maxpasses
; pass
++) {
10486 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10487 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10489 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10492 case 0x0: /* MLA */
10493 case 0x4: /* MLS */
10494 case 0x8: /* MUL */
10496 static NeonGenTwoOpFn
* const fns
[2][2] = {
10497 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10498 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10500 NeonGenTwoOpFn
*genfn
;
10501 bool is_sub
= opcode
== 0x4;
10504 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10506 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10508 if (opcode
== 0x8) {
10511 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10512 genfn
= fns
[size
- 1][is_sub
];
10513 genfn(tcg_res
, tcg_op
, tcg_res
);
10516 case 0x5: /* FMLS */
10517 /* As usual for ARM, separate negation for fused multiply-add */
10518 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10520 case 0x1: /* FMLA */
10521 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10522 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10524 case 0x9: /* FMUL, FMULX */
10526 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10528 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10531 case 0xc: /* SQDMULH */
10533 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10536 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10540 case 0xd: /* SQRDMULH */
10542 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10545 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10550 g_assert_not_reached();
10554 write_fp_sreg(s
, rd
, tcg_res
);
10556 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10559 tcg_temp_free_i32(tcg_op
);
10560 tcg_temp_free_i32(tcg_res
);
10563 tcg_temp_free_i32(tcg_idx
);
10566 clear_vec_high(s
, rd
);
10569 /* long ops: 16x16->32 or 32x32->64 */
10570 TCGv_i64 tcg_res
[2];
10572 bool satop
= extract32(opcode
, 0, 1);
10573 TCGMemOp memop
= MO_32
;
10580 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10582 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10584 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10585 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10586 TCGv_i64 tcg_passres
;
10592 passelt
= pass
+ (is_q
* 2);
10595 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10597 tcg_res
[pass
] = tcg_temp_new_i64();
10599 if (opcode
== 0xa || opcode
== 0xb) {
10600 /* Non-accumulating ops */
10601 tcg_passres
= tcg_res
[pass
];
10603 tcg_passres
= tcg_temp_new_i64();
10606 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10607 tcg_temp_free_i64(tcg_op
);
10610 /* saturating, doubling */
10611 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10612 tcg_passres
, tcg_passres
);
10615 if (opcode
== 0xa || opcode
== 0xb) {
10619 /* Accumulating op: handle accumulate step */
10620 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10623 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10624 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10626 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10627 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10629 case 0x7: /* SQDMLSL, SQDMLSL2 */
10630 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10632 case 0x3: /* SQDMLAL, SQDMLAL2 */
10633 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10638 g_assert_not_reached();
10640 tcg_temp_free_i64(tcg_passres
);
10642 tcg_temp_free_i64(tcg_idx
);
10645 clear_vec_high(s
, rd
);
10648 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10651 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10654 /* The simplest way to handle the 16x16 indexed ops is to
10655 * duplicate the index into both halves of the 32 bit tcg_idx
10656 * and then use the usual Neon helpers.
10658 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10661 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10662 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10663 TCGv_i64 tcg_passres
;
10666 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10668 read_vec_element_i32(s
, tcg_op
, rn
,
10669 pass
+ (is_q
* 2), MO_32
);
10672 tcg_res
[pass
] = tcg_temp_new_i64();
10674 if (opcode
== 0xa || opcode
== 0xb) {
10675 /* Non-accumulating ops */
10676 tcg_passres
= tcg_res
[pass
];
10678 tcg_passres
= tcg_temp_new_i64();
10681 if (memop
& MO_SIGN
) {
10682 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10684 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10687 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10688 tcg_passres
, tcg_passres
);
10690 tcg_temp_free_i32(tcg_op
);
10692 if (opcode
== 0xa || opcode
== 0xb) {
10696 /* Accumulating op: handle accumulate step */
10697 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10700 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10701 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10704 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10705 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10708 case 0x7: /* SQDMLSL, SQDMLSL2 */
10709 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10711 case 0x3: /* SQDMLAL, SQDMLAL2 */
10712 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10717 g_assert_not_reached();
10719 tcg_temp_free_i64(tcg_passres
);
10721 tcg_temp_free_i32(tcg_idx
);
10724 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10729 tcg_res
[1] = tcg_const_i64(0);
10732 for (pass
= 0; pass
< 2; pass
++) {
10733 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10734 tcg_temp_free_i64(tcg_res
[pass
]);
10738 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10739 tcg_temp_free_ptr(fpst
);
10743 /* C3.6.19 Crypto AES
10744 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10745 * +-----------------+------+-----------+--------+-----+------+------+
10746 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10747 * +-----------------+------+-----------+--------+-----+------+------+
10749 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10751 int size
= extract32(insn
, 22, 2);
10752 int opcode
= extract32(insn
, 12, 5);
10753 int rn
= extract32(insn
, 5, 5);
10754 int rd
= extract32(insn
, 0, 5);
10756 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10757 CryptoThreeOpEnvFn
*genfn
;
10759 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10761 unallocated_encoding(s
);
10766 case 0x4: /* AESE */
10768 genfn
= gen_helper_crypto_aese
;
10770 case 0x6: /* AESMC */
10772 genfn
= gen_helper_crypto_aesmc
;
10774 case 0x5: /* AESD */
10776 genfn
= gen_helper_crypto_aese
;
10778 case 0x7: /* AESIMC */
10780 genfn
= gen_helper_crypto_aesmc
;
10783 unallocated_encoding(s
);
10787 /* Note that we convert the Vx register indexes into the
10788 * index within the vfp.regs[] array, so we can share the
10789 * helper with the AArch32 instructions.
10791 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10792 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10793 tcg_decrypt
= tcg_const_i32(decrypt
);
10795 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10797 tcg_temp_free_i32(tcg_rd_regno
);
10798 tcg_temp_free_i32(tcg_rn_regno
);
10799 tcg_temp_free_i32(tcg_decrypt
);
10802 /* C3.6.20 Crypto three-reg SHA
10803 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10804 * +-----------------+------+---+------+---+--------+-----+------+------+
10805 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10806 * +-----------------+------+---+------+---+--------+-----+------+------+
10808 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10810 int size
= extract32(insn
, 22, 2);
10811 int opcode
= extract32(insn
, 12, 3);
10812 int rm
= extract32(insn
, 16, 5);
10813 int rn
= extract32(insn
, 5, 5);
10814 int rd
= extract32(insn
, 0, 5);
10815 CryptoThreeOpEnvFn
*genfn
;
10816 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10817 int feature
= ARM_FEATURE_V8_SHA256
;
10820 unallocated_encoding(s
);
10825 case 0: /* SHA1C */
10826 case 1: /* SHA1P */
10827 case 2: /* SHA1M */
10828 case 3: /* SHA1SU0 */
10830 feature
= ARM_FEATURE_V8_SHA1
;
10832 case 4: /* SHA256H */
10833 genfn
= gen_helper_crypto_sha256h
;
10835 case 5: /* SHA256H2 */
10836 genfn
= gen_helper_crypto_sha256h2
;
10838 case 6: /* SHA256SU1 */
10839 genfn
= gen_helper_crypto_sha256su1
;
10842 unallocated_encoding(s
);
10846 if (!arm_dc_feature(s
, feature
)) {
10847 unallocated_encoding(s
);
10851 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10852 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10853 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10856 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10858 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10860 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10861 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10862 tcg_temp_free_i32(tcg_opcode
);
10865 tcg_temp_free_i32(tcg_rd_regno
);
10866 tcg_temp_free_i32(tcg_rn_regno
);
10867 tcg_temp_free_i32(tcg_rm_regno
);
10870 /* C3.6.21 Crypto two-reg SHA
10871 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10872 * +-----------------+------+-----------+--------+-----+------+------+
10873 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10874 * +-----------------+------+-----------+--------+-----+------+------+
10876 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10878 int size
= extract32(insn
, 22, 2);
10879 int opcode
= extract32(insn
, 12, 5);
10880 int rn
= extract32(insn
, 5, 5);
10881 int rd
= extract32(insn
, 0, 5);
10882 CryptoTwoOpEnvFn
*genfn
;
10884 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10887 unallocated_encoding(s
);
10892 case 0: /* SHA1H */
10893 feature
= ARM_FEATURE_V8_SHA1
;
10894 genfn
= gen_helper_crypto_sha1h
;
10896 case 1: /* SHA1SU1 */
10897 feature
= ARM_FEATURE_V8_SHA1
;
10898 genfn
= gen_helper_crypto_sha1su1
;
10900 case 2: /* SHA256SU0 */
10901 feature
= ARM_FEATURE_V8_SHA256
;
10902 genfn
= gen_helper_crypto_sha256su0
;
10905 unallocated_encoding(s
);
10909 if (!arm_dc_feature(s
, feature
)) {
10910 unallocated_encoding(s
);
10914 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10915 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10917 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10919 tcg_temp_free_i32(tcg_rd_regno
);
10920 tcg_temp_free_i32(tcg_rn_regno
);
10923 /* C3.6 Data processing - SIMD, inc Crypto
10925 * As the decode gets a little complex we are using a table based
10926 * approach for this part of the decode.
10928 static const AArch64DecodeTable data_proc_simd
[] = {
10929 /* pattern , mask , fn */
10930 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10931 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10932 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10933 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10934 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10935 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10936 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10937 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10938 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10939 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10940 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10941 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10942 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10943 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10944 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10945 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10946 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10947 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10948 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10949 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10950 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10951 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10952 { 0x00000000, 0x00000000, NULL
}
10955 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10957 /* Note that this is called with all non-FP cases from
10958 * table C3-6 so it must UNDEF for entries not specifically
10959 * allocated to instructions in that table.
10961 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10965 unallocated_encoding(s
);
10969 /* C3.6 Data processing - SIMD and floating point */
10970 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10972 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10973 disas_data_proc_fp(s
, insn
);
10975 /* SIMD, including crypto */
10976 disas_data_proc_simd(s
, insn
);
10980 /* C3.1 A64 instruction index by encoding */
10981 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10985 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
10989 s
->fp_access_checked
= false;
10991 switch (extract32(insn
, 25, 4)) {
10992 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10993 unallocated_encoding(s
);
10995 case 0x8: case 0x9: /* Data processing - immediate */
10996 disas_data_proc_imm(s
, insn
);
10998 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10999 disas_b_exc_sys(s
, insn
);
11004 case 0xe: /* Loads and stores */
11005 disas_ldst(s
, insn
);
11008 case 0xd: /* Data processing - register */
11009 disas_data_proc_reg(s
, insn
);
11012 case 0xf: /* Data processing - SIMD and floating point */
11013 disas_data_proc_simd_fp(s
, insn
);
11016 assert(FALSE
); /* all 15 cases should be handled above */
11020 /* if we allocated any temporaries, free them here */
11024 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11026 CPUState
*cs
= CPU(cpu
);
11027 CPUARMState
*env
= &cpu
->env
;
11028 DisasContext dc1
, *dc
= &dc1
;
11029 target_ulong pc_start
;
11030 target_ulong next_page_start
;
11038 dc
->is_jmp
= DISAS_NEXT
;
11040 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11044 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11045 * there is no secure EL1, so we route exceptions to EL3.
11047 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11048 !arm_el_is_aa64(env
, 3);
11051 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11052 dc
->condexec_mask
= 0;
11053 dc
->condexec_cond
= 0;
11054 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11055 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11056 #if !defined(CONFIG_USER_ONLY)
11057 dc
->user
= (dc
->current_el
== 0);
11059 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11061 dc
->vec_stride
= 0;
11062 dc
->cp_regs
= cpu
->cp_regs
;
11063 dc
->features
= env
->features
;
11065 /* Single step state. The code-generation logic here is:
11067 * generate code with no special handling for single-stepping (except
11068 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11069 * this happens anyway because those changes are all system register or
11071 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11072 * emit code for one insn
11073 * emit code to clear PSTATE.SS
11074 * emit code to generate software step exception for completed step
11075 * end TB (as usual for having generated an exception)
11076 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11077 * emit code to generate a software step exception
11080 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11081 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11082 dc
->is_ldex
= false;
11083 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11085 init_tmp_a64_array(dc
);
11087 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11089 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11090 if (max_insns
== 0) {
11091 max_insns
= CF_COUNT_MASK
;
11093 if (max_insns
> TCG_MAX_INSNS
) {
11094 max_insns
= TCG_MAX_INSNS
;
11099 tcg_clear_temp_count();
11102 tcg_gen_insn_start(dc
->pc
, 0);
11105 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11107 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11108 if (bp
->pc
== dc
->pc
) {
11109 if (bp
->flags
& BP_CPU
) {
11110 gen_a64_set_pc_im(dc
->pc
);
11111 gen_helper_check_breakpoints(cpu_env
);
11112 /* End the TB early; it likely won't be executed */
11113 dc
->is_jmp
= DISAS_UPDATE
;
11115 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11116 /* The address covered by the breakpoint must be
11117 included in [tb->pc, tb->pc + tb->size) in order
11118 to for it to be properly cleared -- thus we
11119 increment the PC here so that the logic setting
11120 tb->size below does the right thing. */
11122 goto done_generating
;
11129 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11133 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11134 /* Singlestep state is Active-pending.
11135 * If we're in this state at the start of a TB then either
11136 * a) we just took an exception to an EL which is being debugged
11137 * and this is the first insn in the exception handler
11138 * b) debug exceptions were masked and we just unmasked them
11139 * without changing EL (eg by clearing PSTATE.D)
11140 * In either case we're going to take a swstep exception in the
11141 * "did not step an insn" case, and so the syndrome ISV and EX
11142 * bits should be zero.
11144 assert(num_insns
== 1);
11145 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11146 default_exception_el(dc
));
11147 dc
->is_jmp
= DISAS_EXC
;
11151 disas_a64_insn(env
, dc
);
11153 if (tcg_check_temp_count()) {
11154 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11158 /* Translation stops when a conditional branch is encountered.
11159 * Otherwise the subsequent code could get translated several times.
11160 * Also stop translation when a page boundary is reached. This
11161 * ensures prefetch aborts occur at the right place.
11163 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11164 !cs
->singlestep_enabled
&&
11167 dc
->pc
< next_page_start
&&
11168 num_insns
< max_insns
);
11170 if (tb
->cflags
& CF_LAST_IO
) {
11174 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11175 && dc
->is_jmp
!= DISAS_EXC
) {
11176 /* Note that this means single stepping WFI doesn't halt the CPU.
11177 * For conditional branch insns this is harmless unreachable code as
11178 * gen_goto_tb() has already handled emitting the debug exception
11179 * (and thus a tb-jump is not possible when singlestepping).
11181 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11182 if (dc
->is_jmp
!= DISAS_JUMP
) {
11183 gen_a64_set_pc_im(dc
->pc
);
11185 if (cs
->singlestep_enabled
) {
11186 gen_exception_internal(EXCP_DEBUG
);
11188 gen_step_complete_exception(dc
);
11191 switch (dc
->is_jmp
) {
11193 gen_goto_tb(dc
, 1, dc
->pc
);
11197 gen_a64_set_pc_im(dc
->pc
);
11200 /* indicate that the hash table must be used to find the next TB */
11201 tcg_gen_exit_tb(0);
11203 case DISAS_TB_JUMP
:
11208 gen_a64_set_pc_im(dc
->pc
);
11209 gen_helper_wfe(cpu_env
);
11212 gen_a64_set_pc_im(dc
->pc
);
11213 gen_helper_yield(cpu_env
);
11216 /* This is a special case because we don't want to just halt the CPU
11217 * if trying to debug across a WFI.
11219 gen_a64_set_pc_im(dc
->pc
);
11220 gen_helper_wfi(cpu_env
);
11221 /* The helper doesn't necessarily throw an exception, but we
11222 * must go back to the main loop to check for interrupts anyway.
11224 tcg_gen_exit_tb(0);
11230 gen_tb_end(tb
, num_insns
);
11233 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11234 qemu_log_in_addr_range(pc_start
)) {
11235 qemu_log("----------------\n");
11236 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11237 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11238 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11242 tb
->size
= dc
->pc
- pc_start
;
11243 tb
->icount
= num_insns
;