3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/exec-all.h"
40 #include "exec/cpu_ldst.h"
41 #include "exec/semihost.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
46 #include "trace-tcg.h"
50 typedef struct DisasContext
{
51 const XtensaConfig
*config
;
61 int singlestep_enabled
;
65 bool sar_m32_allocated
;
68 uint32_t ccount_delta
;
78 static TCGv_env cpu_env
;
79 static TCGv_i32 cpu_pc
;
80 static TCGv_i32 cpu_R
[16];
81 static TCGv_i32 cpu_FR
[16];
82 static TCGv_i32 cpu_SR
[256];
83 static TCGv_i32 cpu_UR
[256];
85 #include "exec/gen-icount.h"
87 typedef struct XtensaReg
{
99 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
101 .opt_bits = XTENSA_OPTION_BIT(opt), \
105 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
107 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
113 #define XTENSA_REG_BITS(regname, opt) \
114 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
116 static const XtensaReg sregnames
[256] = {
117 [LBEG
] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP
),
118 [LEND
] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP
),
119 [LCOUNT
] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP
),
120 [SAR
] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL
),
121 [BR
] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN
),
122 [LITBASE
] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R
),
123 [SCOMPARE1
] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE
),
124 [ACCLO
] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16
),
125 [ACCHI
] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16
),
126 [MR
] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16
),
127 [MR
+ 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16
),
128 [MR
+ 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16
),
129 [MR
+ 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16
),
130 [WINDOW_BASE
] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER
),
131 [WINDOW_START
] = XTENSA_REG("WINDOW_START",
132 XTENSA_OPTION_WINDOWED_REGISTER
),
133 [PTEVADDR
] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU
),
134 [RASID
] = XTENSA_REG("RASID", XTENSA_OPTION_MMU
),
135 [ITLBCFG
] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU
),
136 [DTLBCFG
] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU
),
137 [IBREAKENABLE
] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG
),
138 [CACHEATTR
] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR
),
139 [ATOMCTL
] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL
),
140 [IBREAKA
] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG
),
141 [IBREAKA
+ 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG
),
142 [DBREAKA
] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG
),
143 [DBREAKA
+ 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG
),
144 [DBREAKC
] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG
),
145 [DBREAKC
+ 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG
),
146 [CONFIGID0
] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL
, SR_R
),
147 [EPC1
] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION
),
148 [EPC1
+ 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
149 [EPC1
+ 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
150 [EPC1
+ 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
151 [EPC1
+ 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
152 [EPC1
+ 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
153 [EPC1
+ 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
154 [DEPC
] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION
),
155 [EPS2
] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
156 [EPS2
+ 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
157 [EPS2
+ 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
158 [EPS2
+ 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
159 [EPS2
+ 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
160 [EPS2
+ 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
161 [CONFIGID1
] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL
, SR_R
),
162 [EXCSAVE1
] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION
),
163 [EXCSAVE1
+ 1] = XTENSA_REG("EXCSAVE2",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
165 [EXCSAVE1
+ 2] = XTENSA_REG("EXCSAVE3",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
167 [EXCSAVE1
+ 3] = XTENSA_REG("EXCSAVE4",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
169 [EXCSAVE1
+ 4] = XTENSA_REG("EXCSAVE5",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
171 [EXCSAVE1
+ 5] = XTENSA_REG("EXCSAVE6",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
173 [EXCSAVE1
+ 6] = XTENSA_REG("EXCSAVE7",
174 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
),
175 [CPENABLE
] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR
),
176 [INTSET
] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT
, SR_RW
),
177 [INTCLEAR
] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT
, SR_W
),
178 [INTENABLE
] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT
),
179 [PS
] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL
),
180 [VECBASE
] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR
),
181 [EXCCAUSE
] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION
),
182 [DEBUGCAUSE
] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG
, SR_R
),
183 [CCOUNT
] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT
),
184 [PRID
] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID
, SR_R
),
185 [ICOUNT
] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG
),
186 [ICOUNTLEVEL
] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG
),
187 [EXCVADDR
] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION
),
188 [CCOMPARE
] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT
),
189 [CCOMPARE
+ 1] = XTENSA_REG("CCOMPARE1",
190 XTENSA_OPTION_TIMER_INTERRUPT
),
191 [CCOMPARE
+ 2] = XTENSA_REG("CCOMPARE2",
192 XTENSA_OPTION_TIMER_INTERRUPT
),
193 [MISC
] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR
),
194 [MISC
+ 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR
),
195 [MISC
+ 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR
),
196 [MISC
+ 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR
),
199 static const XtensaReg uregnames
[256] = {
200 [THREADPTR
] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER
),
201 [FCR
] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR
),
202 [FSR
] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR
),
205 void xtensa_translate_init(void)
207 static const char * const regnames
[] = {
208 "ar0", "ar1", "ar2", "ar3",
209 "ar4", "ar5", "ar6", "ar7",
210 "ar8", "ar9", "ar10", "ar11",
211 "ar12", "ar13", "ar14", "ar15",
213 static const char * const fregnames
[] = {
214 "f0", "f1", "f2", "f3",
215 "f4", "f5", "f6", "f7",
216 "f8", "f9", "f10", "f11",
217 "f12", "f13", "f14", "f15",
221 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
222 cpu_pc
= tcg_global_mem_new_i32(cpu_env
,
223 offsetof(CPUXtensaState
, pc
), "pc");
225 for (i
= 0; i
< 16; i
++) {
226 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
227 offsetof(CPUXtensaState
, regs
[i
]),
231 for (i
= 0; i
< 16; i
++) {
232 cpu_FR
[i
] = tcg_global_mem_new_i32(cpu_env
,
233 offsetof(CPUXtensaState
, fregs
[i
].f32
[FP_F32_LOW
]),
237 for (i
= 0; i
< 256; ++i
) {
238 if (sregnames
[i
].name
) {
239 cpu_SR
[i
] = tcg_global_mem_new_i32(cpu_env
,
240 offsetof(CPUXtensaState
, sregs
[i
]),
245 for (i
= 0; i
< 256; ++i
) {
246 if (uregnames
[i
].name
) {
247 cpu_UR
[i
] = tcg_global_mem_new_i32(cpu_env
,
248 offsetof(CPUXtensaState
, uregs
[i
]),
254 static inline bool option_bits_enabled(DisasContext
*dc
, uint64_t opt
)
256 return xtensa_option_bits_enabled(dc
->config
, opt
);
259 static inline bool option_enabled(DisasContext
*dc
, int opt
)
261 return xtensa_option_enabled(dc
->config
, opt
);
264 static void init_litbase(DisasContext
*dc
)
266 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
267 dc
->litbase
= tcg_temp_local_new_i32();
268 tcg_gen_andi_i32(dc
->litbase
, cpu_SR
[LITBASE
], 0xfffff000);
272 static void reset_litbase(DisasContext
*dc
)
274 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
275 tcg_temp_free(dc
->litbase
);
279 static void init_sar_tracker(DisasContext
*dc
)
281 dc
->sar_5bit
= false;
282 dc
->sar_m32_5bit
= false;
283 dc
->sar_m32_allocated
= false;
286 static void reset_sar_tracker(DisasContext
*dc
)
288 if (dc
->sar_m32_allocated
) {
289 tcg_temp_free(dc
->sar_m32
);
293 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
295 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
296 if (dc
->sar_m32_5bit
) {
297 tcg_gen_discard_i32(dc
->sar_m32
);
300 dc
->sar_m32_5bit
= false;
303 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
305 TCGv_i32 tmp
= tcg_const_i32(32);
306 if (!dc
->sar_m32_allocated
) {
307 dc
->sar_m32
= tcg_temp_local_new_i32();
308 dc
->sar_m32_allocated
= true;
310 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
311 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
312 dc
->sar_5bit
= false;
313 dc
->sar_m32_5bit
= true;
317 static void gen_advance_ccount(DisasContext
*dc
)
319 if (dc
->ccount_delta
> 0) {
320 TCGv_i32 tmp
= tcg_const_i32(dc
->ccount_delta
);
321 gen_helper_advance_ccount(cpu_env
, tmp
);
324 dc
->ccount_delta
= 0;
327 static void gen_exception(DisasContext
*dc
, int excp
)
329 TCGv_i32 tmp
= tcg_const_i32(excp
);
330 gen_advance_ccount(dc
);
331 gen_helper_exception(cpu_env
, tmp
);
335 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
337 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
338 TCGv_i32 tcause
= tcg_const_i32(cause
);
339 gen_advance_ccount(dc
);
340 gen_helper_exception_cause(cpu_env
, tpc
, tcause
);
342 tcg_temp_free(tcause
);
343 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
344 cause
== SYSCALL_CAUSE
) {
345 dc
->is_jmp
= DISAS_UPDATE
;
349 static void gen_exception_cause_vaddr(DisasContext
*dc
, uint32_t cause
,
352 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
353 TCGv_i32 tcause
= tcg_const_i32(cause
);
354 gen_advance_ccount(dc
);
355 gen_helper_exception_cause_vaddr(cpu_env
, tpc
, tcause
, vaddr
);
357 tcg_temp_free(tcause
);
360 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
362 TCGv_i32 tpc
= tcg_const_i32(dc
->pc
);
363 TCGv_i32 tcause
= tcg_const_i32(cause
);
364 gen_advance_ccount(dc
);
365 gen_helper_debug_exception(cpu_env
, tpc
, tcause
);
367 tcg_temp_free(tcause
);
368 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
369 dc
->is_jmp
= DISAS_UPDATE
;
373 static bool gen_check_privilege(DisasContext
*dc
)
376 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
377 dc
->is_jmp
= DISAS_UPDATE
;
383 static bool gen_check_cpenable(DisasContext
*dc
, unsigned cp
)
385 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) &&
386 !(dc
->cpenable
& (1 << cp
))) {
387 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ cp
);
388 dc
->is_jmp
= DISAS_UPDATE
;
394 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
396 tcg_gen_mov_i32(cpu_pc
, dest
);
397 gen_advance_ccount(dc
);
399 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
401 if (dc
->singlestep_enabled
) {
402 gen_exception(dc
, EXCP_DEBUG
);
405 tcg_gen_goto_tb(slot
);
406 tcg_gen_exit_tb((uintptr_t)dc
->tb
+ slot
);
411 dc
->is_jmp
= DISAS_UPDATE
;
414 static void gen_jump(DisasContext
*dc
, TCGv dest
)
416 gen_jump_slot(dc
, dest
, -1);
419 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
421 TCGv_i32 tmp
= tcg_const_i32(dest
);
422 #ifndef CONFIG_USER_ONLY
423 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
427 gen_jump_slot(dc
, tmp
, slot
);
431 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
434 TCGv_i32 tcallinc
= tcg_const_i32(callinc
);
436 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
437 tcallinc
, PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
438 tcg_temp_free(tcallinc
);
439 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
440 (callinc
<< 30) | (dc
->next_pc
& 0x3fffffff));
441 gen_jump_slot(dc
, dest
, slot
);
444 static void gen_callw(DisasContext
*dc
, int callinc
, TCGv_i32 dest
)
446 gen_callw_slot(dc
, callinc
, dest
, -1);
449 static void gen_callwi(DisasContext
*dc
, int callinc
, uint32_t dest
, int slot
)
451 TCGv_i32 tmp
= tcg_const_i32(dest
);
452 #ifndef CONFIG_USER_ONLY
453 if (((dc
->tb
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
457 gen_callw_slot(dc
, callinc
, tmp
, slot
);
461 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
463 if (option_enabled(dc
, XTENSA_OPTION_LOOP
) &&
464 !(dc
->tb
->flags
& XTENSA_TBFLAG_EXCM
) &&
465 dc
->next_pc
== dc
->lend
) {
466 TCGLabel
*label
= gen_new_label();
468 gen_advance_ccount(dc
);
469 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
470 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
471 gen_jumpi(dc
, dc
->lbeg
, slot
);
472 gen_set_label(label
);
473 gen_jumpi(dc
, dc
->next_pc
, -1);
479 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
481 if (!gen_check_loop_end(dc
, slot
)) {
482 gen_jumpi(dc
, dc
->next_pc
, slot
);
486 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
487 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
489 TCGLabel
*label
= gen_new_label();
491 gen_advance_ccount(dc
);
492 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
493 gen_jumpi_check_loop_end(dc
, 0);
494 gen_set_label(label
);
495 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
498 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
499 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
501 TCGv_i32 tmp
= tcg_const_i32(t1
);
502 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
506 static bool gen_check_sr(DisasContext
*dc
, uint32_t sr
, unsigned access
)
508 if (!xtensa_option_bits_enabled(dc
->config
, sregnames
[sr
].opt_bits
)) {
509 if (sregnames
[sr
].name
) {
510 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not configured\n", sregnames
[sr
].name
);
512 qemu_log_mask(LOG_UNIMP
, "SR %d is not implemented\n", sr
);
514 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
516 } else if (!(sregnames
[sr
].access
& access
)) {
517 static const char * const access_text
[] = {
522 assert(access
< ARRAY_SIZE(access_text
) && access_text
[access
]);
523 qemu_log_mask(LOG_GUEST_ERROR
, "SR %s is not available for %s\n", sregnames
[sr
].name
,
524 access_text
[access
]);
525 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
531 static void gen_rsr_ccount(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
533 gen_advance_ccount(dc
);
534 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
537 static void gen_rsr_ptevaddr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
539 tcg_gen_shri_i32(d
, cpu_SR
[EXCVADDR
], 10);
540 tcg_gen_or_i32(d
, d
, cpu_SR
[sr
]);
541 tcg_gen_andi_i32(d
, d
, 0xfffffffc);
544 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
546 static void (* const rsr_handler
[256])(DisasContext
*dc
,
547 TCGv_i32 d
, uint32_t sr
) = {
548 [CCOUNT
] = gen_rsr_ccount
,
549 [PTEVADDR
] = gen_rsr_ptevaddr
,
552 if (rsr_handler
[sr
]) {
553 rsr_handler
[sr
](dc
, d
, sr
);
555 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
559 static void gen_wsr_lbeg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
561 gen_helper_wsr_lbeg(cpu_env
, s
);
562 gen_jumpi_check_loop_end(dc
, 0);
565 static void gen_wsr_lend(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
567 gen_helper_wsr_lend(cpu_env
, s
);
568 gen_jumpi_check_loop_end(dc
, 0);
571 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
573 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
574 if (dc
->sar_m32_5bit
) {
575 tcg_gen_discard_i32(dc
->sar_m32
);
577 dc
->sar_5bit
= false;
578 dc
->sar_m32_5bit
= false;
581 static void gen_wsr_br(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
583 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xffff);
586 static void gen_wsr_litbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
588 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0xfffff001);
589 /* This can change tb->flags, so exit tb */
590 gen_jumpi_check_loop_end(dc
, -1);
593 static void gen_wsr_acchi(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
595 tcg_gen_ext8s_i32(cpu_SR
[sr
], s
);
598 static void gen_wsr_windowbase(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
600 gen_helper_wsr_windowbase(cpu_env
, v
);
601 /* This can change tb->flags, so exit tb */
602 gen_jumpi_check_loop_end(dc
, -1);
605 static void gen_wsr_windowstart(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
607 tcg_gen_andi_i32(cpu_SR
[sr
], v
, (1 << dc
->config
->nareg
/ 4) - 1);
608 /* This can change tb->flags, so exit tb */
609 gen_jumpi_check_loop_end(dc
, -1);
612 static void gen_wsr_ptevaddr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
614 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xffc00000);
617 static void gen_wsr_rasid(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
619 gen_helper_wsr_rasid(cpu_env
, v
);
620 /* This can change tb->flags, so exit tb */
621 gen_jumpi_check_loop_end(dc
, -1);
624 static void gen_wsr_tlbcfg(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
626 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x01130000);
629 static void gen_wsr_ibreakenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
631 gen_helper_wsr_ibreakenable(cpu_env
, v
);
632 gen_jumpi_check_loop_end(dc
, 0);
635 static void gen_wsr_atomctl(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
637 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0x3f);
640 static void gen_wsr_ibreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
642 unsigned id
= sr
- IBREAKA
;
644 if (id
< dc
->config
->nibreak
) {
645 TCGv_i32 tmp
= tcg_const_i32(id
);
646 gen_helper_wsr_ibreaka(cpu_env
, tmp
, v
);
648 gen_jumpi_check_loop_end(dc
, 0);
652 static void gen_wsr_dbreaka(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
654 unsigned id
= sr
- DBREAKA
;
656 if (id
< dc
->config
->ndbreak
) {
657 TCGv_i32 tmp
= tcg_const_i32(id
);
658 gen_helper_wsr_dbreaka(cpu_env
, tmp
, v
);
663 static void gen_wsr_dbreakc(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
665 unsigned id
= sr
- DBREAKC
;
667 if (id
< dc
->config
->ndbreak
) {
668 TCGv_i32 tmp
= tcg_const_i32(id
);
669 gen_helper_wsr_dbreakc(cpu_env
, tmp
, v
);
674 static void gen_wsr_cpenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
676 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xff);
677 /* This can change tb->flags, so exit tb */
678 gen_jumpi_check_loop_end(dc
, -1);
681 static void gen_wsr_intset(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
683 tcg_gen_andi_i32(cpu_SR
[sr
], v
,
684 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
685 gen_helper_check_interrupts(cpu_env
);
686 gen_jumpi_check_loop_end(dc
, 0);
689 static void gen_wsr_intclear(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
691 TCGv_i32 tmp
= tcg_temp_new_i32();
693 tcg_gen_andi_i32(tmp
, v
,
694 dc
->config
->inttype_mask
[INTTYPE_EDGE
] |
695 dc
->config
->inttype_mask
[INTTYPE_NMI
] |
696 dc
->config
->inttype_mask
[INTTYPE_SOFTWARE
]);
697 tcg_gen_andc_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], tmp
);
699 gen_helper_check_interrupts(cpu_env
);
702 static void gen_wsr_intenable(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
704 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
705 gen_helper_check_interrupts(cpu_env
);
706 gen_jumpi_check_loop_end(dc
, 0);
709 static void gen_wsr_ps(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
711 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
712 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
714 if (option_enabled(dc
, XTENSA_OPTION_MMU
)) {
717 tcg_gen_andi_i32(cpu_SR
[sr
], v
, mask
);
718 gen_helper_check_interrupts(cpu_env
);
719 /* This can change mmu index and tb->flags, so exit tb */
720 gen_jumpi_check_loop_end(dc
, -1);
723 static void gen_wsr_icount(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
726 tcg_gen_mov_i32(dc
->next_icount
, v
);
728 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
732 static void gen_wsr_icountlevel(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
734 tcg_gen_andi_i32(cpu_SR
[sr
], v
, 0xf);
735 /* This can change tb->flags, so exit tb */
736 gen_jumpi_check_loop_end(dc
, -1);
739 static void gen_wsr_ccompare(DisasContext
*dc
, uint32_t sr
, TCGv_i32 v
)
741 uint32_t id
= sr
- CCOMPARE
;
742 if (id
< dc
->config
->nccompare
) {
743 uint32_t int_bit
= 1 << dc
->config
->timerint
[id
];
744 gen_advance_ccount(dc
);
745 tcg_gen_mov_i32(cpu_SR
[sr
], v
);
746 tcg_gen_andi_i32(cpu_SR
[INTSET
], cpu_SR
[INTSET
], ~int_bit
);
747 gen_helper_check_interrupts(cpu_env
);
751 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
753 static void (* const wsr_handler
[256])(DisasContext
*dc
,
754 uint32_t sr
, TCGv_i32 v
) = {
755 [LBEG
] = gen_wsr_lbeg
,
756 [LEND
] = gen_wsr_lend
,
759 [LITBASE
] = gen_wsr_litbase
,
760 [ACCHI
] = gen_wsr_acchi
,
761 [WINDOW_BASE
] = gen_wsr_windowbase
,
762 [WINDOW_START
] = gen_wsr_windowstart
,
763 [PTEVADDR
] = gen_wsr_ptevaddr
,
764 [RASID
] = gen_wsr_rasid
,
765 [ITLBCFG
] = gen_wsr_tlbcfg
,
766 [DTLBCFG
] = gen_wsr_tlbcfg
,
767 [IBREAKENABLE
] = gen_wsr_ibreakenable
,
768 [ATOMCTL
] = gen_wsr_atomctl
,
769 [IBREAKA
] = gen_wsr_ibreaka
,
770 [IBREAKA
+ 1] = gen_wsr_ibreaka
,
771 [DBREAKA
] = gen_wsr_dbreaka
,
772 [DBREAKA
+ 1] = gen_wsr_dbreaka
,
773 [DBREAKC
] = gen_wsr_dbreakc
,
774 [DBREAKC
+ 1] = gen_wsr_dbreakc
,
775 [CPENABLE
] = gen_wsr_cpenable
,
776 [INTSET
] = gen_wsr_intset
,
777 [INTCLEAR
] = gen_wsr_intclear
,
778 [INTENABLE
] = gen_wsr_intenable
,
780 [ICOUNT
] = gen_wsr_icount
,
781 [ICOUNTLEVEL
] = gen_wsr_icountlevel
,
782 [CCOMPARE
] = gen_wsr_ccompare
,
783 [CCOMPARE
+ 1] = gen_wsr_ccompare
,
784 [CCOMPARE
+ 2] = gen_wsr_ccompare
,
787 if (wsr_handler
[sr
]) {
788 wsr_handler
[sr
](dc
, sr
, s
);
790 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
794 static void gen_wur(uint32_t ur
, TCGv_i32 s
)
798 gen_helper_wur_fcr(cpu_env
, s
);
802 tcg_gen_andi_i32(cpu_UR
[ur
], s
, 0xffffff80);
806 tcg_gen_mov_i32(cpu_UR
[ur
], s
);
811 static void gen_load_store_alignment(DisasContext
*dc
, int shift
,
812 TCGv_i32 addr
, bool no_hw_alignment
)
814 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
815 tcg_gen_andi_i32(addr
, addr
, ~0 << shift
);
816 } else if (option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
) &&
818 TCGLabel
*label
= gen_new_label();
819 TCGv_i32 tmp
= tcg_temp_new_i32();
820 tcg_gen_andi_i32(tmp
, addr
, ~(~0 << shift
));
821 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
822 gen_exception_cause_vaddr(dc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
823 gen_set_label(label
);
828 static void gen_waiti(DisasContext
*dc
, uint32_t imm4
)
830 TCGv_i32 pc
= tcg_const_i32(dc
->next_pc
);
831 TCGv_i32 intlevel
= tcg_const_i32(imm4
);
832 gen_advance_ccount(dc
);
833 gen_helper_waiti(cpu_env
, pc
, intlevel
);
835 tcg_temp_free(intlevel
);
838 static bool gen_window_check1(DisasContext
*dc
, unsigned r1
)
840 if (r1
/ 4 > dc
->window
) {
841 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
842 TCGv_i32 w
= tcg_const_i32(r1
/ 4);
844 gen_advance_ccount(dc
);
845 gen_helper_window_check(cpu_env
, pc
, w
);
846 dc
->is_jmp
= DISAS_UPDATE
;
852 static bool gen_window_check2(DisasContext
*dc
, unsigned r1
, unsigned r2
)
854 return gen_window_check1(dc
, r1
> r2
? r1
: r2
);
857 static bool gen_window_check3(DisasContext
*dc
, unsigned r1
, unsigned r2
,
860 return gen_window_check2(dc
, r1
, r2
> r3
? r2
: r3
);
863 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
865 TCGv_i32 m
= tcg_temp_new_i32();
868 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
870 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
875 static inline unsigned xtensa_op0_insn_len(unsigned op0
)
877 return op0
>= 8 ? 2 : 3;
880 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
882 #define HAS_OPTION_BITS(opt) do { \
883 if (!option_bits_enabled(dc, opt)) { \
884 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
885 __FILE__, __LINE__); \
886 goto invalid_opcode; \
890 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
892 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
893 #define RESERVED() do { \
894 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
895 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
896 goto invalid_opcode; \
900 #ifdef TARGET_WORDS_BIGENDIAN
901 #define OP0 (((b0) & 0xf0) >> 4)
902 #define OP1 (((b2) & 0xf0) >> 4)
903 #define OP2 ((b2) & 0xf)
904 #define RRR_R ((b1) & 0xf)
905 #define RRR_S (((b1) & 0xf0) >> 4)
906 #define RRR_T ((b0) & 0xf)
908 #define OP0 (((b0) & 0xf))
909 #define OP1 (((b2) & 0xf))
910 #define OP2 (((b2) & 0xf0) >> 4)
911 #define RRR_R (((b1) & 0xf0) >> 4)
912 #define RRR_S (((b1) & 0xf))
913 #define RRR_T (((b0) & 0xf0) >> 4)
915 #define RRR_X ((RRR_R & 0x4) >> 2)
916 #define RRR_Y ((RRR_T & 0x4) >> 2)
917 #define RRR_W (RRR_R & 0x3)
926 #ifdef TARGET_WORDS_BIGENDIAN
927 #define RRI4_IMM4 ((b2) & 0xf)
929 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
935 #define RRI8_IMM8 (b2)
936 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
938 #ifdef TARGET_WORDS_BIGENDIAN
939 #define RI16_IMM16 (((b1) << 8) | (b2))
941 #define RI16_IMM16 (((b2) << 8) | (b1))
944 #ifdef TARGET_WORDS_BIGENDIAN
945 #define CALL_N (((b0) & 0xc) >> 2)
946 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
948 #define CALL_N (((b0) & 0x30) >> 4)
949 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
951 #define CALL_OFFSET_SE \
952 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
954 #define CALLX_N CALL_N
955 #ifdef TARGET_WORDS_BIGENDIAN
956 #define CALLX_M ((b0) & 0x3)
958 #define CALLX_M (((b0) & 0xc0) >> 6)
960 #define CALLX_S RRR_S
962 #define BRI12_M CALLX_M
963 #define BRI12_S RRR_S
964 #ifdef TARGET_WORDS_BIGENDIAN
965 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
967 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
969 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
971 #define BRI8_M BRI12_M
972 #define BRI8_R RRI8_R
973 #define BRI8_S RRI8_S
974 #define BRI8_IMM8 RRI8_IMM8
975 #define BRI8_IMM8_SE RRI8_IMM8_SE
979 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
980 uint8_t b1
= cpu_ldub_code(env
, dc
->pc
+ 1);
982 unsigned len
= xtensa_op0_insn_len(OP0
);
984 static const uint32_t B4CONST
[] = {
985 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
988 static const uint32_t B4CONSTU
[] = {
989 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
994 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
998 b2
= cpu_ldub_code(env
, dc
->pc
+ 2);
1004 dc
->next_pc
= dc
->pc
+ len
;
1012 if ((RRR_R
& 0xc) == 0x8) {
1013 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1020 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1023 case 1: /*reserved*/
1031 if (gen_window_check1(dc
, CALLX_S
)) {
1032 gen_jump(dc
, cpu_R
[CALLX_S
]);
1037 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1039 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
1040 gen_advance_ccount(dc
);
1041 gen_helper_retw(tmp
, cpu_env
, tmp
);
1047 case 3: /*reserved*/
1054 if (!gen_window_check2(dc
, CALLX_S
, CALLX_N
<< 2)) {
1060 TCGv_i32 tmp
= tcg_temp_new_i32();
1061 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1062 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
1070 case 3: /*CALLX12w*/
1071 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1073 TCGv_i32 tmp
= tcg_temp_new_i32();
1075 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
1076 gen_callw(dc
, CALLX_N
, tmp
);
1086 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1087 if (gen_window_check2(dc
, RRR_T
, RRR_S
)) {
1088 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
1089 gen_advance_ccount(dc
);
1090 gen_helper_movsp(cpu_env
, pc
);
1091 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1111 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1123 default: /*reserved*/
1132 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1135 if (gen_check_privilege(dc
)) {
1136 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1137 gen_helper_check_interrupts(cpu_env
);
1138 gen_jump(dc
, cpu_SR
[EPC1
]);
1147 if (gen_check_privilege(dc
)) {
1148 gen_jump(dc
, cpu_SR
[
1149 dc
->config
->ndepc
? DEPC
: EPC1
]);
1155 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1156 if (gen_check_privilege(dc
)) {
1157 TCGv_i32 tmp
= tcg_const_i32(1);
1160 cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
1161 tcg_gen_shl_i32(tmp
, tmp
, cpu_SR
[WINDOW_BASE
]);
1164 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
1165 cpu_SR
[WINDOW_START
], tmp
);
1167 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
1168 cpu_SR
[WINDOW_START
], tmp
);
1171 gen_helper_restore_owb(cpu_env
);
1172 gen_helper_check_interrupts(cpu_env
);
1173 gen_jump(dc
, cpu_SR
[EPC1
]);
1179 default: /*reserved*/
1186 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
);
1187 if (RRR_S
>= 2 && RRR_S
<= dc
->config
->nlevel
) {
1188 if (gen_check_privilege(dc
)) {
1189 tcg_gen_mov_i32(cpu_SR
[PS
],
1190 cpu_SR
[EPS2
+ RRR_S
- 2]);
1191 gen_helper_check_interrupts(cpu_env
);
1192 gen_jump(dc
, cpu_SR
[EPC1
+ RRR_S
- 1]);
1195 qemu_log_mask(LOG_GUEST_ERROR
, "RFI %d is illegal\n", RRR_S
);
1196 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1204 default: /*reserved*/
1212 HAS_OPTION(XTENSA_OPTION_DEBUG
);
1214 gen_debug_exception(dc
, DEBUGCAUSE_BI
);
1218 case 5: /*SYSCALLx*/
1219 HAS_OPTION(XTENSA_OPTION_EXCEPTION
);
1221 case 0: /*SYSCALLx*/
1222 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1226 if (semihosting_enabled()) {
1227 if (gen_check_privilege(dc
)) {
1228 gen_helper_simcall(cpu_env
);
1231 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
1232 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1243 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1244 if (gen_check_privilege(dc
) &&
1245 gen_window_check1(dc
, RRR_T
)) {
1246 tcg_gen_mov_i32(cpu_R
[RRR_T
], cpu_SR
[PS
]);
1247 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
1248 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], RRR_S
);
1249 gen_helper_check_interrupts(cpu_env
);
1250 gen_jumpi_check_loop_end(dc
, 0);
1255 HAS_OPTION(XTENSA_OPTION_INTERRUPT
);
1256 if (gen_check_privilege(dc
)) {
1257 gen_waiti(dc
, RRR_S
);
1265 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1267 const unsigned shift
= (RRR_R
& 2) ? 8 : 4;
1268 TCGv_i32 mask
= tcg_const_i32(
1269 ((1 << shift
) - 1) << RRR_S
);
1270 TCGv_i32 tmp
= tcg_temp_new_i32();
1272 tcg_gen_and_i32(tmp
, cpu_SR
[BR
], mask
);
1273 if (RRR_R
& 1) { /*ALL*/
1274 tcg_gen_addi_i32(tmp
, tmp
, 1 << RRR_S
);
1276 tcg_gen_add_i32(tmp
, tmp
, mask
);
1278 tcg_gen_shri_i32(tmp
, tmp
, RRR_S
+ shift
);
1279 tcg_gen_deposit_i32(cpu_SR
[BR
], cpu_SR
[BR
],
1281 tcg_temp_free(mask
);
1286 default: /*reserved*/
1294 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1295 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1300 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1301 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1306 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1307 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1314 if (gen_window_check1(dc
, RRR_S
)) {
1315 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
1320 if (gen_window_check1(dc
, RRR_S
)) {
1321 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
1326 if (gen_window_check1(dc
, RRR_S
)) {
1327 TCGv_i32 tmp
= tcg_temp_new_i32();
1328 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1329 gen_right_shift_sar(dc
, tmp
);
1335 if (gen_window_check1(dc
, RRR_S
)) {
1336 TCGv_i32 tmp
= tcg_temp_new_i32();
1337 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
1338 gen_left_shift_sar(dc
, tmp
);
1345 TCGv_i32 tmp
= tcg_const_i32(
1346 RRR_S
| ((RRR_T
& 1) << 4));
1347 gen_right_shift_sar(dc
, tmp
);
1361 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1362 if (gen_check_privilege(dc
)) {
1363 TCGv_i32 tmp
= tcg_const_i32(
1364 RRR_T
| ((RRR_T
& 8) ? 0xfffffff0 : 0));
1365 gen_helper_rotw(cpu_env
, tmp
);
1367 /* This can change tb->flags, so exit tb */
1368 gen_jumpi_check_loop_end(dc
, -1);
1373 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1374 if (gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1375 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1380 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA
);
1381 if (gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1382 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1386 default: /*reserved*/
1394 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU
) |
1395 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION
) |
1396 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION
));
1397 if (gen_check_privilege(dc
) &&
1398 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1399 TCGv_i32 dtlb
= tcg_const_i32((RRR_R
& 8) != 0);
1401 switch (RRR_R
& 7) {
1402 case 3: /*RITLB0*/ /*RDTLB0*/
1403 gen_helper_rtlb0(cpu_R
[RRR_T
],
1404 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1407 case 4: /*IITLB*/ /*IDTLB*/
1408 gen_helper_itlb(cpu_env
, cpu_R
[RRR_S
], dtlb
);
1409 /* This could change memory mapping, so exit tb */
1410 gen_jumpi_check_loop_end(dc
, -1);
1413 case 5: /*PITLB*/ /*PDTLB*/
1414 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1415 gen_helper_ptlb(cpu_R
[RRR_T
],
1416 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1419 case 6: /*WITLB*/ /*WDTLB*/
1421 cpu_env
, cpu_R
[RRR_T
], cpu_R
[RRR_S
], dtlb
);
1422 /* This could change memory mapping, so exit tb */
1423 gen_jumpi_check_loop_end(dc
, -1);
1426 case 7: /*RITLB1*/ /*RDTLB1*/
1427 gen_helper_rtlb1(cpu_R
[RRR_T
],
1428 cpu_env
, cpu_R
[RRR_S
], dtlb
);
1432 tcg_temp_free(dtlb
);
1436 tcg_temp_free(dtlb
);
1441 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1446 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
1451 TCGv_i32 zero
= tcg_const_i32(0);
1452 TCGv_i32 neg
= tcg_temp_new_i32();
1454 tcg_gen_neg_i32(neg
, cpu_R
[RRR_T
]);
1455 tcg_gen_movcond_i32(TCG_COND_GE
, cpu_R
[RRR_R
],
1456 cpu_R
[RRR_T
], zero
, cpu_R
[RRR_T
], neg
);
1458 tcg_temp_free(zero
);
1462 default: /*reserved*/
1468 case 7: /*reserved*/
1473 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1474 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1481 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1482 TCGv_i32 tmp
= tcg_temp_new_i32();
1483 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
1484 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1490 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1491 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1498 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1499 TCGv_i32 tmp
= tcg_temp_new_i32();
1500 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
1501 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
1512 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1513 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
1514 32 - (RRR_T
| ((OP2
& 1) << 4)));
1520 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1521 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
1522 RRR_S
| ((OP2
& 1) << 4));
1527 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1528 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
1533 if (gen_check_sr(dc
, RSR_SR
, SR_X
) &&
1534 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1535 gen_window_check1(dc
, RRR_T
)) {
1536 TCGv_i32 tmp
= tcg_temp_new_i32();
1538 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
1539 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1540 gen_wsr(dc
, RSR_SR
, tmp
);
1546 * Note: 64 bit ops are used here solely because SAR values
1549 #define gen_shift_reg(cmd, reg) do { \
1550 TCGv_i64 tmp = tcg_temp_new_i64(); \
1551 tcg_gen_extu_i32_i64(tmp, reg); \
1552 tcg_gen_##cmd##_i64(v, v, tmp); \
1553 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1554 tcg_temp_free_i64(v); \
1555 tcg_temp_free_i64(tmp); \
1558 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1561 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1562 TCGv_i64 v
= tcg_temp_new_i64();
1563 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
1569 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1573 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1575 TCGv_i64 v
= tcg_temp_new_i64();
1576 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
1582 if (!gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1585 if (dc
->sar_m32_5bit
) {
1586 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
1588 TCGv_i64 v
= tcg_temp_new_i64();
1589 TCGv_i32 s
= tcg_const_i32(32);
1590 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
1591 tcg_gen_andi_i32(s
, s
, 0x3f);
1592 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
1593 gen_shift_reg(shl
, s
);
1599 if (!gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1603 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
1605 TCGv_i64 v
= tcg_temp_new_i64();
1606 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
1611 #undef gen_shift_reg
1614 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1615 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1616 TCGv_i32 v1
= tcg_temp_new_i32();
1617 TCGv_i32 v2
= tcg_temp_new_i32();
1618 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
1619 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
1620 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1627 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
1628 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1629 TCGv_i32 v1
= tcg_temp_new_i32();
1630 TCGv_i32 v2
= tcg_temp_new_i32();
1631 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
1632 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
1633 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
1639 default: /*reserved*/
1646 if (OP2
>= 8 && !gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1651 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV
);
1652 TCGLabel
*label
= gen_new_label();
1653 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0, label
);
1654 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
1655 gen_set_label(label
);
1659 #define BOOLEAN_LOGIC(fn, r, s, t) \
1661 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1662 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1663 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1665 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1666 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1667 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1668 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1669 tcg_temp_free(tmp1); \
1670 tcg_temp_free(tmp2); \
1674 BOOLEAN_LOGIC(and, RRR_R
, RRR_S
, RRR_T
);
1678 BOOLEAN_LOGIC(andc
, RRR_R
, RRR_S
, RRR_T
);
1682 BOOLEAN_LOGIC(or, RRR_R
, RRR_S
, RRR_T
);
1686 BOOLEAN_LOGIC(orc
, RRR_R
, RRR_S
, RRR_T
);
1690 BOOLEAN_LOGIC(xor, RRR_R
, RRR_S
, RRR_T
);
1693 #undef BOOLEAN_LOGIC
1696 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL
);
1697 tcg_gen_mul_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1702 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH
);
1704 TCGv lo
= tcg_temp_new();
1707 tcg_gen_mulu2_i32(lo
, cpu_R
[RRR_R
],
1708 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1710 tcg_gen_muls2_i32(lo
, cpu_R
[RRR_R
],
1711 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1718 tcg_gen_divu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1724 TCGLabel
*label1
= gen_new_label();
1725 TCGLabel
*label2
= gen_new_label();
1727 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_S
], 0x80000000,
1729 tcg_gen_brcondi_i32(TCG_COND_NE
, cpu_R
[RRR_T
], 0xffffffff,
1731 tcg_gen_movi_i32(cpu_R
[RRR_R
],
1732 OP2
== 13 ? 0x80000000 : 0);
1734 gen_set_label(label1
);
1736 tcg_gen_div_i32(cpu_R
[RRR_R
],
1737 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1739 tcg_gen_rem_i32(cpu_R
[RRR_R
],
1740 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1742 gen_set_label(label2
);
1747 tcg_gen_remu_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1750 default: /*reserved*/
1759 if (gen_check_sr(dc
, RSR_SR
, SR_R
) &&
1760 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1761 gen_window_check1(dc
, RRR_T
)) {
1762 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
1767 if (gen_check_sr(dc
, RSR_SR
, SR_W
) &&
1768 (RSR_SR
< 64 || gen_check_privilege(dc
)) &&
1769 gen_window_check1(dc
, RRR_T
)) {
1770 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
1775 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT
);
1776 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1777 int shift
= 24 - RRR_T
;
1780 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1781 } else if (shift
== 16) {
1782 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
1784 TCGv_i32 tmp
= tcg_temp_new_i32();
1785 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
1786 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
1793 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS
);
1794 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1795 TCGv_i32 tmp1
= tcg_temp_new_i32();
1796 TCGv_i32 tmp2
= tcg_temp_new_i32();
1797 TCGv_i32 zero
= tcg_const_i32(0);
1799 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
1800 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
1801 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
1803 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
1804 tcg_gen_xori_i32(tmp1
, tmp1
, 0xffffffff >> (25 - RRR_T
));
1806 tcg_gen_movcond_i32(TCG_COND_EQ
, cpu_R
[RRR_R
], tmp2
, zero
,
1807 cpu_R
[RRR_S
], tmp1
);
1808 tcg_temp_free(tmp1
);
1809 tcg_temp_free(tmp2
);
1810 tcg_temp_free(zero
);
1818 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX
);
1819 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1820 static const TCGCond cond
[] = {
1826 tcg_gen_movcond_i32(cond
[OP2
- 4], cpu_R
[RRR_R
],
1827 cpu_R
[RRR_S
], cpu_R
[RRR_T
],
1828 cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1836 if (gen_window_check3(dc
, RRR_R
, RRR_S
, RRR_T
)) {
1837 static const TCGCond cond
[] = {
1843 TCGv_i32 zero
= tcg_const_i32(0);
1845 tcg_gen_movcond_i32(cond
[OP2
- 8], cpu_R
[RRR_R
],
1846 cpu_R
[RRR_T
], zero
, cpu_R
[RRR_S
], cpu_R
[RRR_R
]);
1847 tcg_temp_free(zero
);
1853 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
1854 if (gen_window_check2(dc
, RRR_R
, RRR_S
)) {
1855 TCGv_i32 zero
= tcg_const_i32(0);
1856 TCGv_i32 tmp
= tcg_temp_new_i32();
1858 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
1859 tcg_gen_movcond_i32(OP2
& 1 ? TCG_COND_NE
: TCG_COND_EQ
,
1860 cpu_R
[RRR_R
], tmp
, zero
,
1861 cpu_R
[RRR_S
], cpu_R
[RRR_R
]);
1864 tcg_temp_free(zero
);
1869 if (gen_window_check1(dc
, RRR_R
)) {
1870 int st
= (RRR_S
<< 4) + RRR_T
;
1871 if (uregnames
[st
].name
) {
1872 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
1874 qemu_log_mask(LOG_UNIMP
, "RUR %d not implemented, ", st
);
1881 if (gen_window_check1(dc
, RRR_T
)) {
1882 if (uregnames
[RSR_SR
].name
) {
1883 gen_wur(RSR_SR
, cpu_R
[RRR_T
]);
1885 qemu_log_mask(LOG_UNIMP
, "WUR %d not implemented, ", RSR_SR
);
1896 if (gen_window_check2(dc
, RRR_R
, RRR_T
)) {
1897 int shiftimm
= RRR_S
| ((OP1
& 1) << 4);
1898 int maskimm
= (1 << (OP2
+ 1)) - 1;
1900 TCGv_i32 tmp
= tcg_temp_new_i32();
1901 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
1902 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
1921 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
1922 if (gen_window_check2(dc
, RRR_S
, RRR_T
) &&
1923 gen_check_cpenable(dc
, 0)) {
1924 TCGv_i32 addr
= tcg_temp_new_i32();
1925 tcg_gen_add_i32(addr
, cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
1926 gen_load_store_alignment(dc
, 2, addr
, false);
1928 tcg_gen_qemu_st32(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1930 tcg_gen_qemu_ld32u(cpu_FR
[RRR_R
], addr
, dc
->cring
);
1933 tcg_gen_mov_i32(cpu_R
[RRR_S
], addr
);
1935 tcg_temp_free(addr
);
1939 default: /*reserved*/
1946 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1951 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1952 if (gen_check_privilege(dc
) &&
1953 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1954 TCGv_i32 addr
= tcg_temp_new_i32();
1955 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1956 (0xffffffc0 | (RRR_R
<< 2)));
1957 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], addr
, dc
->ring
);
1958 tcg_temp_free(addr
);
1963 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
1964 if (gen_check_privilege(dc
) &&
1965 gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1966 TCGv_i32 addr
= tcg_temp_new_i32();
1967 tcg_gen_addi_i32(addr
, cpu_R
[RRR_S
],
1968 (0xffffffc0 | (RRR_R
<< 2)));
1969 tcg_gen_qemu_st32(cpu_R
[RRR_T
], addr
, dc
->ring
);
1970 tcg_temp_free(addr
);
1975 if (gen_window_check2(dc
, RRI4_S
, RRI4_T
)) {
1976 TCGv_i32 addr
= tcg_temp_new_i32();
1978 tcg_gen_addi_i32(addr
, cpu_R
[RRI4_S
], RRI4_IMM4
<< 2);
1979 gen_load_store_alignment(dc
, 2, addr
, false);
1980 tcg_gen_qemu_st32(cpu_R
[RRI4_T
], addr
, dc
->cring
);
1981 tcg_temp_free(addr
);
1993 if (option_enabled(dc
, XTENSA_OPTION_DEPBITS
)) {
1994 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
1997 tcg_gen_deposit_i32(cpu_R
[RRR_T
], cpu_R
[RRR_T
], cpu_R
[RRR_S
],
2002 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2005 if (gen_check_cpenable(dc
, 0)) {
2006 gen_helper_add_s(cpu_FR
[RRR_R
], cpu_env
,
2007 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2012 if (gen_check_cpenable(dc
, 0)) {
2013 gen_helper_sub_s(cpu_FR
[RRR_R
], cpu_env
,
2014 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2019 if (gen_check_cpenable(dc
, 0)) {
2020 gen_helper_mul_s(cpu_FR
[RRR_R
], cpu_env
,
2021 cpu_FR
[RRR_S
], cpu_FR
[RRR_T
]);
2026 if (gen_check_cpenable(dc
, 0)) {
2027 gen_helper_madd_s(cpu_FR
[RRR_R
], cpu_env
,
2028 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
],
2034 if (gen_check_cpenable(dc
, 0)) {
2035 gen_helper_msub_s(cpu_FR
[RRR_R
], cpu_env
,
2036 cpu_FR
[RRR_R
], cpu_FR
[RRR_S
],
2041 case 8: /*ROUND.Sf*/
2042 case 9: /*TRUNC.Sf*/
2043 case 10: /*FLOOR.Sf*/
2044 case 11: /*CEIL.Sf*/
2045 case 14: /*UTRUNC.Sf*/
2046 if (gen_window_check1(dc
, RRR_R
) &&
2047 gen_check_cpenable(dc
, 0)) {
2048 static const unsigned rounding_mode_const
[] = {
2049 float_round_nearest_even
,
2050 float_round_to_zero
,
2053 [6] = float_round_to_zero
,
2055 TCGv_i32 rounding_mode
= tcg_const_i32(
2056 rounding_mode_const
[OP2
& 7]);
2057 TCGv_i32 scale
= tcg_const_i32(RRR_T
);
2060 gen_helper_ftoui(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
2061 rounding_mode
, scale
);
2063 gen_helper_ftoi(cpu_R
[RRR_R
], cpu_FR
[RRR_S
],
2064 rounding_mode
, scale
);
2067 tcg_temp_free(rounding_mode
);
2068 tcg_temp_free(scale
);
2072 case 12: /*FLOAT.Sf*/
2073 case 13: /*UFLOAT.Sf*/
2074 if (gen_window_check1(dc
, RRR_S
) &&
2075 gen_check_cpenable(dc
, 0)) {
2076 TCGv_i32 scale
= tcg_const_i32(-RRR_T
);
2079 gen_helper_uitof(cpu_FR
[RRR_R
], cpu_env
,
2080 cpu_R
[RRR_S
], scale
);
2082 gen_helper_itof(cpu_FR
[RRR_R
], cpu_env
,
2083 cpu_R
[RRR_S
], scale
);
2085 tcg_temp_free(scale
);
2092 if (gen_check_cpenable(dc
, 0)) {
2093 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2098 if (gen_check_cpenable(dc
, 0)) {
2099 gen_helper_abs_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2104 if (gen_window_check1(dc
, RRR_R
) &&
2105 gen_check_cpenable(dc
, 0)) {
2106 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_FR
[RRR_S
]);
2111 if (gen_window_check1(dc
, RRR_S
) &&
2112 gen_check_cpenable(dc
, 0)) {
2113 tcg_gen_mov_i32(cpu_FR
[RRR_R
], cpu_R
[RRR_S
]);
2118 if (gen_check_cpenable(dc
, 0)) {
2119 gen_helper_neg_s(cpu_FR
[RRR_R
], cpu_FR
[RRR_S
]);
2123 default: /*reserved*/
2129 default: /*reserved*/
2137 if (option_enabled(dc
, XTENSA_OPTION_DEPBITS
)) {
2138 if (!gen_window_check2(dc
, RRR_S
, RRR_T
)) {
2141 tcg_gen_deposit_i32(cpu_R
[RRR_T
], cpu_R
[RRR_T
], cpu_R
[RRR_S
],
2142 OP2
+ 16, RRR_R
+ 1);
2146 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2148 #define gen_compare(rel, br, a, b) \
2150 if (gen_check_cpenable(dc, 0)) { \
2151 TCGv_i32 bit = tcg_const_i32(1 << br); \
2153 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2154 tcg_temp_free(bit); \
2160 gen_compare(un_s
, RRR_R
, RRR_S
, RRR_T
);
2164 gen_compare(oeq_s
, RRR_R
, RRR_S
, RRR_T
);
2168 gen_compare(ueq_s
, RRR_R
, RRR_S
, RRR_T
);
2172 gen_compare(olt_s
, RRR_R
, RRR_S
, RRR_T
);
2176 gen_compare(ult_s
, RRR_R
, RRR_S
, RRR_T
);
2180 gen_compare(ole_s
, RRR_R
, RRR_S
, RRR_T
);
2184 gen_compare(ule_s
, RRR_R
, RRR_S
, RRR_T
);
2189 case 8: /*MOVEQZ.Sf*/
2190 case 9: /*MOVNEZ.Sf*/
2191 case 10: /*MOVLTZ.Sf*/
2192 case 11: /*MOVGEZ.Sf*/
2193 if (gen_window_check1(dc
, RRR_T
) &&
2194 gen_check_cpenable(dc
, 0)) {
2195 static const TCGCond cond
[] = {
2201 TCGv_i32 zero
= tcg_const_i32(0);
2203 tcg_gen_movcond_i32(cond
[OP2
- 8], cpu_FR
[RRR_R
],
2204 cpu_R
[RRR_T
], zero
, cpu_FR
[RRR_S
], cpu_FR
[RRR_R
]);
2205 tcg_temp_free(zero
);
2209 case 12: /*MOVF.Sf*/
2210 case 13: /*MOVT.Sf*/
2211 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2212 if (gen_check_cpenable(dc
, 0)) {
2213 TCGv_i32 zero
= tcg_const_i32(0);
2214 TCGv_i32 tmp
= tcg_temp_new_i32();
2216 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRR_T
);
2217 tcg_gen_movcond_i32(OP2
& 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2218 cpu_FR
[RRR_R
], tmp
, zero
,
2219 cpu_FR
[RRR_S
], cpu_FR
[RRR_R
]);
2222 tcg_temp_free(zero
);
2226 default: /*reserved*/
2232 default: /*reserved*/
2239 if (gen_window_check1(dc
, RRR_T
)) {
2240 TCGv_i32 tmp
= tcg_const_i32(
2241 ((dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) ?
2242 0 : ((dc
->pc
+ 3) & ~3)) +
2243 (0xfffc0000 | (RI16_IMM16
<< 2)));
2245 if (dc
->tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
2246 tcg_gen_add_i32(tmp
, tmp
, dc
->litbase
);
2248 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, dc
->cring
);
2254 #define gen_load_store(type, shift) do { \
2255 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2256 TCGv_i32 addr = tcg_temp_new_i32(); \
2258 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2260 gen_load_store_alignment(dc, shift, addr, false); \
2262 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2263 tcg_temp_free(addr); \
2269 gen_load_store(ld8u
, 0);
2273 gen_load_store(ld16u
, 1);
2277 gen_load_store(ld32u
, 2);
2281 gen_load_store(st8
, 0);
2285 gen_load_store(st16
, 1);
2289 gen_load_store(st32
, 2);
2292 #define gen_dcache_hit_test(w, shift) do { \
2293 if (gen_window_check1(dc, RRI##w##_S)) { \
2294 TCGv_i32 addr = tcg_temp_new_i32(); \
2295 TCGv_i32 res = tcg_temp_new_i32(); \
2296 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2297 RRI##w##_IMM##w << shift); \
2298 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2299 tcg_temp_free(addr); \
2300 tcg_temp_free(res); \
2304 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2305 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2309 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2314 gen_window_check1(dc
, RRI8_S
);
2318 gen_window_check1(dc
, RRI8_S
);
2322 gen_window_check1(dc
, RRI8_S
);
2326 gen_window_check1(dc
, RRI8_S
);
2330 gen_dcache_hit_test8();
2334 gen_dcache_hit_test8();
2338 if (gen_check_privilege(dc
)) {
2339 gen_dcache_hit_test8();
2344 if (gen_check_privilege(dc
)) {
2345 gen_window_check1(dc
, RRI8_S
);
2352 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2353 if (gen_check_privilege(dc
)) {
2354 gen_dcache_hit_test4();
2359 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2360 if (gen_check_privilege(dc
)) {
2361 gen_dcache_hit_test4();
2366 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK
);
2367 if (gen_check_privilege(dc
)) {
2368 gen_window_check1(dc
, RRI4_S
);
2373 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2374 if (gen_check_privilege(dc
)) {
2375 gen_window_check1(dc
, RRI4_S
);
2380 HAS_OPTION(XTENSA_OPTION_DCACHE
);
2381 if (gen_check_privilege(dc
)) {
2382 gen_window_check1(dc
, RRI4_S
);
2386 default: /*reserved*/
2393 #undef gen_dcache_hit_test
2394 #undef gen_dcache_hit_test4
2395 #undef gen_dcache_hit_test8
2397 #define gen_icache_hit_test(w, shift) do { \
2398 if (gen_window_check1(dc, RRI##w##_S)) { \
2399 TCGv_i32 addr = tcg_temp_new_i32(); \
2400 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2401 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2402 RRI##w##_IMM##w << shift); \
2403 gen_helper_itlb_hit_test(cpu_env, addr); \
2404 tcg_temp_free(addr); \
2408 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2409 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2412 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2413 gen_window_check1(dc
, RRI8_S
);
2419 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2420 if (gen_check_privilege(dc
)) {
2421 gen_icache_hit_test4();
2426 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2427 if (gen_check_privilege(dc
)) {
2428 gen_icache_hit_test4();
2433 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK
);
2434 if (gen_check_privilege(dc
)) {
2435 gen_window_check1(dc
, RRI4_S
);
2439 default: /*reserved*/
2446 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2447 gen_icache_hit_test8();
2451 HAS_OPTION(XTENSA_OPTION_ICACHE
);
2452 if (gen_check_privilege(dc
)) {
2453 gen_window_check1(dc
, RRI8_S
);
2457 default: /*reserved*/
2463 #undef gen_icache_hit_test
2464 #undef gen_icache_hit_test4
2465 #undef gen_icache_hit_test8
2468 gen_load_store(ld16s
, 1);
2470 #undef gen_load_store
2473 if (gen_window_check1(dc
, RRI8_T
)) {
2474 tcg_gen_movi_i32(cpu_R
[RRI8_T
],
2475 RRI8_IMM8
| (RRI8_S
<< 8) |
2476 ((RRI8_S
& 0x8) ? 0xfffff000 : 0));
2480 #define gen_load_store_no_hw_align(type) do { \
2481 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2482 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2483 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2484 gen_load_store_alignment(dc, 2, addr, true); \
2485 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2486 tcg_temp_free(addr); \
2491 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2492 gen_load_store_no_hw_align(ld32u
); /*TODO acquire?*/
2496 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2497 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
], RRI8_IMM8_SE
);
2502 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2503 tcg_gen_addi_i32(cpu_R
[RRI8_T
], cpu_R
[RRI8_S
],
2508 case 14: /*S32C1Iy*/
2509 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE
);
2510 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2511 TCGLabel
*label
= gen_new_label();
2512 TCGv_i32 tmp
= tcg_temp_local_new_i32();
2513 TCGv_i32 addr
= tcg_temp_local_new_i32();
2516 tcg_gen_mov_i32(tmp
, cpu_R
[RRI8_T
]);
2517 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2518 gen_load_store_alignment(dc
, 2, addr
, true);
2520 gen_advance_ccount(dc
);
2521 tpc
= tcg_const_i32(dc
->pc
);
2522 gen_helper_check_atomctl(cpu_env
, tpc
, addr
);
2523 tcg_gen_qemu_ld32u(cpu_R
[RRI8_T
], addr
, dc
->cring
);
2524 tcg_gen_brcond_i32(TCG_COND_NE
, cpu_R
[RRI8_T
],
2525 cpu_SR
[SCOMPARE1
], label
);
2527 tcg_gen_qemu_st32(tmp
, addr
, dc
->cring
);
2529 gen_set_label(label
);
2531 tcg_temp_free(addr
);
2537 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO
);
2538 gen_load_store_no_hw_align(st32
); /*TODO release?*/
2540 #undef gen_load_store_no_hw_align
2542 default: /*reserved*/
2554 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
2555 if (gen_window_check1(dc
, RRI8_S
) &&
2556 gen_check_cpenable(dc
, 0)) {
2557 TCGv_i32 addr
= tcg_temp_new_i32();
2558 tcg_gen_addi_i32(addr
, cpu_R
[RRI8_S
], RRI8_IMM8
<< 2);
2559 gen_load_store_alignment(dc
, 2, addr
, false);
2561 tcg_gen_qemu_st32(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2563 tcg_gen_qemu_ld32u(cpu_FR
[RRI8_T
], addr
, dc
->cring
);
2566 tcg_gen_mov_i32(cpu_R
[RRI8_S
], addr
);
2568 tcg_temp_free(addr
);
2572 default: /*reserved*/
2579 HAS_OPTION(XTENSA_OPTION_MAC16
);
2588 bool is_m1_sr
= (OP2
& 0x3) == 2;
2589 bool is_m2_sr
= (OP2
& 0xc) == 0;
2590 uint32_t ld_offset
= 0;
2597 case 0: /*MACI?/MACC?*/
2599 ld_offset
= (OP2
& 1) ? -4 : 4;
2601 if (OP2
>= 8) { /*MACI/MACC*/
2602 if (OP1
== 0) { /*LDINC/LDDEC*/
2607 } else if (op
!= MAC16_MULA
) { /*MULA.*.*.LDINC/LDDEC*/
2612 case 2: /*MACD?/MACA?*/
2613 if (op
== MAC16_UMUL
&& OP2
!= 7) { /*UMUL only in MACAA*/
2619 if (op
!= MAC16_NONE
) {
2620 if (!is_m1_sr
&& !gen_window_check1(dc
, RRR_S
)) {
2623 if (!is_m2_sr
&& !gen_window_check1(dc
, RRR_T
)) {
2628 if (ld_offset
&& !gen_window_check1(dc
, RRR_S
)) {
2633 TCGv_i32 vaddr
= tcg_temp_new_i32();
2634 TCGv_i32 mem32
= tcg_temp_new_i32();
2637 tcg_gen_addi_i32(vaddr
, cpu_R
[RRR_S
], ld_offset
);
2638 gen_load_store_alignment(dc
, 2, vaddr
, false);
2639 tcg_gen_qemu_ld32u(mem32
, vaddr
, dc
->cring
);
2641 if (op
!= MAC16_NONE
) {
2642 TCGv_i32 m1
= gen_mac16_m(
2643 is_m1_sr
? cpu_SR
[MR
+ RRR_X
] : cpu_R
[RRR_S
],
2644 OP1
& 1, op
== MAC16_UMUL
);
2645 TCGv_i32 m2
= gen_mac16_m(
2646 is_m2_sr
? cpu_SR
[MR
+ 2 + RRR_Y
] : cpu_R
[RRR_T
],
2647 OP1
& 2, op
== MAC16_UMUL
);
2649 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
2650 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
2651 if (op
== MAC16_UMUL
) {
2652 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
2654 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
2657 TCGv_i32 lo
= tcg_temp_new_i32();
2658 TCGv_i32 hi
= tcg_temp_new_i32();
2660 tcg_gen_mul_i32(lo
, m1
, m2
);
2661 tcg_gen_sari_i32(hi
, lo
, 31);
2662 if (op
== MAC16_MULA
) {
2663 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2664 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2667 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2668 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
2671 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
2673 tcg_temp_free_i32(lo
);
2674 tcg_temp_free_i32(hi
);
2680 tcg_gen_mov_i32(cpu_R
[RRR_S
], vaddr
);
2681 tcg_gen_mov_i32(cpu_SR
[MR
+ RRR_W
], mem32
);
2683 tcg_temp_free(vaddr
);
2684 tcg_temp_free(mem32
);
2692 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
2693 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2699 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2700 if (gen_window_check1(dc
, CALL_N
<< 2)) {
2701 gen_callwi(dc
, CALL_N
,
2702 (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
2711 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
2715 if (gen_window_check1(dc
, BRI12_S
)) {
2716 static const TCGCond cond
[] = {
2717 TCG_COND_EQ
, /*BEQZ*/
2718 TCG_COND_NE
, /*BNEZ*/
2719 TCG_COND_LT
, /*BLTZ*/
2720 TCG_COND_GE
, /*BGEZ*/
2723 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
2724 4 + BRI12_IMM12_SE
);
2729 if (gen_window_check1(dc
, BRI8_S
)) {
2730 static const TCGCond cond
[] = {
2731 TCG_COND_EQ
, /*BEQI*/
2732 TCG_COND_NE
, /*BNEI*/
2733 TCG_COND_LT
, /*BLTI*/
2734 TCG_COND_GE
, /*BGEI*/
2737 gen_brcondi(dc
, cond
[BRI8_M
& 3],
2738 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
2745 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2747 TCGv_i32 pc
= tcg_const_i32(dc
->pc
);
2748 TCGv_i32 s
= tcg_const_i32(BRI12_S
);
2749 TCGv_i32 imm
= tcg_const_i32(BRI12_IMM12
);
2750 gen_advance_ccount(dc
);
2751 gen_helper_entry(cpu_env
, pc
, s
, imm
);
2755 /* This can change tb->flags, so exit tb */
2756 gen_jumpi_check_loop_end(dc
, -1);
2764 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
2766 TCGv_i32 tmp
= tcg_temp_new_i32();
2767 tcg_gen_andi_i32(tmp
, cpu_SR
[BR
], 1 << RRI8_S
);
2769 BRI8_R
== 1 ? TCG_COND_NE
: TCG_COND_EQ
,
2770 tmp
, 0, 4 + RRI8_IMM8_SE
);
2777 case 10: /*LOOPGTZ*/
2778 HAS_OPTION(XTENSA_OPTION_LOOP
);
2779 if (gen_window_check1(dc
, RRI8_S
)) {
2780 uint32_t lend
= dc
->pc
+ RRI8_IMM8
+ 4;
2781 TCGv_i32 tmp
= tcg_const_i32(lend
);
2783 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_R
[RRI8_S
], 1);
2784 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->next_pc
);
2785 gen_helper_wsr_lend(cpu_env
, tmp
);
2789 TCGLabel
*label
= gen_new_label();
2790 tcg_gen_brcondi_i32(
2791 BRI8_R
== 9 ? TCG_COND_NE
: TCG_COND_GT
,
2792 cpu_R
[RRI8_S
], 0, label
);
2793 gen_jumpi(dc
, lend
, 1);
2794 gen_set_label(label
);
2797 gen_jumpi(dc
, dc
->next_pc
, 0);
2801 default: /*reserved*/
2810 if (gen_window_check1(dc
, BRI8_S
)) {
2811 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
2812 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
],
2824 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
2826 switch (RRI8_R
& 7) {
2827 case 0: /*BNONE*/ /*BANY*/
2828 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2829 TCGv_i32 tmp
= tcg_temp_new_i32();
2830 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2831 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2836 case 1: /*BEQ*/ /*BNE*/
2837 case 2: /*BLT*/ /*BGE*/
2838 case 3: /*BLTU*/ /*BGEU*/
2839 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2840 static const TCGCond cond
[] = {
2846 [11] = TCG_COND_GEU
,
2848 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
2853 case 4: /*BALL*/ /*BNALL*/
2854 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2855 TCGv_i32 tmp
= tcg_temp_new_i32();
2856 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
2857 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
2863 case 5: /*BBC*/ /*BBS*/
2864 if (gen_window_check2(dc
, RRI8_S
, RRI8_T
)) {
2865 #ifdef TARGET_WORDS_BIGENDIAN
2866 TCGv_i32 bit
= tcg_const_i32(0x80000000);
2868 TCGv_i32 bit
= tcg_const_i32(0x00000001);
2870 TCGv_i32 tmp
= tcg_temp_new_i32();
2871 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
2872 #ifdef TARGET_WORDS_BIGENDIAN
2873 tcg_gen_shr_i32(bit
, bit
, tmp
);
2875 tcg_gen_shl_i32(bit
, bit
, tmp
);
2877 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
2878 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2884 case 6: /*BBCI*/ /*BBSI*/
2886 if (gen_window_check1(dc
, RRI8_S
)) {
2887 TCGv_i32 tmp
= tcg_temp_new_i32();
2888 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
2889 #ifdef TARGET_WORDS_BIGENDIAN
2890 0x80000000 >> (((RRI8_R
& 1) << 4) | RRI8_T
));
2892 0x00000001 << (((RRI8_R
& 1) << 4) | RRI8_T
));
2894 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
2903 #define gen_narrow_load_store(type) do { \
2904 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2905 TCGv_i32 addr = tcg_temp_new_i32(); \
2906 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2907 gen_load_store_alignment(dc, 2, addr, false); \
2908 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2909 tcg_temp_free(addr); \
2914 gen_narrow_load_store(ld32u
);
2918 gen_narrow_load_store(st32
);
2920 #undef gen_narrow_load_store
2923 if (gen_window_check3(dc
, RRRN_R
, RRRN_S
, RRRN_T
)) {
2924 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
2928 case 11: /*ADDI.Nn*/
2929 if (gen_window_check2(dc
, RRRN_R
, RRRN_S
)) {
2930 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
],
2931 RRRN_T
? RRRN_T
: -1);
2936 if (!gen_window_check1(dc
, RRRN_S
)) {
2939 if (RRRN_T
< 8) { /*MOVI.Nn*/
2940 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
2941 RRRN_R
| (RRRN_T
<< 4) |
2942 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
2943 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2944 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
2946 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
2947 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
2954 if (gen_window_check2(dc
, RRRN_S
, RRRN_T
)) {
2955 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
2962 gen_jump(dc
, cpu_R
[0]);
2966 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
2968 TCGv_i32 tmp
= tcg_const_i32(dc
->pc
);
2969 gen_advance_ccount(dc
);
2970 gen_helper_retw(tmp
, cpu_env
, tmp
);
2976 case 2: /*BREAK.Nn*/
2977 HAS_OPTION(XTENSA_OPTION_DEBUG
);
2979 gen_debug_exception(dc
, DEBUGCAUSE_BN
);
2987 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
2990 default: /*reserved*/
2996 default: /*reserved*/
3002 default: /*reserved*/
3007 if (dc
->is_jmp
== DISAS_NEXT
) {
3008 gen_check_loop_end(dc
, 0);
3010 dc
->pc
= dc
->next_pc
;
3015 qemu_log_mask(LOG_GUEST_ERROR
, "INVALID(pc = %08x)\n", dc
->pc
);
3016 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
3020 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
3022 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
3023 return xtensa_op0_insn_len(OP0
);
3026 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
3030 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
3031 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
3032 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
3033 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
3039 void gen_intermediate_code(CPUXtensaState
*env
, TranslationBlock
*tb
)
3041 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
3042 CPUState
*cs
= CPU(cpu
);
3045 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
3046 uint32_t pc_start
= tb
->pc
;
3047 uint32_t next_page_start
=
3048 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3050 if (max_insns
== 0) {
3051 max_insns
= CF_COUNT_MASK
;
3053 if (max_insns
> TCG_MAX_INSNS
) {
3054 max_insns
= TCG_MAX_INSNS
;
3057 dc
.config
= env
->config
;
3058 dc
.singlestep_enabled
= cs
->singlestep_enabled
;
3061 dc
.ring
= tb
->flags
& XTENSA_TBFLAG_RING_MASK
;
3062 dc
.cring
= (tb
->flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
.ring
;
3063 dc
.lbeg
= env
->sregs
[LBEG
];
3064 dc
.lend
= env
->sregs
[LEND
];
3065 dc
.is_jmp
= DISAS_NEXT
;
3066 dc
.ccount_delta
= 0;
3067 dc
.debug
= tb
->flags
& XTENSA_TBFLAG_DEBUG
;
3068 dc
.icount
= tb
->flags
& XTENSA_TBFLAG_ICOUNT
;
3069 dc
.cpenable
= (tb
->flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
3070 XTENSA_TBFLAG_CPENABLE_SHIFT
;
3071 dc
.window
= ((tb
->flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
3072 XTENSA_TBFLAG_WINDOW_SHIFT
);
3075 init_sar_tracker(&dc
);
3077 dc
.next_icount
= tcg_temp_local_new_i32();
3082 if (tb
->flags
& XTENSA_TBFLAG_EXCEPTION
) {
3083 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
3084 gen_exception(&dc
, EXCP_DEBUG
);
3088 tcg_gen_insn_start(dc
.pc
);
3093 if (unlikely(cpu_breakpoint_test(cs
, dc
.pc
, BP_ANY
))) {
3094 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
3095 gen_exception(&dc
, EXCP_DEBUG
);
3096 dc
.is_jmp
= DISAS_UPDATE
;
3097 /* The address covered by the breakpoint must be included in
3098 [tb->pc, tb->pc + tb->size) in order to for it to be
3099 properly cleared -- thus we increment the PC here so that
3100 the logic setting tb->size below does the right thing. */
3105 if (insn_count
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
3110 TCGLabel
*label
= gen_new_label();
3112 tcg_gen_addi_i32(dc
.next_icount
, cpu_SR
[ICOUNT
], 1);
3113 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
.next_icount
, 0, label
);
3114 tcg_gen_mov_i32(dc
.next_icount
, cpu_SR
[ICOUNT
]);
3116 gen_debug_exception(&dc
, DEBUGCAUSE_IC
);
3118 gen_set_label(label
);
3122 gen_ibreak_check(env
, &dc
);
3125 disas_xtensa_insn(env
, &dc
);
3127 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
.next_icount
);
3129 if (cs
->singlestep_enabled
) {
3130 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
3131 gen_exception(&dc
, EXCP_DEBUG
);
3134 } while (dc
.is_jmp
== DISAS_NEXT
&&
3135 insn_count
< max_insns
&&
3136 dc
.pc
< next_page_start
&&
3137 dc
.pc
+ xtensa_insn_len(env
, &dc
) <= next_page_start
&&
3138 !tcg_op_buf_full());
3141 reset_sar_tracker(&dc
);
3143 tcg_temp_free(dc
.next_icount
);
3146 if (tb
->cflags
& CF_LAST_IO
) {
3150 if (dc
.is_jmp
== DISAS_NEXT
) {
3151 gen_jumpi(&dc
, dc
.pc
, 0);
3153 gen_tb_end(tb
, insn_count
);
3156 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
3157 && qemu_log_in_addr_range(pc_start
)) {
3158 qemu_log("----------------\n");
3159 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
3160 log_target_disas(cs
, pc_start
, dc
.pc
- pc_start
, 0);
3164 tb
->size
= dc
.pc
- pc_start
;
3165 tb
->icount
= insn_count
;
3168 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
,
3169 fprintf_function cpu_fprintf
, int flags
)
3171 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
3172 CPUXtensaState
*env
= &cpu
->env
;
3175 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
3177 for (i
= j
= 0; i
< 256; ++i
) {
3178 if (xtensa_option_bits_enabled(env
->config
, sregnames
[i
].opt_bits
)) {
3179 cpu_fprintf(f
, "%12s=%08x%c", sregnames
[i
].name
, env
->sregs
[i
],
3180 (j
++ % 4) == 3 ? '\n' : ' ');
3184 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3186 for (i
= j
= 0; i
< 256; ++i
) {
3187 if (xtensa_option_bits_enabled(env
->config
, uregnames
[i
].opt_bits
)) {
3188 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
].name
, env
->uregs
[i
],
3189 (j
++ % 4) == 3 ? '\n' : ' ');
3193 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
3195 for (i
= 0; i
< 16; ++i
) {
3196 cpu_fprintf(f
, " A%02d=%08x%c", i
, env
->regs
[i
],
3197 (i
% 4) == 3 ? '\n' : ' ');
3200 cpu_fprintf(f
, "\n");
3202 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
3203 cpu_fprintf(f
, "AR%02d=%08x%c", i
, env
->phys_regs
[i
],
3204 (i
% 4) == 3 ? '\n' : ' ');
3207 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
3208 cpu_fprintf(f
, "\n");
3210 for (i
= 0; i
< 16; ++i
) {
3211 cpu_fprintf(f
, "F%02d=%08x (%+10.8e)%c", i
,
3212 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
3213 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
3214 (i
% 2) == 1 ? '\n' : ' ');
3219 void restore_state_to_opc(CPUXtensaState
*env
, TranslationBlock
*tb
,