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target-xtensa: add gdb support
[qemu.git] / gdbstub.c
blob933088578a4f3d012630cfa63d97632a154e12fa
1 /*
2 * gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <stdarg.h>
25 #include <string.h>
26 #include <errno.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "qemu.h"
31 #else
32 #include "monitor.h"
33 #include "qemu-char.h"
34 #include "sysemu.h"
35 #include "gdbstub.h"
36 #endif
37
38 #define MAX_PACKET_LENGTH 4096
39
40 #include "cpu.h"
41 #include "qemu_socket.h"
42 #include "kvm.h"
43
44
45 enum {
46 GDB_SIGNAL_0 = 0,
47 GDB_SIGNAL_INT = 2,
48 GDB_SIGNAL_QUIT = 3,
49 GDB_SIGNAL_TRAP = 5,
50 GDB_SIGNAL_ABRT = 6,
51 GDB_SIGNAL_ALRM = 14,
52 GDB_SIGNAL_IO = 23,
53 GDB_SIGNAL_XCPU = 24,
54 GDB_SIGNAL_UNKNOWN = 143
55 };
56
57 #ifdef CONFIG_USER_ONLY
58
59 /* Map target signal numbers to GDB protocol signal numbers and vice
60 * versa. For user emulation's currently supported systems, we can
61 * assume most signals are defined.
62 */
63
64 static int gdb_signal_table[] = {
65 0,
66 TARGET_SIGHUP,
67 TARGET_SIGINT,
68 TARGET_SIGQUIT,
69 TARGET_SIGILL,
70 TARGET_SIGTRAP,
71 TARGET_SIGABRT,
72 -1, /* SIGEMT */
73 TARGET_SIGFPE,
74 TARGET_SIGKILL,
75 TARGET_SIGBUS,
76 TARGET_SIGSEGV,
77 TARGET_SIGSYS,
78 TARGET_SIGPIPE,
79 TARGET_SIGALRM,
80 TARGET_SIGTERM,
81 TARGET_SIGURG,
82 TARGET_SIGSTOP,
83 TARGET_SIGTSTP,
84 TARGET_SIGCONT,
85 TARGET_SIGCHLD,
86 TARGET_SIGTTIN,
87 TARGET_SIGTTOU,
88 TARGET_SIGIO,
89 TARGET_SIGXCPU,
90 TARGET_SIGXFSZ,
91 TARGET_SIGVTALRM,
92 TARGET_SIGPROF,
93 TARGET_SIGWINCH,
94 -1, /* SIGLOST */
95 TARGET_SIGUSR1,
96 TARGET_SIGUSR2,
97 #ifdef TARGET_SIGPWR
98 TARGET_SIGPWR,
99 #else
100 -1,
101 #endif
102 -1, /* SIGPOLL */
103 -1,
104 -1,
105 -1,
106 -1,
107 -1,
108 -1,
109 -1,
110 -1,
111 -1,
112 -1,
113 -1,
114 #ifdef __SIGRTMIN
115 __SIGRTMIN + 1,
116 __SIGRTMIN + 2,
117 __SIGRTMIN + 3,
118 __SIGRTMIN + 4,
119 __SIGRTMIN + 5,
120 __SIGRTMIN + 6,
121 __SIGRTMIN + 7,
122 __SIGRTMIN + 8,
123 __SIGRTMIN + 9,
124 __SIGRTMIN + 10,
125 __SIGRTMIN + 11,
126 __SIGRTMIN + 12,
127 __SIGRTMIN + 13,
128 __SIGRTMIN + 14,
129 __SIGRTMIN + 15,
130 __SIGRTMIN + 16,
131 __SIGRTMIN + 17,
132 __SIGRTMIN + 18,
133 __SIGRTMIN + 19,
134 __SIGRTMIN + 20,
135 __SIGRTMIN + 21,
136 __SIGRTMIN + 22,
137 __SIGRTMIN + 23,
138 __SIGRTMIN + 24,
139 __SIGRTMIN + 25,
140 __SIGRTMIN + 26,
141 __SIGRTMIN + 27,
142 __SIGRTMIN + 28,
143 __SIGRTMIN + 29,
144 __SIGRTMIN + 30,
145 __SIGRTMIN + 31,
146 -1, /* SIGCANCEL */
147 __SIGRTMIN,
148 __SIGRTMIN + 32,
149 __SIGRTMIN + 33,
150 __SIGRTMIN + 34,
151 __SIGRTMIN + 35,
152 __SIGRTMIN + 36,
153 __SIGRTMIN + 37,
154 __SIGRTMIN + 38,
155 __SIGRTMIN + 39,
156 __SIGRTMIN + 40,
157 __SIGRTMIN + 41,
158 __SIGRTMIN + 42,
159 __SIGRTMIN + 43,
160 __SIGRTMIN + 44,
161 __SIGRTMIN + 45,
162 __SIGRTMIN + 46,
163 __SIGRTMIN + 47,
164 __SIGRTMIN + 48,
165 __SIGRTMIN + 49,
166 __SIGRTMIN + 50,
167 __SIGRTMIN + 51,
168 __SIGRTMIN + 52,
169 __SIGRTMIN + 53,
170 __SIGRTMIN + 54,
171 __SIGRTMIN + 55,
172 __SIGRTMIN + 56,
173 __SIGRTMIN + 57,
174 __SIGRTMIN + 58,
175 __SIGRTMIN + 59,
176 __SIGRTMIN + 60,
177 __SIGRTMIN + 61,
178 __SIGRTMIN + 62,
179 __SIGRTMIN + 63,
180 __SIGRTMIN + 64,
181 __SIGRTMIN + 65,
182 __SIGRTMIN + 66,
183 __SIGRTMIN + 67,
184 __SIGRTMIN + 68,
185 __SIGRTMIN + 69,
186 __SIGRTMIN + 70,
187 __SIGRTMIN + 71,
188 __SIGRTMIN + 72,
189 __SIGRTMIN + 73,
190 __SIGRTMIN + 74,
191 __SIGRTMIN + 75,
192 __SIGRTMIN + 76,
193 __SIGRTMIN + 77,
194 __SIGRTMIN + 78,
195 __SIGRTMIN + 79,
196 __SIGRTMIN + 80,
197 __SIGRTMIN + 81,
198 __SIGRTMIN + 82,
199 __SIGRTMIN + 83,
200 __SIGRTMIN + 84,
201 __SIGRTMIN + 85,
202 __SIGRTMIN + 86,
203 __SIGRTMIN + 87,
204 __SIGRTMIN + 88,
205 __SIGRTMIN + 89,
206 __SIGRTMIN + 90,
207 __SIGRTMIN + 91,
208 __SIGRTMIN + 92,
209 __SIGRTMIN + 93,
210 __SIGRTMIN + 94,
211 __SIGRTMIN + 95,
212 -1, /* SIGINFO */
213 -1, /* UNKNOWN */
214 -1, /* DEFAULT */
215 -1,
216 -1,
217 -1,
218 -1,
219 -1,
220 -1
221 #endif
222 };
223 #else
224 /* In system mode we only need SIGINT and SIGTRAP; other signals
225 are not yet supported. */
226
227 enum {
228 TARGET_SIGINT = 2,
229 TARGET_SIGTRAP = 5
230 };
231
232 static int gdb_signal_table[] = {
233 -1,
234 -1,
235 TARGET_SIGINT,
236 -1,
237 -1,
238 TARGET_SIGTRAP
239 };
240 #endif
241
242 #ifdef CONFIG_USER_ONLY
243 static int target_signal_to_gdb (int sig)
244 {
245 int i;
246 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
247 if (gdb_signal_table[i] == sig)
248 return i;
249 return GDB_SIGNAL_UNKNOWN;
250 }
251 #endif
252
253 static int gdb_signal_to_target (int sig)
254 {
255 if (sig < ARRAY_SIZE (gdb_signal_table))
256 return gdb_signal_table[sig];
257 else
258 return -1;
259 }
260
261 //#define DEBUG_GDB
262
263 typedef struct GDBRegisterState {
264 int base_reg;
265 int num_regs;
266 gdb_reg_cb get_reg;
267 gdb_reg_cb set_reg;
268 const char *xml;
269 struct GDBRegisterState *next;
270 } GDBRegisterState;
271
272 enum RSState {
273 RS_INACTIVE,
274 RS_IDLE,
275 RS_GETLINE,
276 RS_CHKSUM1,
277 RS_CHKSUM2,
278 RS_SYSCALL,
279 };
280 typedef struct GDBState {
281 CPUState *c_cpu; /* current CPU for step/continue ops */
282 CPUState *g_cpu; /* current CPU for other ops */
283 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
284 enum RSState state; /* parsing state */
285 char line_buf[MAX_PACKET_LENGTH];
286 int line_buf_index;
287 int line_csum;
288 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
289 int last_packet_len;
290 int signal;
291 #ifdef CONFIG_USER_ONLY
292 int fd;
293 int running_state;
294 #else
295 CharDriverState *chr;
296 CharDriverState *mon_chr;
297 #endif
298 } GDBState;
299
300 /* By default use no IRQs and no timers while single stepping so as to
301 * make single stepping like an ICE HW step.
302 */
303 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
304
305 static GDBState *gdbserver_state;
306
307 /* This is an ugly hack to cope with both new and old gdb.
308 If gdb sends qXfer:features:read then assume we're talking to a newish
309 gdb that understands target descriptions. */
310 static int gdb_has_xml;
311
312 #ifdef CONFIG_USER_ONLY
313 /* XXX: This is not thread safe. Do we care? */
314 static int gdbserver_fd = -1;
315
316 static int get_char(GDBState *s)
317 {
318 uint8_t ch;
319 int ret;
320
321 for(;;) {
322 ret = qemu_recv(s->fd, &ch, 1, 0);
323 if (ret < 0) {
324 if (errno == ECONNRESET)
325 s->fd = -1;
326 if (errno != EINTR && errno != EAGAIN)
327 return -1;
328 } else if (ret == 0) {
329 close(s->fd);
330 s->fd = -1;
331 return -1;
332 } else {
333 break;
334 }
335 }
336 return ch;
337 }
338 #endif
339
340 static gdb_syscall_complete_cb gdb_current_syscall_cb;
341
342 static enum {
343 GDB_SYS_UNKNOWN,
344 GDB_SYS_ENABLED,
345 GDB_SYS_DISABLED,
346 } gdb_syscall_mode;
347
348 /* If gdb is connected when the first semihosting syscall occurs then use
349 remote gdb syscalls. Otherwise use native file IO. */
350 int use_gdb_syscalls(void)
351 {
352 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
353 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
354 : GDB_SYS_DISABLED);
355 }
356 return gdb_syscall_mode == GDB_SYS_ENABLED;
357 }
358
359 /* Resume execution. */
360 static inline void gdb_continue(GDBState *s)
361 {
362 #ifdef CONFIG_USER_ONLY
363 s->running_state = 1;
364 #else
365 vm_start();
366 #endif
367 }
368
369 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
370 {
371 #ifdef CONFIG_USER_ONLY
372 int ret;
373
374 while (len > 0) {
375 ret = send(s->fd, buf, len, 0);
376 if (ret < 0) {
377 if (errno != EINTR && errno != EAGAIN)
378 return;
379 } else {
380 buf += ret;
381 len -= ret;
382 }
383 }
384 #else
385 qemu_chr_fe_write(s->chr, buf, len);
386 #endif
387 }
388
389 static inline int fromhex(int v)
390 {
391 if (v >= '0' && v <= '9')
392 return v - '0';
393 else if (v >= 'A' && v <= 'F')
394 return v - 'A' + 10;
395 else if (v >= 'a' && v <= 'f')
396 return v - 'a' + 10;
397 else
398 return 0;
399 }
400
401 static inline int tohex(int v)
402 {
403 if (v < 10)
404 return v + '0';
405 else
406 return v - 10 + 'a';
407 }
408
409 static void memtohex(char *buf, const uint8_t *mem, int len)
410 {
411 int i, c;
412 char *q;
413 q = buf;
414 for(i = 0; i < len; i++) {
415 c = mem[i];
416 *q++ = tohex(c >> 4);
417 *q++ = tohex(c & 0xf);
418 }
419 *q = '\0';
420 }
421
422 static void hextomem(uint8_t *mem, const char *buf, int len)
423 {
424 int i;
425
426 for(i = 0; i < len; i++) {
427 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
428 buf += 2;
429 }
430 }
431
432 /* return -1 if error, 0 if OK */
433 static int put_packet_binary(GDBState *s, const char *buf, int len)
434 {
435 int csum, i;
436 uint8_t *p;
437
438 for(;;) {
439 p = s->last_packet;
440 *(p++) = '$';
441 memcpy(p, buf, len);
442 p += len;
443 csum = 0;
444 for(i = 0; i < len; i++) {
445 csum += buf[i];
446 }
447 *(p++) = '#';
448 *(p++) = tohex((csum >> 4) & 0xf);
449 *(p++) = tohex((csum) & 0xf);
450
451 s->last_packet_len = p - s->last_packet;
452 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
453
454 #ifdef CONFIG_USER_ONLY
455 i = get_char(s);
456 if (i < 0)
457 return -1;
458 if (i == '+')
459 break;
460 #else
461 break;
462 #endif
463 }
464 return 0;
465 }
466
467 /* return -1 if error, 0 if OK */
468 static int put_packet(GDBState *s, const char *buf)
469 {
470 #ifdef DEBUG_GDB
471 printf("reply='%s'\n", buf);
472 #endif
473
474 return put_packet_binary(s, buf, strlen(buf));
475 }
476
477 /* The GDB remote protocol transfers values in target byte order. This means
478 we can use the raw memory access routines to access the value buffer.
479 Conveniently, these also handle the case where the buffer is mis-aligned.
480 */
481 #define GET_REG8(val) do { \
482 stb_p(mem_buf, val); \
483 return 1; \
484 } while(0)
485 #define GET_REG16(val) do { \
486 stw_p(mem_buf, val); \
487 return 2; \
488 } while(0)
489 #define GET_REG32(val) do { \
490 stl_p(mem_buf, val); \
491 return 4; \
492 } while(0)
493 #define GET_REG64(val) do { \
494 stq_p(mem_buf, val); \
495 return 8; \
496 } while(0)
497
498 #if TARGET_LONG_BITS == 64
499 #define GET_REGL(val) GET_REG64(val)
500 #define ldtul_p(addr) ldq_p(addr)
501 #else
502 #define GET_REGL(val) GET_REG32(val)
503 #define ldtul_p(addr) ldl_p(addr)
504 #endif
505
506 #if defined(TARGET_I386)
507
508 #ifdef TARGET_X86_64
509 static const int gpr_map[16] = {
510 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
511 8, 9, 10, 11, 12, 13, 14, 15
512 };
513 #else
514 #define gpr_map gpr_map32
515 #endif
516 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
517
518 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
519
520 #define IDX_IP_REG CPU_NB_REGS
521 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
522 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
523 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
524 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
525 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
526
527 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
528 {
529 if (n < CPU_NB_REGS) {
530 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
531 GET_REG64(env->regs[gpr_map[n]]);
532 } else if (n < CPU_NB_REGS32) {
533 GET_REG32(env->regs[gpr_map32[n]]);
534 }
535 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
536 #ifdef USE_X86LDOUBLE
537 /* FIXME: byteswap float values - after fixing fpregs layout. */
538 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
539 #else
540 memset(mem_buf, 0, 10);
541 #endif
542 return 10;
543 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
544 n -= IDX_XMM_REGS;
545 if (n < CPU_NB_REGS32 ||
546 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
547 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
548 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
549 return 16;
550 }
551 } else {
552 switch (n) {
553 case IDX_IP_REG:
554 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
555 GET_REG64(env->eip);
556 } else {
557 GET_REG32(env->eip);
558 }
559 case IDX_FLAGS_REG: GET_REG32(env->eflags);
560
561 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
562 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
563 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
564 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
565 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
566 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
567
568 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
569 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
570 (env->fpstt & 0x7) << 11);
571 case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
572 case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
573 case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
574 case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
575 case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
576 case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
577
578 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
579 }
580 }
581 return 0;
582 }
583
584 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
585 {
586 uint16_t selector = ldl_p(mem_buf);
587
588 if (selector != env->segs[sreg].selector) {
589 #if defined(CONFIG_USER_ONLY)
590 cpu_x86_load_seg(env, sreg, selector);
591 #else
592 unsigned int limit, flags;
593 target_ulong base;
594
595 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
596 base = selector << 4;
597 limit = 0xffff;
598 flags = 0;
599 } else {
600 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
601 return 4;
602 }
603 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
604 #endif
605 }
606 return 4;
607 }
608
609 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
610 {
611 uint32_t tmp;
612
613 if (n < CPU_NB_REGS) {
614 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
615 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
616 return sizeof(target_ulong);
617 } else if (n < CPU_NB_REGS32) {
618 n = gpr_map32[n];
619 env->regs[n] &= ~0xffffffffUL;
620 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
621 return 4;
622 }
623 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
624 #ifdef USE_X86LDOUBLE
625 /* FIXME: byteswap float values - after fixing fpregs layout. */
626 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
627 #endif
628 return 10;
629 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
630 n -= IDX_XMM_REGS;
631 if (n < CPU_NB_REGS32 ||
632 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
633 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
634 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
635 return 16;
636 }
637 } else {
638 switch (n) {
639 case IDX_IP_REG:
640 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
641 env->eip = ldq_p(mem_buf);
642 return 8;
643 } else {
644 env->eip &= ~0xffffffffUL;
645 env->eip |= (uint32_t)ldl_p(mem_buf);
646 return 4;
647 }
648 case IDX_FLAGS_REG:
649 env->eflags = ldl_p(mem_buf);
650 return 4;
651
652 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
653 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
654 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
655 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
656 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
657 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
658
659 case IDX_FP_REGS + 8:
660 env->fpuc = ldl_p(mem_buf);
661 return 4;
662 case IDX_FP_REGS + 9:
663 tmp = ldl_p(mem_buf);
664 env->fpstt = (tmp >> 11) & 7;
665 env->fpus = tmp & ~0x3800;
666 return 4;
667 case IDX_FP_REGS + 10: /* ftag */ return 4;
668 case IDX_FP_REGS + 11: /* fiseg */ return 4;
669 case IDX_FP_REGS + 12: /* fioff */ return 4;
670 case IDX_FP_REGS + 13: /* foseg */ return 4;
671 case IDX_FP_REGS + 14: /* fooff */ return 4;
672 case IDX_FP_REGS + 15: /* fop */ return 4;
673
674 case IDX_MXCSR_REG:
675 env->mxcsr = ldl_p(mem_buf);
676 return 4;
677 }
678 }
679 /* Unrecognised register. */
680 return 0;
681 }
682
683 #elif defined (TARGET_PPC)
684
685 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
686 expects whatever the target description contains. Due to a
687 historical mishap the FP registers appear in between core integer
688 regs and PC, MSR, CR, and so forth. We hack round this by giving the
689 FP regs zero size when talking to a newer gdb. */
690 #define NUM_CORE_REGS 71
691 #if defined (TARGET_PPC64)
692 #define GDB_CORE_XML "power64-core.xml"
693 #else
694 #define GDB_CORE_XML "power-core.xml"
695 #endif
696
697 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
698 {
699 if (n < 32) {
700 /* gprs */
701 GET_REGL(env->gpr[n]);
702 } else if (n < 64) {
703 /* fprs */
704 if (gdb_has_xml)
705 return 0;
706 stfq_p(mem_buf, env->fpr[n-32]);
707 return 8;
708 } else {
709 switch (n) {
710 case 64: GET_REGL(env->nip);
711 case 65: GET_REGL(env->msr);
712 case 66:
713 {
714 uint32_t cr = 0;
715 int i;
716 for (i = 0; i < 8; i++)
717 cr |= env->crf[i] << (32 - ((i + 1) * 4));
718 GET_REG32(cr);
719 }
720 case 67: GET_REGL(env->lr);
721 case 68: GET_REGL(env->ctr);
722 case 69: GET_REGL(env->xer);
723 case 70:
724 {
725 if (gdb_has_xml)
726 return 0;
727 GET_REG32(0); /* fpscr */
728 }
729 }
730 }
731 return 0;
732 }
733
734 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
735 {
736 if (n < 32) {
737 /* gprs */
738 env->gpr[n] = ldtul_p(mem_buf);
739 return sizeof(target_ulong);
740 } else if (n < 64) {
741 /* fprs */
742 if (gdb_has_xml)
743 return 0;
744 env->fpr[n-32] = ldfq_p(mem_buf);
745 return 8;
746 } else {
747 switch (n) {
748 case 64:
749 env->nip = ldtul_p(mem_buf);
750 return sizeof(target_ulong);
751 case 65:
752 ppc_store_msr(env, ldtul_p(mem_buf));
753 return sizeof(target_ulong);
754 case 66:
755 {
756 uint32_t cr = ldl_p(mem_buf);
757 int i;
758 for (i = 0; i < 8; i++)
759 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
760 return 4;
761 }
762 case 67:
763 env->lr = ldtul_p(mem_buf);
764 return sizeof(target_ulong);
765 case 68:
766 env->ctr = ldtul_p(mem_buf);
767 return sizeof(target_ulong);
768 case 69:
769 env->xer = ldtul_p(mem_buf);
770 return sizeof(target_ulong);
771 case 70:
772 /* fpscr */
773 if (gdb_has_xml)
774 return 0;
775 return 4;
776 }
777 }
778 return 0;
779 }
780
781 #elif defined (TARGET_SPARC)
782
783 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
784 #define NUM_CORE_REGS 86
785 #else
786 #define NUM_CORE_REGS 72
787 #endif
788
789 #ifdef TARGET_ABI32
790 #define GET_REGA(val) GET_REG32(val)
791 #else
792 #define GET_REGA(val) GET_REGL(val)
793 #endif
794
795 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
796 {
797 if (n < 8) {
798 /* g0..g7 */
799 GET_REGA(env->gregs[n]);
800 }
801 if (n < 32) {
802 /* register window */
803 GET_REGA(env->regwptr[n - 8]);
804 }
805 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
806 if (n < 64) {
807 /* fprs */
808 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
809 }
810 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
811 switch (n) {
812 case 64: GET_REGA(env->y);
813 case 65: GET_REGA(cpu_get_psr(env));
814 case 66: GET_REGA(env->wim);
815 case 67: GET_REGA(env->tbr);
816 case 68: GET_REGA(env->pc);
817 case 69: GET_REGA(env->npc);
818 case 70: GET_REGA(env->fsr);
819 case 71: GET_REGA(0); /* csr */
820 default: GET_REGA(0);
821 }
822 #else
823 if (n < 64) {
824 /* f0-f31 */
825 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
826 }
827 if (n < 80) {
828 /* f32-f62 (double width, even numbers only) */
829 uint64_t val;
830
831 val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
832 val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
833 GET_REG64(val);
834 }
835 switch (n) {
836 case 80: GET_REGL(env->pc);
837 case 81: GET_REGL(env->npc);
838 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
839 ((env->asi & 0xff) << 24) |
840 ((env->pstate & 0xfff) << 8) |
841 cpu_get_cwp64(env));
842 case 83: GET_REGL(env->fsr);
843 case 84: GET_REGL(env->fprs);
844 case 85: GET_REGL(env->y);
845 }
846 #endif
847 return 0;
848 }
849
850 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
851 {
852 #if defined(TARGET_ABI32)
853 abi_ulong tmp;
854
855 tmp = ldl_p(mem_buf);
856 #else
857 target_ulong tmp;
858
859 tmp = ldtul_p(mem_buf);
860 #endif
861
862 if (n < 8) {
863 /* g0..g7 */
864 env->gregs[n] = tmp;
865 } else if (n < 32) {
866 /* register window */
867 env->regwptr[n - 8] = tmp;
868 }
869 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
870 else if (n < 64) {
871 /* fprs */
872 *((uint32_t *)&env->fpr[n - 32]) = tmp;
873 } else {
874 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
875 switch (n) {
876 case 64: env->y = tmp; break;
877 case 65: cpu_put_psr(env, tmp); break;
878 case 66: env->wim = tmp; break;
879 case 67: env->tbr = tmp; break;
880 case 68: env->pc = tmp; break;
881 case 69: env->npc = tmp; break;
882 case 70: env->fsr = tmp; break;
883 default: return 0;
884 }
885 }
886 return 4;
887 #else
888 else if (n < 64) {
889 /* f0-f31 */
890 env->fpr[n] = ldfl_p(mem_buf);
891 return 4;
892 } else if (n < 80) {
893 /* f32-f62 (double width, even numbers only) */
894 *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
895 *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
896 } else {
897 switch (n) {
898 case 80: env->pc = tmp; break;
899 case 81: env->npc = tmp; break;
900 case 82:
901 cpu_put_ccr(env, tmp >> 32);
902 env->asi = (tmp >> 24) & 0xff;
903 env->pstate = (tmp >> 8) & 0xfff;
904 cpu_put_cwp64(env, tmp & 0xff);
905 break;
906 case 83: env->fsr = tmp; break;
907 case 84: env->fprs = tmp; break;
908 case 85: env->y = tmp; break;
909 default: return 0;
910 }
911 }
912 return 8;
913 #endif
914 }
915 #elif defined (TARGET_ARM)
916
917 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
918 whatever the target description contains. Due to a historical mishap
919 the FPA registers appear in between core integer regs and the CPSR.
920 We hack round this by giving the FPA regs zero size when talking to a
921 newer gdb. */
922 #define NUM_CORE_REGS 26
923 #define GDB_CORE_XML "arm-core.xml"
924
925 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
926 {
927 if (n < 16) {
928 /* Core integer register. */
929 GET_REG32(env->regs[n]);
930 }
931 if (n < 24) {
932 /* FPA registers. */
933 if (gdb_has_xml)
934 return 0;
935 memset(mem_buf, 0, 12);
936 return 12;
937 }
938 switch (n) {
939 case 24:
940 /* FPA status register. */
941 if (gdb_has_xml)
942 return 0;
943 GET_REG32(0);
944 case 25:
945 /* CPSR */
946 GET_REG32(cpsr_read(env));
947 }
948 /* Unknown register. */
949 return 0;
950 }
951
952 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
953 {
954 uint32_t tmp;
955
956 tmp = ldl_p(mem_buf);
957
958 /* Mask out low bit of PC to workaround gdb bugs. This will probably
959 cause problems if we ever implement the Jazelle DBX extensions. */
960 if (n == 15)
961 tmp &= ~1;
962
963 if (n < 16) {
964 /* Core integer register. */
965 env->regs[n] = tmp;
966 return 4;
967 }
968 if (n < 24) { /* 16-23 */
969 /* FPA registers (ignored). */
970 if (gdb_has_xml)
971 return 0;
972 return 12;
973 }
974 switch (n) {
975 case 24:
976 /* FPA status register (ignored). */
977 if (gdb_has_xml)
978 return 0;
979 return 4;
980 case 25:
981 /* CPSR */
982 cpsr_write (env, tmp, 0xffffffff);
983 return 4;
984 }
985 /* Unknown register. */
986 return 0;
987 }
988
989 #elif defined (TARGET_M68K)
990
991 #define NUM_CORE_REGS 18
992
993 #define GDB_CORE_XML "cf-core.xml"
994
995 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
996 {
997 if (n < 8) {
998 /* D0-D7 */
999 GET_REG32(env->dregs[n]);
1000 } else if (n < 16) {
1001 /* A0-A7 */
1002 GET_REG32(env->aregs[n - 8]);
1003 } else {
1004 switch (n) {
1005 case 16: GET_REG32(env->sr);
1006 case 17: GET_REG32(env->pc);
1007 }
1008 }
1009 /* FP registers not included here because they vary between
1010 ColdFire and m68k. Use XML bits for these. */
1011 return 0;
1012 }
1013
1014 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1015 {
1016 uint32_t tmp;
1017
1018 tmp = ldl_p(mem_buf);
1019
1020 if (n < 8) {
1021 /* D0-D7 */
1022 env->dregs[n] = tmp;
1023 } else if (n < 16) {
1024 /* A0-A7 */
1025 env->aregs[n - 8] = tmp;
1026 } else {
1027 switch (n) {
1028 case 16: env->sr = tmp; break;
1029 case 17: env->pc = tmp; break;
1030 default: return 0;
1031 }
1032 }
1033 return 4;
1034 }
1035 #elif defined (TARGET_MIPS)
1036
1037 #define NUM_CORE_REGS 73
1038
1039 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1040 {
1041 if (n < 32) {
1042 GET_REGL(env->active_tc.gpr[n]);
1043 }
1044 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1045 if (n >= 38 && n < 70) {
1046 if (env->CP0_Status & (1 << CP0St_FR))
1047 GET_REGL(env->active_fpu.fpr[n - 38].d);
1048 else
1049 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1050 }
1051 switch (n) {
1052 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1053 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1054 }
1055 }
1056 switch (n) {
1057 case 32: GET_REGL((int32_t)env->CP0_Status);
1058 case 33: GET_REGL(env->active_tc.LO[0]);
1059 case 34: GET_REGL(env->active_tc.HI[0]);
1060 case 35: GET_REGL(env->CP0_BadVAddr);
1061 case 36: GET_REGL((int32_t)env->CP0_Cause);
1062 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1063 case 72: GET_REGL(0); /* fp */
1064 case 89: GET_REGL((int32_t)env->CP0_PRid);
1065 }
1066 if (n >= 73 && n <= 88) {
1067 /* 16 embedded regs. */
1068 GET_REGL(0);
1069 }
1070
1071 return 0;
1072 }
1073
1074 /* convert MIPS rounding mode in FCR31 to IEEE library */
1075 static unsigned int ieee_rm[] =
1076 {
1077 float_round_nearest_even,
1078 float_round_to_zero,
1079 float_round_up,
1080 float_round_down
1081 };
1082 #define RESTORE_ROUNDING_MODE \
1083 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1084
1085 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1086 {
1087 target_ulong tmp;
1088
1089 tmp = ldtul_p(mem_buf);
1090
1091 if (n < 32) {
1092 env->active_tc.gpr[n] = tmp;
1093 return sizeof(target_ulong);
1094 }
1095 if (env->CP0_Config1 & (1 << CP0C1_FP)
1096 && n >= 38 && n < 73) {
1097 if (n < 70) {
1098 if (env->CP0_Status & (1 << CP0St_FR))
1099 env->active_fpu.fpr[n - 38].d = tmp;
1100 else
1101 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1102 }
1103 switch (n) {
1104 case 70:
1105 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1106 /* set rounding mode */
1107 RESTORE_ROUNDING_MODE;
1108 break;
1109 case 71: env->active_fpu.fcr0 = tmp; break;
1110 }
1111 return sizeof(target_ulong);
1112 }
1113 switch (n) {
1114 case 32: env->CP0_Status = tmp; break;
1115 case 33: env->active_tc.LO[0] = tmp; break;
1116 case 34: env->active_tc.HI[0] = tmp; break;
1117 case 35: env->CP0_BadVAddr = tmp; break;
1118 case 36: env->CP0_Cause = tmp; break;
1119 case 37:
1120 env->active_tc.PC = tmp & ~(target_ulong)1;
1121 if (tmp & 1) {
1122 env->hflags |= MIPS_HFLAG_M16;
1123 } else {
1124 env->hflags &= ~(MIPS_HFLAG_M16);
1125 }
1126 break;
1127 case 72: /* fp, ignored */ break;
1128 default:
1129 if (n > 89)
1130 return 0;
1131 /* Other registers are readonly. Ignore writes. */
1132 break;
1133 }
1134
1135 return sizeof(target_ulong);
1136 }
1137 #elif defined (TARGET_SH4)
1138
1139 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1140 /* FIXME: We should use XML for this. */
1141
1142 #define NUM_CORE_REGS 59
1143
1144 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1145 {
1146 if (n < 8) {
1147 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1148 GET_REGL(env->gregs[n + 16]);
1149 } else {
1150 GET_REGL(env->gregs[n]);
1151 }
1152 } else if (n < 16) {
1153 GET_REGL(env->gregs[n]);
1154 } else if (n >= 25 && n < 41) {
1155 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1156 } else if (n >= 43 && n < 51) {
1157 GET_REGL(env->gregs[n - 43]);
1158 } else if (n >= 51 && n < 59) {
1159 GET_REGL(env->gregs[n - (51 - 16)]);
1160 }
1161 switch (n) {
1162 case 16: GET_REGL(env->pc);
1163 case 17: GET_REGL(env->pr);
1164 case 18: GET_REGL(env->gbr);
1165 case 19: GET_REGL(env->vbr);
1166 case 20: GET_REGL(env->mach);
1167 case 21: GET_REGL(env->macl);
1168 case 22: GET_REGL(env->sr);
1169 case 23: GET_REGL(env->fpul);
1170 case 24: GET_REGL(env->fpscr);
1171 case 41: GET_REGL(env->ssr);
1172 case 42: GET_REGL(env->spc);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1179 {
1180 uint32_t tmp;
1181
1182 tmp = ldl_p(mem_buf);
1183
1184 if (n < 8) {
1185 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1186 env->gregs[n + 16] = tmp;
1187 } else {
1188 env->gregs[n] = tmp;
1189 }
1190 return 4;
1191 } else if (n < 16) {
1192 env->gregs[n] = tmp;
1193 return 4;
1194 } else if (n >= 25 && n < 41) {
1195 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1196 return 4;
1197 } else if (n >= 43 && n < 51) {
1198 env->gregs[n - 43] = tmp;
1199 return 4;
1200 } else if (n >= 51 && n < 59) {
1201 env->gregs[n - (51 - 16)] = tmp;
1202 return 4;
1203 }
1204 switch (n) {
1205 case 16: env->pc = tmp; break;
1206 case 17: env->pr = tmp; break;
1207 case 18: env->gbr = tmp; break;
1208 case 19: env->vbr = tmp; break;
1209 case 20: env->mach = tmp; break;
1210 case 21: env->macl = tmp; break;
1211 case 22: env->sr = tmp; break;
1212 case 23: env->fpul = tmp; break;
1213 case 24: env->fpscr = tmp; break;
1214 case 41: env->ssr = tmp; break;
1215 case 42: env->spc = tmp; break;
1216 default: return 0;
1217 }
1218
1219 return 4;
1220 }
1221 #elif defined (TARGET_MICROBLAZE)
1222
1223 #define NUM_CORE_REGS (32 + 5)
1224
1225 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1226 {
1227 if (n < 32) {
1228 GET_REG32(env->regs[n]);
1229 } else {
1230 GET_REG32(env->sregs[n - 32]);
1231 }
1232 return 0;
1233 }
1234
1235 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1236 {
1237 uint32_t tmp;
1238
1239 if (n > NUM_CORE_REGS)
1240 return 0;
1241
1242 tmp = ldl_p(mem_buf);
1243
1244 if (n < 32) {
1245 env->regs[n] = tmp;
1246 } else {
1247 env->sregs[n - 32] = tmp;
1248 }
1249 return 4;
1250 }
1251 #elif defined (TARGET_CRIS)
1252
1253 #define NUM_CORE_REGS 49
1254
1255 static int
1256 read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
1257 {
1258 if (n < 15) {
1259 GET_REG32(env->regs[n]);
1260 }
1261
1262 if (n == 15) {
1263 GET_REG32(env->pc);
1264 }
1265
1266 if (n < 32) {
1267 switch (n) {
1268 case 16:
1269 GET_REG8(env->pregs[n - 16]);
1270 break;
1271 case 17:
1272 GET_REG8(env->pregs[n - 16]);
1273 break;
1274 case 20:
1275 case 21:
1276 GET_REG16(env->pregs[n - 16]);
1277 break;
1278 default:
1279 if (n >= 23) {
1280 GET_REG32(env->pregs[n - 16]);
1281 }
1282 break;
1283 }
1284 }
1285 return 0;
1286 }
1287
1288 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1289 {
1290 uint8_t srs;
1291
1292 if (env->pregs[PR_VR] < 32)
1293 return read_register_crisv10(env, mem_buf, n);
1294
1295 srs = env->pregs[PR_SRS];
1296 if (n < 16) {
1297 GET_REG32(env->regs[n]);
1298 }
1299
1300 if (n >= 21 && n < 32) {
1301 GET_REG32(env->pregs[n - 16]);
1302 }
1303 if (n >= 33 && n < 49) {
1304 GET_REG32(env->sregs[srs][n - 33]);
1305 }
1306 switch (n) {
1307 case 16: GET_REG8(env->pregs[0]);
1308 case 17: GET_REG8(env->pregs[1]);
1309 case 18: GET_REG32(env->pregs[2]);
1310 case 19: GET_REG8(srs);
1311 case 20: GET_REG16(env->pregs[4]);
1312 case 32: GET_REG32(env->pc);
1313 }
1314
1315 return 0;
1316 }
1317
1318 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1319 {
1320 uint32_t tmp;
1321
1322 if (n > 49)
1323 return 0;
1324
1325 tmp = ldl_p(mem_buf);
1326
1327 if (n < 16) {
1328 env->regs[n] = tmp;
1329 }
1330
1331 if (n >= 21 && n < 32) {
1332 env->pregs[n - 16] = tmp;
1333 }
1334
1335 /* FIXME: Should support function regs be writable? */
1336 switch (n) {
1337 case 16: return 1;
1338 case 17: return 1;
1339 case 18: env->pregs[PR_PID] = tmp; break;
1340 case 19: return 1;
1341 case 20: return 2;
1342 case 32: env->pc = tmp; break;
1343 }
1344
1345 return 4;
1346 }
1347 #elif defined (TARGET_ALPHA)
1348
1349 #define NUM_CORE_REGS 67
1350
1351 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1352 {
1353 uint64_t val;
1354 CPU_DoubleU d;
1355
1356 switch (n) {
1357 case 0 ... 30:
1358 val = env->ir[n];
1359 break;
1360 case 32 ... 62:
1361 d.d = env->fir[n - 32];
1362 val = d.ll;
1363 break;
1364 case 63:
1365 val = cpu_alpha_load_fpcr(env);
1366 break;
1367 case 64:
1368 val = env->pc;
1369 break;
1370 case 66:
1371 val = env->unique;
1372 break;
1373 case 31:
1374 case 65:
1375 /* 31 really is the zero register; 65 is unassigned in the
1376 gdb protocol, but is still required to occupy 8 bytes. */
1377 val = 0;
1378 break;
1379 default:
1380 return 0;
1381 }
1382 GET_REGL(val);
1383 }
1384
1385 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1386 {
1387 target_ulong tmp = ldtul_p(mem_buf);
1388 CPU_DoubleU d;
1389
1390 switch (n) {
1391 case 0 ... 30:
1392 env->ir[n] = tmp;
1393 break;
1394 case 32 ... 62:
1395 d.ll = tmp;
1396 env->fir[n - 32] = d.d;
1397 break;
1398 case 63:
1399 cpu_alpha_store_fpcr(env, tmp);
1400 break;
1401 case 64:
1402 env->pc = tmp;
1403 break;
1404 case 66:
1405 env->unique = tmp;
1406 break;
1407 case 31:
1408 case 65:
1409 /* 31 really is the zero register; 65 is unassigned in the
1410 gdb protocol, but is still required to occupy 8 bytes. */
1411 break;
1412 default:
1413 return 0;
1414 }
1415 return 8;
1416 }
1417 #elif defined (TARGET_S390X)
1418
1419 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1420
1421 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1422 {
1423 switch (n) {
1424 case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1425 case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1426 case S390_R0_REGNUM ... S390_R15_REGNUM:
1427 GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1428 case S390_A0_REGNUM ... S390_A15_REGNUM:
1429 GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1430 case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1431 case S390_F0_REGNUM ... S390_F15_REGNUM:
1432 /* XXX */
1433 break;
1434 case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1435 case S390_CC_REGNUM:
1436 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
1437 env->cc_vr);
1438 GET_REG32(env->cc_op);
1439 break;
1440 }
1441
1442 return 0;
1443 }
1444
1445 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1446 {
1447 target_ulong tmpl;
1448 uint32_t tmp32;
1449 int r = 8;
1450 tmpl = ldtul_p(mem_buf);
1451 tmp32 = ldl_p(mem_buf);
1452
1453 switch (n) {
1454 case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1455 case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1456 case S390_R0_REGNUM ... S390_R15_REGNUM:
1457 env->regs[n-S390_R0_REGNUM] = tmpl; break;
1458 case S390_A0_REGNUM ... S390_A15_REGNUM:
1459 env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1460 case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1461 case S390_F0_REGNUM ... S390_F15_REGNUM:
1462 /* XXX */
1463 break;
1464 case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1465 case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
1466 }
1467
1468 return r;
1469 }
1470 #elif defined (TARGET_LM32)
1471
1472 #include "hw/lm32_pic.h"
1473 #define NUM_CORE_REGS (32 + 7)
1474
1475 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1476 {
1477 if (n < 32) {
1478 GET_REG32(env->regs[n]);
1479 } else {
1480 switch (n) {
1481 case 32:
1482 GET_REG32(env->pc);
1483 break;
1484 /* FIXME: put in right exception ID */
1485 case 33:
1486 GET_REG32(0);
1487 break;
1488 case 34:
1489 GET_REG32(env->eba);
1490 break;
1491 case 35:
1492 GET_REG32(env->deba);
1493 break;
1494 case 36:
1495 GET_REG32(env->ie);
1496 break;
1497 case 37:
1498 GET_REG32(lm32_pic_get_im(env->pic_state));
1499 break;
1500 case 38:
1501 GET_REG32(lm32_pic_get_ip(env->pic_state));
1502 break;
1503 }
1504 }
1505 return 0;
1506 }
1507
1508 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1509 {
1510 uint32_t tmp;
1511
1512 if (n > NUM_CORE_REGS) {
1513 return 0;
1514 }
1515
1516 tmp = ldl_p(mem_buf);
1517
1518 if (n < 32) {
1519 env->regs[n] = tmp;
1520 } else {
1521 switch (n) {
1522 case 32:
1523 env->pc = tmp;
1524 break;
1525 case 34:
1526 env->eba = tmp;
1527 break;
1528 case 35:
1529 env->deba = tmp;
1530 break;
1531 case 36:
1532 env->ie = tmp;
1533 break;
1534 case 37:
1535 lm32_pic_set_im(env->pic_state, tmp);
1536 break;
1537 case 38:
1538 lm32_pic_set_ip(env->pic_state, tmp);
1539 break;
1540 }
1541 }
1542 return 4;
1543 }
1544 #elif defined(TARGET_XTENSA)
1545
1546 /* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
1547 * Use num_regs to see all registers. gdb modification is required for that:
1548 * reset bit 0 in the 'flags' field of the registers definitions in the
1549 * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
1550 */
1551 #define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
1552 #define num_g_regs NUM_CORE_REGS
1553
1554 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1555 {
1556 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1557
1558 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1559 return 0;
1560 }
1561
1562 switch (reg->type) {
1563 case 9: /*pc*/
1564 GET_REG32(env->pc);
1565 break;
1566
1567 case 1: /*ar*/
1568 xtensa_sync_phys_from_window(env);
1569 GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
1570 break;
1571
1572 case 2: /*SR*/
1573 GET_REG32(env->sregs[reg->targno & 0xff]);
1574 break;
1575
1576 case 3: /*UR*/
1577 GET_REG32(env->uregs[reg->targno & 0xff]);
1578 break;
1579
1580 case 8: /*a*/
1581 GET_REG32(env->regs[reg->targno & 0x0f]);
1582 break;
1583
1584 default:
1585 qemu_log("%s from reg %d of unsupported type %d\n",
1586 __func__, n, reg->type);
1587 return 0;
1588 }
1589 }
1590
1591 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1592 {
1593 uint32_t tmp;
1594 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1595
1596 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1597 return 0;
1598 }
1599
1600 tmp = ldl_p(mem_buf);
1601
1602 switch (reg->type) {
1603 case 9: /*pc*/
1604 env->pc = tmp;
1605 break;
1606
1607 case 1: /*ar*/
1608 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
1609 xtensa_sync_window_from_phys(env);
1610 break;
1611
1612 case 2: /*SR*/
1613 env->sregs[reg->targno & 0xff] = tmp;
1614 break;
1615
1616 case 3: /*UR*/
1617 env->uregs[reg->targno & 0xff] = tmp;
1618 break;
1619
1620 case 8: /*a*/
1621 env->regs[reg->targno & 0x0f] = tmp;
1622 break;
1623
1624 default:
1625 qemu_log("%s to reg %d of unsupported type %d\n",
1626 __func__, n, reg->type);
1627 return 0;
1628 }
1629
1630 return 4;
1631 }
1632 #else
1633
1634 #define NUM_CORE_REGS 0
1635
1636 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1637 {
1638 return 0;
1639 }
1640
1641 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1642 {
1643 return 0;
1644 }
1645
1646 #endif
1647
1648 #if !defined(TARGET_XTENSA)
1649 static int num_g_regs = NUM_CORE_REGS;
1650 #endif
1651
1652 #ifdef GDB_CORE_XML
1653 /* Encode data using the encoding for 'x' packets. */
1654 static int memtox(char *buf, const char *mem, int len)
1655 {
1656 char *p = buf;
1657 char c;
1658
1659 while (len--) {
1660 c = *(mem++);
1661 switch (c) {
1662 case '#': case '$': case '*': case '}':
1663 *(p++) = '}';
1664 *(p++) = c ^ 0x20;
1665 break;
1666 default:
1667 *(p++) = c;
1668 break;
1669 }
1670 }
1671 return p - buf;
1672 }
1673
1674 static const char *get_feature_xml(const char *p, const char **newp)
1675 {
1676 size_t len;
1677 int i;
1678 const char *name;
1679 static char target_xml[1024];
1680
1681 len = 0;
1682 while (p[len] && p[len] != ':')
1683 len++;
1684 *newp = p + len;
1685
1686 name = NULL;
1687 if (strncmp(p, "target.xml", len) == 0) {
1688 /* Generate the XML description for this CPU. */
1689 if (!target_xml[0]) {
1690 GDBRegisterState *r;
1691
1692 snprintf(target_xml, sizeof(target_xml),
1693 "<?xml version=\"1.0\"?>"
1694 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1695 "<target>"
1696 "<xi:include href=\"%s\"/>",
1697 GDB_CORE_XML);
1698
1699 for (r = first_cpu->gdb_regs; r; r = r->next) {
1700 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1701 pstrcat(target_xml, sizeof(target_xml), r->xml);
1702 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1703 }
1704 pstrcat(target_xml, sizeof(target_xml), "</target>");
1705 }
1706 return target_xml;
1707 }
1708 for (i = 0; ; i++) {
1709 name = xml_builtin[i][0];
1710 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1711 break;
1712 }
1713 return name ? xml_builtin[i][1] : NULL;
1714 }
1715 #endif
1716
1717 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1718 {
1719 GDBRegisterState *r;
1720
1721 if (reg < NUM_CORE_REGS)
1722 return cpu_gdb_read_register(env, mem_buf, reg);
1723
1724 for (r = env->gdb_regs; r; r = r->next) {
1725 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1726 return r->get_reg(env, mem_buf, reg - r->base_reg);
1727 }
1728 }
1729 return 0;
1730 }
1731
1732 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1733 {
1734 GDBRegisterState *r;
1735
1736 if (reg < NUM_CORE_REGS)
1737 return cpu_gdb_write_register(env, mem_buf, reg);
1738
1739 for (r = env->gdb_regs; r; r = r->next) {
1740 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1741 return r->set_reg(env, mem_buf, reg - r->base_reg);
1742 }
1743 }
1744 return 0;
1745 }
1746
1747 #if !defined(TARGET_XTENSA)
1748 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1749 specifies the first register number and these registers are included in
1750 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1751 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1752 */
1753
1754 void gdb_register_coprocessor(CPUState * env,
1755 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1756 int num_regs, const char *xml, int g_pos)
1757 {
1758 GDBRegisterState *s;
1759 GDBRegisterState **p;
1760 static int last_reg = NUM_CORE_REGS;
1761
1762 s = (GDBRegisterState *)g_malloc0(sizeof(GDBRegisterState));
1763 s->base_reg = last_reg;
1764 s->num_regs = num_regs;
1765 s->get_reg = get_reg;
1766 s->set_reg = set_reg;
1767 s->xml = xml;
1768 p = &env->gdb_regs;
1769 while (*p) {
1770 /* Check for duplicates. */
1771 if (strcmp((*p)->xml, xml) == 0)
1772 return;
1773 p = &(*p)->next;
1774 }
1775 /* Add to end of list. */
1776 last_reg += num_regs;
1777 *p = s;
1778 if (g_pos) {
1779 if (g_pos != s->base_reg) {
1780 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1781 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1782 } else {
1783 num_g_regs = last_reg;
1784 }
1785 }
1786 }
1787 #endif
1788
1789 #ifndef CONFIG_USER_ONLY
1790 static const int xlat_gdb_type[] = {
1791 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1792 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1793 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1794 };
1795 #endif
1796
1797 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1798 {
1799 CPUState *env;
1800 int err = 0;
1801
1802 if (kvm_enabled())
1803 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1804
1805 switch (type) {
1806 case GDB_BREAKPOINT_SW:
1807 case GDB_BREAKPOINT_HW:
1808 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1809 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1810 if (err)
1811 break;
1812 }
1813 return err;
1814 #ifndef CONFIG_USER_ONLY
1815 case GDB_WATCHPOINT_WRITE:
1816 case GDB_WATCHPOINT_READ:
1817 case GDB_WATCHPOINT_ACCESS:
1818 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1819 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1820 NULL);
1821 if (err)
1822 break;
1823 }
1824 return err;
1825 #endif
1826 default:
1827 return -ENOSYS;
1828 }
1829 }
1830
1831 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1832 {
1833 CPUState *env;
1834 int err = 0;
1835
1836 if (kvm_enabled())
1837 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1838
1839 switch (type) {
1840 case GDB_BREAKPOINT_SW:
1841 case GDB_BREAKPOINT_HW:
1842 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1843 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1844 if (err)
1845 break;
1846 }
1847 return err;
1848 #ifndef CONFIG_USER_ONLY
1849 case GDB_WATCHPOINT_WRITE:
1850 case GDB_WATCHPOINT_READ:
1851 case GDB_WATCHPOINT_ACCESS:
1852 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1853 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1854 if (err)
1855 break;
1856 }
1857 return err;
1858 #endif
1859 default:
1860 return -ENOSYS;
1861 }
1862 }
1863
1864 static void gdb_breakpoint_remove_all(void)
1865 {
1866 CPUState *env;
1867
1868 if (kvm_enabled()) {
1869 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1870 return;
1871 }
1872
1873 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1874 cpu_breakpoint_remove_all(env, BP_GDB);
1875 #ifndef CONFIG_USER_ONLY
1876 cpu_watchpoint_remove_all(env, BP_GDB);
1877 #endif
1878 }
1879 }
1880
1881 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1882 {
1883 #if defined(TARGET_I386)
1884 cpu_synchronize_state(s->c_cpu);
1885 s->c_cpu->eip = pc;
1886 #elif defined (TARGET_PPC)
1887 s->c_cpu->nip = pc;
1888 #elif defined (TARGET_SPARC)
1889 s->c_cpu->pc = pc;
1890 s->c_cpu->npc = pc + 4;
1891 #elif defined (TARGET_ARM)
1892 s->c_cpu->regs[15] = pc;
1893 #elif defined (TARGET_SH4)
1894 s->c_cpu->pc = pc;
1895 #elif defined (TARGET_MIPS)
1896 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1897 if (pc & 1) {
1898 s->c_cpu->hflags |= MIPS_HFLAG_M16;
1899 } else {
1900 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1901 }
1902 #elif defined (TARGET_MICROBLAZE)
1903 s->c_cpu->sregs[SR_PC] = pc;
1904 #elif defined (TARGET_CRIS)
1905 s->c_cpu->pc = pc;
1906 #elif defined (TARGET_ALPHA)
1907 s->c_cpu->pc = pc;
1908 #elif defined (TARGET_S390X)
1909 cpu_synchronize_state(s->c_cpu);
1910 s->c_cpu->psw.addr = pc;
1911 #elif defined (TARGET_LM32)
1912 s->c_cpu->pc = pc;
1913 #elif defined(TARGET_XTENSA)
1914 s->c_cpu->pc = pc;
1915 #endif
1916 }
1917
1918 static inline int gdb_id(CPUState *env)
1919 {
1920 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1921 return env->host_tid;
1922 #else
1923 return env->cpu_index + 1;
1924 #endif
1925 }
1926
1927 static CPUState *find_cpu(uint32_t thread_id)
1928 {
1929 CPUState *env;
1930
1931 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1932 if (gdb_id(env) == thread_id) {
1933 return env;
1934 }
1935 }
1936
1937 return NULL;
1938 }
1939
1940 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1941 {
1942 CPUState *env;
1943 const char *p;
1944 uint32_t thread;
1945 int ch, reg_size, type, res;
1946 char buf[MAX_PACKET_LENGTH];
1947 uint8_t mem_buf[MAX_PACKET_LENGTH];
1948 uint8_t *registers;
1949 target_ulong addr, len;
1950
1951 #ifdef DEBUG_GDB
1952 printf("command='%s'\n", line_buf);
1953 #endif
1954 p = line_buf;
1955 ch = *p++;
1956 switch(ch) {
1957 case '?':
1958 /* TODO: Make this return the correct value for user-mode. */
1959 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1960 gdb_id(s->c_cpu));
1961 put_packet(s, buf);
1962 /* Remove all the breakpoints when this query is issued,
1963 * because gdb is doing and initial connect and the state
1964 * should be cleaned up.
1965 */
1966 gdb_breakpoint_remove_all();
1967 break;
1968 case 'c':
1969 if (*p != '\0') {
1970 addr = strtoull(p, (char **)&p, 16);
1971 gdb_set_cpu_pc(s, addr);
1972 }
1973 s->signal = 0;
1974 gdb_continue(s);
1975 return RS_IDLE;
1976 case 'C':
1977 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1978 if (s->signal == -1)
1979 s->signal = 0;
1980 gdb_continue(s);
1981 return RS_IDLE;
1982 case 'v':
1983 if (strncmp(p, "Cont", 4) == 0) {
1984 int res_signal, res_thread;
1985
1986 p += 4;
1987 if (*p == '?') {
1988 put_packet(s, "vCont;c;C;s;S");
1989 break;
1990 }
1991 res = 0;
1992 res_signal = 0;
1993 res_thread = 0;
1994 while (*p) {
1995 int action, signal;
1996
1997 if (*p++ != ';') {
1998 res = 0;
1999 break;
2000 }
2001 action = *p++;
2002 signal = 0;
2003 if (action == 'C' || action == 'S') {
2004 signal = strtoul(p, (char **)&p, 16);
2005 } else if (action != 'c' && action != 's') {
2006 res = 0;
2007 break;
2008 }
2009 thread = 0;
2010 if (*p == ':') {
2011 thread = strtoull(p+1, (char **)&p, 16);
2012 }
2013 action = tolower(action);
2014 if (res == 0 || (res == 'c' && action == 's')) {
2015 res = action;
2016 res_signal = signal;
2017 res_thread = thread;
2018 }
2019 }
2020 if (res) {
2021 if (res_thread != -1 && res_thread != 0) {
2022 env = find_cpu(res_thread);
2023 if (env == NULL) {
2024 put_packet(s, "E22");
2025 break;
2026 }
2027 s->c_cpu = env;
2028 }
2029 if (res == 's') {
2030 cpu_single_step(s->c_cpu, sstep_flags);
2031 }
2032 s->signal = res_signal;
2033 gdb_continue(s);
2034 return RS_IDLE;
2035 }
2036 break;
2037 } else {
2038 goto unknown_command;
2039 }
2040 case 'k':
2041 /* Kill the target */
2042 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
2043 exit(0);
2044 case 'D':
2045 /* Detach packet */
2046 gdb_breakpoint_remove_all();
2047 gdb_syscall_mode = GDB_SYS_DISABLED;
2048 gdb_continue(s);
2049 put_packet(s, "OK");
2050 break;
2051 case 's':
2052 if (*p != '\0') {
2053 addr = strtoull(p, (char **)&p, 16);
2054 gdb_set_cpu_pc(s, addr);
2055 }
2056 cpu_single_step(s->c_cpu, sstep_flags);
2057 gdb_continue(s);
2058 return RS_IDLE;
2059 case 'F':
2060 {
2061 target_ulong ret;
2062 target_ulong err;
2063
2064 ret = strtoull(p, (char **)&p, 16);
2065 if (*p == ',') {
2066 p++;
2067 err = strtoull(p, (char **)&p, 16);
2068 } else {
2069 err = 0;
2070 }
2071 if (*p == ',')
2072 p++;
2073 type = *p;
2074 if (gdb_current_syscall_cb)
2075 gdb_current_syscall_cb(s->c_cpu, ret, err);
2076 if (type == 'C') {
2077 put_packet(s, "T02");
2078 } else {
2079 gdb_continue(s);
2080 }
2081 }
2082 break;
2083 case 'g':
2084 cpu_synchronize_state(s->g_cpu);
2085 env = s->g_cpu;
2086 len = 0;
2087 for (addr = 0; addr < num_g_regs; addr++) {
2088 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
2089 len += reg_size;
2090 }
2091 memtohex(buf, mem_buf, len);
2092 put_packet(s, buf);
2093 break;
2094 case 'G':
2095 cpu_synchronize_state(s->g_cpu);
2096 env = s->g_cpu;
2097 registers = mem_buf;
2098 len = strlen(p) / 2;
2099 hextomem((uint8_t *)registers, p, len);
2100 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2101 reg_size = gdb_write_register(s->g_cpu, registers, addr);
2102 len -= reg_size;
2103 registers += reg_size;
2104 }
2105 put_packet(s, "OK");
2106 break;
2107 case 'm':
2108 addr = strtoull(p, (char **)&p, 16);
2109 if (*p == ',')
2110 p++;
2111 len = strtoull(p, NULL, 16);
2112 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2113 put_packet (s, "E14");
2114 } else {
2115 memtohex(buf, mem_buf, len);
2116 put_packet(s, buf);
2117 }
2118 break;
2119 case 'M':
2120 addr = strtoull(p, (char **)&p, 16);
2121 if (*p == ',')
2122 p++;
2123 len = strtoull(p, (char **)&p, 16);
2124 if (*p == ':')
2125 p++;
2126 hextomem(mem_buf, p, len);
2127 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
2128 put_packet(s, "E14");
2129 else
2130 put_packet(s, "OK");
2131 break;
2132 case 'p':
2133 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2134 This works, but can be very slow. Anything new enough to
2135 understand XML also knows how to use this properly. */
2136 if (!gdb_has_xml)
2137 goto unknown_command;
2138 addr = strtoull(p, (char **)&p, 16);
2139 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2140 if (reg_size) {
2141 memtohex(buf, mem_buf, reg_size);
2142 put_packet(s, buf);
2143 } else {
2144 put_packet(s, "E14");
2145 }
2146 break;
2147 case 'P':
2148 if (!gdb_has_xml)
2149 goto unknown_command;
2150 addr = strtoull(p, (char **)&p, 16);
2151 if (*p == '=')
2152 p++;
2153 reg_size = strlen(p) / 2;
2154 hextomem(mem_buf, p, reg_size);
2155 gdb_write_register(s->g_cpu, mem_buf, addr);
2156 put_packet(s, "OK");
2157 break;
2158 case 'Z':
2159 case 'z':
2160 type = strtoul(p, (char **)&p, 16);
2161 if (*p == ',')
2162 p++;
2163 addr = strtoull(p, (char **)&p, 16);
2164 if (*p == ',')
2165 p++;
2166 len = strtoull(p, (char **)&p, 16);
2167 if (ch == 'Z')
2168 res = gdb_breakpoint_insert(addr, len, type);
2169 else
2170 res = gdb_breakpoint_remove(addr, len, type);
2171 if (res >= 0)
2172 put_packet(s, "OK");
2173 else if (res == -ENOSYS)
2174 put_packet(s, "");
2175 else
2176 put_packet(s, "E22");
2177 break;
2178 case 'H':
2179 type = *p++;
2180 thread = strtoull(p, (char **)&p, 16);
2181 if (thread == -1 || thread == 0) {
2182 put_packet(s, "OK");
2183 break;
2184 }
2185 env = find_cpu(thread);
2186 if (env == NULL) {
2187 put_packet(s, "E22");
2188 break;
2189 }
2190 switch (type) {
2191 case 'c':
2192 s->c_cpu = env;
2193 put_packet(s, "OK");
2194 break;
2195 case 'g':
2196 s->g_cpu = env;
2197 put_packet(s, "OK");
2198 break;
2199 default:
2200 put_packet(s, "E22");
2201 break;
2202 }
2203 break;
2204 case 'T':
2205 thread = strtoull(p, (char **)&p, 16);
2206 env = find_cpu(thread);
2207
2208 if (env != NULL) {
2209 put_packet(s, "OK");
2210 } else {
2211 put_packet(s, "E22");
2212 }
2213 break;
2214 case 'q':
2215 case 'Q':
2216 /* parse any 'q' packets here */
2217 if (!strcmp(p,"qemu.sstepbits")) {
2218 /* Query Breakpoint bit definitions */
2219 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2220 SSTEP_ENABLE,
2221 SSTEP_NOIRQ,
2222 SSTEP_NOTIMER);
2223 put_packet(s, buf);
2224 break;
2225 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2226 /* Display or change the sstep_flags */
2227 p += 10;
2228 if (*p != '=') {
2229 /* Display current setting */
2230 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2231 put_packet(s, buf);
2232 break;
2233 }
2234 p++;
2235 type = strtoul(p, (char **)&p, 16);
2236 sstep_flags = type;
2237 put_packet(s, "OK");
2238 break;
2239 } else if (strcmp(p,"C") == 0) {
2240 /* "Current thread" remains vague in the spec, so always return
2241 * the first CPU (gdb returns the first thread). */
2242 put_packet(s, "QC1");
2243 break;
2244 } else if (strcmp(p,"fThreadInfo") == 0) {
2245 s->query_cpu = first_cpu;
2246 goto report_cpuinfo;
2247 } else if (strcmp(p,"sThreadInfo") == 0) {
2248 report_cpuinfo:
2249 if (s->query_cpu) {
2250 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2251 put_packet(s, buf);
2252 s->query_cpu = s->query_cpu->next_cpu;
2253 } else
2254 put_packet(s, "l");
2255 break;
2256 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2257 thread = strtoull(p+16, (char **)&p, 16);
2258 env = find_cpu(thread);
2259 if (env != NULL) {
2260 cpu_synchronize_state(env);
2261 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2262 "CPU#%d [%s]", env->cpu_index,
2263 env->halted ? "halted " : "running");
2264 memtohex(buf, mem_buf, len);
2265 put_packet(s, buf);
2266 }
2267 break;
2268 }
2269 #ifdef CONFIG_USER_ONLY
2270 else if (strncmp(p, "Offsets", 7) == 0) {
2271 TaskState *ts = s->c_cpu->opaque;
2272
2273 snprintf(buf, sizeof(buf),
2274 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2275 ";Bss=" TARGET_ABI_FMT_lx,
2276 ts->info->code_offset,
2277 ts->info->data_offset,
2278 ts->info->data_offset);
2279 put_packet(s, buf);
2280 break;
2281 }
2282 #else /* !CONFIG_USER_ONLY */
2283 else if (strncmp(p, "Rcmd,", 5) == 0) {
2284 int len = strlen(p + 5);
2285
2286 if ((len % 2) != 0) {
2287 put_packet(s, "E01");
2288 break;
2289 }
2290 hextomem(mem_buf, p + 5, len);
2291 len = len / 2;
2292 mem_buf[len++] = 0;
2293 qemu_chr_be_write(s->mon_chr, mem_buf, len);
2294 put_packet(s, "OK");
2295 break;
2296 }
2297 #endif /* !CONFIG_USER_ONLY */
2298 if (strncmp(p, "Supported", 9) == 0) {
2299 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2300 #ifdef GDB_CORE_XML
2301 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2302 #endif
2303 put_packet(s, buf);
2304 break;
2305 }
2306 #ifdef GDB_CORE_XML
2307 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2308 const char *xml;
2309 target_ulong total_len;
2310
2311 gdb_has_xml = 1;
2312 p += 19;
2313 xml = get_feature_xml(p, &p);
2314 if (!xml) {
2315 snprintf(buf, sizeof(buf), "E00");
2316 put_packet(s, buf);
2317 break;
2318 }
2319
2320 if (*p == ':')
2321 p++;
2322 addr = strtoul(p, (char **)&p, 16);
2323 if (*p == ',')
2324 p++;
2325 len = strtoul(p, (char **)&p, 16);
2326
2327 total_len = strlen(xml);
2328 if (addr > total_len) {
2329 snprintf(buf, sizeof(buf), "E00");
2330 put_packet(s, buf);
2331 break;
2332 }
2333 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2334 len = (MAX_PACKET_LENGTH - 5) / 2;
2335 if (len < total_len - addr) {
2336 buf[0] = 'm';
2337 len = memtox(buf + 1, xml + addr, len);
2338 } else {
2339 buf[0] = 'l';
2340 len = memtox(buf + 1, xml + addr, total_len - addr);
2341 }
2342 put_packet_binary(s, buf, len + 1);
2343 break;
2344 }
2345 #endif
2346 /* Unrecognised 'q' command. */
2347 goto unknown_command;
2348
2349 default:
2350 unknown_command:
2351 /* put empty packet */
2352 buf[0] = '\0';
2353 put_packet(s, buf);
2354 break;
2355 }
2356 return RS_IDLE;
2357 }
2358
2359 void gdb_set_stop_cpu(CPUState *env)
2360 {
2361 gdbserver_state->c_cpu = env;
2362 gdbserver_state->g_cpu = env;
2363 }
2364
2365 #ifndef CONFIG_USER_ONLY
2366 static void gdb_vm_state_change(void *opaque, int running, int reason)
2367 {
2368 GDBState *s = gdbserver_state;
2369 CPUState *env = s->c_cpu;
2370 char buf[256];
2371 const char *type;
2372 int ret;
2373
2374 if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
2375 return;
2376 }
2377 switch (reason) {
2378 case VMSTOP_DEBUG:
2379 if (env->watchpoint_hit) {
2380 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2381 case BP_MEM_READ:
2382 type = "r";
2383 break;
2384 case BP_MEM_ACCESS:
2385 type = "a";
2386 break;
2387 default:
2388 type = "";
2389 break;
2390 }
2391 snprintf(buf, sizeof(buf),
2392 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2393 GDB_SIGNAL_TRAP, gdb_id(env), type,
2394 env->watchpoint_hit->vaddr);
2395 env->watchpoint_hit = NULL;
2396 goto send_packet;
2397 }
2398 tb_flush(env);
2399 ret = GDB_SIGNAL_TRAP;
2400 break;
2401 case VMSTOP_USER:
2402 ret = GDB_SIGNAL_INT;
2403 break;
2404 case VMSTOP_SHUTDOWN:
2405 ret = GDB_SIGNAL_QUIT;
2406 break;
2407 case VMSTOP_DISKFULL:
2408 ret = GDB_SIGNAL_IO;
2409 break;
2410 case VMSTOP_WATCHDOG:
2411 ret = GDB_SIGNAL_ALRM;
2412 break;
2413 case VMSTOP_PANIC:
2414 ret = GDB_SIGNAL_ABRT;
2415 break;
2416 case VMSTOP_SAVEVM:
2417 case VMSTOP_LOADVM:
2418 return;
2419 case VMSTOP_MIGRATE:
2420 ret = GDB_SIGNAL_XCPU;
2421 break;
2422 default:
2423 ret = GDB_SIGNAL_UNKNOWN;
2424 break;
2425 }
2426 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2427
2428 send_packet:
2429 put_packet(s, buf);
2430
2431 /* disable single step if it was enabled */
2432 cpu_single_step(env, 0);
2433 }
2434 #endif
2435
2436 /* Send a gdb syscall request.
2437 This accepts limited printf-style format specifiers, specifically:
2438 %x - target_ulong argument printed in hex.
2439 %lx - 64-bit argument printed in hex.
2440 %s - string pointer (target_ulong) and length (int) pair. */
2441 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2442 {
2443 va_list va;
2444 char buf[256];
2445 char *p;
2446 target_ulong addr;
2447 uint64_t i64;
2448 GDBState *s;
2449
2450 s = gdbserver_state;
2451 if (!s)
2452 return;
2453 gdb_current_syscall_cb = cb;
2454 s->state = RS_SYSCALL;
2455 #ifndef CONFIG_USER_ONLY
2456 vm_stop(VMSTOP_DEBUG);
2457 #endif
2458 s->state = RS_IDLE;
2459 va_start(va, fmt);
2460 p = buf;
2461 *(p++) = 'F';
2462 while (*fmt) {
2463 if (*fmt == '%') {
2464 fmt++;
2465 switch (*fmt++) {
2466 case 'x':
2467 addr = va_arg(va, target_ulong);
2468 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2469 break;
2470 case 'l':
2471 if (*(fmt++) != 'x')
2472 goto bad_format;
2473 i64 = va_arg(va, uint64_t);
2474 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2475 break;
2476 case 's':
2477 addr = va_arg(va, target_ulong);
2478 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2479 addr, va_arg(va, int));
2480 break;
2481 default:
2482 bad_format:
2483 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2484 fmt - 1);
2485 break;
2486 }
2487 } else {
2488 *(p++) = *(fmt++);
2489 }
2490 }
2491 *p = 0;
2492 va_end(va);
2493 put_packet(s, buf);
2494 #ifdef CONFIG_USER_ONLY
2495 gdb_handlesig(s->c_cpu, 0);
2496 #else
2497 cpu_exit(s->c_cpu);
2498 #endif
2499 }
2500
2501 static void gdb_read_byte(GDBState *s, int ch)
2502 {
2503 int i, csum;
2504 uint8_t reply;
2505
2506 #ifndef CONFIG_USER_ONLY
2507 if (s->last_packet_len) {
2508 /* Waiting for a response to the last packet. If we see the start
2509 of a new command then abandon the previous response. */
2510 if (ch == '-') {
2511 #ifdef DEBUG_GDB
2512 printf("Got NACK, retransmitting\n");
2513 #endif
2514 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2515 }
2516 #ifdef DEBUG_GDB
2517 else if (ch == '+')
2518 printf("Got ACK\n");
2519 else
2520 printf("Got '%c' when expecting ACK/NACK\n", ch);
2521 #endif
2522 if (ch == '+' || ch == '$')
2523 s->last_packet_len = 0;
2524 if (ch != '$')
2525 return;
2526 }
2527 if (vm_running) {
2528 /* when the CPU is running, we cannot do anything except stop
2529 it when receiving a char */
2530 vm_stop(VMSTOP_USER);
2531 } else
2532 #endif
2533 {
2534 switch(s->state) {
2535 case RS_IDLE:
2536 if (ch == '$') {
2537 s->line_buf_index = 0;
2538 s->state = RS_GETLINE;
2539 }
2540 break;
2541 case RS_GETLINE:
2542 if (ch == '#') {
2543 s->state = RS_CHKSUM1;
2544 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2545 s->state = RS_IDLE;
2546 } else {
2547 s->line_buf[s->line_buf_index++] = ch;
2548 }
2549 break;
2550 case RS_CHKSUM1:
2551 s->line_buf[s->line_buf_index] = '\0';
2552 s->line_csum = fromhex(ch) << 4;
2553 s->state = RS_CHKSUM2;
2554 break;
2555 case RS_CHKSUM2:
2556 s->line_csum |= fromhex(ch);
2557 csum = 0;
2558 for(i = 0; i < s->line_buf_index; i++) {
2559 csum += s->line_buf[i];
2560 }
2561 if (s->line_csum != (csum & 0xff)) {
2562 reply = '-';
2563 put_buffer(s, &reply, 1);
2564 s->state = RS_IDLE;
2565 } else {
2566 reply = '+';
2567 put_buffer(s, &reply, 1);
2568 s->state = gdb_handle_packet(s, s->line_buf);
2569 }
2570 break;
2571 default:
2572 abort();
2573 }
2574 }
2575 }
2576
2577 /* Tell the remote gdb that the process has exited. */
2578 void gdb_exit(CPUState *env, int code)
2579 {
2580 GDBState *s;
2581 char buf[4];
2582
2583 s = gdbserver_state;
2584 if (!s) {
2585 return;
2586 }
2587 #ifdef CONFIG_USER_ONLY
2588 if (gdbserver_fd < 0 || s->fd < 0) {
2589 return;
2590 }
2591 #endif
2592
2593 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2594 put_packet(s, buf);
2595
2596 #ifndef CONFIG_USER_ONLY
2597 if (s->chr) {
2598 qemu_chr_delete(s->chr);
2599 }
2600 #endif
2601 }
2602
2603 #ifdef CONFIG_USER_ONLY
2604 int
2605 gdb_queuesig (void)
2606 {
2607 GDBState *s;
2608
2609 s = gdbserver_state;
2610
2611 if (gdbserver_fd < 0 || s->fd < 0)
2612 return 0;
2613 else
2614 return 1;
2615 }
2616
2617 int
2618 gdb_handlesig (CPUState *env, int sig)
2619 {
2620 GDBState *s;
2621 char buf[256];
2622 int n;
2623
2624 s = gdbserver_state;
2625 if (gdbserver_fd < 0 || s->fd < 0)
2626 return sig;
2627
2628 /* disable single step if it was enabled */
2629 cpu_single_step(env, 0);
2630 tb_flush(env);
2631
2632 if (sig != 0)
2633 {
2634 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2635 put_packet(s, buf);
2636 }
2637 /* put_packet() might have detected that the peer terminated the
2638 connection. */
2639 if (s->fd < 0)
2640 return sig;
2641
2642 sig = 0;
2643 s->state = RS_IDLE;
2644 s->running_state = 0;
2645 while (s->running_state == 0) {
2646 n = read (s->fd, buf, 256);
2647 if (n > 0)
2648 {
2649 int i;
2650
2651 for (i = 0; i < n; i++)
2652 gdb_read_byte (s, buf[i]);
2653 }
2654 else if (n == 0 || errno != EAGAIN)
2655 {
2656 /* XXX: Connection closed. Should probably wait for annother
2657 connection before continuing. */
2658 return sig;
2659 }
2660 }
2661 sig = s->signal;
2662 s->signal = 0;
2663 return sig;
2664 }
2665
2666 /* Tell the remote gdb that the process has exited due to SIG. */
2667 void gdb_signalled(CPUState *env, int sig)
2668 {
2669 GDBState *s;
2670 char buf[4];
2671
2672 s = gdbserver_state;
2673 if (gdbserver_fd < 0 || s->fd < 0)
2674 return;
2675
2676 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2677 put_packet(s, buf);
2678 }
2679
2680 static void gdb_accept(void)
2681 {
2682 GDBState *s;
2683 struct sockaddr_in sockaddr;
2684 socklen_t len;
2685 int val, fd;
2686
2687 for(;;) {
2688 len = sizeof(sockaddr);
2689 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2690 if (fd < 0 && errno != EINTR) {
2691 perror("accept");
2692 return;
2693 } else if (fd >= 0) {
2694 #ifndef _WIN32
2695 fcntl(fd, F_SETFD, FD_CLOEXEC);
2696 #endif
2697 break;
2698 }
2699 }
2700
2701 /* set short latency */
2702 val = 1;
2703 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2704
2705 s = g_malloc0(sizeof(GDBState));
2706 s->c_cpu = first_cpu;
2707 s->g_cpu = first_cpu;
2708 s->fd = fd;
2709 gdb_has_xml = 0;
2710
2711 gdbserver_state = s;
2712
2713 fcntl(fd, F_SETFL, O_NONBLOCK);
2714 }
2715
2716 static int gdbserver_open(int port)
2717 {
2718 struct sockaddr_in sockaddr;
2719 int fd, val, ret;
2720
2721 fd = socket(PF_INET, SOCK_STREAM, 0);
2722 if (fd < 0) {
2723 perror("socket");
2724 return -1;
2725 }
2726 #ifndef _WIN32
2727 fcntl(fd, F_SETFD, FD_CLOEXEC);
2728 #endif
2729
2730 /* allow fast reuse */
2731 val = 1;
2732 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2733
2734 sockaddr.sin_family = AF_INET;
2735 sockaddr.sin_port = htons(port);
2736 sockaddr.sin_addr.s_addr = 0;
2737 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2738 if (ret < 0) {
2739 perror("bind");
2740 return -1;
2741 }
2742 ret = listen(fd, 0);
2743 if (ret < 0) {
2744 perror("listen");
2745 return -1;
2746 }
2747 return fd;
2748 }
2749
2750 int gdbserver_start(int port)
2751 {
2752 gdbserver_fd = gdbserver_open(port);
2753 if (gdbserver_fd < 0)
2754 return -1;
2755 /* accept connections */
2756 gdb_accept();
2757 return 0;
2758 }
2759
2760 /* Disable gdb stub for child processes. */
2761 void gdbserver_fork(CPUState *env)
2762 {
2763 GDBState *s = gdbserver_state;
2764 if (gdbserver_fd < 0 || s->fd < 0)
2765 return;
2766 close(s->fd);
2767 s->fd = -1;
2768 cpu_breakpoint_remove_all(env, BP_GDB);
2769 cpu_watchpoint_remove_all(env, BP_GDB);
2770 }
2771 #else
2772 static int gdb_chr_can_receive(void *opaque)
2773 {
2774 /* We can handle an arbitrarily large amount of data.
2775 Pick the maximum packet size, which is as good as anything. */
2776 return MAX_PACKET_LENGTH;
2777 }
2778
2779 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2780 {
2781 int i;
2782
2783 for (i = 0; i < size; i++) {
2784 gdb_read_byte(gdbserver_state, buf[i]);
2785 }
2786 }
2787
2788 static void gdb_chr_event(void *opaque, int event)
2789 {
2790 switch (event) {
2791 case CHR_EVENT_OPENED:
2792 vm_stop(VMSTOP_USER);
2793 gdb_has_xml = 0;
2794 break;
2795 default:
2796 break;
2797 }
2798 }
2799
2800 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2801 {
2802 char buf[MAX_PACKET_LENGTH];
2803
2804 buf[0] = 'O';
2805 if (len > (MAX_PACKET_LENGTH/2) - 1)
2806 len = (MAX_PACKET_LENGTH/2) - 1;
2807 memtohex(buf + 1, (uint8_t *)msg, len);
2808 put_packet(s, buf);
2809 }
2810
2811 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2812 {
2813 const char *p = (const char *)buf;
2814 int max_sz;
2815
2816 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2817 for (;;) {
2818 if (len <= max_sz) {
2819 gdb_monitor_output(gdbserver_state, p, len);
2820 break;
2821 }
2822 gdb_monitor_output(gdbserver_state, p, max_sz);
2823 p += max_sz;
2824 len -= max_sz;
2825 }
2826 return len;
2827 }
2828
2829 #ifndef _WIN32
2830 static void gdb_sigterm_handler(int signal)
2831 {
2832 if (vm_running) {
2833 vm_stop(VMSTOP_USER);
2834 }
2835 }
2836 #endif
2837
2838 int gdbserver_start(const char *device)
2839 {
2840 GDBState *s;
2841 char gdbstub_device_name[128];
2842 CharDriverState *chr = NULL;
2843 CharDriverState *mon_chr;
2844
2845 if (!device)
2846 return -1;
2847 if (strcmp(device, "none") != 0) {
2848 if (strstart(device, "tcp:", NULL)) {
2849 /* enforce required TCP attributes */
2850 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2851 "%s,nowait,nodelay,server", device);
2852 device = gdbstub_device_name;
2853 }
2854 #ifndef _WIN32
2855 else if (strcmp(device, "stdio") == 0) {
2856 struct sigaction act;
2857
2858 memset(&act, 0, sizeof(act));
2859 act.sa_handler = gdb_sigterm_handler;
2860 sigaction(SIGINT, &act, NULL);
2861 }
2862 #endif
2863 chr = qemu_chr_new("gdb", device, NULL);
2864 if (!chr)
2865 return -1;
2866
2867 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2868 gdb_chr_event, NULL);
2869 }
2870
2871 s = gdbserver_state;
2872 if (!s) {
2873 s = g_malloc0(sizeof(GDBState));
2874 gdbserver_state = s;
2875
2876 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2877
2878 /* Initialize a monitor terminal for gdb */
2879 mon_chr = g_malloc0(sizeof(*mon_chr));
2880 mon_chr->chr_write = gdb_monitor_write;
2881 monitor_init(mon_chr, 0);
2882 } else {
2883 if (s->chr)
2884 qemu_chr_delete(s->chr);
2885 mon_chr = s->mon_chr;
2886 memset(s, 0, sizeof(GDBState));
2887 }
2888 s->c_cpu = first_cpu;
2889 s->g_cpu = first_cpu;
2890 s->chr = chr;
2891 s->state = chr ? RS_IDLE : RS_INACTIVE;
2892 s->mon_chr = mon_chr;
2893
2894 return 0;
2895 }
2896 #endif
QEmu