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iotests: add small-granularity mirror test
[qemu.git] / hw / block / fdc.c
blobf73af7db46837de19be990595ec49f83ca8ce5db
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/hw.h"
32 #include "hw/block/fdc.h"
33 #include "qapi/error.h"
34 #include "qemu/error-report.h"
35 #include "qemu/timer.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/blockdev.h"
40 #include "sysemu/sysemu.h"
41 #include "qemu/log.h"
42
43 /********************************************************/
44 /* debug Floppy devices */
45
46 #define DEBUG_FLOPPY 0
47
48 #define FLOPPY_DPRINTF(fmt, ...) \
49 do { \
50 if (DEBUG_FLOPPY) { \
51 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
52 } \
53 } while (0)
54
55 /********************************************************/
56 /* Floppy drive emulation */
57
58 typedef enum FDriveRate {
59 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
60 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
61 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
62 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
63 } FDriveRate;
64
65 typedef enum FDriveSize {
66 FDRIVE_SIZE_UNKNOWN,
67 FDRIVE_SIZE_350,
68 FDRIVE_SIZE_525,
69 } FDriveSize;
70
71 typedef struct FDFormat {
72 FloppyDriveType drive;
73 uint8_t last_sect;
74 uint8_t max_track;
75 uint8_t max_head;
76 FDriveRate rate;
77 } FDFormat;
78
79 /* In many cases, the total sector size of a format is enough to uniquely
80 * identify it. However, there are some total sector collisions between
81 * formats of different physical size, and these are noted below by
82 * highlighting the total sector size for entries with collisions. */
83 static const FDFormat fd_formats[] = {
84 /* First entry is default format */
85 /* 1.44 MB 3"1/2 floppy disks */
86 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
87 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
88 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
89 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
90 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
91 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
92 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
93 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
94 /* 2.88 MB 3"1/2 floppy disks */
95 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
96 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
97 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
98 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
99 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
100 /* 720 kB 3"1/2 floppy disks */
101 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
102 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
104 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
105 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
106 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
107 /* 1.2 MB 5"1/4 floppy disks */
108 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
110 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
111 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
112 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
113 /* 720 kB 5"1/4 floppy disks */
114 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
115 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
116 /* 360 kB 5"1/4 floppy disks */
117 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
118 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
119 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
120 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
121 /* 320 kB 5"1/4 floppy disks */
122 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
123 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
124 /* 360 kB must match 5"1/4 better than 3"1/2... */
125 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
126 /* end */
127 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
128 };
129
130 static FDriveSize drive_size(FloppyDriveType drive)
131 {
132 switch (drive) {
133 case FLOPPY_DRIVE_TYPE_120:
134 return FDRIVE_SIZE_525;
135 case FLOPPY_DRIVE_TYPE_144:
136 case FLOPPY_DRIVE_TYPE_288:
137 return FDRIVE_SIZE_350;
138 default:
139 return FDRIVE_SIZE_UNKNOWN;
140 }
141 }
142
143 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
144 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
145
146 /* Will always be a fixed parameter for us */
147 #define FD_SECTOR_LEN 512
148 #define FD_SECTOR_SC 2 /* Sector size code */
149 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
150
151 typedef struct FDCtrl FDCtrl;
152
153 /* Floppy disk drive emulation */
154 typedef enum FDiskFlags {
155 FDISK_DBL_SIDES = 0x01,
156 } FDiskFlags;
157
158 typedef struct FDrive {
159 FDCtrl *fdctrl;
160 BlockBackend *blk;
161 /* Drive status */
162 FloppyDriveType drive; /* CMOS drive type */
163 uint8_t perpendicular; /* 2.88 MB access mode */
164 /* Position */
165 uint8_t head;
166 uint8_t track;
167 uint8_t sect;
168 /* Media */
169 FloppyDriveType disk; /* Current disk type */
170 FDiskFlags flags;
171 uint8_t last_sect; /* Nb sector per track */
172 uint8_t max_track; /* Nb of tracks */
173 uint16_t bps; /* Bytes per sector */
174 uint8_t ro; /* Is read-only */
175 uint8_t media_changed; /* Is media changed */
176 uint8_t media_rate; /* Data rate of medium */
177
178 bool media_validated; /* Have we validated the media? */
179 } FDrive;
180
181
182 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
183
184 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
185 * currently goes through some pains to keep seeks within the bounds
186 * established by last_sect and max_track. Correcting this is difficult,
187 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
188 *
189 * For now: allow empty drives to have large bounds so we can seek around,
190 * with the understanding that when a diskette is inserted, the bounds will
191 * properly tighten to match the geometry of that inserted medium.
192 */
193 static void fd_empty_seek_hack(FDrive *drv)
194 {
195 drv->last_sect = 0xFF;
196 drv->max_track = 0xFF;
197 }
198
199 static void fd_init(FDrive *drv)
200 {
201 /* Drive */
202 drv->perpendicular = 0;
203 /* Disk */
204 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
205 drv->last_sect = 0;
206 drv->max_track = 0;
207 drv->ro = true;
208 drv->media_changed = 1;
209 }
210
211 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
212
213 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
214 uint8_t last_sect, uint8_t num_sides)
215 {
216 return (((track * num_sides) + head) * last_sect) + sect - 1;
217 }
218
219 /* Returns current position, in sectors, for given drive */
220 static int fd_sector(FDrive *drv)
221 {
222 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
223 NUM_SIDES(drv));
224 }
225
226 /* Returns current position, in bytes, for given drive */
227 static int fd_offset(FDrive *drv)
228 {
229 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
230 return fd_sector(drv) << BDRV_SECTOR_BITS;
231 }
232
233 /* Seek to a new position:
234 * returns 0 if already on right track
235 * returns 1 if track changed
236 * returns 2 if track is invalid
237 * returns 3 if sector is invalid
238 * returns 4 if seek is disabled
239 */
240 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
241 int enable_seek)
242 {
243 uint32_t sector;
244 int ret;
245
246 if (track > drv->max_track ||
247 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
248 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
249 head, track, sect, 1,
250 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
251 drv->max_track, drv->last_sect);
252 return 2;
253 }
254 if (sect > drv->last_sect) {
255 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
256 head, track, sect, 1,
257 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
258 drv->max_track, drv->last_sect);
259 return 3;
260 }
261 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
262 ret = 0;
263 if (sector != fd_sector(drv)) {
264 #if 0
265 if (!enable_seek) {
266 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
267 " (max=%d %02x %02x)\n",
268 head, track, sect, 1, drv->max_track,
269 drv->last_sect);
270 return 4;
271 }
272 #endif
273 drv->head = head;
274 if (drv->track != track) {
275 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
276 drv->media_changed = 0;
277 }
278 ret = 1;
279 }
280 drv->track = track;
281 drv->sect = sect;
282 }
283
284 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
285 ret = 2;
286 }
287
288 return ret;
289 }
290
291 /* Set drive back to track 0 */
292 static void fd_recalibrate(FDrive *drv)
293 {
294 FLOPPY_DPRINTF("recalibrate\n");
295 fd_seek(drv, 0, 0, 1, 1);
296 }
297
298 /**
299 * Determine geometry based on inserted diskette.
300 * Will not operate on an empty drive.
301 *
302 * @return: 0 on success, -1 if the drive is empty.
303 */
304 static int pick_geometry(FDrive *drv)
305 {
306 BlockBackend *blk = drv->blk;
307 const FDFormat *parse;
308 uint64_t nb_sectors, size;
309 int i;
310 int match, size_match, type_match;
311 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
312
313 /* We can only pick a geometry if we have a diskette. */
314 if (!drv->blk || !blk_is_inserted(drv->blk) ||
315 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
316 {
317 return -1;
318 }
319
320 /* We need to determine the likely geometry of the inserted medium.
321 * In order of preference, we look for:
322 * (1) The same drive type and number of sectors,
323 * (2) The same diskette size and number of sectors,
324 * (3) The same drive type.
325 *
326 * In all cases, matches that occur higher in the drive table will take
327 * precedence over matches that occur later in the table.
328 */
329 blk_get_geometry(blk, &nb_sectors);
330 match = size_match = type_match = -1;
331 for (i = 0; ; i++) {
332 parse = &fd_formats[i];
333 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
334 break;
335 }
336 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
337 if (nb_sectors == size) {
338 if (magic || parse->drive == drv->drive) {
339 /* (1) perfect match -- nb_sectors and drive type */
340 goto out;
341 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
342 /* (2) size match -- nb_sectors and physical medium size */
343 match = (match == -1) ? i : match;
344 } else {
345 /* This is suspicious -- Did the user misconfigure? */
346 size_match = (size_match == -1) ? i : size_match;
347 }
348 } else if (type_match == -1) {
349 if ((parse->drive == drv->drive) ||
350 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
351 /* (3) type match -- nb_sectors mismatch, but matches the type
352 * specified explicitly by the user, or matches the fallback
353 * default type when using the drive autodetect mechanism */
354 type_match = i;
355 }
356 }
357 }
358
359 /* No exact match found */
360 if (match == -1) {
361 if (size_match != -1) {
362 parse = &fd_formats[size_match];
363 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
364 "but inserted medium appears to be a "
365 "%"PRId64" sector '%s' type\n",
366 FloppyDriveType_lookup[drv->drive],
367 nb_sectors,
368 FloppyDriveType_lookup[parse->drive]);
369 }
370 match = type_match;
371 }
372
373 /* No match of any kind found -- fd_format is misconfigured, abort. */
374 if (match == -1) {
375 error_setg(&error_abort, "No candidate geometries present in table "
376 " for floppy drive type '%s'",
377 FloppyDriveType_lookup[drv->drive]);
378 }
379
380 parse = &(fd_formats[match]);
381
382 out:
383 if (parse->max_head == 0) {
384 drv->flags &= ~FDISK_DBL_SIDES;
385 } else {
386 drv->flags |= FDISK_DBL_SIDES;
387 }
388 drv->max_track = parse->max_track;
389 drv->last_sect = parse->last_sect;
390 drv->disk = parse->drive;
391 drv->media_rate = parse->rate;
392 return 0;
393 }
394
395 static void pick_drive_type(FDrive *drv)
396 {
397 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
398 return;
399 }
400
401 if (pick_geometry(drv) == 0) {
402 drv->drive = drv->disk;
403 } else {
404 drv->drive = get_fallback_drive_type(drv);
405 }
406
407 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
408 }
409
410 /* Revalidate a disk drive after a disk change */
411 static void fd_revalidate(FDrive *drv)
412 {
413 int rc;
414
415 FLOPPY_DPRINTF("revalidate\n");
416 if (drv->blk != NULL) {
417 drv->ro = blk_is_read_only(drv->blk);
418 if (!blk_is_inserted(drv->blk)) {
419 FLOPPY_DPRINTF("No disk in drive\n");
420 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
421 fd_empty_seek_hack(drv);
422 } else if (!drv->media_validated) {
423 rc = pick_geometry(drv);
424 if (rc) {
425 FLOPPY_DPRINTF("Could not validate floppy drive media");
426 } else {
427 drv->media_validated = true;
428 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
429 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
430 drv->max_track, drv->last_sect,
431 drv->ro ? "ro" : "rw");
432 }
433 }
434 } else {
435 FLOPPY_DPRINTF("No drive connected\n");
436 drv->last_sect = 0;
437 drv->max_track = 0;
438 drv->flags &= ~FDISK_DBL_SIDES;
439 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
440 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
441 }
442 }
443
444 /********************************************************/
445 /* Intel 82078 floppy disk controller emulation */
446
447 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
448 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
449 static int fdctrl_transfer_handler (void *opaque, int nchan,
450 int dma_pos, int dma_len);
451 static void fdctrl_raise_irq(FDCtrl *fdctrl);
452 static FDrive *get_cur_drv(FDCtrl *fdctrl);
453
454 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
455 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
456 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
457 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
458 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
459 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
460 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
461 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
462 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
463 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
464 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
465 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
466
467 enum {
468 FD_DIR_WRITE = 0,
469 FD_DIR_READ = 1,
470 FD_DIR_SCANE = 2,
471 FD_DIR_SCANL = 3,
472 FD_DIR_SCANH = 4,
473 FD_DIR_VERIFY = 5,
474 };
475
476 enum {
477 FD_STATE_MULTI = 0x01, /* multi track flag */
478 FD_STATE_FORMAT = 0x02, /* format flag */
479 };
480
481 enum {
482 FD_REG_SRA = 0x00,
483 FD_REG_SRB = 0x01,
484 FD_REG_DOR = 0x02,
485 FD_REG_TDR = 0x03,
486 FD_REG_MSR = 0x04,
487 FD_REG_DSR = 0x04,
488 FD_REG_FIFO = 0x05,
489 FD_REG_DIR = 0x07,
490 FD_REG_CCR = 0x07,
491 };
492
493 enum {
494 FD_CMD_READ_TRACK = 0x02,
495 FD_CMD_SPECIFY = 0x03,
496 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
497 FD_CMD_WRITE = 0x05,
498 FD_CMD_READ = 0x06,
499 FD_CMD_RECALIBRATE = 0x07,
500 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
501 FD_CMD_WRITE_DELETED = 0x09,
502 FD_CMD_READ_ID = 0x0a,
503 FD_CMD_READ_DELETED = 0x0c,
504 FD_CMD_FORMAT_TRACK = 0x0d,
505 FD_CMD_DUMPREG = 0x0e,
506 FD_CMD_SEEK = 0x0f,
507 FD_CMD_VERSION = 0x10,
508 FD_CMD_SCAN_EQUAL = 0x11,
509 FD_CMD_PERPENDICULAR_MODE = 0x12,
510 FD_CMD_CONFIGURE = 0x13,
511 FD_CMD_LOCK = 0x14,
512 FD_CMD_VERIFY = 0x16,
513 FD_CMD_POWERDOWN_MODE = 0x17,
514 FD_CMD_PART_ID = 0x18,
515 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
516 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
517 FD_CMD_SAVE = 0x2e,
518 FD_CMD_OPTION = 0x33,
519 FD_CMD_RESTORE = 0x4e,
520 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
521 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
522 FD_CMD_FORMAT_AND_WRITE = 0xcd,
523 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
524 };
525
526 enum {
527 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
528 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
529 FD_CONFIG_POLL = 0x10, /* Poll enabled */
530 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
531 FD_CONFIG_EIS = 0x40, /* No implied seeks */
532 };
533
534 enum {
535 FD_SR0_DS0 = 0x01,
536 FD_SR0_DS1 = 0x02,
537 FD_SR0_HEAD = 0x04,
538 FD_SR0_EQPMT = 0x10,
539 FD_SR0_SEEK = 0x20,
540 FD_SR0_ABNTERM = 0x40,
541 FD_SR0_INVCMD = 0x80,
542 FD_SR0_RDYCHG = 0xc0,
543 };
544
545 enum {
546 FD_SR1_MA = 0x01, /* Missing address mark */
547 FD_SR1_NW = 0x02, /* Not writable */
548 FD_SR1_EC = 0x80, /* End of cylinder */
549 };
550
551 enum {
552 FD_SR2_SNS = 0x04, /* Scan not satisfied */
553 FD_SR2_SEH = 0x08, /* Scan equal hit */
554 };
555
556 enum {
557 FD_SRA_DIR = 0x01,
558 FD_SRA_nWP = 0x02,
559 FD_SRA_nINDX = 0x04,
560 FD_SRA_HDSEL = 0x08,
561 FD_SRA_nTRK0 = 0x10,
562 FD_SRA_STEP = 0x20,
563 FD_SRA_nDRV2 = 0x40,
564 FD_SRA_INTPEND = 0x80,
565 };
566
567 enum {
568 FD_SRB_MTR0 = 0x01,
569 FD_SRB_MTR1 = 0x02,
570 FD_SRB_WGATE = 0x04,
571 FD_SRB_RDATA = 0x08,
572 FD_SRB_WDATA = 0x10,
573 FD_SRB_DR0 = 0x20,
574 };
575
576 enum {
577 #if MAX_FD == 4
578 FD_DOR_SELMASK = 0x03,
579 #else
580 FD_DOR_SELMASK = 0x01,
581 #endif
582 FD_DOR_nRESET = 0x04,
583 FD_DOR_DMAEN = 0x08,
584 FD_DOR_MOTEN0 = 0x10,
585 FD_DOR_MOTEN1 = 0x20,
586 FD_DOR_MOTEN2 = 0x40,
587 FD_DOR_MOTEN3 = 0x80,
588 };
589
590 enum {
591 #if MAX_FD == 4
592 FD_TDR_BOOTSEL = 0x0c,
593 #else
594 FD_TDR_BOOTSEL = 0x04,
595 #endif
596 };
597
598 enum {
599 FD_DSR_DRATEMASK= 0x03,
600 FD_DSR_PWRDOWN = 0x40,
601 FD_DSR_SWRESET = 0x80,
602 };
603
604 enum {
605 FD_MSR_DRV0BUSY = 0x01,
606 FD_MSR_DRV1BUSY = 0x02,
607 FD_MSR_DRV2BUSY = 0x04,
608 FD_MSR_DRV3BUSY = 0x08,
609 FD_MSR_CMDBUSY = 0x10,
610 FD_MSR_NONDMA = 0x20,
611 FD_MSR_DIO = 0x40,
612 FD_MSR_RQM = 0x80,
613 };
614
615 enum {
616 FD_DIR_DSKCHG = 0x80,
617 };
618
619 /*
620 * See chapter 5.0 "Controller phases" of the spec:
621 *
622 * Command phase:
623 * The host writes a command and its parameters into the FIFO. The command
624 * phase is completed when all parameters for the command have been supplied,
625 * and execution phase is entered.
626 *
627 * Execution phase:
628 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
629 * contains the payload now, otherwise it's unused. When all bytes of the
630 * required data have been transferred, the state is switched to either result
631 * phase (if the command produces status bytes) or directly back into the
632 * command phase for the next command.
633 *
634 * Result phase:
635 * The host reads out the FIFO, which contains one or more result bytes now.
636 */
637 enum {
638 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
639 FD_PHASE_RECONSTRUCT = 0,
640
641 FD_PHASE_COMMAND = 1,
642 FD_PHASE_EXECUTION = 2,
643 FD_PHASE_RESULT = 3,
644 };
645
646 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
647 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
648
649 struct FDCtrl {
650 MemoryRegion iomem;
651 qemu_irq irq;
652 /* Controller state */
653 QEMUTimer *result_timer;
654 int dma_chann;
655 uint8_t phase;
656 IsaDma *dma;
657 /* Controller's identification */
658 uint8_t version;
659 /* HW */
660 uint8_t sra;
661 uint8_t srb;
662 uint8_t dor;
663 uint8_t dor_vmstate; /* only used as temp during vmstate */
664 uint8_t tdr;
665 uint8_t dsr;
666 uint8_t msr;
667 uint8_t cur_drv;
668 uint8_t status0;
669 uint8_t status1;
670 uint8_t status2;
671 /* Command FIFO */
672 uint8_t *fifo;
673 int32_t fifo_size;
674 uint32_t data_pos;
675 uint32_t data_len;
676 uint8_t data_state;
677 uint8_t data_dir;
678 uint8_t eot; /* last wanted sector */
679 /* States kept only to be returned back */
680 /* precompensation */
681 uint8_t precomp_trk;
682 uint8_t config;
683 uint8_t lock;
684 /* Power down config (also with status regB access mode */
685 uint8_t pwrd;
686 /* Floppy drives */
687 uint8_t num_floppies;
688 FDrive drives[MAX_FD];
689 int reset_sensei;
690 uint32_t check_media_rate;
691 FloppyDriveType fallback; /* type=auto failure fallback */
692 /* Timers state */
693 uint8_t timer0;
694 uint8_t timer1;
695 };
696
697 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
698 {
699 return drv->fdctrl->fallback;
700 }
701
702 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
703 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
704
705 typedef struct FDCtrlSysBus {
706 /*< private >*/
707 SysBusDevice parent_obj;
708 /*< public >*/
709
710 struct FDCtrl state;
711 } FDCtrlSysBus;
712
713 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
714
715 typedef struct FDCtrlISABus {
716 ISADevice parent_obj;
717
718 uint32_t iobase;
719 uint32_t irq;
720 uint32_t dma;
721 struct FDCtrl state;
722 int32_t bootindexA;
723 int32_t bootindexB;
724 } FDCtrlISABus;
725
726 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
727 {
728 FDCtrl *fdctrl = opaque;
729 uint32_t retval;
730
731 reg &= 7;
732 switch (reg) {
733 case FD_REG_SRA:
734 retval = fdctrl_read_statusA(fdctrl);
735 break;
736 case FD_REG_SRB:
737 retval = fdctrl_read_statusB(fdctrl);
738 break;
739 case FD_REG_DOR:
740 retval = fdctrl_read_dor(fdctrl);
741 break;
742 case FD_REG_TDR:
743 retval = fdctrl_read_tape(fdctrl);
744 break;
745 case FD_REG_MSR:
746 retval = fdctrl_read_main_status(fdctrl);
747 break;
748 case FD_REG_FIFO:
749 retval = fdctrl_read_data(fdctrl);
750 break;
751 case FD_REG_DIR:
752 retval = fdctrl_read_dir(fdctrl);
753 break;
754 default:
755 retval = (uint32_t)(-1);
756 break;
757 }
758 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
759
760 return retval;
761 }
762
763 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
764 {
765 FDCtrl *fdctrl = opaque;
766
767 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
768
769 reg &= 7;
770 switch (reg) {
771 case FD_REG_DOR:
772 fdctrl_write_dor(fdctrl, value);
773 break;
774 case FD_REG_TDR:
775 fdctrl_write_tape(fdctrl, value);
776 break;
777 case FD_REG_DSR:
778 fdctrl_write_rate(fdctrl, value);
779 break;
780 case FD_REG_FIFO:
781 fdctrl_write_data(fdctrl, value);
782 break;
783 case FD_REG_CCR:
784 fdctrl_write_ccr(fdctrl, value);
785 break;
786 default:
787 break;
788 }
789 }
790
791 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
792 unsigned ize)
793 {
794 return fdctrl_read(opaque, (uint32_t)reg);
795 }
796
797 static void fdctrl_write_mem (void *opaque, hwaddr reg,
798 uint64_t value, unsigned size)
799 {
800 fdctrl_write(opaque, (uint32_t)reg, value);
801 }
802
803 static const MemoryRegionOps fdctrl_mem_ops = {
804 .read = fdctrl_read_mem,
805 .write = fdctrl_write_mem,
806 .endianness = DEVICE_NATIVE_ENDIAN,
807 };
808
809 static const MemoryRegionOps fdctrl_mem_strict_ops = {
810 .read = fdctrl_read_mem,
811 .write = fdctrl_write_mem,
812 .endianness = DEVICE_NATIVE_ENDIAN,
813 .valid = {
814 .min_access_size = 1,
815 .max_access_size = 1,
816 },
817 };
818
819 static bool fdrive_media_changed_needed(void *opaque)
820 {
821 FDrive *drive = opaque;
822
823 return (drive->blk != NULL && drive->media_changed != 1);
824 }
825
826 static const VMStateDescription vmstate_fdrive_media_changed = {
827 .name = "fdrive/media_changed",
828 .version_id = 1,
829 .minimum_version_id = 1,
830 .needed = fdrive_media_changed_needed,
831 .fields = (VMStateField[]) {
832 VMSTATE_UINT8(media_changed, FDrive),
833 VMSTATE_END_OF_LIST()
834 }
835 };
836
837 static bool fdrive_media_rate_needed(void *opaque)
838 {
839 FDrive *drive = opaque;
840
841 return drive->fdctrl->check_media_rate;
842 }
843
844 static const VMStateDescription vmstate_fdrive_media_rate = {
845 .name = "fdrive/media_rate",
846 .version_id = 1,
847 .minimum_version_id = 1,
848 .needed = fdrive_media_rate_needed,
849 .fields = (VMStateField[]) {
850 VMSTATE_UINT8(media_rate, FDrive),
851 VMSTATE_END_OF_LIST()
852 }
853 };
854
855 static bool fdrive_perpendicular_needed(void *opaque)
856 {
857 FDrive *drive = opaque;
858
859 return drive->perpendicular != 0;
860 }
861
862 static const VMStateDescription vmstate_fdrive_perpendicular = {
863 .name = "fdrive/perpendicular",
864 .version_id = 1,
865 .minimum_version_id = 1,
866 .needed = fdrive_perpendicular_needed,
867 .fields = (VMStateField[]) {
868 VMSTATE_UINT8(perpendicular, FDrive),
869 VMSTATE_END_OF_LIST()
870 }
871 };
872
873 static int fdrive_post_load(void *opaque, int version_id)
874 {
875 fd_revalidate(opaque);
876 return 0;
877 }
878
879 static const VMStateDescription vmstate_fdrive = {
880 .name = "fdrive",
881 .version_id = 1,
882 .minimum_version_id = 1,
883 .post_load = fdrive_post_load,
884 .fields = (VMStateField[]) {
885 VMSTATE_UINT8(head, FDrive),
886 VMSTATE_UINT8(track, FDrive),
887 VMSTATE_UINT8(sect, FDrive),
888 VMSTATE_END_OF_LIST()
889 },
890 .subsections = (const VMStateDescription*[]) {
891 &vmstate_fdrive_media_changed,
892 &vmstate_fdrive_media_rate,
893 &vmstate_fdrive_perpendicular,
894 NULL
895 }
896 };
897
898 /*
899 * Reconstructs the phase from register values according to the logic that was
900 * implemented in qemu 2.3. This is the default value that is used if the phase
901 * subsection is not present on migration.
902 *
903 * Don't change this function to reflect newer qemu versions, it is part of
904 * the migration ABI.
905 */
906 static int reconstruct_phase(FDCtrl *fdctrl)
907 {
908 if (fdctrl->msr & FD_MSR_NONDMA) {
909 return FD_PHASE_EXECUTION;
910 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
911 /* qemu 2.3 disabled RQM only during DMA transfers */
912 return FD_PHASE_EXECUTION;
913 } else if (fdctrl->msr & FD_MSR_DIO) {
914 return FD_PHASE_RESULT;
915 } else {
916 return FD_PHASE_COMMAND;
917 }
918 }
919
920 static void fdc_pre_save(void *opaque)
921 {
922 FDCtrl *s = opaque;
923
924 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
925 }
926
927 static int fdc_pre_load(void *opaque)
928 {
929 FDCtrl *s = opaque;
930 s->phase = FD_PHASE_RECONSTRUCT;
931 return 0;
932 }
933
934 static int fdc_post_load(void *opaque, int version_id)
935 {
936 FDCtrl *s = opaque;
937
938 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
939 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
940
941 if (s->phase == FD_PHASE_RECONSTRUCT) {
942 s->phase = reconstruct_phase(s);
943 }
944
945 return 0;
946 }
947
948 static bool fdc_reset_sensei_needed(void *opaque)
949 {
950 FDCtrl *s = opaque;
951
952 return s->reset_sensei != 0;
953 }
954
955 static const VMStateDescription vmstate_fdc_reset_sensei = {
956 .name = "fdc/reset_sensei",
957 .version_id = 1,
958 .minimum_version_id = 1,
959 .needed = fdc_reset_sensei_needed,
960 .fields = (VMStateField[]) {
961 VMSTATE_INT32(reset_sensei, FDCtrl),
962 VMSTATE_END_OF_LIST()
963 }
964 };
965
966 static bool fdc_result_timer_needed(void *opaque)
967 {
968 FDCtrl *s = opaque;
969
970 return timer_pending(s->result_timer);
971 }
972
973 static const VMStateDescription vmstate_fdc_result_timer = {
974 .name = "fdc/result_timer",
975 .version_id = 1,
976 .minimum_version_id = 1,
977 .needed = fdc_result_timer_needed,
978 .fields = (VMStateField[]) {
979 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
980 VMSTATE_END_OF_LIST()
981 }
982 };
983
984 static bool fdc_phase_needed(void *opaque)
985 {
986 FDCtrl *fdctrl = opaque;
987
988 return reconstruct_phase(fdctrl) != fdctrl->phase;
989 }
990
991 static const VMStateDescription vmstate_fdc_phase = {
992 .name = "fdc/phase",
993 .version_id = 1,
994 .minimum_version_id = 1,
995 .needed = fdc_phase_needed,
996 .fields = (VMStateField[]) {
997 VMSTATE_UINT8(phase, FDCtrl),
998 VMSTATE_END_OF_LIST()
999 }
1000 };
1001
1002 static const VMStateDescription vmstate_fdc = {
1003 .name = "fdc",
1004 .version_id = 2,
1005 .minimum_version_id = 2,
1006 .pre_save = fdc_pre_save,
1007 .pre_load = fdc_pre_load,
1008 .post_load = fdc_post_load,
1009 .fields = (VMStateField[]) {
1010 /* Controller State */
1011 VMSTATE_UINT8(sra, FDCtrl),
1012 VMSTATE_UINT8(srb, FDCtrl),
1013 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1014 VMSTATE_UINT8(tdr, FDCtrl),
1015 VMSTATE_UINT8(dsr, FDCtrl),
1016 VMSTATE_UINT8(msr, FDCtrl),
1017 VMSTATE_UINT8(status0, FDCtrl),
1018 VMSTATE_UINT8(status1, FDCtrl),
1019 VMSTATE_UINT8(status2, FDCtrl),
1020 /* Command FIFO */
1021 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1022 uint8_t),
1023 VMSTATE_UINT32(data_pos, FDCtrl),
1024 VMSTATE_UINT32(data_len, FDCtrl),
1025 VMSTATE_UINT8(data_state, FDCtrl),
1026 VMSTATE_UINT8(data_dir, FDCtrl),
1027 VMSTATE_UINT8(eot, FDCtrl),
1028 /* States kept only to be returned back */
1029 VMSTATE_UINT8(timer0, FDCtrl),
1030 VMSTATE_UINT8(timer1, FDCtrl),
1031 VMSTATE_UINT8(precomp_trk, FDCtrl),
1032 VMSTATE_UINT8(config, FDCtrl),
1033 VMSTATE_UINT8(lock, FDCtrl),
1034 VMSTATE_UINT8(pwrd, FDCtrl),
1035 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1036 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1037 vmstate_fdrive, FDrive),
1038 VMSTATE_END_OF_LIST()
1039 },
1040 .subsections = (const VMStateDescription*[]) {
1041 &vmstate_fdc_reset_sensei,
1042 &vmstate_fdc_result_timer,
1043 &vmstate_fdc_phase,
1044 NULL
1045 }
1046 };
1047
1048 static void fdctrl_external_reset_sysbus(DeviceState *d)
1049 {
1050 FDCtrlSysBus *sys = SYSBUS_FDC(d);
1051 FDCtrl *s = &sys->state;
1052
1053 fdctrl_reset(s, 0);
1054 }
1055
1056 static void fdctrl_external_reset_isa(DeviceState *d)
1057 {
1058 FDCtrlISABus *isa = ISA_FDC(d);
1059 FDCtrl *s = &isa->state;
1060
1061 fdctrl_reset(s, 0);
1062 }
1063
1064 static void fdctrl_handle_tc(void *opaque, int irq, int level)
1065 {
1066 //FDCtrl *s = opaque;
1067
1068 if (level) {
1069 // XXX
1070 FLOPPY_DPRINTF("TC pulsed\n");
1071 }
1072 }
1073
1074 /* Change IRQ state */
1075 static void fdctrl_reset_irq(FDCtrl *fdctrl)
1076 {
1077 fdctrl->status0 = 0;
1078 if (!(fdctrl->sra & FD_SRA_INTPEND))
1079 return;
1080 FLOPPY_DPRINTF("Reset interrupt\n");
1081 qemu_set_irq(fdctrl->irq, 0);
1082 fdctrl->sra &= ~FD_SRA_INTPEND;
1083 }
1084
1085 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1086 {
1087 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1088 qemu_set_irq(fdctrl->irq, 1);
1089 fdctrl->sra |= FD_SRA_INTPEND;
1090 }
1091
1092 fdctrl->reset_sensei = 0;
1093 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1094 }
1095
1096 /* Reset controller */
1097 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1098 {
1099 int i;
1100
1101 FLOPPY_DPRINTF("reset controller\n");
1102 fdctrl_reset_irq(fdctrl);
1103 /* Initialise controller */
1104 fdctrl->sra = 0;
1105 fdctrl->srb = 0xc0;
1106 if (!fdctrl->drives[1].blk) {
1107 fdctrl->sra |= FD_SRA_nDRV2;
1108 }
1109 fdctrl->cur_drv = 0;
1110 fdctrl->dor = FD_DOR_nRESET;
1111 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1112 fdctrl->msr = FD_MSR_RQM;
1113 fdctrl->reset_sensei = 0;
1114 timer_del(fdctrl->result_timer);
1115 /* FIFO state */
1116 fdctrl->data_pos = 0;
1117 fdctrl->data_len = 0;
1118 fdctrl->data_state = 0;
1119 fdctrl->data_dir = FD_DIR_WRITE;
1120 for (i = 0; i < MAX_FD; i++)
1121 fd_recalibrate(&fdctrl->drives[i]);
1122 fdctrl_to_command_phase(fdctrl);
1123 if (do_irq) {
1124 fdctrl->status0 |= FD_SR0_RDYCHG;
1125 fdctrl_raise_irq(fdctrl);
1126 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1127 }
1128 }
1129
1130 static inline FDrive *drv0(FDCtrl *fdctrl)
1131 {
1132 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1133 }
1134
1135 static inline FDrive *drv1(FDCtrl *fdctrl)
1136 {
1137 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1138 return &fdctrl->drives[1];
1139 else
1140 return &fdctrl->drives[0];
1141 }
1142
1143 #if MAX_FD == 4
1144 static inline FDrive *drv2(FDCtrl *fdctrl)
1145 {
1146 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1147 return &fdctrl->drives[2];
1148 else
1149 return &fdctrl->drives[1];
1150 }
1151
1152 static inline FDrive *drv3(FDCtrl *fdctrl)
1153 {
1154 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1155 return &fdctrl->drives[3];
1156 else
1157 return &fdctrl->drives[2];
1158 }
1159 #endif
1160
1161 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1162 {
1163 switch (fdctrl->cur_drv) {
1164 case 0: return drv0(fdctrl);
1165 case 1: return drv1(fdctrl);
1166 #if MAX_FD == 4
1167 case 2: return drv2(fdctrl);
1168 case 3: return drv3(fdctrl);
1169 #endif
1170 default: return NULL;
1171 }
1172 }
1173
1174 /* Status A register : 0x00 (read-only) */
1175 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1176 {
1177 uint32_t retval = fdctrl->sra;
1178
1179 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1180
1181 return retval;
1182 }
1183
1184 /* Status B register : 0x01 (read-only) */
1185 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1186 {
1187 uint32_t retval = fdctrl->srb;
1188
1189 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1190
1191 return retval;
1192 }
1193
1194 /* Digital output register : 0x02 */
1195 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1196 {
1197 uint32_t retval = fdctrl->dor;
1198
1199 /* Selected drive */
1200 retval |= fdctrl->cur_drv;
1201 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1202
1203 return retval;
1204 }
1205
1206 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1207 {
1208 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1209
1210 /* Motors */
1211 if (value & FD_DOR_MOTEN0)
1212 fdctrl->srb |= FD_SRB_MTR0;
1213 else
1214 fdctrl->srb &= ~FD_SRB_MTR0;
1215 if (value & FD_DOR_MOTEN1)
1216 fdctrl->srb |= FD_SRB_MTR1;
1217 else
1218 fdctrl->srb &= ~FD_SRB_MTR1;
1219
1220 /* Drive */
1221 if (value & 1)
1222 fdctrl->srb |= FD_SRB_DR0;
1223 else
1224 fdctrl->srb &= ~FD_SRB_DR0;
1225
1226 /* Reset */
1227 if (!(value & FD_DOR_nRESET)) {
1228 if (fdctrl->dor & FD_DOR_nRESET) {
1229 FLOPPY_DPRINTF("controller enter RESET state\n");
1230 }
1231 } else {
1232 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1233 FLOPPY_DPRINTF("controller out of RESET state\n");
1234 fdctrl_reset(fdctrl, 1);
1235 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1236 }
1237 }
1238 /* Selected drive */
1239 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1240
1241 fdctrl->dor = value;
1242 }
1243
1244 /* Tape drive register : 0x03 */
1245 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1246 {
1247 uint32_t retval = fdctrl->tdr;
1248
1249 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1250
1251 return retval;
1252 }
1253
1254 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1255 {
1256 /* Reset mode */
1257 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1258 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1259 return;
1260 }
1261 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1262 /* Disk boot selection indicator */
1263 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1264 /* Tape indicators: never allow */
1265 }
1266
1267 /* Main status register : 0x04 (read) */
1268 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1269 {
1270 uint32_t retval = fdctrl->msr;
1271
1272 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1273 fdctrl->dor |= FD_DOR_nRESET;
1274
1275 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1276
1277 return retval;
1278 }
1279
1280 /* Data select rate register : 0x04 (write) */
1281 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1282 {
1283 /* Reset mode */
1284 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1285 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1286 return;
1287 }
1288 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1289 /* Reset: autoclear */
1290 if (value & FD_DSR_SWRESET) {
1291 fdctrl->dor &= ~FD_DOR_nRESET;
1292 fdctrl_reset(fdctrl, 1);
1293 fdctrl->dor |= FD_DOR_nRESET;
1294 }
1295 if (value & FD_DSR_PWRDOWN) {
1296 fdctrl_reset(fdctrl, 1);
1297 }
1298 fdctrl->dsr = value;
1299 }
1300
1301 /* Configuration control register: 0x07 (write) */
1302 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1303 {
1304 /* Reset mode */
1305 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1306 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1307 return;
1308 }
1309 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1310
1311 /* Only the rate selection bits used in AT mode, and we
1312 * store those in the DSR.
1313 */
1314 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1315 (value & FD_DSR_DRATEMASK);
1316 }
1317
1318 static int fdctrl_media_changed(FDrive *drv)
1319 {
1320 return drv->media_changed;
1321 }
1322
1323 /* Digital input register : 0x07 (read-only) */
1324 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1325 {
1326 uint32_t retval = 0;
1327
1328 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1329 retval |= FD_DIR_DSKCHG;
1330 }
1331 if (retval != 0) {
1332 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1333 }
1334
1335 return retval;
1336 }
1337
1338 /* Clear the FIFO and update the state for receiving the next command */
1339 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1340 {
1341 fdctrl->phase = FD_PHASE_COMMAND;
1342 fdctrl->data_dir = FD_DIR_WRITE;
1343 fdctrl->data_pos = 0;
1344 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1345 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1346 fdctrl->msr |= FD_MSR_RQM;
1347 }
1348
1349 /* Update the state to allow the guest to read out the command status.
1350 * @fifo_len is the number of result bytes to be read out. */
1351 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1352 {
1353 fdctrl->phase = FD_PHASE_RESULT;
1354 fdctrl->data_dir = FD_DIR_READ;
1355 fdctrl->data_len = fifo_len;
1356 fdctrl->data_pos = 0;
1357 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1358 }
1359
1360 /* Set an error: unimplemented/unknown command */
1361 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1362 {
1363 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1364 fdctrl->fifo[0]);
1365 fdctrl->fifo[0] = FD_SR0_INVCMD;
1366 fdctrl_to_result_phase(fdctrl, 1);
1367 }
1368
1369 /* Seek to next sector
1370 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1371 * otherwise returns 1
1372 */
1373 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1374 {
1375 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1376 cur_drv->head, cur_drv->track, cur_drv->sect,
1377 fd_sector(cur_drv));
1378 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1379 error in fact */
1380 uint8_t new_head = cur_drv->head;
1381 uint8_t new_track = cur_drv->track;
1382 uint8_t new_sect = cur_drv->sect;
1383
1384 int ret = 1;
1385
1386 if (new_sect >= cur_drv->last_sect ||
1387 new_sect == fdctrl->eot) {
1388 new_sect = 1;
1389 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1390 if (new_head == 0 &&
1391 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1392 new_head = 1;
1393 } else {
1394 new_head = 0;
1395 new_track++;
1396 fdctrl->status0 |= FD_SR0_SEEK;
1397 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1398 ret = 0;
1399 }
1400 }
1401 } else {
1402 fdctrl->status0 |= FD_SR0_SEEK;
1403 new_track++;
1404 ret = 0;
1405 }
1406 if (ret == 1) {
1407 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1408 new_head, new_track, new_sect, fd_sector(cur_drv));
1409 }
1410 } else {
1411 new_sect++;
1412 }
1413 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1414 return ret;
1415 }
1416
1417 /* Callback for transfer end (stop or abort) */
1418 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1419 uint8_t status1, uint8_t status2)
1420 {
1421 FDrive *cur_drv;
1422 cur_drv = get_cur_drv(fdctrl);
1423
1424 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1425 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1426 if (cur_drv->head) {
1427 fdctrl->status0 |= FD_SR0_HEAD;
1428 }
1429 fdctrl->status0 |= status0;
1430
1431 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1432 status0, status1, status2, fdctrl->status0);
1433 fdctrl->fifo[0] = fdctrl->status0;
1434 fdctrl->fifo[1] = status1;
1435 fdctrl->fifo[2] = status2;
1436 fdctrl->fifo[3] = cur_drv->track;
1437 fdctrl->fifo[4] = cur_drv->head;
1438 fdctrl->fifo[5] = cur_drv->sect;
1439 fdctrl->fifo[6] = FD_SECTOR_SC;
1440 fdctrl->data_dir = FD_DIR_READ;
1441 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1442 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1443 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
1444 }
1445 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1446 fdctrl->msr &= ~FD_MSR_NONDMA;
1447
1448 fdctrl_to_result_phase(fdctrl, 7);
1449 fdctrl_raise_irq(fdctrl);
1450 }
1451
1452 /* Prepare a data transfer (either DMA or FIFO) */
1453 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1454 {
1455 FDrive *cur_drv;
1456 uint8_t kh, kt, ks;
1457
1458 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1459 cur_drv = get_cur_drv(fdctrl);
1460 kt = fdctrl->fifo[2];
1461 kh = fdctrl->fifo[3];
1462 ks = fdctrl->fifo[4];
1463 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1464 GET_CUR_DRV(fdctrl), kh, kt, ks,
1465 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1466 NUM_SIDES(cur_drv)));
1467 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1468 case 2:
1469 /* sect too big */
1470 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1471 fdctrl->fifo[3] = kt;
1472 fdctrl->fifo[4] = kh;
1473 fdctrl->fifo[5] = ks;
1474 return;
1475 case 3:
1476 /* track too big */
1477 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1478 fdctrl->fifo[3] = kt;
1479 fdctrl->fifo[4] = kh;
1480 fdctrl->fifo[5] = ks;
1481 return;
1482 case 4:
1483 /* No seek enabled */
1484 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1485 fdctrl->fifo[3] = kt;
1486 fdctrl->fifo[4] = kh;
1487 fdctrl->fifo[5] = ks;
1488 return;
1489 case 1:
1490 fdctrl->status0 |= FD_SR0_SEEK;
1491 break;
1492 default:
1493 break;
1494 }
1495
1496 /* Check the data rate. If the programmed data rate does not match
1497 * the currently inserted medium, the operation has to fail. */
1498 if (fdctrl->check_media_rate &&
1499 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1500 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1501 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1502 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1503 fdctrl->fifo[3] = kt;
1504 fdctrl->fifo[4] = kh;
1505 fdctrl->fifo[5] = ks;
1506 return;
1507 }
1508
1509 /* Set the FIFO state */
1510 fdctrl->data_dir = direction;
1511 fdctrl->data_pos = 0;
1512 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1513 if (fdctrl->fifo[0] & 0x80)
1514 fdctrl->data_state |= FD_STATE_MULTI;
1515 else
1516 fdctrl->data_state &= ~FD_STATE_MULTI;
1517 if (fdctrl->fifo[5] == 0) {
1518 fdctrl->data_len = fdctrl->fifo[8];
1519 } else {
1520 int tmp;
1521 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1522 tmp = (fdctrl->fifo[6] - ks + 1);
1523 if (fdctrl->fifo[0] & 0x80)
1524 tmp += fdctrl->fifo[6];
1525 fdctrl->data_len *= tmp;
1526 }
1527 fdctrl->eot = fdctrl->fifo[6];
1528 if (fdctrl->dor & FD_DOR_DMAEN) {
1529 IsaDmaTransferMode dma_mode;
1530 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1531 bool dma_mode_ok;
1532 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1533 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
1534 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1535 dma_mode, direction,
1536 (128 << fdctrl->fifo[5]) *
1537 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1538 switch (direction) {
1539 case FD_DIR_SCANE:
1540 case FD_DIR_SCANL:
1541 case FD_DIR_SCANH:
1542 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1543 break;
1544 case FD_DIR_WRITE:
1545 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1546 break;
1547 case FD_DIR_READ:
1548 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1549 break;
1550 case FD_DIR_VERIFY:
1551 dma_mode_ok = true;
1552 break;
1553 default:
1554 dma_mode_ok = false;
1555 break;
1556 }
1557 if (dma_mode_ok) {
1558 /* No access is allowed until DMA transfer has completed */
1559 fdctrl->msr &= ~FD_MSR_RQM;
1560 if (direction != FD_DIR_VERIFY) {
1561 /* Now, we just have to wait for the DMA controller to
1562 * recall us...
1563 */
1564 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1565 k->schedule(fdctrl->dma);
1566 } else {
1567 /* Start transfer */
1568 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1569 fdctrl->data_len);
1570 }
1571 return;
1572 } else {
1573 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1574 direction);
1575 }
1576 }
1577 FLOPPY_DPRINTF("start non-DMA transfer\n");
1578 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1579 if (direction != FD_DIR_WRITE)
1580 fdctrl->msr |= FD_MSR_DIO;
1581 /* IO based transfer: calculate len */
1582 fdctrl_raise_irq(fdctrl);
1583 }
1584
1585 /* Prepare a transfer of deleted data */
1586 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1587 {
1588 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1589
1590 /* We don't handle deleted data,
1591 * so we don't return *ANYTHING*
1592 */
1593 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1594 }
1595
1596 /* handlers for DMA transfers */
1597 static int fdctrl_transfer_handler (void *opaque, int nchan,
1598 int dma_pos, int dma_len)
1599 {
1600 FDCtrl *fdctrl;
1601 FDrive *cur_drv;
1602 int len, start_pos, rel_pos;
1603 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1604 IsaDmaClass *k;
1605
1606 fdctrl = opaque;
1607 if (fdctrl->msr & FD_MSR_RQM) {
1608 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1609 return 0;
1610 }
1611 k = ISADMA_GET_CLASS(fdctrl->dma);
1612 cur_drv = get_cur_drv(fdctrl);
1613 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1614 fdctrl->data_dir == FD_DIR_SCANH)
1615 status2 = FD_SR2_SNS;
1616 if (dma_len > fdctrl->data_len)
1617 dma_len = fdctrl->data_len;
1618 if (cur_drv->blk == NULL) {
1619 if (fdctrl->data_dir == FD_DIR_WRITE)
1620 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1621 else
1622 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1623 len = 0;
1624 goto transfer_error;
1625 }
1626 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1627 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1628 len = dma_len - fdctrl->data_pos;
1629 if (len + rel_pos > FD_SECTOR_LEN)
1630 len = FD_SECTOR_LEN - rel_pos;
1631 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1632 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1633 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1634 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1635 fd_sector(cur_drv) * FD_SECTOR_LEN);
1636 if (fdctrl->data_dir != FD_DIR_WRITE ||
1637 len < FD_SECTOR_LEN || rel_pos != 0) {
1638 /* READ & SCAN commands and realign to a sector for WRITE */
1639 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1640 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
1641 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1642 fd_sector(cur_drv));
1643 /* Sure, image size is too small... */
1644 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1645 }
1646 }
1647 switch (fdctrl->data_dir) {
1648 case FD_DIR_READ:
1649 /* READ commands */
1650 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1651 fdctrl->data_pos, len);
1652 break;
1653 case FD_DIR_WRITE:
1654 /* WRITE commands */
1655 if (cur_drv->ro) {
1656 /* Handle readonly medium early, no need to do DMA, touch the
1657 * LED or attempt any writes. A real floppy doesn't attempt
1658 * to write to readonly media either. */
1659 fdctrl_stop_transfer(fdctrl,
1660 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1661 0x00);
1662 goto transfer_error;
1663 }
1664
1665 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1666 fdctrl->data_pos, len);
1667 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1668 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
1669 FLOPPY_DPRINTF("error writing sector %d\n",
1670 fd_sector(cur_drv));
1671 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1672 goto transfer_error;
1673 }
1674 break;
1675 case FD_DIR_VERIFY:
1676 /* VERIFY commands */
1677 break;
1678 default:
1679 /* SCAN commands */
1680 {
1681 uint8_t tmpbuf[FD_SECTOR_LEN];
1682 int ret;
1683 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1684 len);
1685 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1686 if (ret == 0) {
1687 status2 = FD_SR2_SEH;
1688 goto end_transfer;
1689 }
1690 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1691 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1692 status2 = 0x00;
1693 goto end_transfer;
1694 }
1695 }
1696 break;
1697 }
1698 fdctrl->data_pos += len;
1699 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1700 if (rel_pos == 0) {
1701 /* Seek to next sector */
1702 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1703 break;
1704 }
1705 }
1706 end_transfer:
1707 len = fdctrl->data_pos - start_pos;
1708 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1709 fdctrl->data_pos, len, fdctrl->data_len);
1710 if (fdctrl->data_dir == FD_DIR_SCANE ||
1711 fdctrl->data_dir == FD_DIR_SCANL ||
1712 fdctrl->data_dir == FD_DIR_SCANH)
1713 status2 = FD_SR2_SEH;
1714 fdctrl->data_len -= len;
1715 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1716 transfer_error:
1717
1718 return len;
1719 }
1720
1721 /* Data register : 0x05 */
1722 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1723 {
1724 FDrive *cur_drv;
1725 uint32_t retval = 0;
1726 uint32_t pos;
1727
1728 cur_drv = get_cur_drv(fdctrl);
1729 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1730 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1731 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1732 return 0;
1733 }
1734
1735 /* If data_len spans multiple sectors, the current position in the FIFO
1736 * wraps around while fdctrl->data_pos is the real position in the whole
1737 * request. */
1738 pos = fdctrl->data_pos;
1739 pos %= FD_SECTOR_LEN;
1740
1741 switch (fdctrl->phase) {
1742 case FD_PHASE_EXECUTION:
1743 assert(fdctrl->msr & FD_MSR_NONDMA);
1744 if (pos == 0) {
1745 if (fdctrl->data_pos != 0)
1746 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1747 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1748 fd_sector(cur_drv));
1749 return 0;
1750 }
1751 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1752 BDRV_SECTOR_SIZE)
1753 < 0) {
1754 FLOPPY_DPRINTF("error getting sector %d\n",
1755 fd_sector(cur_drv));
1756 /* Sure, image size is too small... */
1757 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1758 }
1759 }
1760
1761 if (++fdctrl->data_pos == fdctrl->data_len) {
1762 fdctrl->msr &= ~FD_MSR_RQM;
1763 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1764 }
1765 break;
1766
1767 case FD_PHASE_RESULT:
1768 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1769 if (++fdctrl->data_pos == fdctrl->data_len) {
1770 fdctrl->msr &= ~FD_MSR_RQM;
1771 fdctrl_to_command_phase(fdctrl);
1772 fdctrl_reset_irq(fdctrl);
1773 }
1774 break;
1775
1776 case FD_PHASE_COMMAND:
1777 default:
1778 abort();
1779 }
1780
1781 retval = fdctrl->fifo[pos];
1782 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1783
1784 return retval;
1785 }
1786
1787 static void fdctrl_format_sector(FDCtrl *fdctrl)
1788 {
1789 FDrive *cur_drv;
1790 uint8_t kh, kt, ks;
1791
1792 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1793 cur_drv = get_cur_drv(fdctrl);
1794 kt = fdctrl->fifo[6];
1795 kh = fdctrl->fifo[7];
1796 ks = fdctrl->fifo[8];
1797 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1798 GET_CUR_DRV(fdctrl), kh, kt, ks,
1799 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1800 NUM_SIDES(cur_drv)));
1801 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1802 case 2:
1803 /* sect too big */
1804 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1805 fdctrl->fifo[3] = kt;
1806 fdctrl->fifo[4] = kh;
1807 fdctrl->fifo[5] = ks;
1808 return;
1809 case 3:
1810 /* track too big */
1811 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1812 fdctrl->fifo[3] = kt;
1813 fdctrl->fifo[4] = kh;
1814 fdctrl->fifo[5] = ks;
1815 return;
1816 case 4:
1817 /* No seek enabled */
1818 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1819 fdctrl->fifo[3] = kt;
1820 fdctrl->fifo[4] = kh;
1821 fdctrl->fifo[5] = ks;
1822 return;
1823 case 1:
1824 fdctrl->status0 |= FD_SR0_SEEK;
1825 break;
1826 default:
1827 break;
1828 }
1829 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1830 if (cur_drv->blk == NULL ||
1831 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1832 BDRV_SECTOR_SIZE, 0) < 0) {
1833 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1834 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1835 } else {
1836 if (cur_drv->sect == cur_drv->last_sect) {
1837 fdctrl->data_state &= ~FD_STATE_FORMAT;
1838 /* Last sector done */
1839 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1840 } else {
1841 /* More to do */
1842 fdctrl->data_pos = 0;
1843 fdctrl->data_len = 4;
1844 }
1845 }
1846 }
1847
1848 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1849 {
1850 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1851 fdctrl->fifo[0] = fdctrl->lock << 4;
1852 fdctrl_to_result_phase(fdctrl, 1);
1853 }
1854
1855 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1856 {
1857 FDrive *cur_drv = get_cur_drv(fdctrl);
1858
1859 /* Drives position */
1860 fdctrl->fifo[0] = drv0(fdctrl)->track;
1861 fdctrl->fifo[1] = drv1(fdctrl)->track;
1862 #if MAX_FD == 4
1863 fdctrl->fifo[2] = drv2(fdctrl)->track;
1864 fdctrl->fifo[3] = drv3(fdctrl)->track;
1865 #else
1866 fdctrl->fifo[2] = 0;
1867 fdctrl->fifo[3] = 0;
1868 #endif
1869 /* timers */
1870 fdctrl->fifo[4] = fdctrl->timer0;
1871 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1872 fdctrl->fifo[6] = cur_drv->last_sect;
1873 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1874 (cur_drv->perpendicular << 2);
1875 fdctrl->fifo[8] = fdctrl->config;
1876 fdctrl->fifo[9] = fdctrl->precomp_trk;
1877 fdctrl_to_result_phase(fdctrl, 10);
1878 }
1879
1880 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1881 {
1882 /* Controller's version */
1883 fdctrl->fifo[0] = fdctrl->version;
1884 fdctrl_to_result_phase(fdctrl, 1);
1885 }
1886
1887 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1888 {
1889 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1890 fdctrl_to_result_phase(fdctrl, 1);
1891 }
1892
1893 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1894 {
1895 FDrive *cur_drv = get_cur_drv(fdctrl);
1896
1897 /* Drives position */
1898 drv0(fdctrl)->track = fdctrl->fifo[3];
1899 drv1(fdctrl)->track = fdctrl->fifo[4];
1900 #if MAX_FD == 4
1901 drv2(fdctrl)->track = fdctrl->fifo[5];
1902 drv3(fdctrl)->track = fdctrl->fifo[6];
1903 #endif
1904 /* timers */
1905 fdctrl->timer0 = fdctrl->fifo[7];
1906 fdctrl->timer1 = fdctrl->fifo[8];
1907 cur_drv->last_sect = fdctrl->fifo[9];
1908 fdctrl->lock = fdctrl->fifo[10] >> 7;
1909 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1910 fdctrl->config = fdctrl->fifo[11];
1911 fdctrl->precomp_trk = fdctrl->fifo[12];
1912 fdctrl->pwrd = fdctrl->fifo[13];
1913 fdctrl_to_command_phase(fdctrl);
1914 }
1915
1916 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1917 {
1918 FDrive *cur_drv = get_cur_drv(fdctrl);
1919
1920 fdctrl->fifo[0] = 0;
1921 fdctrl->fifo[1] = 0;
1922 /* Drives position */
1923 fdctrl->fifo[2] = drv0(fdctrl)->track;
1924 fdctrl->fifo[3] = drv1(fdctrl)->track;
1925 #if MAX_FD == 4
1926 fdctrl->fifo[4] = drv2(fdctrl)->track;
1927 fdctrl->fifo[5] = drv3(fdctrl)->track;
1928 #else
1929 fdctrl->fifo[4] = 0;
1930 fdctrl->fifo[5] = 0;
1931 #endif
1932 /* timers */
1933 fdctrl->fifo[6] = fdctrl->timer0;
1934 fdctrl->fifo[7] = fdctrl->timer1;
1935 fdctrl->fifo[8] = cur_drv->last_sect;
1936 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1937 (cur_drv->perpendicular << 2);
1938 fdctrl->fifo[10] = fdctrl->config;
1939 fdctrl->fifo[11] = fdctrl->precomp_trk;
1940 fdctrl->fifo[12] = fdctrl->pwrd;
1941 fdctrl->fifo[13] = 0;
1942 fdctrl->fifo[14] = 0;
1943 fdctrl_to_result_phase(fdctrl, 15);
1944 }
1945
1946 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1947 {
1948 FDrive *cur_drv = get_cur_drv(fdctrl);
1949
1950 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1951 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1952 (NANOSECONDS_PER_SECOND / 50));
1953 }
1954
1955 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1956 {
1957 FDrive *cur_drv;
1958
1959 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1960 cur_drv = get_cur_drv(fdctrl);
1961 fdctrl->data_state |= FD_STATE_FORMAT;
1962 if (fdctrl->fifo[0] & 0x80)
1963 fdctrl->data_state |= FD_STATE_MULTI;
1964 else
1965 fdctrl->data_state &= ~FD_STATE_MULTI;
1966 cur_drv->bps =
1967 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1968 #if 0
1969 cur_drv->last_sect =
1970 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1971 fdctrl->fifo[3] / 2;
1972 #else
1973 cur_drv->last_sect = fdctrl->fifo[3];
1974 #endif
1975 /* TODO: implement format using DMA expected by the Bochs BIOS
1976 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1977 * the sector with the specified fill byte
1978 */
1979 fdctrl->data_state &= ~FD_STATE_FORMAT;
1980 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1981 }
1982
1983 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1984 {
1985 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1986 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1987 if (fdctrl->fifo[2] & 1)
1988 fdctrl->dor &= ~FD_DOR_DMAEN;
1989 else
1990 fdctrl->dor |= FD_DOR_DMAEN;
1991 /* No result back */
1992 fdctrl_to_command_phase(fdctrl);
1993 }
1994
1995 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1996 {
1997 FDrive *cur_drv;
1998
1999 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2000 cur_drv = get_cur_drv(fdctrl);
2001 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2002 /* 1 Byte status back */
2003 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2004 (cur_drv->track == 0 ? 0x10 : 0x00) |
2005 (cur_drv->head << 2) |
2006 GET_CUR_DRV(fdctrl) |
2007 0x28;
2008 fdctrl_to_result_phase(fdctrl, 1);
2009 }
2010
2011 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
2012 {
2013 FDrive *cur_drv;
2014
2015 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2016 cur_drv = get_cur_drv(fdctrl);
2017 fd_recalibrate(cur_drv);
2018 fdctrl_to_command_phase(fdctrl);
2019 /* Raise Interrupt */
2020 fdctrl->status0 |= FD_SR0_SEEK;
2021 fdctrl_raise_irq(fdctrl);
2022 }
2023
2024 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
2025 {
2026 FDrive *cur_drv = get_cur_drv(fdctrl);
2027
2028 if (fdctrl->reset_sensei > 0) {
2029 fdctrl->fifo[0] =
2030 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2031 fdctrl->reset_sensei--;
2032 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2033 fdctrl->fifo[0] = FD_SR0_INVCMD;
2034 fdctrl_to_result_phase(fdctrl, 1);
2035 return;
2036 } else {
2037 fdctrl->fifo[0] =
2038 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2039 | GET_CUR_DRV(fdctrl);
2040 }
2041
2042 fdctrl->fifo[1] = cur_drv->track;
2043 fdctrl_to_result_phase(fdctrl, 2);
2044 fdctrl_reset_irq(fdctrl);
2045 fdctrl->status0 = FD_SR0_RDYCHG;
2046 }
2047
2048 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
2049 {
2050 FDrive *cur_drv;
2051
2052 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2053 cur_drv = get_cur_drv(fdctrl);
2054 fdctrl_to_command_phase(fdctrl);
2055 /* The seek command just sends step pulses to the drive and doesn't care if
2056 * there is a medium inserted of if it's banging the head against the drive.
2057 */
2058 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
2059 /* Raise Interrupt */
2060 fdctrl->status0 |= FD_SR0_SEEK;
2061 fdctrl_raise_irq(fdctrl);
2062 }
2063
2064 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
2065 {
2066 FDrive *cur_drv = get_cur_drv(fdctrl);
2067
2068 if (fdctrl->fifo[1] & 0x80)
2069 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2070 /* No result back */
2071 fdctrl_to_command_phase(fdctrl);
2072 }
2073
2074 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
2075 {
2076 fdctrl->config = fdctrl->fifo[2];
2077 fdctrl->precomp_trk = fdctrl->fifo[3];
2078 /* No result back */
2079 fdctrl_to_command_phase(fdctrl);
2080 }
2081
2082 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
2083 {
2084 fdctrl->pwrd = fdctrl->fifo[1];
2085 fdctrl->fifo[0] = fdctrl->fifo[1];
2086 fdctrl_to_result_phase(fdctrl, 1);
2087 }
2088
2089 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
2090 {
2091 /* No result back */
2092 fdctrl_to_command_phase(fdctrl);
2093 }
2094
2095 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
2096 {
2097 FDrive *cur_drv = get_cur_drv(fdctrl);
2098 uint32_t pos;
2099
2100 pos = fdctrl->data_pos - 1;
2101 pos %= FD_SECTOR_LEN;
2102 if (fdctrl->fifo[pos] & 0x80) {
2103 /* Command parameters done */
2104 if (fdctrl->fifo[pos] & 0x40) {
2105 fdctrl->fifo[0] = fdctrl->fifo[1];
2106 fdctrl->fifo[2] = 0;
2107 fdctrl->fifo[3] = 0;
2108 fdctrl_to_result_phase(fdctrl, 4);
2109 } else {
2110 fdctrl_to_command_phase(fdctrl);
2111 }
2112 } else if (fdctrl->data_len > 7) {
2113 /* ERROR */
2114 fdctrl->fifo[0] = 0x80 |
2115 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2116 fdctrl_to_result_phase(fdctrl, 1);
2117 }
2118 }
2119
2120 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2121 {
2122 FDrive *cur_drv;
2123
2124 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2125 cur_drv = get_cur_drv(fdctrl);
2126 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2127 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2128 cur_drv->sect, 1);
2129 } else {
2130 fd_seek(cur_drv, cur_drv->head,
2131 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2132 }
2133 fdctrl_to_command_phase(fdctrl);
2134 /* Raise Interrupt */
2135 fdctrl->status0 |= FD_SR0_SEEK;
2136 fdctrl_raise_irq(fdctrl);
2137 }
2138
2139 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2140 {
2141 FDrive *cur_drv;
2142
2143 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2144 cur_drv = get_cur_drv(fdctrl);
2145 if (fdctrl->fifo[2] > cur_drv->track) {
2146 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2147 } else {
2148 fd_seek(cur_drv, cur_drv->head,
2149 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2150 }
2151 fdctrl_to_command_phase(fdctrl);
2152 /* Raise Interrupt */
2153 fdctrl->status0 |= FD_SR0_SEEK;
2154 fdctrl_raise_irq(fdctrl);
2155 }
2156
2157 /*
2158 * Handlers for the execution phase of each command
2159 */
2160 typedef struct FDCtrlCommand {
2161 uint8_t value;
2162 uint8_t mask;
2163 const char* name;
2164 int parameters;
2165 void (*handler)(FDCtrl *fdctrl, int direction);
2166 int direction;
2167 } FDCtrlCommand;
2168
2169 static const FDCtrlCommand handlers[] = {
2170 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2171 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2172 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2173 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2174 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2175 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2176 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2177 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2178 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2179 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2180 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2181 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2182 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2183 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2184 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2185 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2186 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2187 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2188 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2189 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2190 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2191 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2192 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2193 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2194 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2195 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2196 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2197 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2198 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2199 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2200 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2201 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2202 };
2203 /* Associate command to an index in the 'handlers' array */
2204 static uint8_t command_to_handler[256];
2205
2206 static const FDCtrlCommand *get_command(uint8_t cmd)
2207 {
2208 int idx;
2209
2210 idx = command_to_handler[cmd];
2211 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2212 return &handlers[idx];
2213 }
2214
2215 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2216 {
2217 FDrive *cur_drv;
2218 const FDCtrlCommand *cmd;
2219 uint32_t pos;
2220
2221 /* Reset mode */
2222 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2223 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2224 return;
2225 }
2226 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2227 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2228 return;
2229 }
2230 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2231
2232 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2233
2234 /* If data_len spans multiple sectors, the current position in the FIFO
2235 * wraps around while fdctrl->data_pos is the real position in the whole
2236 * request. */
2237 pos = fdctrl->data_pos++;
2238 pos %= FD_SECTOR_LEN;
2239 fdctrl->fifo[pos] = value;
2240
2241 if (fdctrl->data_pos == fdctrl->data_len) {
2242 fdctrl->msr &= ~FD_MSR_RQM;
2243 }
2244
2245 switch (fdctrl->phase) {
2246 case FD_PHASE_EXECUTION:
2247 /* For DMA requests, RQM should be cleared during execution phase, so
2248 * we would have errored out above. */
2249 assert(fdctrl->msr & FD_MSR_NONDMA);
2250
2251 /* FIFO data write */
2252 if (pos == FD_SECTOR_LEN - 1 ||
2253 fdctrl->data_pos == fdctrl->data_len) {
2254 cur_drv = get_cur_drv(fdctrl);
2255 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2256 BDRV_SECTOR_SIZE, 0) < 0) {
2257 FLOPPY_DPRINTF("error writing sector %d\n",
2258 fd_sector(cur_drv));
2259 break;
2260 }
2261 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2262 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2263 fd_sector(cur_drv));
2264 break;
2265 }
2266 }
2267
2268 /* Switch to result phase when done with the transfer */
2269 if (fdctrl->data_pos == fdctrl->data_len) {
2270 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2271 }
2272 break;
2273
2274 case FD_PHASE_COMMAND:
2275 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2276 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2277
2278 if (pos == 0) {
2279 /* The first byte specifies the command. Now we start reading
2280 * as many parameters as this command requires. */
2281 cmd = get_command(value);
2282 fdctrl->data_len = cmd->parameters + 1;
2283 if (cmd->parameters) {
2284 fdctrl->msr |= FD_MSR_RQM;
2285 }
2286 fdctrl->msr |= FD_MSR_CMDBUSY;
2287 }
2288
2289 if (fdctrl->data_pos == fdctrl->data_len) {
2290 /* We have all parameters now, execute the command */
2291 fdctrl->phase = FD_PHASE_EXECUTION;
2292
2293 if (fdctrl->data_state & FD_STATE_FORMAT) {
2294 fdctrl_format_sector(fdctrl);
2295 break;
2296 }
2297
2298 cmd = get_command(fdctrl->fifo[0]);
2299 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2300 cmd->handler(fdctrl, cmd->direction);
2301 }
2302 break;
2303
2304 case FD_PHASE_RESULT:
2305 default:
2306 abort();
2307 }
2308 }
2309
2310 static void fdctrl_result_timer(void *opaque)
2311 {
2312 FDCtrl *fdctrl = opaque;
2313 FDrive *cur_drv = get_cur_drv(fdctrl);
2314
2315 /* Pretend we are spinning.
2316 * This is needed for Coherent, which uses READ ID to check for
2317 * sector interleaving.
2318 */
2319 if (cur_drv->last_sect != 0) {
2320 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2321 }
2322 /* READ_ID can't automatically succeed! */
2323 if (fdctrl->check_media_rate &&
2324 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2325 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2326 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2327 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2328 } else {
2329 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2330 }
2331 }
2332
2333 static void fdctrl_change_cb(void *opaque, bool load)
2334 {
2335 FDrive *drive = opaque;
2336
2337 drive->media_changed = 1;
2338 drive->media_validated = false;
2339 fd_revalidate(drive);
2340 }
2341
2342 static const BlockDevOps fdctrl_block_ops = {
2343 .change_media_cb = fdctrl_change_cb,
2344 };
2345
2346 /* Init functions */
2347 static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
2348 {
2349 unsigned int i;
2350 FDrive *drive;
2351
2352 for (i = 0; i < MAX_FD; i++) {
2353 drive = &fdctrl->drives[i];
2354 drive->fdctrl = fdctrl;
2355
2356 if (drive->blk) {
2357 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
2358 error_setg(errp, "fdc doesn't support drive option werror");
2359 return;
2360 }
2361 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
2362 error_setg(errp, "fdc doesn't support drive option rerror");
2363 return;
2364 }
2365 }
2366
2367 fd_init(drive);
2368 if (drive->blk) {
2369 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
2370 pick_drive_type(drive);
2371 }
2372 fd_revalidate(drive);
2373 }
2374 }
2375
2376 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2377 {
2378 DeviceState *dev;
2379 ISADevice *isadev;
2380
2381 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2382 if (!isadev) {
2383 return NULL;
2384 }
2385 dev = DEVICE(isadev);
2386
2387 if (fds[0]) {
2388 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2389 &error_fatal);
2390 }
2391 if (fds[1]) {
2392 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2393 &error_fatal);
2394 }
2395 qdev_init_nofail(dev);
2396
2397 return isadev;
2398 }
2399
2400 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2401 hwaddr mmio_base, DriveInfo **fds)
2402 {
2403 FDCtrl *fdctrl;
2404 DeviceState *dev;
2405 SysBusDevice *sbd;
2406 FDCtrlSysBus *sys;
2407
2408 dev = qdev_create(NULL, "sysbus-fdc");
2409 sys = SYSBUS_FDC(dev);
2410 fdctrl = &sys->state;
2411 fdctrl->dma_chann = dma_chann; /* FIXME */
2412 if (fds[0]) {
2413 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2414 &error_fatal);
2415 }
2416 if (fds[1]) {
2417 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2418 &error_fatal);
2419 }
2420 qdev_init_nofail(dev);
2421 sbd = SYS_BUS_DEVICE(dev);
2422 sysbus_connect_irq(sbd, 0, irq);
2423 sysbus_mmio_map(sbd, 0, mmio_base);
2424 }
2425
2426 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2427 DriveInfo **fds, qemu_irq *fdc_tc)
2428 {
2429 DeviceState *dev;
2430 FDCtrlSysBus *sys;
2431
2432 dev = qdev_create(NULL, "SUNW,fdtwo");
2433 if (fds[0]) {
2434 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2435 &error_fatal);
2436 }
2437 qdev_init_nofail(dev);
2438 sys = SYSBUS_FDC(dev);
2439 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2440 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2441 *fdc_tc = qdev_get_gpio_in(dev, 0);
2442 }
2443
2444 static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
2445 {
2446 int i, j;
2447 static int command_tables_inited = 0;
2448
2449 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2450 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2451 }
2452
2453 /* Fill 'command_to_handler' lookup table */
2454 if (!command_tables_inited) {
2455 command_tables_inited = 1;
2456 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2457 for (j = 0; j < sizeof(command_to_handler); j++) {
2458 if ((j & handlers[i].mask) == handlers[i].value) {
2459 command_to_handler[j] = i;
2460 }
2461 }
2462 }
2463 }
2464
2465 FLOPPY_DPRINTF("init controller\n");
2466 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2467 fdctrl->fifo_size = 512;
2468 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2469 fdctrl_result_timer, fdctrl);
2470
2471 fdctrl->version = 0x90; /* Intel 82078 controller */
2472 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2473 fdctrl->num_floppies = MAX_FD;
2474
2475 if (fdctrl->dma_chann != -1) {
2476 IsaDmaClass *k;
2477 assert(fdctrl->dma);
2478 k = ISADMA_GET_CLASS(fdctrl->dma);
2479 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2480 &fdctrl_transfer_handler, fdctrl);
2481 }
2482 fdctrl_connect_drives(fdctrl, errp);
2483 }
2484
2485 static const MemoryRegionPortio fdc_portio_list[] = {
2486 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2487 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2488 PORTIO_END_OF_LIST(),
2489 };
2490
2491 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2492 {
2493 ISADevice *isadev = ISA_DEVICE(dev);
2494 FDCtrlISABus *isa = ISA_FDC(dev);
2495 FDCtrl *fdctrl = &isa->state;
2496 Error *err = NULL;
2497
2498 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2499 "fdc");
2500
2501 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2502 fdctrl->dma_chann = isa->dma;
2503 if (fdctrl->dma_chann != -1) {
2504 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2505 assert(fdctrl->dma);
2506 }
2507
2508 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2509 fdctrl_realize_common(fdctrl, &err);
2510 if (err != NULL) {
2511 error_propagate(errp, err);
2512 return;
2513 }
2514 }
2515
2516 static void sysbus_fdc_initfn(Object *obj)
2517 {
2518 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2519 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2520 FDCtrl *fdctrl = &sys->state;
2521
2522 fdctrl->dma_chann = -1;
2523
2524 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2525 "fdc", 0x08);
2526 sysbus_init_mmio(sbd, &fdctrl->iomem);
2527 }
2528
2529 static void sun4m_fdc_initfn(Object *obj)
2530 {
2531 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2532 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2533 FDCtrl *fdctrl = &sys->state;
2534
2535 fdctrl->dma_chann = -1;
2536
2537 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2538 fdctrl, "fdctrl", 0x08);
2539 sysbus_init_mmio(sbd, &fdctrl->iomem);
2540 }
2541
2542 static void sysbus_fdc_common_initfn(Object *obj)
2543 {
2544 DeviceState *dev = DEVICE(obj);
2545 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2546 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2547 FDCtrl *fdctrl = &sys->state;
2548
2549 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2550
2551 sysbus_init_irq(sbd, &fdctrl->irq);
2552 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2553 }
2554
2555 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2556 {
2557 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2558 FDCtrl *fdctrl = &sys->state;
2559
2560 fdctrl_realize_common(fdctrl, errp);
2561 }
2562
2563 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2564 {
2565 FDCtrlISABus *isa = ISA_FDC(fdc);
2566
2567 return isa->state.drives[i].drive;
2568 }
2569
2570 void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2571 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2572 {
2573 const FDFormat *fdf;
2574
2575 *maxc = *maxh = *maxs = 0;
2576 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2577 if (fdf->drive != type) {
2578 continue;
2579 }
2580 if (*maxc < fdf->max_track) {
2581 *maxc = fdf->max_track;
2582 }
2583 if (*maxh < fdf->max_head) {
2584 *maxh = fdf->max_head;
2585 }
2586 if (*maxs < fdf->last_sect) {
2587 *maxs = fdf->last_sect;
2588 }
2589 }
2590 (*maxc)--;
2591 }
2592
2593 static const VMStateDescription vmstate_isa_fdc ={
2594 .name = "fdc",
2595 .version_id = 2,
2596 .minimum_version_id = 2,
2597 .fields = (VMStateField[]) {
2598 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2599 VMSTATE_END_OF_LIST()
2600 }
2601 };
2602
2603 static Property isa_fdc_properties[] = {
2604 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2605 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2606 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2607 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2608 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
2609 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2610 0, true),
2611 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2612 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2613 FloppyDriveType),
2614 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2615 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2616 FloppyDriveType),
2617 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2618 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
2619 FloppyDriveType),
2620 DEFINE_PROP_END_OF_LIST(),
2621 };
2622
2623 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2624 {
2625 DeviceClass *dc = DEVICE_CLASS(klass);
2626
2627 dc->realize = isabus_fdc_realize;
2628 dc->fw_name = "fdc";
2629 dc->reset = fdctrl_external_reset_isa;
2630 dc->vmsd = &vmstate_isa_fdc;
2631 dc->props = isa_fdc_properties;
2632 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2633 }
2634
2635 static void isabus_fdc_instance_init(Object *obj)
2636 {
2637 FDCtrlISABus *isa = ISA_FDC(obj);
2638
2639 device_add_bootindex_property(obj, &isa->bootindexA,
2640 "bootindexA", "/floppy@0",
2641 DEVICE(obj), NULL);
2642 device_add_bootindex_property(obj, &isa->bootindexB,
2643 "bootindexB", "/floppy@1",
2644 DEVICE(obj), NULL);
2645 }
2646
2647 static const TypeInfo isa_fdc_info = {
2648 .name = TYPE_ISA_FDC,
2649 .parent = TYPE_ISA_DEVICE,
2650 .instance_size = sizeof(FDCtrlISABus),
2651 .class_init = isabus_fdc_class_init,
2652 .instance_init = isabus_fdc_instance_init,
2653 };
2654
2655 static const VMStateDescription vmstate_sysbus_fdc ={
2656 .name = "fdc",
2657 .version_id = 2,
2658 .minimum_version_id = 2,
2659 .fields = (VMStateField[]) {
2660 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2661 VMSTATE_END_OF_LIST()
2662 }
2663 };
2664
2665 static Property sysbus_fdc_properties[] = {
2666 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2667 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
2668 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2669 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2670 FloppyDriveType),
2671 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2672 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2673 FloppyDriveType),
2674 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2675 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2676 FloppyDriveType),
2677 DEFINE_PROP_END_OF_LIST(),
2678 };
2679
2680 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2681 {
2682 DeviceClass *dc = DEVICE_CLASS(klass);
2683
2684 dc->props = sysbus_fdc_properties;
2685 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2686 }
2687
2688 static const TypeInfo sysbus_fdc_info = {
2689 .name = "sysbus-fdc",
2690 .parent = TYPE_SYSBUS_FDC,
2691 .instance_init = sysbus_fdc_initfn,
2692 .class_init = sysbus_fdc_class_init,
2693 };
2694
2695 static Property sun4m_fdc_properties[] = {
2696 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
2697 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2698 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2699 FloppyDriveType),
2700 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2701 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2702 FloppyDriveType),
2703 DEFINE_PROP_END_OF_LIST(),
2704 };
2705
2706 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2707 {
2708 DeviceClass *dc = DEVICE_CLASS(klass);
2709
2710 dc->props = sun4m_fdc_properties;
2711 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2712 }
2713
2714 static const TypeInfo sun4m_fdc_info = {
2715 .name = "SUNW,fdtwo",
2716 .parent = TYPE_SYSBUS_FDC,
2717 .instance_init = sun4m_fdc_initfn,
2718 .class_init = sun4m_fdc_class_init,
2719 };
2720
2721 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2722 {
2723 DeviceClass *dc = DEVICE_CLASS(klass);
2724
2725 dc->realize = sysbus_fdc_common_realize;
2726 dc->reset = fdctrl_external_reset_sysbus;
2727 dc->vmsd = &vmstate_sysbus_fdc;
2728 }
2729
2730 static const TypeInfo sysbus_fdc_type_info = {
2731 .name = TYPE_SYSBUS_FDC,
2732 .parent = TYPE_SYS_BUS_DEVICE,
2733 .instance_size = sizeof(FDCtrlSysBus),
2734 .instance_init = sysbus_fdc_common_initfn,
2735 .abstract = true,
2736 .class_init = sysbus_fdc_common_class_init,
2737 };
2738
2739 static void fdc_register_types(void)
2740 {
2741 type_register_static(&isa_fdc_info);
2742 type_register_static(&sysbus_fdc_type_info);
2743 type_register_static(&sysbus_fdc_info);
2744 type_register_static(&sun4m_fdc_info);
2745 }
2746
2747 type_init(fdc_register_types)
QEmu