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eepro100: Prettify code (no functional changes)
[qemu.git] / hw / eepro100.c
blobcf4e0ac2451bebc85440e684aa3a6a77e4336a2e
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include <stdbool.h>
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 /* Common declarations for all PCI devices. */
52
53 #define PCI_CONFIG_8(offset, value) \
54 (pci_conf[offset] = (value))
55 #define PCI_CONFIG_16(offset, value) \
56 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
57 #define PCI_CONFIG_32(offset, value) \
58 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RU_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 /* Offsets to the various registers.
130 All accesses need not be longword aligned. */
131 enum speedo_offsets {
132 SCBStatus = 0, /* Status Word. */
133 SCBAck = 1,
134 SCBCmd = 2, /* Rx/Command Unit command and status. */
135 SCBIntmask = 3,
136 SCBPointer = 4, /* General purpose pointer. */
137 SCBPort = 8, /* Misc. commands and operands. */
138 SCBflash = 12, /* Flash memory control. */
139 SCBeeprom = 14, /* EEPROM control. */
140 SCBCtrlMDI = 16, /* MDI interface control. */
141 SCBEarlyRx = 20, /* Early receive byte count. */
142 SCBFlow = 24, /* Flow Control. */
143 SCBpmdr = 27, /* Power Management Driver. */
144 SCBgctrl = 28, /* General Control. */
145 SCBgstat = 29, /* General Status. */
146 };
147
148 /* A speedo3 transmit buffer descriptor with two buffers... */
149 typedef struct {
150 uint16_t status;
151 uint16_t command;
152 uint32_t link; /* void * */
153 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
154 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
155 uint8_t tx_threshold; /* transmit threshold */
156 uint8_t tbd_count; /* TBD number */
157 //~ /* This constitutes two "TBD" entries: hdr and data */
158 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
159 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
160 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
161 //~ int32_t tx_buf_size1; /* Length of Tx data. */
162 } eepro100_tx_t;
163
164 /* Receive frame descriptor. */
165 typedef struct {
166 int16_t status;
167 uint16_t command;
168 uint32_t link; /* struct RxFD * */
169 uint32_t rx_buf_addr; /* void * */
170 uint16_t count;
171 uint16_t size;
172 char packet[MAX_ETH_FRAME_SIZE + 4];
173 } eepro100_rx_t;
174
175 typedef enum {
176 COMMAND_EL = BIT(15),
177 COMMAND_S = BIT(14),
178 COMMAND_I = BIT(13),
179 COMMAND_NC = BIT(4),
180 COMMAND_SF = BIT(3),
181 COMMAND_CMD = BITS(2, 0),
182 } scb_command_bit;
183
184 typedef enum {
185 STATUS_C = BIT(15),
186 STATUS_OK = BIT(13),
187 } scb_status_bit;
188
189 typedef struct {
190 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
191 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
192 tx_multiple_collisions, tx_total_collisions;
193 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
194 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
195 rx_short_frame_errors;
196 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
197 uint16_t xmt_tco_frames, rcv_tco_frames;
198 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
199 uint32_t reserved[4];
200 } eepro100_stats_t;
201
202 typedef enum {
203 cu_idle = 0,
204 cu_suspended = 1,
205 cu_active = 2,
206 cu_lpq_active = 2,
207 cu_hqp_active = 3
208 } cu_state_t;
209
210 typedef enum {
211 ru_idle = 0,
212 ru_suspended = 1,
213 ru_no_resources = 2,
214 ru_ready = 4
215 } ru_state_t;
216
217 typedef struct {
218 PCIDevice dev;
219 uint8_t mult[8]; /* multicast mask array */
220 int mmio_index;
221 NICState *nic;
222 NICConf conf;
223 uint8_t scb_stat; /* SCB stat/ack byte */
224 uint8_t int_stat; /* PCI interrupt status */
225 /* region must not be saved by nic_save. */
226 uint32_t region[3]; /* PCI region addresses */
227 uint16_t mdimem[32];
228 eeprom_t *eeprom;
229 uint32_t device; /* device variant */
230 uint32_t pointer;
231 /* (cu_base + cu_offset) address the next command block in the command block list. */
232 uint32_t cu_base; /* CU base address */
233 uint32_t cu_offset; /* CU address offset */
234 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
235 uint32_t ru_base; /* RU base address */
236 uint32_t ru_offset; /* RU address offset */
237 uint32_t statsaddr; /* pointer to eepro100_stats_t */
238
239 /* Temporary status information (no need to save these values),
240 * used while processing CU commands. */
241 eepro100_tx_t tx; /* transmit buffer descriptor */
242 uint32_t cb_address; /* = cu_base + cu_offset */
243
244 /* Statistical counters. Also used for wake-up packet (i82559). */
245 eepro100_stats_t statistics;
246
247 #if 0
248 uint16_t status;
249 #endif
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Bit values for EEPROM ID word. */
276 typedef enum {
277 EEPROM_ID_MDM = BIT(0), /* Modem */
278 EEPROM_ID_STB = BIT(1), /* Standby Enable */
279 EEPROM_ID_WMR = BIT(2), /* ??? */
280 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
281 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
282 EEPROM_ID_ALT = BIT(7), /* */
283 /* BITS(10, 8) device revision */
284 EEPROM_ID_BD = BIT(11), /* boot disable */
285 EEPROM_ID_ID = BIT(13), /* id bit */
286 /* BITS(15, 14) signature */
287 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
288 } eeprom_id_bit;
289
290 /* Default values for MDI (PHY) registers */
291 static const uint16_t eepro100_mdi_default[] = {
292 /* MDI Registers 0 - 6, 7 */
293 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294 /* MDI Registers 8 - 15 */
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 /* MDI Registers 16 - 31 */
297 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 };
300
301 /* Readonly mask for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_mask[] = {
303 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
306 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 };
308
309 /* XXX: optimize */
310 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
311 {
312 val = cpu_to_le32(val);
313 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
314 }
315
316 #define POLYNOMIAL 0x04c11db6
317
318 /* From FreeBSD */
319 /* XXX: optimize */
320 static unsigned compute_mcast_idx(const uint8_t * ep)
321 {
322 uint32_t crc;
323 int carry, i, j;
324 uint8_t b;
325
326 crc = 0xffffffff;
327 for (i = 0; i < 6; i++) {
328 b = *ep++;
329 for (j = 0; j < 8; j++) {
330 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
331 crc <<= 1;
332 b >>= 1;
333 if (carry) {
334 crc = ((crc ^ POLYNOMIAL) | carry);
335 }
336 }
337 }
338 return (crc & BITS(7, 2)) >> 2;
339 }
340
341 #if defined(DEBUG_EEPRO100)
342 static const char *nic_dump(const uint8_t * buf, unsigned size)
343 {
344 static char dump[3 * 16 + 1];
345 char *p = &dump[0];
346 if (size > 16) {
347 size = 16;
348 }
349 while (size-- > 0) {
350 p += sprintf(p, " %02x", *buf++);
351 }
352 return dump;
353 }
354 #endif /* DEBUG_EEPRO100 */
355
356 enum scb_stat_ack {
357 stat_ack_not_ours = 0x00,
358 stat_ack_sw_gen = 0x04,
359 stat_ack_rnr = 0x10,
360 stat_ack_cu_idle = 0x20,
361 stat_ack_frame_rx = 0x40,
362 stat_ack_cu_cmd_done = 0x80,
363 stat_ack_not_present = 0xFF,
364 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
366 };
367
368 static void disable_interrupt(EEPRO100State * s)
369 {
370 if (s->int_stat) {
371 TRACE(INT, logout("interrupt disabled\n"));
372 qemu_irq_lower(s->dev.irq[0]);
373 s->int_stat = 0;
374 }
375 }
376
377 static void enable_interrupt(EEPRO100State * s)
378 {
379 if (!s->int_stat) {
380 TRACE(INT, logout("interrupt enabled\n"));
381 qemu_irq_raise(s->dev.irq[0]);
382 s->int_stat = 1;
383 }
384 }
385
386 static void eepro100_acknowledge(EEPRO100State * s)
387 {
388 s->scb_stat &= ~s->mem[SCBAck];
389 s->mem[SCBAck] = s->scb_stat;
390 if (s->scb_stat == 0) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
396 {
397 uint8_t mask = ~s->mem[SCBIntmask];
398 s->mem[SCBAck] |= status;
399 status = s->scb_stat = s->mem[SCBAck];
400 status &= (mask | 0x0f);
401 //~ status &= (~s->mem[SCBIntmask] | 0x0xf);
402 if (status && (mask & 0x01)) {
403 /* SCB mask and SCB Bit M do not disable interrupt. */
404 enable_interrupt(s);
405 } else if (s->int_stat) {
406 disable_interrupt(s);
407 }
408 }
409
410 static void eepro100_cx_interrupt(EEPRO100State * s)
411 {
412 /* CU completed action command. */
413 /* Transmit not ok (82557 only, not in emulation). */
414 eepro100_interrupt(s, 0x80);
415 }
416
417 static void eepro100_cna_interrupt(EEPRO100State * s)
418 {
419 /* CU left the active state. */
420 eepro100_interrupt(s, 0x20);
421 }
422
423 static void eepro100_fr_interrupt(EEPRO100State * s)
424 {
425 /* RU received a complete frame. */
426 eepro100_interrupt(s, 0x40);
427 }
428
429 static void eepro100_rnr_interrupt(EEPRO100State * s)
430 {
431 /* RU is not ready. */
432 eepro100_interrupt(s, 0x10);
433 }
434
435 static void eepro100_mdi_interrupt(EEPRO100State * s)
436 {
437 /* MDI completed read or write cycle. */
438 eepro100_interrupt(s, 0x08);
439 }
440
441 static void eepro100_swi_interrupt(EEPRO100State * s)
442 {
443 /* Software has requested an interrupt. */
444 eepro100_interrupt(s, 0x04);
445 }
446
447 #if 0
448 static void eepro100_fcp_interrupt(EEPRO100State * s)
449 {
450 /* Flow control pause interrupt (82558 and later). */
451 eepro100_interrupt(s, 0x01);
452 }
453 #endif
454
455 static void pci_reset(EEPRO100State * s)
456 {
457 uint32_t device = s->device;
458 uint8_t *pci_conf = s->dev.config;
459 bool power_management = 1;
460
461 TRACE(OTHER, logout("%p\n", s));
462
463 /* PCI Vendor ID */
464 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
465 /* PCI Device ID depends on device and is set below. */
466 /* PCI Command */
467 /* TODO: this is the default, do not override. */
468 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
469 /* PCI Status */
470 /* TODO: Value at RST# should be 0. */
471 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
472 /* PCI Revision ID */
473 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
474 /* TODO: this is the default, do not override. */
475 /* PCI Class Code */
476 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
477 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
478 /* PCI Cache Line Size */
479 /* check cache line size!!! */
480 //~ PCI_CONFIG_8(0x0c, 0x00);
481 /* PCI Latency Timer */
482 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
483 /* PCI Header Type */
484 /* BIST (built-in self test) */
485 /* Expansion ROM Base Address (depends on boot disable!!!) */
486 /* TODO: not needed, set when BAR is registered */
487 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
488 /* Capability Pointer */
489 /* TODO: revisions with power_management 1 use this but
490 * do not set new capability list bit in status register. */
491 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
492 /* Interrupt Line */
493 /* Interrupt Pin */
494 /* TODO: RST# value should be 0 */
495 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
496 /* Minimum Grant */
497 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
498 /* Maximum Latency */
499 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
500
501 switch (device) {
502 case i82550:
503 // TODO: check device id.
504 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
505 /* Revision ID: 0x0c, 0x0d, 0x0e. */
506 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
507 // TODO: check size of statistical counters.
508 s->stats_size = 80;
509 // TODO: check extended tcb support.
510 s->has_extended_tcb_support = 1;
511 break;
512 case i82551:
513 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
514 /* Revision ID: 0x0f, 0x10. */
515 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
516 // TODO: check size of statistical counters.
517 s->stats_size = 80;
518 s->has_extended_tcb_support = 1;
519 break;
520 case i82557A:
521 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
522 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
523 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
524 power_management = 0;
525 break;
526 case i82557B:
527 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
528 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
529 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
530 power_management = 0;
531 break;
532 case i82557C:
533 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
534 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
535 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
536 power_management = 0;
537 break;
538 case i82558A:
539 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
540 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
541 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
542 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
543 s->stats_size = 76;
544 s->has_extended_tcb_support = 1;
545 break;
546 case i82558B:
547 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
548 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
549 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
550 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
551 s->stats_size = 76;
552 s->has_extended_tcb_support = 1;
553 break;
554 case i82559A:
555 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
556 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
557 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
558 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
559 s->stats_size = 80;
560 s->has_extended_tcb_support = 1;
561 break;
562 case i82559B:
563 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
564 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
565 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
566 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
567 s->stats_size = 80;
568 s->has_extended_tcb_support = 1;
569 break;
570 case i82559C:
571 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
572 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
573 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
574 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
575 // TODO: Windows wants revision id 0x0c.
576 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
577 #if EEPROM_SIZE > 0
578 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
579 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
580 #endif
581 s->stats_size = 80;
582 s->has_extended_tcb_support = 1;
583 break;
584 case i82559ER:
585 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
586 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
587 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
588 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
589 s->stats_size = 80;
590 s->has_extended_tcb_support = 1;
591 break;
592 case i82562:
593 // TODO: check device id.
594 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
595 /* TODO: wrong revision id. */
596 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
597 s->stats_size = 80;
598 s->has_extended_tcb_support = 1;
599 break;
600 default:
601 logout("Device %X is undefined!\n", device);
602 }
603
604 s->configuration[6] |= BIT(5);
605
606 if (s->stats_size == 80) {
607 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
608 if (s->configuration[6] & BIT(2)) {
609 /* TCO statistical counters. */
610 assert(s->configuration[6] & BIT(5));
611 } else {
612 if (s->configuration[6] & BIT(5)) {
613 /* No extended statistical counters, i82557 compatible. */
614 s->stats_size = 64;
615 } else {
616 /* i82558 compatible. */
617 s->stats_size = 76;
618 }
619 }
620 } else {
621 if (s->configuration[6] & BIT(5)) {
622 /* No extended statistical counters. */
623 s->stats_size = 64;
624 }
625 }
626 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
627
628 if (power_management) {
629 /* Power Management Capabilities */
630 PCI_CONFIG_8(0xdc, 0x01);
631 /* Next Item Pointer */
632 /* Capability ID */
633 PCI_CONFIG_16(0xde, 0x7e21);
634 /* TODO: Power Management Control / Status. */
635 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
636 }
637
638 #if EEPROM_SIZE > 0
639 if (device == i82557C || device == i82558B || device == i82559C) {
640 // TODO: get vendor id from EEPROM for i82557C or later.
641 // TODO: get device id from EEPROM for i82557C or later.
642 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
643 // TODO: header type is determined by EEPROM for i82559.
644 // TODO: get subsystem id from EEPROM for i82557C or later.
645 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
646 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
647 // TODO: capability pointer depends on EEPROM for i82558.
648 logout("Get device id and revision from EEPROM!!!\n");
649 }
650 #endif /* EEPROM_SIZE > 0 */
651 }
652
653 static void nic_selective_reset(EEPRO100State * s)
654 {
655 size_t i;
656 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
657 //~ eeprom93xx_reset(s->eeprom);
658 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
659 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
660 if (s->device == i82557B || s->device == i82557C)
661 eeprom_contents[5] = 0x0100;
662 eeprom_contents[EEPROM_PHY_ID] = 1;
663 uint16_t sum = 0;
664 for (i = 0; i < EEPROM_SIZE - 1; i++) {
665 sum += eeprom_contents[i];
666 }
667 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
668 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
669
670 memset(s->mem, 0, sizeof(s->mem));
671 uint32_t val = BIT(21);
672 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
673
674 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
675 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
676 }
677
678 static void nic_reset(void *opaque)
679 {
680 EEPRO100State *s = opaque;
681 TRACE(OTHER, logout("%p\n", s));
682 /* TODO: Clearing of multicast table for selective reset, too? */
683 memset(&s->mult[0], 0, sizeof(s->mult));
684 nic_selective_reset(s);
685 }
686
687 #if defined(DEBUG_EEPRO100)
688 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
689 "Command/Status",
690 "General Pointer",
691 "Port",
692 "EEPROM/Flash Control",
693 "MDI Control",
694 "Receive DMA Byte Count",
695 "Flow Control",
696 "General Status/Control"
697 };
698
699 static char *regname(uint32_t addr)
700 {
701 static char buf[32];
702 if (addr < PCI_IO_SIZE) {
703 const char *r = e100_reg[addr / 4];
704 if (r != 0) {
705 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
706 } else {
707 snprintf(buf, sizeof(buf), "0x%02x", addr);
708 }
709 } else {
710 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
711 }
712 return buf;
713 }
714 #endif /* DEBUG_EEPRO100 */
715
716 #if 0
717 static uint16_t eepro100_read_status(EEPRO100State * s)
718 {
719 uint16_t val = s->status;
720 TRACE(OTHER, logout("val=0x%04x\n", val));
721 return val;
722 }
723
724 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
725 {
726 TRACE(OTHER, logout("val=0x%04x\n", val));
727 s->status = val;
728 }
729 #endif
730
731 /*****************************************************************************
732 *
733 * Command emulation.
734 *
735 ****************************************************************************/
736
737 #if 0
738 static uint16_t eepro100_read_command(EEPRO100State * s)
739 {
740 uint16_t val = 0xffff;
741 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
742 return val;
743 }
744 #endif
745
746 /* Commands that can be put in a command list entry. */
747 enum commands {
748 CmdNOp = 0,
749 CmdIASetup = 1,
750 CmdConfigure = 2,
751 CmdMulticastList = 3,
752 CmdTx = 4,
753 CmdTDR = 5, /* load microcode */
754 CmdDump = 6,
755 CmdDiagnose = 7,
756
757 /* And some extra flags: */
758 CmdSuspend = 0x4000, /* Suspend after completion. */
759 CmdIntr = 0x2000, /* Interrupt after completion. */
760 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
761 };
762
763 static cu_state_t get_cu_state(EEPRO100State * s)
764 {
765 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
766 }
767
768 static void set_cu_state(EEPRO100State * s, cu_state_t state)
769 {
770 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
771 }
772
773 static ru_state_t get_ru_state(EEPRO100State * s)
774 {
775 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
776 }
777
778 static void set_ru_state(EEPRO100State * s, ru_state_t state)
779 {
780 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
781 }
782
783 static void dump_statistics(EEPRO100State * s)
784 {
785 /* Dump statistical data. Most data is never changed by the emulation
786 * and always 0, so we first just copy the whole block and then those
787 * values which really matter.
788 * Number of data should check configuration!!!
789 */
790 cpu_physical_memory_write(s->statsaddr,
791 (uint8_t *) & s->statistics, s->stats_size);
792 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
793 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
794 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
795 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
796 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
797 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
798 //~ missing("CU dump statistical counters");
799 }
800
801 static void tx_command(EEPRO100State *s)
802 {
803 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
804 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
805 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
806 uint8_t buf[2600];
807 uint16_t size = 0;
808 uint32_t tbd_address = s->cb_address + 0x10;
809 TRACE(RXTX, logout
810 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
811 tbd_array, tcb_bytes, s->tx.tbd_count));
812
813 if (tcb_bytes > 2600) {
814 logout("TCB byte count too large, using 2600\n");
815 tcb_bytes = 2600;
816 }
817 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
818 logout
819 ("illegal values of TBD array address and TCB byte count!\n");
820 }
821 assert(tcb_bytes <= sizeof(buf));
822 while (size < tcb_bytes) {
823 uint32_t tx_buffer_address = ldl_phys(tbd_address);
824 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
825 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
826 tbd_address += 8;
827 TRACE(RXTX, logout
828 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
829 tx_buffer_address, tx_buffer_size));
830 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
831 cpu_physical_memory_read(tx_buffer_address, &buf[size],
832 tx_buffer_size);
833 size += tx_buffer_size;
834 }
835 if (tbd_array == 0xffffffff) {
836 /* Simplified mode. Was already handled by code above. */
837 } else {
838 /* Flexible mode. */
839 uint8_t tbd_count = 0;
840 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
841 /* Extended Flexible TCB. */
842 for (; tbd_count < 2; tbd_count++) {
843 uint32_t tx_buffer_address = ldl_phys(tbd_address);
844 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
845 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
846 tbd_address += 8;
847 TRACE(RXTX, logout
848 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
849 tx_buffer_address, tx_buffer_size));
850 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
851 cpu_physical_memory_read(tx_buffer_address, &buf[size],
852 tx_buffer_size);
853 size += tx_buffer_size;
854 if (tx_buffer_el & 1) {
855 break;
856 }
857 }
858 }
859 tbd_address = tbd_array;
860 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
861 uint32_t tx_buffer_address = ldl_phys(tbd_address);
862 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
863 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
864 tbd_address += 8;
865 TRACE(RXTX, logout
866 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
867 tx_buffer_address, tx_buffer_size));
868 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
869 cpu_physical_memory_read(tx_buffer_address, &buf[size],
870 tx_buffer_size);
871 size += tx_buffer_size;
872 if (tx_buffer_el & 1) {
873 break;
874 }
875 }
876 }
877 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
878 qemu_send_packet(&s->nic->nc, buf, size);
879 s->statistics.tx_good_frames++;
880 /* Transmit with bad status would raise an CX/TNO interrupt.
881 * (82557 only). Emulation never has bad status. */
882 //~ eepro100_cx_interrupt(s);
883 }
884
885 static void set_multicast_list(EEPRO100State *s)
886 {
887 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
888 uint16_t i;
889 memset(&s->mult[0], 0, sizeof(s->mult));
890 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
891 for (i = 0; i < multicast_count; i += 6) {
892 uint8_t multicast_addr[6];
893 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
894 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
895 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
896 assert(mcast_idx < 64);
897 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
898 }
899 }
900
901 static void action_command(EEPRO100State *s)
902 {
903 for (;;) {
904 s->cb_address = s->cu_base + s->cu_offset;
905 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
906 uint16_t status = le16_to_cpu(s->tx.status);
907 uint16_t command = le16_to_cpu(s->tx.command);
908 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
909 status, command, s->tx.link);
910 bool bit_el = ((command & COMMAND_EL) != 0);
911 bool bit_s = ((command & COMMAND_S) != 0);
912 bool bit_i = ((command & COMMAND_I) != 0);
913 bool bit_nc = ((command & COMMAND_NC) != 0);
914 bool success = true;
915 //~ bool bit_sf = ((command & COMMAND_SF) != 0);
916 uint16_t cmd = command & COMMAND_CMD;
917 s->cu_offset = le32_to_cpu(s->tx.link);
918 switch (cmd) {
919 case CmdNOp:
920 /* Do nothing. */
921 break;
922 case CmdIASetup:
923 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
924 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
925 break;
926 case CmdConfigure:
927 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
928 sizeof(s->configuration));
929 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
930 break;
931 case CmdMulticastList:
932 set_multicast_list(s);
933 break;
934 case CmdTx:
935 if (bit_nc) {
936 missing("CmdTx: NC = 0");
937 success = false;
938 break;
939 }
940 tx_command(s);
941 break;
942 case CmdTDR:
943 TRACE(OTHER, logout("load microcode\n"));
944 /* Starting with offset 8, the command contains
945 * 64 dwords microcode which we just ignore here. */
946 break;
947 default:
948 missing("undefined command");
949 success = false;
950 break;
951 }
952 /* Write new status. */
953 stw_phys(s->cb_address, status | STATUS_C | (success ? STATUS_OK : 0));
954 if (bit_i) {
955 /* CU completed action. */
956 eepro100_cx_interrupt(s);
957 }
958 if (bit_el) {
959 /* CU becomes idle. Terminate command loop. */
960 set_cu_state(s, cu_idle);
961 eepro100_cna_interrupt(s);
962 break;
963 } else if (bit_s) {
964 /* CU becomes suspended. Terminate command loop. */
965 set_cu_state(s, cu_suspended);
966 eepro100_cna_interrupt(s);
967 break;
968 } else {
969 /* More entries in list. */
970 TRACE(OTHER, logout("CU list with at least one more entry\n"));
971 }
972 }
973 TRACE(OTHER, logout("CU list empty\n"));
974 /* List is empty. Now CU is idle or suspended. */
975 }
976
977 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
978 {
979 cu_state_t cu_state;
980 switch (val) {
981 case CU_NOP:
982 /* No operation. */
983 break;
984 case CU_START:
985 cu_state = get_cu_state(s);
986 if (cu_state != cu_idle && cu_state != cu_suspended) {
987 /* Intel documentation says that CU must be idle or suspended
988 * for the CU start command. */
989 logout("unexpected CU state is %u\n", cu_state);
990 }
991 set_cu_state(s, cu_active);
992 s->cu_offset = s->pointer;
993 action_command(s);
994 break;
995 case CU_RESUME:
996 if (get_cu_state(s) != cu_suspended) {
997 logout("bad CU resume from CU state %u\n", get_cu_state(s));
998 /* Workaround for bad Linux eepro100 driver which resumes
999 * from idle state. */
1000 //~ missing("cu resume");
1001 set_cu_state(s, cu_suspended);
1002 }
1003 if (get_cu_state(s) == cu_suspended) {
1004 TRACE(OTHER, logout("CU resuming\n"));
1005 set_cu_state(s, cu_active);
1006 action_command(s);
1007 }
1008 break;
1009 case CU_STATSADDR:
1010 /* Load dump counters address. */
1011 s->statsaddr = s->pointer;
1012 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1013 break;
1014 case CU_SHOWSTATS:
1015 /* Dump statistical counters. */
1016 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1017 dump_statistics(s);
1018 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1019 break;
1020 case CU_CMD_BASE:
1021 /* Load CU base. */
1022 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1023 s->cu_base = s->pointer;
1024 break;
1025 case CU_DUMPSTATS:
1026 /* Dump and reset statistical counters. */
1027 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1028 dump_statistics(s);
1029 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1030 memset(&s->statistics, 0, sizeof(s->statistics));
1031 break;
1032 case CU_SRESUME:
1033 /* CU static resume. */
1034 missing("CU static resume");
1035 break;
1036 default:
1037 missing("Undefined CU command");
1038 }
1039 }
1040
1041 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1042 {
1043 switch (val) {
1044 case RU_NOP:
1045 /* No operation. */
1046 break;
1047 case RX_START:
1048 /* RU start. */
1049 if (get_ru_state(s) != ru_idle) {
1050 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1051 //~ assert(!"wrong RU state");
1052 }
1053 set_ru_state(s, ru_ready);
1054 s->ru_offset = s->pointer;
1055 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1056 break;
1057 case RX_RESUME:
1058 /* Restart RU. */
1059 if (get_ru_state(s) != ru_suspended) {
1060 logout("RU state is %u, should be %u\n", get_ru_state(s),
1061 ru_suspended);
1062 //~ assert(!"wrong RU state");
1063 }
1064 set_ru_state(s, ru_ready);
1065 break;
1066 case RU_ABORT:
1067 /* RU abort. */
1068 if (get_ru_state(s) == ru_ready) {
1069 eepro100_rnr_interrupt(s);
1070 }
1071 set_ru_state(s, ru_idle);
1072 break;
1073 case RX_ADDR_LOAD:
1074 /* Load RU base. */
1075 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1076 s->ru_base = s->pointer;
1077 break;
1078 default:
1079 logout("val=0x%02x (undefined RU command)\n", val);
1080 missing("Undefined SU command");
1081 }
1082 }
1083
1084 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1085 {
1086 eepro100_ru_command(s, val & 0x0f);
1087 eepro100_cu_command(s, val & 0xf0);
1088 if ((val) == 0) {
1089 TRACE(OTHER, logout("val=0x%02x\n", val));
1090 }
1091 /* Clear command byte after command was accepted. */
1092 s->mem[SCBCmd] = 0;
1093 }
1094
1095 /*****************************************************************************
1096 *
1097 * EEPROM emulation.
1098 *
1099 ****************************************************************************/
1100
1101 #define EEPROM_CS 0x02
1102 #define EEPROM_SK 0x01
1103 #define EEPROM_DI 0x04
1104 #define EEPROM_DO 0x08
1105
1106 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1107 {
1108 uint16_t val;
1109 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1110 if (eeprom93xx_read(s->eeprom)) {
1111 val |= EEPROM_DO;
1112 } else {
1113 val &= ~EEPROM_DO;
1114 }
1115 TRACE(EEPROM, logout("val=0x%04x\n", val));
1116 return val;
1117 }
1118
1119 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1120 {
1121 TRACE(EEPROM, logout("val=0x%02x\n", val));
1122
1123 /* mask unwriteable bits */
1124 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1125
1126 int eecs = ((val & EEPROM_CS) != 0);
1127 int eesk = ((val & EEPROM_SK) != 0);
1128 int eedi = ((val & EEPROM_DI) != 0);
1129 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1130 }
1131
1132 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1133 {
1134 s->pointer = le32_to_cpu(val);
1135 TRACE(OTHER, logout("val=0x%08x\n", val));
1136 }
1137
1138 /*****************************************************************************
1139 *
1140 * MDI emulation.
1141 *
1142 ****************************************************************************/
1143
1144 #if defined(DEBUG_EEPRO100)
1145 static const char * const mdi_op_name[] = {
1146 "opcode 0",
1147 "write",
1148 "read",
1149 "opcode 3"
1150 };
1151
1152 static const char * const mdi_reg_name[] = {
1153 "Control",
1154 "Status",
1155 "PHY Identification (Word 1)",
1156 "PHY Identification (Word 2)",
1157 "Auto-Negotiation Advertisement",
1158 "Auto-Negotiation Link Partner Ability",
1159 "Auto-Negotiation Expansion"
1160 };
1161
1162 static const char *reg2name(uint8_t reg)
1163 {
1164 static char buffer[10];
1165 const char *p = buffer;
1166 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1167 p = mdi_reg_name[reg];
1168 } else {
1169 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1170 }
1171 return p;
1172 }
1173 #endif /* DEBUG_EEPRO100 */
1174
1175 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1176 {
1177 uint32_t val;
1178 memcpy(&val, &s->mem[0x10], sizeof(val));
1179
1180 #ifdef DEBUG_EEPRO100
1181 uint8_t raiseint = (val & BIT(29)) >> 29;
1182 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1183 uint8_t phy = (val & BITS(25, 21)) >> 21;
1184 uint8_t reg = (val & BITS(20, 16)) >> 16;
1185 uint16_t data = (val & BITS(15, 0));
1186 #endif
1187 /* Emulation takes no time to finish MDI transaction. */
1188 val |= BIT(28);
1189 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1190 val, raiseint, mdi_op_name[opcode], phy,
1191 reg2name(reg), data));
1192 return val;
1193 }
1194
1195 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1196 {
1197 uint8_t raiseint = (val & BIT(29)) >> 29;
1198 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1199 uint8_t phy = (val & BITS(25, 21)) >> 21;
1200 uint8_t reg = (val & BITS(20, 16)) >> 16;
1201 uint16_t data = (val & BITS(15, 0));
1202 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1203 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1204 if (phy != 1) {
1205 /* Unsupported PHY address. */
1206 //~ logout("phy must be 1 but is %u\n", phy);
1207 data = 0;
1208 } else if (opcode != 1 && opcode != 2) {
1209 /* Unsupported opcode. */
1210 logout("opcode must be 1 or 2 but is %u\n", opcode);
1211 data = 0;
1212 } else if (reg > 6) {
1213 /* Unsupported register. */
1214 logout("register must be 0...6 but is %u\n", reg);
1215 data = 0;
1216 } else {
1217 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1218 val, raiseint, mdi_op_name[opcode], phy,
1219 reg2name(reg), data));
1220 if (opcode == 1) {
1221 /* MDI write */
1222 switch (reg) {
1223 case 0: /* Control Register */
1224 if (data & 0x8000) {
1225 /* Reset status and control registers to default. */
1226 s->mdimem[0] = eepro100_mdi_default[0];
1227 s->mdimem[1] = eepro100_mdi_default[1];
1228 data = s->mdimem[reg];
1229 } else {
1230 /* Restart Auto Configuration = Normal Operation */
1231 data &= ~0x0200;
1232 }
1233 break;
1234 case 1: /* Status Register */
1235 missing("not writable");
1236 data = s->mdimem[reg];
1237 break;
1238 case 2: /* PHY Identification Register (Word 1) */
1239 case 3: /* PHY Identification Register (Word 2) */
1240 missing("not implemented");
1241 break;
1242 case 4: /* Auto-Negotiation Advertisement Register */
1243 case 5: /* Auto-Negotiation Link Partner Ability Register */
1244 break;
1245 case 6: /* Auto-Negotiation Expansion Register */
1246 default:
1247 missing("not implemented");
1248 }
1249 s->mdimem[reg] = data;
1250 } else if (opcode == 2) {
1251 /* MDI read */
1252 switch (reg) {
1253 case 0: /* Control Register */
1254 if (data & 0x8000) {
1255 /* Reset status and control registers to default. */
1256 s->mdimem[0] = eepro100_mdi_default[0];
1257 s->mdimem[1] = eepro100_mdi_default[1];
1258 }
1259 break;
1260 case 1: /* Status Register */
1261 s->mdimem[reg] |= 0x0020;
1262 break;
1263 case 2: /* PHY Identification Register (Word 1) */
1264 case 3: /* PHY Identification Register (Word 2) */
1265 case 4: /* Auto-Negotiation Advertisement Register */
1266 break;
1267 case 5: /* Auto-Negotiation Link Partner Ability Register */
1268 s->mdimem[reg] = 0x41fe;
1269 break;
1270 case 6: /* Auto-Negotiation Expansion Register */
1271 s->mdimem[reg] = 0x0001;
1272 break;
1273 }
1274 data = s->mdimem[reg];
1275 }
1276 /* Emulation takes no time to finish MDI transaction.
1277 * Set MDI bit in SCB status register. */
1278 s->mem[SCBAck] |= 0x08;
1279 val |= BIT(28);
1280 if (raiseint) {
1281 eepro100_mdi_interrupt(s);
1282 }
1283 }
1284 val = (val & 0xffff0000) + data;
1285 memcpy(&s->mem[0x10], &val, sizeof(val));
1286 }
1287
1288 /*****************************************************************************
1289 *
1290 * Port emulation.
1291 *
1292 ****************************************************************************/
1293
1294 #define PORT_SOFTWARE_RESET 0
1295 #define PORT_SELFTEST 1
1296 #define PORT_SELECTIVE_RESET 2
1297 #define PORT_DUMP 3
1298 #define PORT_SELECTION_MASK 3
1299
1300 typedef struct {
1301 uint32_t st_sign; /* Self Test Signature */
1302 uint32_t st_result; /* Self Test Results */
1303 } eepro100_selftest_t;
1304
1305 static uint32_t eepro100_read_port(EEPRO100State * s)
1306 {
1307 return 0;
1308 }
1309
1310 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1311 {
1312 val = le32_to_cpu(val);
1313 uint32_t address = (val & ~PORT_SELECTION_MASK);
1314 uint8_t selection = (val & PORT_SELECTION_MASK);
1315 switch (selection) {
1316 case PORT_SOFTWARE_RESET:
1317 nic_reset(s);
1318 break;
1319 case PORT_SELFTEST:
1320 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1321 eepro100_selftest_t data;
1322 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1323 data.st_sign = 0xffffffff;
1324 data.st_result = 0;
1325 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1326 break;
1327 case PORT_SELECTIVE_RESET:
1328 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1329 nic_selective_reset(s);
1330 break;
1331 default:
1332 logout("val=0x%08x\n", val);
1333 missing("unknown port selection");
1334 }
1335 }
1336
1337 /*****************************************************************************
1338 *
1339 * General hardware emulation.
1340 *
1341 ****************************************************************************/
1342
1343 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1344 {
1345 uint8_t val;
1346 if (addr <= sizeof(s->mem) - sizeof(val)) {
1347 memcpy(&val, &s->mem[addr], sizeof(val));
1348 }
1349
1350 switch (addr) {
1351 case SCBStatus:
1352 //~ val = eepro100_read_status(s);
1353 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1354 break;
1355 case SCBAck:
1356 //~ val = eepro100_read_status(s);
1357 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1358 break;
1359 case SCBCmd:
1360 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1361 //~ val = eepro100_read_command(s);
1362 break;
1363 case SCBIntmask:
1364 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1365 break;
1366 case SCBPort + 3:
1367 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1368 break;
1369 case SCBeeprom:
1370 val = eepro100_read_eeprom(s);
1371 break;
1372 case SCBpmdr: /* Power Management Driver Register */
1373 val = 0;
1374 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1375 break;
1376 case SCBgstat: /* General Status Register */
1377 /* 100 Mbps full duplex, valid link */
1378 val = 0x07;
1379 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1380 break;
1381 default:
1382 logout("addr=%s val=0x%02x\n", regname(addr), val);
1383 missing("unknown byte read");
1384 }
1385 return val;
1386 }
1387
1388 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1389 {
1390 uint16_t val;
1391 if (addr <= sizeof(s->mem) - sizeof(val)) {
1392 memcpy(&val, &s->mem[addr], sizeof(val));
1393 }
1394
1395 switch (addr) {
1396 case SCBStatus:
1397 //~ val = eepro100_read_status(s);
1398 case SCBCmd:
1399 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1400 break;
1401 case SCBeeprom:
1402 val = eepro100_read_eeprom(s);
1403 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1404 break;
1405 default:
1406 logout("addr=%s val=0x%04x\n", regname(addr), val);
1407 missing("unknown word read");
1408 }
1409 return val;
1410 }
1411
1412 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1413 {
1414 uint32_t val;
1415 if (addr <= sizeof(s->mem) - sizeof(val)) {
1416 memcpy(&val, &s->mem[addr], sizeof(val));
1417 }
1418
1419 switch (addr) {
1420 case SCBStatus:
1421 //~ val = eepro100_read_status(s);
1422 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1423 break;
1424 case SCBPointer:
1425 //~ val = eepro100_read_pointer(s);
1426 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1427 break;
1428 case SCBPort:
1429 val = eepro100_read_port(s);
1430 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1431 break;
1432 case SCBCtrlMDI:
1433 val = eepro100_read_mdi(s);
1434 break;
1435 default:
1436 logout("addr=%s val=0x%08x\n", regname(addr), val);
1437 missing("unknown longword read");
1438 }
1439 return val;
1440 }
1441
1442 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1443 {
1444 if (addr <= sizeof(s->mem) - sizeof(val)) {
1445 memcpy(&s->mem[addr], &val, sizeof(val));
1446 }
1447
1448 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1449
1450 switch (addr) {
1451 case SCBStatus:
1452 //~ eepro100_write_status(s, val);
1453 break;
1454 case SCBAck:
1455 eepro100_acknowledge(s);
1456 break;
1457 case SCBCmd:
1458 eepro100_write_command(s, val);
1459 break;
1460 case SCBIntmask:
1461 if (val & BIT(1)) {
1462 eepro100_swi_interrupt(s);
1463 }
1464 eepro100_interrupt(s, 0);
1465 break;
1466 case SCBPort + 3:
1467 case SCBFlow: /* does not exist on 82557 */
1468 case SCBFlow + 1:
1469 case SCBFlow + 2:
1470 case SCBpmdr: /* does not exist on 82557 */
1471 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1472 break;
1473 case SCBeeprom:
1474 eepro100_write_eeprom(s->eeprom, val);
1475 break;
1476 default:
1477 logout("addr=%s val=0x%02x\n", regname(addr), val);
1478 missing("unknown byte write");
1479 }
1480 }
1481
1482 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1483 {
1484 if (addr <= sizeof(s->mem) - sizeof(val)) {
1485 memcpy(&s->mem[addr], &val, sizeof(val));
1486 }
1487
1488 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1489
1490 switch (addr) {
1491 case SCBStatus:
1492 //~ eepro100_write_status(s, val);
1493 eepro100_acknowledge(s);
1494 break;
1495 case SCBCmd:
1496 eepro100_write_command(s, val);
1497 eepro100_write1(s, SCBIntmask, val >> 8);
1498 break;
1499 case SCBeeprom:
1500 eepro100_write_eeprom(s->eeprom, val);
1501 break;
1502 default:
1503 logout("addr=%s val=0x%04x\n", regname(addr), val);
1504 missing("unknown word write");
1505 }
1506 }
1507
1508 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1509 {
1510 if (addr <= sizeof(s->mem) - sizeof(val)) {
1511 memcpy(&s->mem[addr], &val, sizeof(val));
1512 }
1513
1514 switch (addr) {
1515 case SCBPointer:
1516 eepro100_write_pointer(s, val);
1517 break;
1518 case SCBPort:
1519 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1520 eepro100_write_port(s, val);
1521 break;
1522 case SCBCtrlMDI:
1523 eepro100_write_mdi(s, val);
1524 break;
1525 default:
1526 logout("addr=%s val=0x%08x\n", regname(addr), val);
1527 missing("unknown longword write");
1528 }
1529 }
1530
1531 /*****************************************************************************
1532 *
1533 * Port mapped I/O.
1534 *
1535 ****************************************************************************/
1536
1537 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1538 {
1539 EEPRO100State *s = opaque;
1540 //~ logout("addr=%s\n", regname(addr));
1541 return eepro100_read1(s, addr - s->region[1]);
1542 }
1543
1544 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1545 {
1546 EEPRO100State *s = opaque;
1547 return eepro100_read2(s, addr - s->region[1]);
1548 }
1549
1550 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1551 {
1552 EEPRO100State *s = opaque;
1553 return eepro100_read4(s, addr - s->region[1]);
1554 }
1555
1556 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1557 {
1558 EEPRO100State *s = opaque;
1559 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1560 eepro100_write1(s, addr - s->region[1], val);
1561 }
1562
1563 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1564 {
1565 EEPRO100State *s = opaque;
1566 eepro100_write2(s, addr - s->region[1], val);
1567 }
1568
1569 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1570 {
1571 EEPRO100State *s = opaque;
1572 eepro100_write4(s, addr - s->region[1], val);
1573 }
1574
1575 /***********************************************************/
1576 /* PCI EEPRO100 definitions */
1577
1578 static void pci_map(PCIDevice * pci_dev, int region_num,
1579 pcibus_t addr, pcibus_t size, int type)
1580 {
1581 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1582
1583 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1584 "size=0x%08"FMT_PCIBUS", type=%d\n",
1585 region_num, addr, size, type));
1586
1587 assert(region_num == 1);
1588 register_ioport_write(addr, size, 1, ioport_write1, s);
1589 register_ioport_read(addr, size, 1, ioport_read1, s);
1590 register_ioport_write(addr, size, 2, ioport_write2, s);
1591 register_ioport_read(addr, size, 2, ioport_read2, s);
1592 register_ioport_write(addr, size, 4, ioport_write4, s);
1593 register_ioport_read(addr, size, 4, ioport_read4, s);
1594
1595 s->region[region_num] = addr;
1596 }
1597
1598 /*****************************************************************************
1599 *
1600 * Memory mapped I/O.
1601 *
1602 ****************************************************************************/
1603
1604 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1605 {
1606 EEPRO100State *s = opaque;
1607 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1608 eepro100_write1(s, addr, val);
1609 }
1610
1611 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1612 {
1613 EEPRO100State *s = opaque;
1614 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1615 eepro100_write2(s, addr, val);
1616 }
1617
1618 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1619 {
1620 EEPRO100State *s = opaque;
1621 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1622 eepro100_write4(s, addr, val);
1623 }
1624
1625 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1626 {
1627 EEPRO100State *s = opaque;
1628 //~ logout("addr=%s\n", regname(addr));
1629 return eepro100_read1(s, addr);
1630 }
1631
1632 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1633 {
1634 EEPRO100State *s = opaque;
1635 //~ logout("addr=%s\n", regname(addr));
1636 return eepro100_read2(s, addr);
1637 }
1638
1639 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1640 {
1641 EEPRO100State *s = opaque;
1642 //~ logout("addr=%s\n", regname(addr));
1643 return eepro100_read4(s, addr);
1644 }
1645
1646 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1647 pci_mmio_writeb,
1648 pci_mmio_writew,
1649 pci_mmio_writel
1650 };
1651
1652 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1653 pci_mmio_readb,
1654 pci_mmio_readw,
1655 pci_mmio_readl
1656 };
1657
1658 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1659 pcibus_t addr, pcibus_t size, int type)
1660 {
1661 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1662
1663 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1664 "size=0x%08"FMT_PCIBUS", type=%d\n",
1665 region_num, addr, size, type));
1666
1667 if (region_num == 0) {
1668 /* Map control / status registers. */
1669 cpu_register_physical_memory(addr, size, s->mmio_index);
1670 s->region[region_num] = addr;
1671 }
1672 }
1673
1674 static int nic_can_receive(VLANClientState *nc)
1675 {
1676 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1677 TRACE(RXTX, logout("%p\n", s));
1678 return get_ru_state(s) == ru_ready;
1679 //~ return !eepro100_buffer_full(s);
1680 }
1681
1682 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1683 {
1684 /* TODO:
1685 * - Magic packets should set bit 30 in power management driver register.
1686 * - Interesting packets should set bit 29 in power management driver register.
1687 */
1688 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1689 uint16_t rfd_status = 0xa000;
1690 static const uint8_t broadcast_macaddr[6] =
1691 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1692
1693 /* TODO: check multiple IA bit. */
1694 if (s->configuration[20] & BIT(6)) {
1695 missing("Multiple IA bit");
1696 return -1;
1697 }
1698
1699 if (s->configuration[8] & 0x80) {
1700 /* CSMA is disabled. */
1701 logout("%p received while CSMA is disabled\n", s);
1702 return -1;
1703 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1704 /* Short frame and configuration byte 7/0 (discard short receive) set:
1705 * Short frame is discarded */
1706 logout("%p received short frame (%zu byte)\n", s, size);
1707 s->statistics.rx_short_frame_errors++;
1708 //~ return -1;
1709 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1710 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1711 * Long frames are discarded. */
1712 logout("%p received long frame (%zu byte), ignored\n", s, size);
1713 return -1;
1714 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1715 /* Frame matches individual address. */
1716 /* TODO: check configuration byte 15/4 (ignore U/L). */
1717 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1718 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1719 /* Broadcast frame. */
1720 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1721 rfd_status |= 0x0002;
1722 } else if (buf[0] & 0x01) {
1723 /* Multicast frame. */
1724 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1725 if (s->configuration[21] & BIT(3)) {
1726 /* Multicast all bit is set, receive all multicast frames. */
1727 } else {
1728 unsigned mcast_idx = compute_mcast_idx(buf);
1729 assert(mcast_idx < 64);
1730 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1731 /* Multicast frame is allowed in hash table. */
1732 } else if (s->configuration[15] & BIT(0)) {
1733 /* Promiscuous: receive all. */
1734 rfd_status |= 0x0004;
1735 } else {
1736 TRACE(RXTX, logout("%p multicast ignored\n", s));
1737 return -1;
1738 }
1739 }
1740 /* TODO: Next not for promiscuous mode? */
1741 rfd_status |= 0x0002;
1742 } else if (s->configuration[15] & BIT(0)) {
1743 /* Promiscuous: receive all. */
1744 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1745 rfd_status |= 0x0004;
1746 } else {
1747 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1748 nic_dump(buf, size)));
1749 return size;
1750 }
1751
1752 if (get_ru_state(s) != ru_ready) {
1753 /* No resources available. */
1754 logout("no resources, state=%u\n", get_ru_state(s));
1755 /* TODO: RNR interrupt only at first failed frame? */
1756 eepro100_rnr_interrupt(s);
1757 s->statistics.rx_resource_errors++;
1758 //~ assert(!"no resources");
1759 return -1;
1760 }
1761 //~ !!!
1762 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1763 eepro100_rx_t rx;
1764 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1765 offsetof(eepro100_rx_t, packet));
1766 uint16_t rfd_command = le16_to_cpu(rx.command);
1767 uint16_t rfd_size = le16_to_cpu(rx.size);
1768
1769 if (size > rfd_size) {
1770 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1771 "(%zu bytes); data truncated\n", rfd_size, size);
1772 size = rfd_size;
1773 }
1774 if (size < 64) {
1775 rfd_status |= 0x0080;
1776 }
1777 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1778 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1779 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1780 rfd_status);
1781 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1782 /* Early receive interrupt not supported. */
1783 //~ eepro100_er_interrupt(s);
1784 /* Receive CRC Transfer not supported. */
1785 if (s->configuration[18] & BIT(2)) {
1786 missing("Receive CRC Transfer");
1787 return -1;
1788 }
1789 /* TODO: check stripping enable bit. */
1790 //~ assert(!(s->configuration[17] & BIT(0)));
1791 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1792 offsetof(eepro100_rx_t, packet), buf, size);
1793 s->statistics.rx_good_frames++;
1794 eepro100_fr_interrupt(s);
1795 s->ru_offset = le32_to_cpu(rx.link);
1796 if (rfd_command & COMMAND_EL) {
1797 /* EL bit is set, so this was the last frame. */
1798 logout("receive: Running out of frames\n");
1799 set_ru_state(s, ru_suspended);
1800 }
1801 if (rfd_command & COMMAND_S) {
1802 /* S bit is set. */
1803 set_ru_state(s, ru_suspended);
1804 }
1805 return size;
1806 }
1807
1808 static const VMStateDescription vmstate_eepro100 = {
1809 .version_id = 3,
1810 .minimum_version_id = 2,
1811 .minimum_version_id_old = 2,
1812 .fields = (VMStateField []) {
1813 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1814 VMSTATE_UNUSED(32),
1815 VMSTATE_BUFFER(mult, EEPRO100State),
1816 VMSTATE_BUFFER(mem, EEPRO100State),
1817 /* Save all members of struct between scb_stat and mem. */
1818 VMSTATE_UINT8(scb_stat, EEPRO100State),
1819 VMSTATE_UINT8(int_stat, EEPRO100State),
1820 VMSTATE_UNUSED(3*4),
1821 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1822 VMSTATE_UNUSED(19*4),
1823 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1824 /* The eeprom should be saved and restored by its own routines. */
1825 VMSTATE_UINT32(device, EEPRO100State),
1826 /* TODO check device. */
1827 VMSTATE_UINT32(pointer, EEPRO100State),
1828 VMSTATE_UINT32(cu_base, EEPRO100State),
1829 VMSTATE_UINT32(cu_offset, EEPRO100State),
1830 VMSTATE_UINT32(ru_base, EEPRO100State),
1831 VMSTATE_UINT32(ru_offset, EEPRO100State),
1832 VMSTATE_UINT32(statsaddr, EEPRO100State),
1833 /* Save eepro100_stats_t statistics. */
1834 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1835 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1836 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1837 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1838 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1839 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1840 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1841 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1842 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1843 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1844 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1845 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1846 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1847 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1848 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1849 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1850 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1851 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1852 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1853 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1854 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1855 #if 0
1856 VMSTATE_UINT16(status, EEPRO100State),
1857 #endif
1858 /* Configuration bytes. */
1859 VMSTATE_BUFFER(configuration, EEPRO100State),
1860 VMSTATE_END_OF_LIST()
1861 }
1862 };
1863
1864 static void nic_cleanup(VLANClientState *nc)
1865 {
1866 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1867
1868 s->nic = NULL;
1869 }
1870
1871 static int pci_nic_uninit(PCIDevice *pci_dev)
1872 {
1873 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1874
1875 cpu_unregister_io_memory(s->mmio_index);
1876 vmstate_unregister(s->vmstate, s);
1877 eeprom93xx_free(s->eeprom);
1878 qemu_del_vlan_client(&s->nic->nc);
1879 return 0;
1880 }
1881
1882 static NetClientInfo net_eepro100_info = {
1883 .type = NET_CLIENT_TYPE_NIC,
1884 .size = sizeof(NICState),
1885 .can_receive = nic_can_receive,
1886 .receive = nic_receive,
1887 .cleanup = nic_cleanup,
1888 };
1889
1890 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1891 {
1892 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1893
1894 TRACE(OTHER, logout("\n"));
1895
1896 s->device = device;
1897
1898 pci_reset(s);
1899
1900 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1901 * i82559 and later support 64 or 256 word EEPROM. */
1902 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1903
1904 /* Handler for memory-mapped I/O */
1905 s->mmio_index =
1906 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1907
1908 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1909 PCI_BASE_ADDRESS_SPACE_MEMORY |
1910 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1911 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1912 pci_map);
1913 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1914 pci_mmio_map);
1915
1916 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1917 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1918 assert(s->region[1] == 0);
1919
1920 nic_reset(s);
1921
1922 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1923 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1924
1925 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1926 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1927
1928 qemu_register_reset(nic_reset, s);
1929
1930 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1931 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1932 s->vmstate->name = s->nic->nc.model;
1933 vmstate_register(-1, s->vmstate, s);
1934
1935 return 0;
1936 }
1937
1938 static int pci_i82550_init(PCIDevice *pci_dev)
1939 {
1940 return nic_init(pci_dev, i82550);
1941 }
1942
1943 static int pci_i82551_init(PCIDevice *pci_dev)
1944 {
1945 return nic_init(pci_dev, i82551);
1946 }
1947
1948 static int pci_i82557a_init(PCIDevice *pci_dev)
1949 {
1950 return nic_init(pci_dev, i82557A);
1951 }
1952
1953 static int pci_i82557b_init(PCIDevice *pci_dev)
1954 {
1955 return nic_init(pci_dev, i82557B);
1956 }
1957
1958 static int pci_i82557c_init(PCIDevice *pci_dev)
1959 {
1960 return nic_init(pci_dev, i82557C);
1961 }
1962
1963 static int pci_i82558a_init(PCIDevice *pci_dev)
1964 {
1965 return nic_init(pci_dev, i82558A);
1966 }
1967
1968 static int pci_i82558b_init(PCIDevice *pci_dev)
1969 {
1970 return nic_init(pci_dev, i82558B);
1971 }
1972
1973 static int pci_i82559a_init(PCIDevice *pci_dev)
1974 {
1975 return nic_init(pci_dev, i82559A);
1976 }
1977
1978 static int pci_i82559b_init(PCIDevice *pci_dev)
1979 {
1980 return nic_init(pci_dev, i82559B);
1981 }
1982
1983 static int pci_i82559c_init(PCIDevice *pci_dev)
1984 {
1985 return nic_init(pci_dev, i82559C);
1986 }
1987
1988 static int pci_i82559er_init(PCIDevice *pci_dev)
1989 {
1990 return nic_init(pci_dev, i82559ER);
1991 }
1992
1993 static int pci_i82562_init(PCIDevice *pci_dev)
1994 {
1995 return nic_init(pci_dev, i82562);
1996 }
1997
1998 static PCIDeviceInfo eepro100_info[] = {
1999 {
2000 .qdev.name = "i82550",
2001 .qdev.desc = "Intel i82550 Ethernet",
2002 .qdev.size = sizeof(EEPRO100State),
2003 .init = pci_i82550_init,
2004 .exit = pci_nic_uninit,
2005 .romfile = "gpxe-eepro100-80861209.rom",
2006 .qdev.props = (Property[]) {
2007 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2008 DEFINE_PROP_END_OF_LIST(),
2009 },
2010 },{
2011 .qdev.name = "i82551",
2012 .qdev.desc = "Intel i82551 Ethernet",
2013 .qdev.size = sizeof(EEPRO100State),
2014 .init = pci_i82551_init,
2015 .exit = pci_nic_uninit,
2016 .romfile = "gpxe-eepro100-80861209.rom",
2017 .qdev.props = (Property[]) {
2018 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2019 DEFINE_PROP_END_OF_LIST(),
2020 },
2021 },{
2022 .qdev.name = "i82557a",
2023 .qdev.desc = "Intel i82557A Ethernet",
2024 .qdev.size = sizeof(EEPRO100State),
2025 .init = pci_i82557a_init,
2026 .exit = pci_nic_uninit,
2027 .romfile = "gpxe-eepro100-80861229.rom",
2028 .qdev.props = (Property[]) {
2029 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2030 DEFINE_PROP_END_OF_LIST(),
2031 },
2032 },{
2033 .qdev.name = "i82557b",
2034 .qdev.desc = "Intel i82557B Ethernet",
2035 .qdev.size = sizeof(EEPRO100State),
2036 .init = pci_i82557b_init,
2037 .exit = pci_nic_uninit,
2038 .romfile = "gpxe-eepro100-80861229.rom",
2039 .qdev.props = (Property[]) {
2040 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2041 DEFINE_PROP_END_OF_LIST(),
2042 },
2043 },{
2044 .qdev.name = "i82557c",
2045 .qdev.desc = "Intel i82557C Ethernet",
2046 .qdev.size = sizeof(EEPRO100State),
2047 .init = pci_i82557c_init,
2048 .exit = pci_nic_uninit,
2049 .romfile = "gpxe-eepro100-80861229.rom",
2050 .qdev.props = (Property[]) {
2051 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2052 DEFINE_PROP_END_OF_LIST(),
2053 },
2054 },{
2055 .qdev.name = "i82558a",
2056 .qdev.desc = "Intel i82558A Ethernet",
2057 .qdev.size = sizeof(EEPRO100State),
2058 .init = pci_i82558a_init,
2059 .exit = pci_nic_uninit,
2060 .romfile = "gpxe-eepro100-80861229.rom",
2061 .qdev.props = (Property[]) {
2062 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2063 DEFINE_PROP_END_OF_LIST(),
2064 },
2065 },{
2066 .qdev.name = "i82558b",
2067 .qdev.desc = "Intel i82558B Ethernet",
2068 .qdev.size = sizeof(EEPRO100State),
2069 .init = pci_i82558b_init,
2070 .exit = pci_nic_uninit,
2071 .romfile = "gpxe-eepro100-80861229.rom",
2072 .qdev.props = (Property[]) {
2073 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2074 DEFINE_PROP_END_OF_LIST(),
2075 },
2076 },{
2077 .qdev.name = "i82559a",
2078 .qdev.desc = "Intel i82559A Ethernet",
2079 .qdev.size = sizeof(EEPRO100State),
2080 .init = pci_i82559a_init,
2081 .exit = pci_nic_uninit,
2082 .romfile = "gpxe-eepro100-80861229.rom",
2083 .qdev.props = (Property[]) {
2084 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2085 DEFINE_PROP_END_OF_LIST(),
2086 },
2087 },{
2088 .qdev.name = "i82559b",
2089 .qdev.desc = "Intel i82559B Ethernet",
2090 .qdev.size = sizeof(EEPRO100State),
2091 .init = pci_i82559b_init,
2092 .exit = pci_nic_uninit,
2093 .romfile = "gpxe-eepro100-80861229.rom",
2094 .qdev.props = (Property[]) {
2095 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2096 DEFINE_PROP_END_OF_LIST(),
2097 },
2098 },{
2099 .qdev.name = "i82559c",
2100 .qdev.desc = "Intel i82559C Ethernet",
2101 .qdev.size = sizeof(EEPRO100State),
2102 .init = pci_i82559c_init,
2103 .exit = pci_nic_uninit,
2104 .romfile = "gpxe-eepro100-80861229.rom",
2105 .qdev.props = (Property[]) {
2106 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2107 DEFINE_PROP_END_OF_LIST(),
2108 },
2109 },{
2110 .qdev.name = "i82559er",
2111 .qdev.desc = "Intel i82559ER Ethernet",
2112 .qdev.size = sizeof(EEPRO100State),
2113 .init = pci_i82559er_init,
2114 .exit = pci_nic_uninit,
2115 .romfile = "gpxe-eepro100-80861209.rom",
2116 .qdev.props = (Property[]) {
2117 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2118 DEFINE_PROP_END_OF_LIST(),
2119 },
2120 },{
2121 .qdev.name = "i82562",
2122 .qdev.desc = "Intel i82562 Ethernet",
2123 .qdev.size = sizeof(EEPRO100State),
2124 .init = pci_i82562_init,
2125 .exit = pci_nic_uninit,
2126 .romfile = "gpxe-eepro100-80861209.rom",
2127 .qdev.props = (Property[]) {
2128 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2129 DEFINE_PROP_END_OF_LIST(),
2130 },
2131 },{
2132 /* end of list */
2133 }
2134 };
2135
2136 static void eepro100_register_devices(void)
2137 {
2138 pci_qdev_register_many(eepro100_info);
2139 }
2140
2141 device_init(eepro100_register_devices)
QEmu