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Merge remote-tracking branch 'sstabellini/disk_io' into staging
[qemu.git] / hw / vga.c
blobf80860caed39cefdefd23bca2d61e1cced2b05cc
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "vga.h"
26 #include "console.h"
27 #include "pc.h"
28 #include "pci.h"
29 #include "vga_int.h"
30 #include "pixel_ops.h"
31 #include "qemu-timer.h"
32 #include "xen.h"
33 #include "trace.h"
34
35 //#define DEBUG_VGA
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
38
39 //#define DEBUG_BOCHS_VBE
40
41 /*
42 * Video Graphics Array (VGA)
43 *
44 * Chipset docs for original IBM VGA:
45 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
46 *
47 * FreeVGA site:
48 * http://www.osdever.net/FreeVGA/home.htm
49 *
50 * Standard VGA features and Bochs VBE extensions are implemented.
51 */
52
53 /* force some bits to zero */
54 const uint8_t sr_mask[8] = {
55 0x03,
56 0x3d,
57 0x0f,
58 0x3f,
59 0x0e,
60 0x00,
61 0x00,
62 0xff,
63 };
64
65 const uint8_t gr_mask[16] = {
66 0x0f, /* 0x00 */
67 0x0f, /* 0x01 */
68 0x0f, /* 0x02 */
69 0x1f, /* 0x03 */
70 0x03, /* 0x04 */
71 0x7b, /* 0x05 */
72 0x0f, /* 0x06 */
73 0x0f, /* 0x07 */
74 0xff, /* 0x08 */
75 0x00, /* 0x09 */
76 0x00, /* 0x0a */
77 0x00, /* 0x0b */
78 0x00, /* 0x0c */
79 0x00, /* 0x0d */
80 0x00, /* 0x0e */
81 0x00, /* 0x0f */
82 };
83
84 #define cbswap_32(__x) \
85 ((uint32_t)( \
86 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
87 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
88 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
89 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
90
91 #ifdef HOST_WORDS_BIGENDIAN
92 #define PAT(x) cbswap_32(x)
93 #else
94 #define PAT(x) (x)
95 #endif
96
97 #ifdef HOST_WORDS_BIGENDIAN
98 #define BIG 1
99 #else
100 #define BIG 0
101 #endif
102
103 #ifdef HOST_WORDS_BIGENDIAN
104 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
105 #else
106 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
107 #endif
108
109 static const uint32_t mask16[16] = {
110 PAT(0x00000000),
111 PAT(0x000000ff),
112 PAT(0x0000ff00),
113 PAT(0x0000ffff),
114 PAT(0x00ff0000),
115 PAT(0x00ff00ff),
116 PAT(0x00ffff00),
117 PAT(0x00ffffff),
118 PAT(0xff000000),
119 PAT(0xff0000ff),
120 PAT(0xff00ff00),
121 PAT(0xff00ffff),
122 PAT(0xffff0000),
123 PAT(0xffff00ff),
124 PAT(0xffffff00),
125 PAT(0xffffffff),
126 };
127
128 #undef PAT
129
130 #ifdef HOST_WORDS_BIGENDIAN
131 #define PAT(x) (x)
132 #else
133 #define PAT(x) cbswap_32(x)
134 #endif
135
136 static const uint32_t dmask16[16] = {
137 PAT(0x00000000),
138 PAT(0x000000ff),
139 PAT(0x0000ff00),
140 PAT(0x0000ffff),
141 PAT(0x00ff0000),
142 PAT(0x00ff00ff),
143 PAT(0x00ffff00),
144 PAT(0x00ffffff),
145 PAT(0xff000000),
146 PAT(0xff0000ff),
147 PAT(0xff00ff00),
148 PAT(0xff00ffff),
149 PAT(0xffff0000),
150 PAT(0xffff00ff),
151 PAT(0xffffff00),
152 PAT(0xffffffff),
153 };
154
155 static const uint32_t dmask4[4] = {
156 PAT(0x00000000),
157 PAT(0x0000ffff),
158 PAT(0xffff0000),
159 PAT(0xffffffff),
160 };
161
162 static uint32_t expand4[256];
163 static uint16_t expand2[256];
164 static uint8_t expand4to8[16];
165
166 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch);
167
168 static void vga_update_memory_access(VGACommonState *s)
169 {
170 MemoryRegion *region, *old_region = s->chain4_alias;
171 target_phys_addr_t base, offset, size;
172
173 s->chain4_alias = NULL;
174
175 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
176 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
177 offset = 0;
178 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
179 case 0:
180 base = 0xa0000;
181 size = 0x20000;
182 break;
183 case 1:
184 base = 0xa0000;
185 size = 0x10000;
186 offset = s->bank_offset;
187 break;
188 case 2:
189 base = 0xb0000;
190 size = 0x8000;
191 break;
192 case 3:
193 default:
194 base = 0xb8000;
195 size = 0x8000;
196 break;
197 }
198 base += isa_mem_base;
199 region = g_malloc(sizeof(*region));
200 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
201 memory_region_add_subregion_overlap(s->legacy_address_space, base,
202 region, 2);
203 s->chain4_alias = region;
204 }
205 if (old_region) {
206 memory_region_del_subregion(s->legacy_address_space, old_region);
207 memory_region_destroy(old_region);
208 g_free(old_region);
209 s->plane_updated = 0xf;
210 }
211 }
212
213 static void vga_dumb_update_retrace_info(VGACommonState *s)
214 {
215 (void) s;
216 }
217
218 static void vga_precise_update_retrace_info(VGACommonState *s)
219 {
220 int htotal_chars;
221 int hretr_start_char;
222 int hretr_skew_chars;
223 int hretr_end_char;
224
225 int vtotal_lines;
226 int vretr_start_line;
227 int vretr_end_line;
228
229 int dots;
230 #if 0
231 int div2, sldiv2;
232 #endif
233 int clocking_mode;
234 int clock_sel;
235 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
236 int64_t chars_per_sec;
237 struct vga_precise_retrace *r = &s->retrace_info.precise;
238
239 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
240 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
241 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
242 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
243
244 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
245 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
246 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
247 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
248 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
249 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
250 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
251
252 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
253 clock_sel = (s->msr >> 2) & 3;
254 dots = (s->msr & 1) ? 8 : 9;
255
256 chars_per_sec = clk_hz[clock_sel] / dots;
257
258 htotal_chars <<= clocking_mode;
259
260 r->total_chars = vtotal_lines * htotal_chars;
261 if (r->freq) {
262 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
263 } else {
264 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
265 }
266
267 r->vstart = vretr_start_line;
268 r->vend = r->vstart + vretr_end_line + 1;
269
270 r->hstart = hretr_start_char + hretr_skew_chars;
271 r->hend = r->hstart + hretr_end_char + 1;
272 r->htotal = htotal_chars;
273
274 #if 0
275 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
276 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
277 printf (
278 "hz=%f\n"
279 "htotal = %d\n"
280 "hretr_start = %d\n"
281 "hretr_skew = %d\n"
282 "hretr_end = %d\n"
283 "vtotal = %d\n"
284 "vretr_start = %d\n"
285 "vretr_end = %d\n"
286 "div2 = %d sldiv2 = %d\n"
287 "clocking_mode = %d\n"
288 "clock_sel = %d %d\n"
289 "dots = %d\n"
290 "ticks/char = %" PRId64 "\n"
291 "\n",
292 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
293 htotal_chars,
294 hretr_start_char,
295 hretr_skew_chars,
296 hretr_end_char,
297 vtotal_lines,
298 vretr_start_line,
299 vretr_end_line,
300 div2, sldiv2,
301 clocking_mode,
302 clock_sel,
303 clk_hz[clock_sel],
304 dots,
305 r->ticks_per_char
306 );
307 #endif
308 }
309
310 static uint8_t vga_precise_retrace(VGACommonState *s)
311 {
312 struct vga_precise_retrace *r = &s->retrace_info.precise;
313 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
314
315 if (r->total_chars) {
316 int cur_line, cur_line_char, cur_char;
317 int64_t cur_tick;
318
319 cur_tick = qemu_get_clock_ns(vm_clock);
320
321 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
322 cur_line = cur_char / r->htotal;
323
324 if (cur_line >= r->vstart && cur_line <= r->vend) {
325 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
326 } else {
327 cur_line_char = cur_char % r->htotal;
328 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
329 val |= ST01_DISP_ENABLE;
330 }
331 }
332
333 return val;
334 } else {
335 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
336 }
337 }
338
339 static uint8_t vga_dumb_retrace(VGACommonState *s)
340 {
341 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
342 }
343
344 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
345 {
346 if (s->msr & VGA_MIS_COLOR) {
347 /* Color */
348 return (addr >= 0x3b0 && addr <= 0x3bf);
349 } else {
350 /* Monochrome */
351 return (addr >= 0x3d0 && addr <= 0x3df);
352 }
353 }
354
355 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
356 {
357 VGACommonState *s = opaque;
358 int val, index;
359
360 if (vga_ioport_invalid(s, addr)) {
361 val = 0xff;
362 } else {
363 switch(addr) {
364 case VGA_ATT_W:
365 if (s->ar_flip_flop == 0) {
366 val = s->ar_index;
367 } else {
368 val = 0;
369 }
370 break;
371 case VGA_ATT_R:
372 index = s->ar_index & 0x1f;
373 if (index < VGA_ATT_C) {
374 val = s->ar[index];
375 } else {
376 val = 0;
377 }
378 break;
379 case VGA_MIS_W:
380 val = s->st00;
381 break;
382 case VGA_SEQ_I:
383 val = s->sr_index;
384 break;
385 case VGA_SEQ_D:
386 val = s->sr[s->sr_index];
387 #ifdef DEBUG_VGA_REG
388 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
389 #endif
390 break;
391 case VGA_PEL_IR:
392 val = s->dac_state;
393 break;
394 case VGA_PEL_IW:
395 val = s->dac_write_index;
396 break;
397 case VGA_PEL_D:
398 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
399 if (++s->dac_sub_index == 3) {
400 s->dac_sub_index = 0;
401 s->dac_read_index++;
402 }
403 break;
404 case VGA_FTC_R:
405 val = s->fcr;
406 break;
407 case VGA_MIS_R:
408 val = s->msr;
409 break;
410 case VGA_GFX_I:
411 val = s->gr_index;
412 break;
413 case VGA_GFX_D:
414 val = s->gr[s->gr_index];
415 #ifdef DEBUG_VGA_REG
416 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
417 #endif
418 break;
419 case VGA_CRT_IM:
420 case VGA_CRT_IC:
421 val = s->cr_index;
422 break;
423 case VGA_CRT_DM:
424 case VGA_CRT_DC:
425 val = s->cr[s->cr_index];
426 #ifdef DEBUG_VGA_REG
427 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
428 #endif
429 break;
430 case VGA_IS1_RM:
431 case VGA_IS1_RC:
432 /* just toggle to fool polling */
433 val = s->st01 = s->retrace(s);
434 s->ar_flip_flop = 0;
435 break;
436 default:
437 val = 0x00;
438 break;
439 }
440 }
441 #if defined(DEBUG_VGA)
442 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
443 #endif
444 return val;
445 }
446
447 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
448 {
449 VGACommonState *s = opaque;
450 int index;
451
452 /* check port range access depending on color/monochrome mode */
453 if (vga_ioport_invalid(s, addr)) {
454 return;
455 }
456 #ifdef DEBUG_VGA
457 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
458 #endif
459
460 switch(addr) {
461 case VGA_ATT_W:
462 if (s->ar_flip_flop == 0) {
463 val &= 0x3f;
464 s->ar_index = val;
465 } else {
466 index = s->ar_index & 0x1f;
467 switch(index) {
468 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
469 s->ar[index] = val & 0x3f;
470 break;
471 case VGA_ATC_MODE:
472 s->ar[index] = val & ~0x10;
473 break;
474 case VGA_ATC_OVERSCAN:
475 s->ar[index] = val;
476 break;
477 case VGA_ATC_PLANE_ENABLE:
478 s->ar[index] = val & ~0xc0;
479 break;
480 case VGA_ATC_PEL:
481 s->ar[index] = val & ~0xf0;
482 break;
483 case VGA_ATC_COLOR_PAGE:
484 s->ar[index] = val & ~0xf0;
485 break;
486 default:
487 break;
488 }
489 }
490 s->ar_flip_flop ^= 1;
491 break;
492 case VGA_MIS_W:
493 s->msr = val & ~0x10;
494 s->update_retrace_info(s);
495 break;
496 case VGA_SEQ_I:
497 s->sr_index = val & 7;
498 break;
499 case VGA_SEQ_D:
500 #ifdef DEBUG_VGA_REG
501 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
502 #endif
503 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
504 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
505 s->update_retrace_info(s);
506 }
507 vga_update_memory_access(s);
508 break;
509 case VGA_PEL_IR:
510 s->dac_read_index = val;
511 s->dac_sub_index = 0;
512 s->dac_state = 3;
513 break;
514 case VGA_PEL_IW:
515 s->dac_write_index = val;
516 s->dac_sub_index = 0;
517 s->dac_state = 0;
518 break;
519 case VGA_PEL_D:
520 s->dac_cache[s->dac_sub_index] = val;
521 if (++s->dac_sub_index == 3) {
522 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
523 s->dac_sub_index = 0;
524 s->dac_write_index++;
525 }
526 break;
527 case VGA_GFX_I:
528 s->gr_index = val & 0x0f;
529 break;
530 case VGA_GFX_D:
531 #ifdef DEBUG_VGA_REG
532 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
533 #endif
534 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
535 vga_update_memory_access(s);
536 break;
537 case VGA_CRT_IM:
538 case VGA_CRT_IC:
539 s->cr_index = val;
540 break;
541 case VGA_CRT_DM:
542 case VGA_CRT_DC:
543 #ifdef DEBUG_VGA_REG
544 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
545 #endif
546 /* handle CR0-7 protection */
547 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
548 s->cr_index <= VGA_CRTC_OVERFLOW) {
549 /* can always write bit 4 of CR7 */
550 if (s->cr_index == VGA_CRTC_OVERFLOW) {
551 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
552 (val & 0x10);
553 }
554 return;
555 }
556 s->cr[s->cr_index] = val;
557
558 switch(s->cr_index) {
559 case VGA_CRTC_H_TOTAL:
560 case VGA_CRTC_H_SYNC_START:
561 case VGA_CRTC_H_SYNC_END:
562 case VGA_CRTC_V_TOTAL:
563 case VGA_CRTC_OVERFLOW:
564 case VGA_CRTC_V_SYNC_END:
565 case VGA_CRTC_MODE:
566 s->update_retrace_info(s);
567 break;
568 }
569 break;
570 case VGA_IS1_RM:
571 case VGA_IS1_RC:
572 s->fcr = val & 0x10;
573 break;
574 }
575 }
576
577 #ifdef CONFIG_BOCHS_VBE
578 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
579 {
580 VGACommonState *s = opaque;
581 uint32_t val;
582 val = s->vbe_index;
583 return val;
584 }
585
586 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
587 {
588 VGACommonState *s = opaque;
589 uint32_t val;
590
591 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
592 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
593 switch(s->vbe_index) {
594 /* XXX: do not hardcode ? */
595 case VBE_DISPI_INDEX_XRES:
596 val = VBE_DISPI_MAX_XRES;
597 break;
598 case VBE_DISPI_INDEX_YRES:
599 val = VBE_DISPI_MAX_YRES;
600 break;
601 case VBE_DISPI_INDEX_BPP:
602 val = VBE_DISPI_MAX_BPP;
603 break;
604 default:
605 val = s->vbe_regs[s->vbe_index];
606 break;
607 }
608 } else {
609 val = s->vbe_regs[s->vbe_index];
610 }
611 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
612 val = s->vram_size / (64 * 1024);
613 } else {
614 val = 0;
615 }
616 #ifdef DEBUG_BOCHS_VBE
617 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
618 #endif
619 return val;
620 }
621
622 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
623 {
624 VGACommonState *s = opaque;
625 s->vbe_index = val;
626 }
627
628 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
629 {
630 VGACommonState *s = opaque;
631
632 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
633 #ifdef DEBUG_BOCHS_VBE
634 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
635 #endif
636 switch(s->vbe_index) {
637 case VBE_DISPI_INDEX_ID:
638 if (val == VBE_DISPI_ID0 ||
639 val == VBE_DISPI_ID1 ||
640 val == VBE_DISPI_ID2 ||
641 val == VBE_DISPI_ID3 ||
642 val == VBE_DISPI_ID4) {
643 s->vbe_regs[s->vbe_index] = val;
644 }
645 break;
646 case VBE_DISPI_INDEX_XRES:
647 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
648 s->vbe_regs[s->vbe_index] = val;
649 }
650 break;
651 case VBE_DISPI_INDEX_YRES:
652 if (val <= VBE_DISPI_MAX_YRES) {
653 s->vbe_regs[s->vbe_index] = val;
654 }
655 break;
656 case VBE_DISPI_INDEX_BPP:
657 if (val == 0)
658 val = 8;
659 if (val == 4 || val == 8 || val == 15 ||
660 val == 16 || val == 24 || val == 32) {
661 s->vbe_regs[s->vbe_index] = val;
662 }
663 break;
664 case VBE_DISPI_INDEX_BANK:
665 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
666 val &= (s->vbe_bank_mask >> 2);
667 } else {
668 val &= s->vbe_bank_mask;
669 }
670 s->vbe_regs[s->vbe_index] = val;
671 s->bank_offset = (val << 16);
672 vga_update_memory_access(s);
673 break;
674 case VBE_DISPI_INDEX_ENABLE:
675 if ((val & VBE_DISPI_ENABLED) &&
676 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
677 int h, shift_control;
678
679 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
680 s->vbe_regs[VBE_DISPI_INDEX_XRES];
681 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
682 s->vbe_regs[VBE_DISPI_INDEX_YRES];
683 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
684 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
685
686 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
687 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
688 else
689 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
690 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
691 s->vbe_start_addr = 0;
692
693 /* clear the screen (should be done in BIOS) */
694 if (!(val & VBE_DISPI_NOCLEARMEM)) {
695 memset(s->vram_ptr, 0,
696 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
697 }
698
699 /* we initialize the VGA graphic mode (should be done
700 in BIOS) */
701 /* graphic mode + memory map 1 */
702 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
703 VGA_GR06_GRAPHICS_MODE;
704 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
705 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
706 /* width */
707 s->cr[VGA_CRTC_H_DISP] =
708 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
709 /* height (only meaningful if < 1024) */
710 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
711 s->cr[VGA_CRTC_V_DISP_END] = h;
712 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
713 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
714 /* line compare to 1023 */
715 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
716 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
717 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
718
719 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
720 shift_control = 0;
721 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
722 } else {
723 shift_control = 2;
724 /* set chain 4 mode */
725 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
726 /* activate all planes */
727 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
728 }
729 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
730 (shift_control << 5);
731 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
732 } else {
733 /* XXX: the bios should do that */
734 s->bank_offset = 0;
735 }
736 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
737 s->vbe_regs[s->vbe_index] = val;
738 vga_update_memory_access(s);
739 break;
740 case VBE_DISPI_INDEX_VIRT_WIDTH:
741 {
742 int w, h, line_offset;
743
744 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
745 return;
746 w = val;
747 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
748 line_offset = w >> 1;
749 else
750 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
751 h = s->vram_size / line_offset;
752 /* XXX: support weird bochs semantics ? */
753 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
754 return;
755 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
756 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
757 s->vbe_line_offset = line_offset;
758 }
759 break;
760 case VBE_DISPI_INDEX_X_OFFSET:
761 case VBE_DISPI_INDEX_Y_OFFSET:
762 {
763 int x;
764 s->vbe_regs[s->vbe_index] = val;
765 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
766 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
767 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
768 s->vbe_start_addr += x >> 1;
769 else
770 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
771 s->vbe_start_addr >>= 2;
772 }
773 break;
774 default:
775 break;
776 }
777 }
778 }
779 #endif
780
781 /* called for accesses between 0xa0000 and 0xc0000 */
782 uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
783 {
784 int memory_map_mode, plane;
785 uint32_t ret;
786
787 /* convert to VGA memory offset */
788 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
789 addr &= 0x1ffff;
790 switch(memory_map_mode) {
791 case 0:
792 break;
793 case 1:
794 if (addr >= 0x10000)
795 return 0xff;
796 addr += s->bank_offset;
797 break;
798 case 2:
799 addr -= 0x10000;
800 if (addr >= 0x8000)
801 return 0xff;
802 break;
803 default:
804 case 3:
805 addr -= 0x18000;
806 if (addr >= 0x8000)
807 return 0xff;
808 break;
809 }
810
811 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
812 /* chain 4 mode : simplest access */
813 ret = s->vram_ptr[addr];
814 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
815 /* odd/even mode (aka text mode mapping) */
816 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
817 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
818 } else {
819 /* standard VGA latched access */
820 s->latch = ((uint32_t *)s->vram_ptr)[addr];
821
822 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
823 /* read mode 0 */
824 plane = s->gr[VGA_GFX_PLANE_READ];
825 ret = GET_PLANE(s->latch, plane);
826 } else {
827 /* read mode 1 */
828 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
829 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
830 ret |= ret >> 16;
831 ret |= ret >> 8;
832 ret = (~ret) & 0xff;
833 }
834 }
835 return ret;
836 }
837
838 /* called for accesses between 0xa0000 and 0xc0000 */
839 void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
840 {
841 int memory_map_mode, plane, write_mode, b, func_select, mask;
842 uint32_t write_mask, bit_mask, set_mask;
843
844 #ifdef DEBUG_VGA_MEM
845 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
846 #endif
847 /* convert to VGA memory offset */
848 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
849 addr &= 0x1ffff;
850 switch(memory_map_mode) {
851 case 0:
852 break;
853 case 1:
854 if (addr >= 0x10000)
855 return;
856 addr += s->bank_offset;
857 break;
858 case 2:
859 addr -= 0x10000;
860 if (addr >= 0x8000)
861 return;
862 break;
863 default:
864 case 3:
865 addr -= 0x18000;
866 if (addr >= 0x8000)
867 return;
868 break;
869 }
870
871 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
872 /* chain 4 mode : simplest access */
873 plane = addr & 3;
874 mask = (1 << plane);
875 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
876 s->vram_ptr[addr] = val;
877 #ifdef DEBUG_VGA_MEM
878 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
879 #endif
880 s->plane_updated |= mask; /* only used to detect font change */
881 memory_region_set_dirty(&s->vram, addr, 1);
882 }
883 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
884 /* odd/even mode (aka text mode mapping) */
885 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
886 mask = (1 << plane);
887 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
888 addr = ((addr & ~1) << 1) | plane;
889 s->vram_ptr[addr] = val;
890 #ifdef DEBUG_VGA_MEM
891 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
892 #endif
893 s->plane_updated |= mask; /* only used to detect font change */
894 memory_region_set_dirty(&s->vram, addr, 1);
895 }
896 } else {
897 /* standard VGA latched access */
898 write_mode = s->gr[VGA_GFX_MODE] & 3;
899 switch(write_mode) {
900 default:
901 case 0:
902 /* rotate */
903 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
904 val = ((val >> b) | (val << (8 - b))) & 0xff;
905 val |= val << 8;
906 val |= val << 16;
907
908 /* apply set/reset mask */
909 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
910 val = (val & ~set_mask) |
911 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
912 bit_mask = s->gr[VGA_GFX_BIT_MASK];
913 break;
914 case 1:
915 val = s->latch;
916 goto do_write;
917 case 2:
918 val = mask16[val & 0x0f];
919 bit_mask = s->gr[VGA_GFX_BIT_MASK];
920 break;
921 case 3:
922 /* rotate */
923 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
924 val = (val >> b) | (val << (8 - b));
925
926 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
927 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
928 break;
929 }
930
931 /* apply logical operation */
932 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
933 switch(func_select) {
934 case 0:
935 default:
936 /* nothing to do */
937 break;
938 case 1:
939 /* and */
940 val &= s->latch;
941 break;
942 case 2:
943 /* or */
944 val |= s->latch;
945 break;
946 case 3:
947 /* xor */
948 val ^= s->latch;
949 break;
950 }
951
952 /* apply bit mask */
953 bit_mask |= bit_mask << 8;
954 bit_mask |= bit_mask << 16;
955 val = (val & bit_mask) | (s->latch & ~bit_mask);
956
957 do_write:
958 /* mask data according to sr[2] */
959 mask = s->sr[VGA_SEQ_PLANE_WRITE];
960 s->plane_updated |= mask; /* only used to detect font change */
961 write_mask = mask16[mask];
962 ((uint32_t *)s->vram_ptr)[addr] =
963 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
964 (val & write_mask);
965 #ifdef DEBUG_VGA_MEM
966 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
967 addr * 4, write_mask, val);
968 #endif
969 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
970 }
971 }
972
973 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
974 const uint8_t *font_ptr, int h,
975 uint32_t fgcol, uint32_t bgcol);
976 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
977 const uint8_t *font_ptr, int h,
978 uint32_t fgcol, uint32_t bgcol, int dup9);
979 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
980 const uint8_t *s, int width);
981
982 #define DEPTH 8
983 #include "vga_template.h"
984
985 #define DEPTH 15
986 #include "vga_template.h"
987
988 #define BGR_FORMAT
989 #define DEPTH 15
990 #include "vga_template.h"
991
992 #define DEPTH 16
993 #include "vga_template.h"
994
995 #define BGR_FORMAT
996 #define DEPTH 16
997 #include "vga_template.h"
998
999 #define DEPTH 32
1000 #include "vga_template.h"
1001
1002 #define BGR_FORMAT
1003 #define DEPTH 32
1004 #include "vga_template.h"
1005
1006 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1007 {
1008 unsigned int col;
1009 col = rgb_to_pixel8(r, g, b);
1010 col |= col << 8;
1011 col |= col << 16;
1012 return col;
1013 }
1014
1015 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1016 {
1017 unsigned int col;
1018 col = rgb_to_pixel15(r, g, b);
1019 col |= col << 16;
1020 return col;
1021 }
1022
1023 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025 {
1026 unsigned int col;
1027 col = rgb_to_pixel15bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030 }
1031
1032 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1033 {
1034 unsigned int col;
1035 col = rgb_to_pixel16(r, g, b);
1036 col |= col << 16;
1037 return col;
1038 }
1039
1040 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1041 unsigned int b)
1042 {
1043 unsigned int col;
1044 col = rgb_to_pixel16bgr(r, g, b);
1045 col |= col << 16;
1046 return col;
1047 }
1048
1049 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1050 {
1051 unsigned int col;
1052 col = rgb_to_pixel32(r, g, b);
1053 return col;
1054 }
1055
1056 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1057 {
1058 unsigned int col;
1059 col = rgb_to_pixel32bgr(r, g, b);
1060 return col;
1061 }
1062
1063 /* return true if the palette was modified */
1064 static int update_palette16(VGACommonState *s)
1065 {
1066 int full_update, i;
1067 uint32_t v, col, *palette;
1068
1069 full_update = 0;
1070 palette = s->last_palette;
1071 for(i = 0; i < 16; i++) {
1072 v = s->ar[i];
1073 if (s->ar[VGA_ATC_MODE] & 0x80) {
1074 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1075 } else {
1076 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1077 }
1078 v = v * 3;
1079 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1080 c6_to_8(s->palette[v + 1]),
1081 c6_to_8(s->palette[v + 2]));
1082 if (col != palette[i]) {
1083 full_update = 1;
1084 palette[i] = col;
1085 }
1086 }
1087 return full_update;
1088 }
1089
1090 /* return true if the palette was modified */
1091 static int update_palette256(VGACommonState *s)
1092 {
1093 int full_update, i;
1094 uint32_t v, col, *palette;
1095
1096 full_update = 0;
1097 palette = s->last_palette;
1098 v = 0;
1099 for(i = 0; i < 256; i++) {
1100 if (s->dac_8bit) {
1101 col = s->rgb_to_pixel(s->palette[v],
1102 s->palette[v + 1],
1103 s->palette[v + 2]);
1104 } else {
1105 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1106 c6_to_8(s->palette[v + 1]),
1107 c6_to_8(s->palette[v + 2]));
1108 }
1109 if (col != palette[i]) {
1110 full_update = 1;
1111 palette[i] = col;
1112 }
1113 v += 3;
1114 }
1115 return full_update;
1116 }
1117
1118 static void vga_get_offsets(VGACommonState *s,
1119 uint32_t *pline_offset,
1120 uint32_t *pstart_addr,
1121 uint32_t *pline_compare)
1122 {
1123 uint32_t start_addr, line_offset, line_compare;
1124 #ifdef CONFIG_BOCHS_VBE
1125 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1126 line_offset = s->vbe_line_offset;
1127 start_addr = s->vbe_start_addr;
1128 line_compare = 65535;
1129 } else
1130 #endif
1131 {
1132 /* compute line_offset in bytes */
1133 line_offset = s->cr[VGA_CRTC_OFFSET];
1134 line_offset <<= 3;
1135
1136 /* starting address */
1137 start_addr = s->cr[VGA_CRTC_START_LO] |
1138 (s->cr[VGA_CRTC_START_HI] << 8);
1139
1140 /* line compare */
1141 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1142 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1143 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1144 }
1145 *pline_offset = line_offset;
1146 *pstart_addr = start_addr;
1147 *pline_compare = line_compare;
1148 }
1149
1150 /* update start_addr and line_offset. Return TRUE if modified */
1151 static int update_basic_params(VGACommonState *s)
1152 {
1153 int full_update;
1154 uint32_t start_addr, line_offset, line_compare;
1155
1156 full_update = 0;
1157
1158 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1159
1160 if (line_offset != s->line_offset ||
1161 start_addr != s->start_addr ||
1162 line_compare != s->line_compare) {
1163 s->line_offset = line_offset;
1164 s->start_addr = start_addr;
1165 s->line_compare = line_compare;
1166 full_update = 1;
1167 }
1168 return full_update;
1169 }
1170
1171 #define NB_DEPTHS 7
1172
1173 static inline int get_depth_index(DisplayState *s)
1174 {
1175 switch(ds_get_bits_per_pixel(s)) {
1176 default:
1177 case 8:
1178 return 0;
1179 case 15:
1180 return 1;
1181 case 16:
1182 return 2;
1183 case 32:
1184 if (is_surface_bgr(s->surface))
1185 return 4;
1186 else
1187 return 3;
1188 }
1189 }
1190
1191 static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
1192 vga_draw_glyph8_8,
1193 vga_draw_glyph8_16,
1194 vga_draw_glyph8_16,
1195 vga_draw_glyph8_32,
1196 vga_draw_glyph8_32,
1197 vga_draw_glyph8_16,
1198 vga_draw_glyph8_16,
1199 };
1200
1201 static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
1202 vga_draw_glyph16_8,
1203 vga_draw_glyph16_16,
1204 vga_draw_glyph16_16,
1205 vga_draw_glyph16_32,
1206 vga_draw_glyph16_32,
1207 vga_draw_glyph16_16,
1208 vga_draw_glyph16_16,
1209 };
1210
1211 static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
1212 vga_draw_glyph9_8,
1213 vga_draw_glyph9_16,
1214 vga_draw_glyph9_16,
1215 vga_draw_glyph9_32,
1216 vga_draw_glyph9_32,
1217 vga_draw_glyph9_16,
1218 vga_draw_glyph9_16,
1219 };
1220
1221 static const uint8_t cursor_glyph[32 * 4] = {
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1238 };
1239
1240 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1241 int *pcwidth, int *pcheight)
1242 {
1243 int width, cwidth, height, cheight;
1244
1245 /* total width & height */
1246 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1247 cwidth = 8;
1248 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1249 cwidth = 9;
1250 }
1251 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1252 cwidth = 16; /* NOTE: no 18 pixel wide */
1253 }
1254 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1255 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1256 /* ugly hack for CGA 160x100x16 - explain me the logic */
1257 height = 100;
1258 } else {
1259 height = s->cr[VGA_CRTC_V_DISP_END] |
1260 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1261 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1262 height = (height + 1) / cheight;
1263 }
1264
1265 *pwidth = width;
1266 *pheight = height;
1267 *pcwidth = cwidth;
1268 *pcheight = cheight;
1269 }
1270
1271 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1272
1273 static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
1274 rgb_to_pixel8_dup,
1275 rgb_to_pixel15_dup,
1276 rgb_to_pixel16_dup,
1277 rgb_to_pixel32_dup,
1278 rgb_to_pixel32bgr_dup,
1279 rgb_to_pixel15bgr_dup,
1280 rgb_to_pixel16bgr_dup,
1281 };
1282
1283 /*
1284 * Text mode update
1285 * Missing:
1286 * - double scan
1287 * - double width
1288 * - underline
1289 * - flashing
1290 */
1291 static void vga_draw_text(VGACommonState *s, int full_update)
1292 {
1293 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1294 int cx_min, cx_max, linesize, x_incr, line, line1;
1295 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1296 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1297 const uint8_t *font_ptr, *font_base[2];
1298 int dup9, line_offset, depth_index;
1299 uint32_t *palette;
1300 uint32_t *ch_attr_ptr;
1301 vga_draw_glyph8_func *vga_draw_glyph8;
1302 vga_draw_glyph9_func *vga_draw_glyph9;
1303
1304 /* compute font data address (in plane 2) */
1305 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1306 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1307 if (offset != s->font_offsets[0]) {
1308 s->font_offsets[0] = offset;
1309 full_update = 1;
1310 }
1311 font_base[0] = s->vram_ptr + offset;
1312
1313 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1314 font_base[1] = s->vram_ptr + offset;
1315 if (offset != s->font_offsets[1]) {
1316 s->font_offsets[1] = offset;
1317 full_update = 1;
1318 }
1319 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
1320 /* if the plane 2 was modified since the last display, it
1321 indicates the font may have been modified */
1322 s->plane_updated = 0;
1323 full_update = 1;
1324 }
1325 full_update |= update_basic_params(s);
1326
1327 line_offset = s->line_offset;
1328
1329 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1330 if ((height * width) > CH_ATTR_SIZE) {
1331 /* better than nothing: exit if transient size is too big */
1332 return;
1333 }
1334
1335 if (width != s->last_width || height != s->last_height ||
1336 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1337 s->last_scr_width = width * cw;
1338 s->last_scr_height = height * cheight;
1339 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1340 s->last_depth = 0;
1341 s->last_width = width;
1342 s->last_height = height;
1343 s->last_ch = cheight;
1344 s->last_cw = cw;
1345 full_update = 1;
1346 }
1347 s->rgb_to_pixel =
1348 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1349 full_update |= update_palette16(s);
1350 palette = s->last_palette;
1351 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1352
1353 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1354 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1355 if (cursor_offset != s->cursor_offset ||
1356 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1357 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1358 /* if the cursor position changed, we update the old and new
1359 chars */
1360 if (s->cursor_offset < CH_ATTR_SIZE)
1361 s->last_ch_attr[s->cursor_offset] = -1;
1362 if (cursor_offset < CH_ATTR_SIZE)
1363 s->last_ch_attr[cursor_offset] = -1;
1364 s->cursor_offset = cursor_offset;
1365 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1366 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1367 }
1368 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1369
1370 depth_index = get_depth_index(s->ds);
1371 if (cw == 16)
1372 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1373 else
1374 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1375 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1376
1377 dest = ds_get_data(s->ds);
1378 linesize = ds_get_linesize(s->ds);
1379 ch_attr_ptr = s->last_ch_attr;
1380 line = 0;
1381 offset = s->start_addr * 4;
1382 for(cy = 0; cy < height; cy++) {
1383 d1 = dest;
1384 src = s->vram_ptr + offset;
1385 cx_min = width;
1386 cx_max = -1;
1387 for(cx = 0; cx < width; cx++) {
1388 ch_attr = *(uint16_t *)src;
1389 if (full_update || ch_attr != *ch_attr_ptr) {
1390 if (cx < cx_min)
1391 cx_min = cx;
1392 if (cx > cx_max)
1393 cx_max = cx;
1394 *ch_attr_ptr = ch_attr;
1395 #ifdef HOST_WORDS_BIGENDIAN
1396 ch = ch_attr >> 8;
1397 cattr = ch_attr & 0xff;
1398 #else
1399 ch = ch_attr & 0xff;
1400 cattr = ch_attr >> 8;
1401 #endif
1402 font_ptr = font_base[(cattr >> 3) & 1];
1403 font_ptr += 32 * 4 * ch;
1404 bgcol = palette[cattr >> 4];
1405 fgcol = palette[cattr & 0x0f];
1406 if (cw != 9) {
1407 vga_draw_glyph8(d1, linesize,
1408 font_ptr, cheight, fgcol, bgcol);
1409 } else {
1410 dup9 = 0;
1411 if (ch >= 0xb0 && ch <= 0xdf &&
1412 (s->ar[VGA_ATC_MODE] & 0x04)) {
1413 dup9 = 1;
1414 }
1415 vga_draw_glyph9(d1, linesize,
1416 font_ptr, cheight, fgcol, bgcol, dup9);
1417 }
1418 if (src == cursor_ptr &&
1419 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20)) {
1420 int line_start, line_last, h;
1421 /* draw the cursor */
1422 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1423 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1424 /* XXX: check that */
1425 if (line_last > cheight - 1)
1426 line_last = cheight - 1;
1427 if (line_last >= line_start && line_start < cheight) {
1428 h = line_last - line_start + 1;
1429 d = d1 + linesize * line_start;
1430 if (cw != 9) {
1431 vga_draw_glyph8(d, linesize,
1432 cursor_glyph, h, fgcol, bgcol);
1433 } else {
1434 vga_draw_glyph9(d, linesize,
1435 cursor_glyph, h, fgcol, bgcol, 1);
1436 }
1437 }
1438 }
1439 }
1440 d1 += x_incr;
1441 src += 4;
1442 ch_attr_ptr++;
1443 }
1444 if (cx_max != -1) {
1445 dpy_update(s->ds, cx_min * cw, cy * cheight,
1446 (cx_max - cx_min + 1) * cw, cheight);
1447 }
1448 dest += linesize * cheight;
1449 line1 = line + cheight;
1450 offset += line_offset;
1451 if (line < s->line_compare && line1 >= s->line_compare) {
1452 offset = 0;
1453 }
1454 line = line1;
1455 }
1456 }
1457
1458 enum {
1459 VGA_DRAW_LINE2,
1460 VGA_DRAW_LINE2D2,
1461 VGA_DRAW_LINE4,
1462 VGA_DRAW_LINE4D2,
1463 VGA_DRAW_LINE8D2,
1464 VGA_DRAW_LINE8,
1465 VGA_DRAW_LINE15,
1466 VGA_DRAW_LINE16,
1467 VGA_DRAW_LINE24,
1468 VGA_DRAW_LINE32,
1469 VGA_DRAW_LINE_NB,
1470 };
1471
1472 static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1473 vga_draw_line2_8,
1474 vga_draw_line2_16,
1475 vga_draw_line2_16,
1476 vga_draw_line2_32,
1477 vga_draw_line2_32,
1478 vga_draw_line2_16,
1479 vga_draw_line2_16,
1480
1481 vga_draw_line2d2_8,
1482 vga_draw_line2d2_16,
1483 vga_draw_line2d2_16,
1484 vga_draw_line2d2_32,
1485 vga_draw_line2d2_32,
1486 vga_draw_line2d2_16,
1487 vga_draw_line2d2_16,
1488
1489 vga_draw_line4_8,
1490 vga_draw_line4_16,
1491 vga_draw_line4_16,
1492 vga_draw_line4_32,
1493 vga_draw_line4_32,
1494 vga_draw_line4_16,
1495 vga_draw_line4_16,
1496
1497 vga_draw_line4d2_8,
1498 vga_draw_line4d2_16,
1499 vga_draw_line4d2_16,
1500 vga_draw_line4d2_32,
1501 vga_draw_line4d2_32,
1502 vga_draw_line4d2_16,
1503 vga_draw_line4d2_16,
1504
1505 vga_draw_line8d2_8,
1506 vga_draw_line8d2_16,
1507 vga_draw_line8d2_16,
1508 vga_draw_line8d2_32,
1509 vga_draw_line8d2_32,
1510 vga_draw_line8d2_16,
1511 vga_draw_line8d2_16,
1512
1513 vga_draw_line8_8,
1514 vga_draw_line8_16,
1515 vga_draw_line8_16,
1516 vga_draw_line8_32,
1517 vga_draw_line8_32,
1518 vga_draw_line8_16,
1519 vga_draw_line8_16,
1520
1521 vga_draw_line15_8,
1522 vga_draw_line15_15,
1523 vga_draw_line15_16,
1524 vga_draw_line15_32,
1525 vga_draw_line15_32bgr,
1526 vga_draw_line15_15bgr,
1527 vga_draw_line15_16bgr,
1528
1529 vga_draw_line16_8,
1530 vga_draw_line16_15,
1531 vga_draw_line16_16,
1532 vga_draw_line16_32,
1533 vga_draw_line16_32bgr,
1534 vga_draw_line16_15bgr,
1535 vga_draw_line16_16bgr,
1536
1537 vga_draw_line24_8,
1538 vga_draw_line24_15,
1539 vga_draw_line24_16,
1540 vga_draw_line24_32,
1541 vga_draw_line24_32bgr,
1542 vga_draw_line24_15bgr,
1543 vga_draw_line24_16bgr,
1544
1545 vga_draw_line32_8,
1546 vga_draw_line32_15,
1547 vga_draw_line32_16,
1548 vga_draw_line32_32,
1549 vga_draw_line32_32bgr,
1550 vga_draw_line32_15bgr,
1551 vga_draw_line32_16bgr,
1552 };
1553
1554 static int vga_get_bpp(VGACommonState *s)
1555 {
1556 int ret;
1557 #ifdef CONFIG_BOCHS_VBE
1558 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1559 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1560 } else
1561 #endif
1562 {
1563 ret = 0;
1564 }
1565 return ret;
1566 }
1567
1568 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1569 {
1570 int width, height;
1571
1572 #ifdef CONFIG_BOCHS_VBE
1573 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1574 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1575 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1576 } else
1577 #endif
1578 {
1579 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1580 height = s->cr[VGA_CRTC_V_DISP_END] |
1581 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1582 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1583 height = (height + 1);
1584 }
1585 *pwidth = width;
1586 *pheight = height;
1587 }
1588
1589 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1590 {
1591 int y;
1592 if (y1 >= VGA_MAX_HEIGHT)
1593 return;
1594 if (y2 >= VGA_MAX_HEIGHT)
1595 y2 = VGA_MAX_HEIGHT;
1596 for(y = y1; y < y2; y++) {
1597 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1598 }
1599 }
1600
1601 static void vga_sync_dirty_bitmap(VGACommonState *s)
1602 {
1603 memory_region_sync_dirty_bitmap(&s->vram);
1604 }
1605
1606 void vga_dirty_log_start(VGACommonState *s)
1607 {
1608 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1609 }
1610
1611 void vga_dirty_log_stop(VGACommonState *s)
1612 {
1613 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1614 }
1615
1616 /*
1617 * graphic modes
1618 */
1619 static void vga_draw_graphic(VGACommonState *s, int full_update)
1620 {
1621 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1622 int width, height, shift_control, line_offset, bwidth, bits;
1623 ram_addr_t page0, page1, page_min, page_max;
1624 int disp_width, multi_scan, multi_run;
1625 uint8_t *d;
1626 uint32_t v, addr1, addr;
1627 vga_draw_line_func *vga_draw_line;
1628
1629 full_update |= update_basic_params(s);
1630
1631 if (!full_update)
1632 vga_sync_dirty_bitmap(s);
1633
1634 s->get_resolution(s, &width, &height);
1635 disp_width = width;
1636
1637 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1638 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1639 if (shift_control != 1) {
1640 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1641 - 1;
1642 } else {
1643 /* in CGA modes, multi_scan is ignored */
1644 /* XXX: is it correct ? */
1645 multi_scan = double_scan;
1646 }
1647 multi_run = multi_scan;
1648 if (shift_control != s->shift_control ||
1649 double_scan != s->double_scan) {
1650 full_update = 1;
1651 s->shift_control = shift_control;
1652 s->double_scan = double_scan;
1653 }
1654
1655 if (shift_control == 0) {
1656 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1657 disp_width <<= 1;
1658 }
1659 } else if (shift_control == 1) {
1660 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1661 disp_width <<= 1;
1662 }
1663 }
1664
1665 depth = s->get_bpp(s);
1666 if (s->line_offset != s->last_line_offset ||
1667 disp_width != s->last_width ||
1668 height != s->last_height ||
1669 s->last_depth != depth) {
1670 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1671 if (depth == 16 || depth == 32) {
1672 #else
1673 if (depth == 32) {
1674 #endif
1675 qemu_free_displaysurface(s->ds);
1676 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1677 s->line_offset,
1678 s->vram_ptr + (s->start_addr * 4));
1679 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1680 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1681 #endif
1682 dpy_resize(s->ds);
1683 } else {
1684 qemu_console_resize(s->ds, disp_width, height);
1685 }
1686 s->last_scr_width = disp_width;
1687 s->last_scr_height = height;
1688 s->last_width = disp_width;
1689 s->last_height = height;
1690 s->last_line_offset = s->line_offset;
1691 s->last_depth = depth;
1692 full_update = 1;
1693 } else if (is_buffer_shared(s->ds->surface) &&
1694 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1695 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1696 dpy_setdata(s->ds);
1697 }
1698
1699 s->rgb_to_pixel =
1700 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1701
1702 if (shift_control == 0) {
1703 full_update |= update_palette16(s);
1704 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1705 v = VGA_DRAW_LINE4D2;
1706 } else {
1707 v = VGA_DRAW_LINE4;
1708 }
1709 bits = 4;
1710 } else if (shift_control == 1) {
1711 full_update |= update_palette16(s);
1712 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1713 v = VGA_DRAW_LINE2D2;
1714 } else {
1715 v = VGA_DRAW_LINE2;
1716 }
1717 bits = 4;
1718 } else {
1719 switch(s->get_bpp(s)) {
1720 default:
1721 case 0:
1722 full_update |= update_palette256(s);
1723 v = VGA_DRAW_LINE8D2;
1724 bits = 4;
1725 break;
1726 case 8:
1727 full_update |= update_palette256(s);
1728 v = VGA_DRAW_LINE8;
1729 bits = 8;
1730 break;
1731 case 15:
1732 v = VGA_DRAW_LINE15;
1733 bits = 16;
1734 break;
1735 case 16:
1736 v = VGA_DRAW_LINE16;
1737 bits = 16;
1738 break;
1739 case 24:
1740 v = VGA_DRAW_LINE24;
1741 bits = 24;
1742 break;
1743 case 32:
1744 v = VGA_DRAW_LINE32;
1745 bits = 32;
1746 break;
1747 }
1748 }
1749 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1750
1751 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1752 s->cursor_invalidate(s);
1753
1754 line_offset = s->line_offset;
1755 #if 0
1756 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1757 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1758 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1759 #endif
1760 addr1 = (s->start_addr * 4);
1761 bwidth = (width * bits + 7) / 8;
1762 y_start = -1;
1763 page_min = -1;
1764 page_max = 0;
1765 d = ds_get_data(s->ds);
1766 linesize = ds_get_linesize(s->ds);
1767 y1 = 0;
1768 for(y = 0; y < height; y++) {
1769 addr = addr1;
1770 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1771 int shift;
1772 /* CGA compatibility handling */
1773 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1774 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1775 }
1776 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1777 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1778 }
1779 update = full_update;
1780 page0 = addr;
1781 page1 = addr + bwidth - 1;
1782 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1783 DIRTY_MEMORY_VGA);
1784 /* explicit invalidation for the hardware cursor */
1785 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1786 if (update) {
1787 if (y_start < 0)
1788 y_start = y;
1789 if (page0 < page_min)
1790 page_min = page0;
1791 if (page1 > page_max)
1792 page_max = page1;
1793 if (!(is_buffer_shared(s->ds->surface))) {
1794 vga_draw_line(s, d, s->vram_ptr + addr, width);
1795 if (s->cursor_draw_line)
1796 s->cursor_draw_line(s, d, y);
1797 }
1798 } else {
1799 if (y_start >= 0) {
1800 /* flush to display */
1801 dpy_update(s->ds, 0, y_start,
1802 disp_width, y - y_start);
1803 y_start = -1;
1804 }
1805 }
1806 if (!multi_run) {
1807 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1808 if ((y1 & mask) == mask)
1809 addr1 += line_offset;
1810 y1++;
1811 multi_run = multi_scan;
1812 } else {
1813 multi_run--;
1814 }
1815 /* line compare acts on the displayed lines */
1816 if (y == s->line_compare)
1817 addr1 = 0;
1818 d += linesize;
1819 }
1820 if (y_start >= 0) {
1821 /* flush to display */
1822 dpy_update(s->ds, 0, y_start,
1823 disp_width, y - y_start);
1824 }
1825 /* reset modified pages */
1826 if (page_max >= page_min) {
1827 memory_region_reset_dirty(&s->vram,
1828 page_min,
1829 page_max - page_min,
1830 DIRTY_MEMORY_VGA);
1831 }
1832 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1833 }
1834
1835 static void vga_draw_blank(VGACommonState *s, int full_update)
1836 {
1837 int i, w, val;
1838 uint8_t *d;
1839
1840 if (!full_update)
1841 return;
1842 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1843 return;
1844
1845 s->rgb_to_pixel =
1846 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1847 if (ds_get_bits_per_pixel(s->ds) == 8)
1848 val = s->rgb_to_pixel(0, 0, 0);
1849 else
1850 val = 0;
1851 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1852 d = ds_get_data(s->ds);
1853 for(i = 0; i < s->last_scr_height; i++) {
1854 memset(d, val, w);
1855 d += ds_get_linesize(s->ds);
1856 }
1857 dpy_update(s->ds, 0, 0,
1858 s->last_scr_width, s->last_scr_height);
1859 }
1860
1861 #define GMODE_TEXT 0
1862 #define GMODE_GRAPH 1
1863 #define GMODE_BLANK 2
1864
1865 static void vga_update_display(void *opaque)
1866 {
1867 VGACommonState *s = opaque;
1868 int full_update, graphic_mode;
1869
1870 qemu_flush_coalesced_mmio_buffer();
1871
1872 if (ds_get_bits_per_pixel(s->ds) == 0) {
1873 /* nothing to do */
1874 } else {
1875 full_update = 0;
1876 if (!(s->ar_index & 0x20)) {
1877 graphic_mode = GMODE_BLANK;
1878 } else {
1879 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1880 }
1881 if (graphic_mode != s->graphic_mode) {
1882 s->graphic_mode = graphic_mode;
1883 full_update = 1;
1884 }
1885 switch(graphic_mode) {
1886 case GMODE_TEXT:
1887 vga_draw_text(s, full_update);
1888 break;
1889 case GMODE_GRAPH:
1890 vga_draw_graphic(s, full_update);
1891 break;
1892 case GMODE_BLANK:
1893 default:
1894 vga_draw_blank(s, full_update);
1895 break;
1896 }
1897 }
1898 }
1899
1900 /* force a full display refresh */
1901 static void vga_invalidate_display(void *opaque)
1902 {
1903 VGACommonState *s = opaque;
1904
1905 s->last_width = -1;
1906 s->last_height = -1;
1907 }
1908
1909 void vga_common_reset(VGACommonState *s)
1910 {
1911 s->sr_index = 0;
1912 memset(s->sr, '\0', sizeof(s->sr));
1913 s->gr_index = 0;
1914 memset(s->gr, '\0', sizeof(s->gr));
1915 s->ar_index = 0;
1916 memset(s->ar, '\0', sizeof(s->ar));
1917 s->ar_flip_flop = 0;
1918 s->cr_index = 0;
1919 memset(s->cr, '\0', sizeof(s->cr));
1920 s->msr = 0;
1921 s->fcr = 0;
1922 s->st00 = 0;
1923 s->st01 = 0;
1924 s->dac_state = 0;
1925 s->dac_sub_index = 0;
1926 s->dac_read_index = 0;
1927 s->dac_write_index = 0;
1928 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1929 s->dac_8bit = 0;
1930 memset(s->palette, '\0', sizeof(s->palette));
1931 s->bank_offset = 0;
1932 #ifdef CONFIG_BOCHS_VBE
1933 s->vbe_index = 0;
1934 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1935 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1936 s->vbe_start_addr = 0;
1937 s->vbe_line_offset = 0;
1938 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1939 #endif
1940 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1941 s->graphic_mode = -1; /* force full update */
1942 s->shift_control = 0;
1943 s->double_scan = 0;
1944 s->line_offset = 0;
1945 s->line_compare = 0;
1946 s->start_addr = 0;
1947 s->plane_updated = 0;
1948 s->last_cw = 0;
1949 s->last_ch = 0;
1950 s->last_width = 0;
1951 s->last_height = 0;
1952 s->last_scr_width = 0;
1953 s->last_scr_height = 0;
1954 s->cursor_start = 0;
1955 s->cursor_end = 0;
1956 s->cursor_offset = 0;
1957 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1958 memset(s->last_palette, '\0', sizeof(s->last_palette));
1959 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1960 switch (vga_retrace_method) {
1961 case VGA_RETRACE_DUMB:
1962 break;
1963 case VGA_RETRACE_PRECISE:
1964 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1965 break;
1966 }
1967 vga_update_memory_access(s);
1968 }
1969
1970 static void vga_reset(void *opaque)
1971 {
1972 VGACommonState *s = opaque;
1973 vga_common_reset(s);
1974 }
1975
1976 #define TEXTMODE_X(x) ((x) % width)
1977 #define TEXTMODE_Y(x) ((x) / width)
1978 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1979 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1980 /* relay text rendering to the display driver
1981 * instead of doing a full vga_update_display() */
1982 static void vga_update_text(void *opaque, console_ch_t *chardata)
1983 {
1984 VGACommonState *s = opaque;
1985 int graphic_mode, i, cursor_offset, cursor_visible;
1986 int cw, cheight, width, height, size, c_min, c_max;
1987 uint32_t *src;
1988 console_ch_t *dst, val;
1989 char msg_buffer[80];
1990 int full_update = 0;
1991
1992 qemu_flush_coalesced_mmio_buffer();
1993
1994 if (!(s->ar_index & 0x20)) {
1995 graphic_mode = GMODE_BLANK;
1996 } else {
1997 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1998 }
1999 if (graphic_mode != s->graphic_mode) {
2000 s->graphic_mode = graphic_mode;
2001 full_update = 1;
2002 }
2003 if (s->last_width == -1) {
2004 s->last_width = 0;
2005 full_update = 1;
2006 }
2007
2008 switch (graphic_mode) {
2009 case GMODE_TEXT:
2010 /* TODO: update palette */
2011 full_update |= update_basic_params(s);
2012
2013 /* total width & height */
2014 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
2015 cw = 8;
2016 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
2017 cw = 9;
2018 }
2019 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
2020 cw = 16; /* NOTE: no 18 pixel wide */
2021 }
2022 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2023 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
2024 /* ugly hack for CGA 160x100x16 - explain me the logic */
2025 height = 100;
2026 } else {
2027 height = s->cr[VGA_CRTC_V_DISP_END] |
2028 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2029 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
2030 height = (height + 1) / cheight;
2031 }
2032
2033 size = (height * width);
2034 if (size > CH_ATTR_SIZE) {
2035 if (!full_update)
2036 return;
2037
2038 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2039 width, height);
2040 break;
2041 }
2042
2043 if (width != s->last_width || height != s->last_height ||
2044 cw != s->last_cw || cheight != s->last_ch) {
2045 s->last_scr_width = width * cw;
2046 s->last_scr_height = height * cheight;
2047 s->ds->surface->width = width;
2048 s->ds->surface->height = height;
2049 dpy_resize(s->ds);
2050 s->last_width = width;
2051 s->last_height = height;
2052 s->last_ch = cheight;
2053 s->last_cw = cw;
2054 full_update = 1;
2055 }
2056
2057 /* Update "hardware" cursor */
2058 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2059 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
2060 if (cursor_offset != s->cursor_offset ||
2061 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2062 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2063 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
2064 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2065 dpy_cursor(s->ds,
2066 TEXTMODE_X(cursor_offset),
2067 TEXTMODE_Y(cursor_offset));
2068 else
2069 dpy_cursor(s->ds, -1, -1);
2070 s->cursor_offset = cursor_offset;
2071 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2072 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
2073 }
2074
2075 src = (uint32_t *) s->vram_ptr + s->start_addr;
2076 dst = chardata;
2077
2078 if (full_update) {
2079 for (i = 0; i < size; src ++, dst ++, i ++)
2080 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
2081
2082 dpy_update(s->ds, 0, 0, width, height);
2083 } else {
2084 c_max = 0;
2085
2086 for (i = 0; i < size; src ++, dst ++, i ++) {
2087 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2088 if (*dst != val) {
2089 *dst = val;
2090 c_max = i;
2091 break;
2092 }
2093 }
2094 c_min = i;
2095 for (; i < size; src ++, dst ++, i ++) {
2096 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2097 if (*dst != val) {
2098 *dst = val;
2099 c_max = i;
2100 }
2101 }
2102
2103 if (c_min <= c_max) {
2104 i = TEXTMODE_Y(c_min);
2105 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2106 }
2107 }
2108
2109 return;
2110 case GMODE_GRAPH:
2111 if (!full_update)
2112 return;
2113
2114 s->get_resolution(s, &width, &height);
2115 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2116 width, height);
2117 break;
2118 case GMODE_BLANK:
2119 default:
2120 if (!full_update)
2121 return;
2122
2123 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2124 break;
2125 }
2126
2127 /* Display a message */
2128 s->last_width = 60;
2129 s->last_height = height = 3;
2130 dpy_cursor(s->ds, -1, -1);
2131 s->ds->surface->width = s->last_width;
2132 s->ds->surface->height = height;
2133 dpy_resize(s->ds);
2134
2135 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2136 console_write_ch(dst ++, ' ');
2137
2138 size = strlen(msg_buffer);
2139 width = (s->last_width - size) / 2;
2140 dst = chardata + s->last_width + width;
2141 for (i = 0; i < size; i ++)
2142 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2143
2144 dpy_update(s->ds, 0, 0, s->last_width, height);
2145 }
2146
2147 static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
2148 unsigned size)
2149 {
2150 VGACommonState *s = opaque;
2151
2152 return vga_mem_readb(s, addr);
2153 }
2154
2155 static void vga_mem_write(void *opaque, target_phys_addr_t addr,
2156 uint64_t data, unsigned size)
2157 {
2158 VGACommonState *s = opaque;
2159
2160 return vga_mem_writeb(s, addr, data);
2161 }
2162
2163 const MemoryRegionOps vga_mem_ops = {
2164 .read = vga_mem_read,
2165 .write = vga_mem_write,
2166 .endianness = DEVICE_LITTLE_ENDIAN,
2167 .impl = {
2168 .min_access_size = 1,
2169 .max_access_size = 1,
2170 },
2171 };
2172
2173 static int vga_common_post_load(void *opaque, int version_id)
2174 {
2175 VGACommonState *s = opaque;
2176
2177 /* force refresh */
2178 s->graphic_mode = -1;
2179 return 0;
2180 }
2181
2182 const VMStateDescription vmstate_vga_common = {
2183 .name = "vga",
2184 .version_id = 2,
2185 .minimum_version_id = 2,
2186 .minimum_version_id_old = 2,
2187 .post_load = vga_common_post_load,
2188 .fields = (VMStateField []) {
2189 VMSTATE_UINT32(latch, VGACommonState),
2190 VMSTATE_UINT8(sr_index, VGACommonState),
2191 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2192 VMSTATE_UINT8(gr_index, VGACommonState),
2193 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2194 VMSTATE_UINT8(ar_index, VGACommonState),
2195 VMSTATE_BUFFER(ar, VGACommonState),
2196 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2197 VMSTATE_UINT8(cr_index, VGACommonState),
2198 VMSTATE_BUFFER(cr, VGACommonState),
2199 VMSTATE_UINT8(msr, VGACommonState),
2200 VMSTATE_UINT8(fcr, VGACommonState),
2201 VMSTATE_UINT8(st00, VGACommonState),
2202 VMSTATE_UINT8(st01, VGACommonState),
2203
2204 VMSTATE_UINT8(dac_state, VGACommonState),
2205 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2206 VMSTATE_UINT8(dac_read_index, VGACommonState),
2207 VMSTATE_UINT8(dac_write_index, VGACommonState),
2208 VMSTATE_BUFFER(dac_cache, VGACommonState),
2209 VMSTATE_BUFFER(palette, VGACommonState),
2210
2211 VMSTATE_INT32(bank_offset, VGACommonState),
2212 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2213 #ifdef CONFIG_BOCHS_VBE
2214 VMSTATE_UINT16(vbe_index, VGACommonState),
2215 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2216 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2217 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2218 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2219 #endif
2220 VMSTATE_END_OF_LIST()
2221 }
2222 };
2223
2224 void vga_common_init(VGACommonState *s, int vga_ram_size)
2225 {
2226 int i, j, v, b;
2227
2228 for(i = 0;i < 256; i++) {
2229 v = 0;
2230 for(j = 0; j < 8; j++) {
2231 v |= ((i >> j) & 1) << (j * 4);
2232 }
2233 expand4[i] = v;
2234
2235 v = 0;
2236 for(j = 0; j < 4; j++) {
2237 v |= ((i >> (2 * j)) & 3) << (j * 4);
2238 }
2239 expand2[i] = v;
2240 }
2241 for(i = 0; i < 16; i++) {
2242 v = 0;
2243 for(j = 0; j < 4; j++) {
2244 b = ((i >> j) & 1);
2245 v |= b << (2 * j);
2246 v |= b << (2 * j + 1);
2247 }
2248 expand4to8[i] = v;
2249 }
2250
2251 #ifdef CONFIG_BOCHS_VBE
2252 s->is_vbe_vmstate = 1;
2253 #else
2254 s->is_vbe_vmstate = 0;
2255 #endif
2256 memory_region_init_ram(&s->vram, "vga.vram", vga_ram_size);
2257 vmstate_register_ram_global(&s->vram);
2258 xen_register_framebuffer(&s->vram);
2259 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2260 s->vram_size = vga_ram_size;
2261 s->get_bpp = vga_get_bpp;
2262 s->get_offsets = vga_get_offsets;
2263 s->get_resolution = vga_get_resolution;
2264 s->update = vga_update_display;
2265 s->invalidate = vga_invalidate_display;
2266 s->screen_dump = vga_screen_dump;
2267 s->text_update = vga_update_text;
2268 switch (vga_retrace_method) {
2269 case VGA_RETRACE_DUMB:
2270 s->retrace = vga_dumb_retrace;
2271 s->update_retrace_info = vga_dumb_update_retrace_info;
2272 break;
2273
2274 case VGA_RETRACE_PRECISE:
2275 s->retrace = vga_precise_retrace;
2276 s->update_retrace_info = vga_precise_update_retrace_info;
2277 break;
2278 }
2279 vga_dirty_log_start(s);
2280 }
2281
2282 static const MemoryRegionPortio vga_portio_list[] = {
2283 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2284 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2285 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2286 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2287 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2288 PORTIO_END_OF_LIST(),
2289 };
2290
2291 #ifdef CONFIG_BOCHS_VBE
2292 static const MemoryRegionPortio vbe_portio_list[] = {
2293 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2294 # ifdef TARGET_I386
2295 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2296 # else
2297 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2298 # endif
2299 PORTIO_END_OF_LIST(),
2300 };
2301 #endif /* CONFIG_BOCHS_VBE */
2302
2303 /* Used by both ISA and PCI */
2304 MemoryRegion *vga_init_io(VGACommonState *s,
2305 const MemoryRegionPortio **vga_ports,
2306 const MemoryRegionPortio **vbe_ports)
2307 {
2308 MemoryRegion *vga_mem;
2309
2310 *vga_ports = vga_portio_list;
2311 *vbe_ports = NULL;
2312 #ifdef CONFIG_BOCHS_VBE
2313 *vbe_ports = vbe_portio_list;
2314 #endif
2315
2316 vga_mem = g_malloc(sizeof(*vga_mem));
2317 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2318 "vga-lowmem", 0x20000);
2319
2320 return vga_mem;
2321 }
2322
2323 void vga_init(VGACommonState *s, MemoryRegion *address_space,
2324 MemoryRegion *address_space_io, bool init_vga_ports)
2325 {
2326 MemoryRegion *vga_io_memory;
2327 const MemoryRegionPortio *vga_ports, *vbe_ports;
2328 PortioList *vga_port_list = g_new(PortioList, 1);
2329 PortioList *vbe_port_list = g_new(PortioList, 1);
2330
2331 qemu_register_reset(vga_reset, s);
2332
2333 s->bank_offset = 0;
2334
2335 s->legacy_address_space = address_space;
2336
2337 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
2338 memory_region_add_subregion_overlap(address_space,
2339 isa_mem_base + 0x000a0000,
2340 vga_io_memory,
2341 1);
2342 memory_region_set_coalescing(vga_io_memory);
2343 if (init_vga_ports) {
2344 portio_list_init(vga_port_list, vga_ports, s, "vga");
2345 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2346 }
2347 if (vbe_ports) {
2348 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2349 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2350 }
2351 }
2352
2353 void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
2354 {
2355 #ifdef CONFIG_BOCHS_VBE
2356 /* XXX: use optimized standard vga accesses */
2357 memory_region_add_subregion(system_memory,
2358 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2359 &s->vram);
2360 s->vbe_mapped = 1;
2361 #endif
2362 }
2363 /********************************************************/
2364 /* vga screen dump */
2365
2366 int ppm_save(const char *filename, struct DisplaySurface *ds)
2367 {
2368 FILE *f;
2369 uint8_t *d, *d1;
2370 uint32_t v;
2371 int y, x;
2372 uint8_t r, g, b;
2373 int ret;
2374 char *linebuf, *pbuf;
2375
2376 trace_ppm_save(filename, ds);
2377 f = fopen(filename, "wb");
2378 if (!f)
2379 return -1;
2380 fprintf(f, "P6\n%d %d\n%d\n",
2381 ds->width, ds->height, 255);
2382 linebuf = g_malloc(ds->width * 3);
2383 d1 = ds->data;
2384 for(y = 0; y < ds->height; y++) {
2385 d = d1;
2386 pbuf = linebuf;
2387 for(x = 0; x < ds->width; x++) {
2388 if (ds->pf.bits_per_pixel == 32)
2389 v = *(uint32_t *)d;
2390 else
2391 v = (uint32_t) (*(uint16_t *)d);
2392 /* Limited to 8 or fewer bits per channel: */
2393 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2394 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2395 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
2396 *pbuf++ = r;
2397 *pbuf++ = g;
2398 *pbuf++ = b;
2399 d += ds->pf.bytes_per_pixel;
2400 }
2401 d1 += ds->linesize;
2402 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2403 (void)ret;
2404 }
2405 g_free(linebuf);
2406 fclose(f);
2407 return 0;
2408 }
2409
2410 /* save the vga display in a PPM image even if no display is
2411 available */
2412 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch)
2413 {
2414 VGACommonState *s = opaque;
2415
2416 if (cswitch) {
2417 vga_invalidate_display(s);
2418 }
2419 vga_hw_update();
2420 ppm_save(filename, s->ds->surface);
2421 }
QEmu