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Merge remote-tracking branch 'sstabellini/disk_io' into staging
[qemu.git] / hw / qxl.c
blob47a162e4795c1882a4de2812fcdb2c7549a0d1b9
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26 #include "trace.h"
27
28 #include "qxl.h"
29
30 #undef SPICE_RING_PROD_ITEM
31 #define SPICE_RING_PROD_ITEM(r, ret) { \
32 typeof(r) start = r; \
33 typeof(r) end = r + 1; \
34 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
35 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
36 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
37 abort(); \
38 } \
39 ret = &m_item->el; \
40 }
41
42 #undef SPICE_RING_CONS_ITEM
43 #define SPICE_RING_CONS_ITEM(r, ret) { \
44 typeof(r) start = r; \
45 typeof(r) end = r + 1; \
46 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
47 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
48 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
49 abort(); \
50 } \
51 ret = &m_item->el; \
52 }
53
54 #undef ALIGN
55 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
56
57 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
58
59 #define QXL_MODE(_x, _y, _b, _o) \
60 { .x_res = _x, \
61 .y_res = _y, \
62 .bits = _b, \
63 .stride = (_x) * (_b) / 8, \
64 .x_mili = PIXEL_SIZE * (_x), \
65 .y_mili = PIXEL_SIZE * (_y), \
66 .orientation = _o, \
67 }
68
69 #define QXL_MODE_16_32(x_res, y_res, orientation) \
70 QXL_MODE(x_res, y_res, 16, orientation), \
71 QXL_MODE(x_res, y_res, 32, orientation)
72
73 #define QXL_MODE_EX(x_res, y_res) \
74 QXL_MODE_16_32(x_res, y_res, 0), \
75 QXL_MODE_16_32(y_res, x_res, 1), \
76 QXL_MODE_16_32(x_res, y_res, 2), \
77 QXL_MODE_16_32(y_res, x_res, 3)
78
79 static QXLMode qxl_modes[] = {
80 QXL_MODE_EX(640, 480),
81 QXL_MODE_EX(800, 480),
82 QXL_MODE_EX(800, 600),
83 QXL_MODE_EX(832, 624),
84 QXL_MODE_EX(960, 640),
85 QXL_MODE_EX(1024, 600),
86 QXL_MODE_EX(1024, 768),
87 QXL_MODE_EX(1152, 864),
88 QXL_MODE_EX(1152, 870),
89 QXL_MODE_EX(1280, 720),
90 QXL_MODE_EX(1280, 760),
91 QXL_MODE_EX(1280, 768),
92 QXL_MODE_EX(1280, 800),
93 QXL_MODE_EX(1280, 960),
94 QXL_MODE_EX(1280, 1024),
95 QXL_MODE_EX(1360, 768),
96 QXL_MODE_EX(1366, 768),
97 QXL_MODE_EX(1400, 1050),
98 QXL_MODE_EX(1440, 900),
99 QXL_MODE_EX(1600, 900),
100 QXL_MODE_EX(1600, 1200),
101 QXL_MODE_EX(1680, 1050),
102 QXL_MODE_EX(1920, 1080),
103 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
104 /* these modes need more than 8 MB video memory */
105 QXL_MODE_EX(1920, 1200),
106 QXL_MODE_EX(1920, 1440),
107 QXL_MODE_EX(2048, 1536),
108 QXL_MODE_EX(2560, 1440),
109 QXL_MODE_EX(2560, 1600),
110 #endif
111 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
112 /* these modes need more than 16 MB video memory */
113 QXL_MODE_EX(2560, 2048),
114 QXL_MODE_EX(2800, 2100),
115 QXL_MODE_EX(3200, 2400),
116 #endif
117 };
118
119 static PCIQXLDevice *qxl0;
120
121 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
122 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
123 static void qxl_reset_memslots(PCIQXLDevice *d);
124 static void qxl_reset_surfaces(PCIQXLDevice *d);
125 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
126
127 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
128 {
129 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
130 if (qxl->guestdebug) {
131 va_list ap;
132 va_start(ap, msg);
133 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
134 vfprintf(stderr, msg, ap);
135 fprintf(stderr, "\n");
136 va_end(ap);
137 }
138 }
139
140
141 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
142 struct QXLRect *area, struct QXLRect *dirty_rects,
143 uint32_t num_dirty_rects,
144 uint32_t clear_dirty_region,
145 qxl_async_io async, struct QXLCookie *cookie)
146 {
147 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
148 area->top, area->bottom);
149 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
150 clear_dirty_region);
151 if (async == QXL_SYNC) {
152 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
153 dirty_rects, num_dirty_rects, clear_dirty_region);
154 } else {
155 assert(cookie != NULL);
156 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
157 clear_dirty_region, (uintptr_t)cookie);
158 }
159 }
160
161 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
162 uint32_t id)
163 {
164 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
165 qemu_mutex_lock(&qxl->track_lock);
166 qxl->guest_surfaces.cmds[id] = 0;
167 qxl->guest_surfaces.count--;
168 qemu_mutex_unlock(&qxl->track_lock);
169 }
170
171 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
172 qxl_async_io async)
173 {
174 QXLCookie *cookie;
175
176 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
177 if (async) {
178 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
179 QXL_IO_DESTROY_SURFACE_ASYNC);
180 cookie->u.surface_id = id;
181 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
182 } else {
183 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
184 }
185 }
186
187 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
188 {
189 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
190 qxl->num_free_res);
191 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
192 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
193 QXL_IO_FLUSH_SURFACES_ASYNC));
194 }
195
196 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
197 uint32_t count)
198 {
199 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
200 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
201 }
202
203 void qxl_spice_oom(PCIQXLDevice *qxl)
204 {
205 trace_qxl_spice_oom(qxl->id);
206 qxl->ssd.worker->oom(qxl->ssd.worker);
207 }
208
209 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
210 {
211 trace_qxl_spice_reset_memslots(qxl->id);
212 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
213 }
214
215 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
216 {
217 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
218 qemu_mutex_lock(&qxl->track_lock);
219 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
220 qxl->guest_surfaces.count = 0;
221 qemu_mutex_unlock(&qxl->track_lock);
222 }
223
224 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
225 {
226 trace_qxl_spice_destroy_surfaces(qxl->id, async);
227 if (async) {
228 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
229 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
230 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
231 } else {
232 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
233 qxl_spice_destroy_surfaces_complete(qxl);
234 }
235 }
236
237 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
238 {
239 trace_qxl_spice_reset_image_cache(qxl->id);
240 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
241 }
242
243 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
244 {
245 trace_qxl_spice_reset_cursor(qxl->id);
246 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
247 qemu_mutex_lock(&qxl->track_lock);
248 qxl->guest_cursor = 0;
249 qemu_mutex_unlock(&qxl->track_lock);
250 }
251
252
253 static inline uint32_t msb_mask(uint32_t val)
254 {
255 uint32_t mask;
256
257 do {
258 mask = ~(val - 1) & val;
259 val &= ~mask;
260 } while (mask < val);
261
262 return mask;
263 }
264
265 static ram_addr_t qxl_rom_size(void)
266 {
267 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
268 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
269 rom_size = msb_mask(rom_size * 2 - 1);
270 return rom_size;
271 }
272
273 static void init_qxl_rom(PCIQXLDevice *d)
274 {
275 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
276 QXLModes *modes = (QXLModes *)(rom + 1);
277 uint32_t ram_header_size;
278 uint32_t surface0_area_size;
279 uint32_t num_pages;
280 uint32_t fb, maxfb = 0;
281 int i;
282
283 memset(rom, 0, d->rom_size);
284
285 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
286 rom->id = cpu_to_le32(d->id);
287 rom->log_level = cpu_to_le32(d->guestdebug);
288 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
289
290 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
291 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
292 rom->slots_start = 1;
293 rom->slots_end = NUM_MEMSLOTS - 1;
294 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
295
296 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
297 for (i = 0; i < modes->n_modes; i++) {
298 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
299 if (maxfb < fb) {
300 maxfb = fb;
301 }
302 modes->modes[i].id = cpu_to_le32(i);
303 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
304 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
305 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
306 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
307 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
308 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
309 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
310 }
311 if (maxfb < VGA_RAM_SIZE && d->id == 0)
312 maxfb = VGA_RAM_SIZE;
313
314 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
315 surface0_area_size = ALIGN(maxfb, 4096);
316 num_pages = d->vga.vram_size;
317 num_pages -= ram_header_size;
318 num_pages -= surface0_area_size;
319 num_pages = num_pages / TARGET_PAGE_SIZE;
320
321 rom->draw_area_offset = cpu_to_le32(0);
322 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
323 rom->pages_offset = cpu_to_le32(surface0_area_size);
324 rom->num_pages = cpu_to_le32(num_pages);
325 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
326
327 d->shadow_rom = *rom;
328 d->rom = rom;
329 d->modes = modes;
330 }
331
332 static void init_qxl_ram(PCIQXLDevice *d)
333 {
334 uint8_t *buf;
335 uint64_t *item;
336
337 buf = d->vga.vram_ptr;
338 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
339 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
340 d->ram->int_pending = cpu_to_le32(0);
341 d->ram->int_mask = cpu_to_le32(0);
342 d->ram->update_surface = 0;
343 SPICE_RING_INIT(&d->ram->cmd_ring);
344 SPICE_RING_INIT(&d->ram->cursor_ring);
345 SPICE_RING_INIT(&d->ram->release_ring);
346 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
347 *item = 0;
348 qxl_ring_set_dirty(d);
349 }
350
351 /* can be called from spice server thread context */
352 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
353 {
354 memory_region_set_dirty(mr, addr, end - addr);
355 }
356
357 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
358 {
359 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
360 }
361
362 /* called from spice server thread context only */
363 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
364 {
365 void *base = qxl->vga.vram_ptr;
366 intptr_t offset;
367
368 offset = ptr - base;
369 offset &= ~(TARGET_PAGE_SIZE-1);
370 assert(offset < qxl->vga.vram_size);
371 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
372 }
373
374 /* can be called from spice server thread context */
375 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
376 {
377 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
378 ram_addr_t end = qxl->vga.vram_size;
379 qxl_set_dirty(&qxl->vga.vram, addr, end);
380 }
381
382 /*
383 * keep track of some command state, for savevm/loadvm.
384 * called from spice server thread context only
385 */
386 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
387 {
388 switch (le32_to_cpu(ext->cmd.type)) {
389 case QXL_CMD_SURFACE:
390 {
391 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
392 uint32_t id = le32_to_cpu(cmd->surface_id);
393 PANIC_ON(id >= NUM_SURFACES);
394 qemu_mutex_lock(&qxl->track_lock);
395 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
396 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
397 qxl->guest_surfaces.count++;
398 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
399 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
400 }
401 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
402 qxl->guest_surfaces.cmds[id] = 0;
403 qxl->guest_surfaces.count--;
404 }
405 qemu_mutex_unlock(&qxl->track_lock);
406 break;
407 }
408 case QXL_CMD_CURSOR:
409 {
410 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
411 if (cmd->type == QXL_CURSOR_SET) {
412 qemu_mutex_lock(&qxl->track_lock);
413 qxl->guest_cursor = ext->cmd.data;
414 qemu_mutex_unlock(&qxl->track_lock);
415 }
416 break;
417 }
418 }
419 }
420
421 /* spice display interface callbacks */
422
423 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
424 {
425 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
426
427 trace_qxl_interface_attach_worker(qxl->id);
428 qxl->ssd.worker = qxl_worker;
429 }
430
431 static void interface_set_compression_level(QXLInstance *sin, int level)
432 {
433 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
434
435 trace_qxl_interface_set_compression_level(qxl->id, level);
436 qxl->shadow_rom.compression_level = cpu_to_le32(level);
437 qxl->rom->compression_level = cpu_to_le32(level);
438 qxl_rom_set_dirty(qxl);
439 }
440
441 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
442 {
443 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
444
445 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
446 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
447 qxl->rom->mm_clock = cpu_to_le32(mm_time);
448 qxl_rom_set_dirty(qxl);
449 }
450
451 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
452 {
453 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
454
455 trace_qxl_interface_get_init_info(qxl->id);
456 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
457 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
458 info->num_memslots = NUM_MEMSLOTS;
459 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
460 info->internal_groupslot_id = 0;
461 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
462 info->n_surfaces = NUM_SURFACES;
463 }
464
465 static const char *qxl_mode_to_string(int mode)
466 {
467 switch (mode) {
468 case QXL_MODE_COMPAT:
469 return "compat";
470 case QXL_MODE_NATIVE:
471 return "native";
472 case QXL_MODE_UNDEFINED:
473 return "undefined";
474 case QXL_MODE_VGA:
475 return "vga";
476 }
477 return "INVALID";
478 }
479
480 static const char *io_port_to_string(uint32_t io_port)
481 {
482 if (io_port >= QXL_IO_RANGE_SIZE) {
483 return "out of range";
484 }
485 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
486 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
487 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
488 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
489 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
490 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
491 [QXL_IO_RESET] = "QXL_IO_RESET",
492 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
493 [QXL_IO_LOG] = "QXL_IO_LOG",
494 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
495 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
496 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
497 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
498 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
499 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
500 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
501 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
502 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
503 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
504 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
505 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
506 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
507 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
508 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
509 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
510 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
511 };
512 return io_port_to_string[io_port];
513 }
514
515 /* called from spice server thread context only */
516 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
517 {
518 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
519 SimpleSpiceUpdate *update;
520 QXLCommandRing *ring;
521 QXLCommand *cmd;
522 int notify, ret;
523
524 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
525
526 switch (qxl->mode) {
527 case QXL_MODE_VGA:
528 ret = false;
529 qemu_mutex_lock(&qxl->ssd.lock);
530 if (qxl->ssd.update != NULL) {
531 update = qxl->ssd.update;
532 qxl->ssd.update = NULL;
533 *ext = update->ext;
534 ret = true;
535 }
536 qemu_mutex_unlock(&qxl->ssd.lock);
537 if (ret) {
538 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
539 qxl_log_command(qxl, "vga", ext);
540 }
541 return ret;
542 case QXL_MODE_COMPAT:
543 case QXL_MODE_NATIVE:
544 case QXL_MODE_UNDEFINED:
545 ring = &qxl->ram->cmd_ring;
546 if (SPICE_RING_IS_EMPTY(ring)) {
547 return false;
548 }
549 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
550 SPICE_RING_CONS_ITEM(ring, cmd);
551 ext->cmd = *cmd;
552 ext->group_id = MEMSLOT_GROUP_GUEST;
553 ext->flags = qxl->cmdflags;
554 SPICE_RING_POP(ring, notify);
555 qxl_ring_set_dirty(qxl);
556 if (notify) {
557 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
558 }
559 qxl->guest_primary.commands++;
560 qxl_track_command(qxl, ext);
561 qxl_log_command(qxl, "cmd", ext);
562 return true;
563 default:
564 return false;
565 }
566 }
567
568 /* called from spice server thread context only */
569 static int interface_req_cmd_notification(QXLInstance *sin)
570 {
571 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
572 int wait = 1;
573
574 trace_qxl_ring_command_req_notification(qxl->id);
575 switch (qxl->mode) {
576 case QXL_MODE_COMPAT:
577 case QXL_MODE_NATIVE:
578 case QXL_MODE_UNDEFINED:
579 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
580 qxl_ring_set_dirty(qxl);
581 break;
582 default:
583 /* nothing */
584 break;
585 }
586 return wait;
587 }
588
589 /* called from spice server thread context only */
590 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
591 {
592 QXLReleaseRing *ring = &d->ram->release_ring;
593 uint64_t *item;
594 int notify;
595
596 #define QXL_FREE_BUNCH_SIZE 32
597
598 if (ring->prod - ring->cons + 1 == ring->num_items) {
599 /* ring full -- can't push */
600 return;
601 }
602 if (!flush && d->oom_running) {
603 /* collect everything from oom handler before pushing */
604 return;
605 }
606 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
607 /* collect a bit more before pushing */
608 return;
609 }
610
611 SPICE_RING_PUSH(ring, notify);
612 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
613 d->guest_surfaces.count, d->num_free_res,
614 d->last_release, notify ? "yes" : "no");
615 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
616 ring->num_items, ring->prod, ring->cons);
617 if (notify) {
618 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
619 }
620 SPICE_RING_PROD_ITEM(ring, item);
621 *item = 0;
622 d->num_free_res = 0;
623 d->last_release = NULL;
624 qxl_ring_set_dirty(d);
625 }
626
627 /* called from spice server thread context only */
628 static void interface_release_resource(QXLInstance *sin,
629 struct QXLReleaseInfoExt ext)
630 {
631 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
632 QXLReleaseRing *ring;
633 uint64_t *item, id;
634
635 if (ext.group_id == MEMSLOT_GROUP_HOST) {
636 /* host group -> vga mode update request */
637 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
638 return;
639 }
640
641 /*
642 * ext->info points into guest-visible memory
643 * pci bar 0, $command.release_info
644 */
645 ring = &qxl->ram->release_ring;
646 SPICE_RING_PROD_ITEM(ring, item);
647 if (*item == 0) {
648 /* stick head into the ring */
649 id = ext.info->id;
650 ext.info->next = 0;
651 qxl_ram_set_dirty(qxl, &ext.info->next);
652 *item = id;
653 qxl_ring_set_dirty(qxl);
654 } else {
655 /* append item to the list */
656 qxl->last_release->next = ext.info->id;
657 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
658 ext.info->next = 0;
659 qxl_ram_set_dirty(qxl, &ext.info->next);
660 }
661 qxl->last_release = ext.info;
662 qxl->num_free_res++;
663 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
664 qxl_push_free_res(qxl, 0);
665 }
666
667 /* called from spice server thread context only */
668 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
669 {
670 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
671 QXLCursorRing *ring;
672 QXLCommand *cmd;
673 int notify;
674
675 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
676
677 switch (qxl->mode) {
678 case QXL_MODE_COMPAT:
679 case QXL_MODE_NATIVE:
680 case QXL_MODE_UNDEFINED:
681 ring = &qxl->ram->cursor_ring;
682 if (SPICE_RING_IS_EMPTY(ring)) {
683 return false;
684 }
685 SPICE_RING_CONS_ITEM(ring, cmd);
686 ext->cmd = *cmd;
687 ext->group_id = MEMSLOT_GROUP_GUEST;
688 ext->flags = qxl->cmdflags;
689 SPICE_RING_POP(ring, notify);
690 qxl_ring_set_dirty(qxl);
691 if (notify) {
692 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
693 }
694 qxl->guest_primary.commands++;
695 qxl_track_command(qxl, ext);
696 qxl_log_command(qxl, "csr", ext);
697 if (qxl->id == 0) {
698 qxl_render_cursor(qxl, ext);
699 }
700 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
701 return true;
702 default:
703 return false;
704 }
705 }
706
707 /* called from spice server thread context only */
708 static int interface_req_cursor_notification(QXLInstance *sin)
709 {
710 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
711 int wait = 1;
712
713 trace_qxl_ring_cursor_req_notification(qxl->id);
714 switch (qxl->mode) {
715 case QXL_MODE_COMPAT:
716 case QXL_MODE_NATIVE:
717 case QXL_MODE_UNDEFINED:
718 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
719 qxl_ring_set_dirty(qxl);
720 break;
721 default:
722 /* nothing */
723 break;
724 }
725 return wait;
726 }
727
728 /* called from spice server thread context */
729 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
730 {
731 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
732 abort();
733 }
734
735 /* called from spice server thread context only */
736 static int interface_flush_resources(QXLInstance *sin)
737 {
738 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
739 int ret;
740
741 ret = qxl->num_free_res;
742 if (ret) {
743 qxl_push_free_res(qxl, 1);
744 }
745 return ret;
746 }
747
748 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
749
750 /* called from spice server thread context only */
751 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
752 {
753 uint32_t current_async;
754
755 qemu_mutex_lock(&qxl->async_lock);
756 current_async = qxl->current_async;
757 qxl->current_async = QXL_UNDEFINED_IO;
758 qemu_mutex_unlock(&qxl->async_lock);
759
760 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
761 if (!cookie) {
762 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
763 return;
764 }
765 if (cookie && current_async != cookie->io) {
766 fprintf(stderr,
767 "qxl: %s: error: current_async = %d != %" PRId64 " = cookie->io\n",
768 __func__, current_async, cookie->io);
769 }
770 switch (current_async) {
771 case QXL_IO_MEMSLOT_ADD_ASYNC:
772 case QXL_IO_DESTROY_PRIMARY_ASYNC:
773 case QXL_IO_UPDATE_AREA_ASYNC:
774 case QXL_IO_FLUSH_SURFACES_ASYNC:
775 break;
776 case QXL_IO_CREATE_PRIMARY_ASYNC:
777 qxl_create_guest_primary_complete(qxl);
778 break;
779 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
780 qxl_spice_destroy_surfaces_complete(qxl);
781 break;
782 case QXL_IO_DESTROY_SURFACE_ASYNC:
783 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
784 break;
785 default:
786 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
787 current_async);
788 }
789 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
790 }
791
792 /* called from spice server thread context only */
793 static void interface_update_area_complete(QXLInstance *sin,
794 uint32_t surface_id,
795 QXLRect *dirty, uint32_t num_updated_rects)
796 {
797 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
798 int i;
799 int qxl_i;
800
801 qemu_mutex_lock(&qxl->ssd.lock);
802 if (surface_id != 0 || !qxl->render_update_cookie_num) {
803 qemu_mutex_unlock(&qxl->ssd.lock);
804 return;
805 }
806 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
807 dirty->right, dirty->top, dirty->bottom);
808 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
809 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
810 /*
811 * overflow - treat this as a full update. Not expected to be common.
812 */
813 trace_qxl_interface_update_area_complete_overflow(qxl->id,
814 QXL_NUM_DIRTY_RECTS);
815 qxl->guest_primary.resized = 1;
816 }
817 if (qxl->guest_primary.resized) {
818 /*
819 * Don't bother copying or scheduling the bh since we will flip
820 * the whole area anyway on completion of the update_area async call
821 */
822 qemu_mutex_unlock(&qxl->ssd.lock);
823 return;
824 }
825 qxl_i = qxl->num_dirty_rects;
826 for (i = 0; i < num_updated_rects; i++) {
827 qxl->dirty[qxl_i++] = dirty[i];
828 }
829 qxl->num_dirty_rects += num_updated_rects;
830 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
831 qxl->num_dirty_rects);
832 qemu_bh_schedule(qxl->update_area_bh);
833 qemu_mutex_unlock(&qxl->ssd.lock);
834 }
835
836 /* called from spice server thread context only */
837 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
838 {
839 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
840 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
841
842 switch (cookie->type) {
843 case QXL_COOKIE_TYPE_IO:
844 interface_async_complete_io(qxl, cookie);
845 g_free(cookie);
846 break;
847 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
848 qxl_render_update_area_done(qxl, cookie);
849 break;
850 default:
851 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
852 __func__, cookie->type);
853 g_free(cookie);
854 }
855 }
856
857 static const QXLInterface qxl_interface = {
858 .base.type = SPICE_INTERFACE_QXL,
859 .base.description = "qxl gpu",
860 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
861 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
862
863 .attache_worker = interface_attach_worker,
864 .set_compression_level = interface_set_compression_level,
865 .set_mm_time = interface_set_mm_time,
866 .get_init_info = interface_get_init_info,
867
868 /* the callbacks below are called from spice server thread context */
869 .get_command = interface_get_command,
870 .req_cmd_notification = interface_req_cmd_notification,
871 .release_resource = interface_release_resource,
872 .get_cursor_command = interface_get_cursor_command,
873 .req_cursor_notification = interface_req_cursor_notification,
874 .notify_update = interface_notify_update,
875 .flush_resources = interface_flush_resources,
876 .async_complete = interface_async_complete,
877 .update_area_complete = interface_update_area_complete,
878 };
879
880 static void qxl_enter_vga_mode(PCIQXLDevice *d)
881 {
882 if (d->mode == QXL_MODE_VGA) {
883 return;
884 }
885 trace_qxl_enter_vga_mode(d->id);
886 qemu_spice_create_host_primary(&d->ssd);
887 d->mode = QXL_MODE_VGA;
888 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
889 }
890
891 static void qxl_exit_vga_mode(PCIQXLDevice *d)
892 {
893 if (d->mode != QXL_MODE_VGA) {
894 return;
895 }
896 trace_qxl_exit_vga_mode(d->id);
897 qxl_destroy_primary(d, QXL_SYNC);
898 }
899
900 static void qxl_update_irq(PCIQXLDevice *d)
901 {
902 uint32_t pending = le32_to_cpu(d->ram->int_pending);
903 uint32_t mask = le32_to_cpu(d->ram->int_mask);
904 int level = !!(pending & mask);
905 qemu_set_irq(d->pci.irq[0], level);
906 qxl_ring_set_dirty(d);
907 }
908
909 static void qxl_check_state(PCIQXLDevice *d)
910 {
911 QXLRam *ram = d->ram;
912
913 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
914 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
915 }
916
917 static void qxl_reset_state(PCIQXLDevice *d)
918 {
919 QXLRom *rom = d->rom;
920
921 qxl_check_state(d);
922 d->shadow_rom.update_id = cpu_to_le32(0);
923 *rom = d->shadow_rom;
924 qxl_rom_set_dirty(d);
925 init_qxl_ram(d);
926 d->num_free_res = 0;
927 d->last_release = NULL;
928 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
929 }
930
931 static void qxl_soft_reset(PCIQXLDevice *d)
932 {
933 trace_qxl_soft_reset(d->id);
934 qxl_check_state(d);
935
936 if (d->id == 0) {
937 qxl_enter_vga_mode(d);
938 } else {
939 d->mode = QXL_MODE_UNDEFINED;
940 }
941 }
942
943 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
944 {
945 trace_qxl_hard_reset(d->id, loadvm);
946
947 qxl_spice_reset_cursor(d);
948 qxl_spice_reset_image_cache(d);
949 qxl_reset_surfaces(d);
950 qxl_reset_memslots(d);
951
952 /* pre loadvm reset must not touch QXLRam. This lives in
953 * device memory, is migrated together with RAM and thus
954 * already loaded at this point */
955 if (!loadvm) {
956 qxl_reset_state(d);
957 }
958 qemu_spice_create_host_memslot(&d->ssd);
959 qxl_soft_reset(d);
960 }
961
962 static void qxl_reset_handler(DeviceState *dev)
963 {
964 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
965
966 qxl_hard_reset(d, 0);
967 }
968
969 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
970 {
971 VGACommonState *vga = opaque;
972 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
973
974 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
975 if (qxl->mode != QXL_MODE_VGA) {
976 qxl_destroy_primary(qxl, QXL_SYNC);
977 qxl_soft_reset(qxl);
978 }
979 vga_ioport_write(opaque, addr, val);
980 }
981
982 static const MemoryRegionPortio qxl_vga_portio_list[] = {
983 { 0x04, 2, 1, .read = vga_ioport_read,
984 .write = qxl_vga_ioport_write }, /* 3b4 */
985 { 0x0a, 1, 1, .read = vga_ioport_read,
986 .write = qxl_vga_ioport_write }, /* 3ba */
987 { 0x10, 16, 1, .read = vga_ioport_read,
988 .write = qxl_vga_ioport_write }, /* 3c0 */
989 { 0x24, 2, 1, .read = vga_ioport_read,
990 .write = qxl_vga_ioport_write }, /* 3d4 */
991 { 0x2a, 1, 1, .read = vga_ioport_read,
992 .write = qxl_vga_ioport_write }, /* 3da */
993 PORTIO_END_OF_LIST(),
994 };
995
996 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
997 qxl_async_io async)
998 {
999 static const int regions[] = {
1000 QXL_RAM_RANGE_INDEX,
1001 QXL_VRAM_RANGE_INDEX,
1002 QXL_VRAM64_RANGE_INDEX,
1003 };
1004 uint64_t guest_start;
1005 uint64_t guest_end;
1006 int pci_region;
1007 pcibus_t pci_start;
1008 pcibus_t pci_end;
1009 intptr_t virt_start;
1010 QXLDevMemSlot memslot;
1011 int i;
1012
1013 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1014 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1015
1016 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1017
1018 PANIC_ON(slot_id >= NUM_MEMSLOTS);
1019 PANIC_ON(guest_start > guest_end);
1020
1021 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1022 pci_region = regions[i];
1023 pci_start = d->pci.io_regions[pci_region].addr;
1024 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1025 /* mapped? */
1026 if (pci_start == -1) {
1027 continue;
1028 }
1029 /* start address in range ? */
1030 if (guest_start < pci_start || guest_start > pci_end) {
1031 continue;
1032 }
1033 /* end address in range ? */
1034 if (guest_end > pci_end) {
1035 continue;
1036 }
1037 /* passed */
1038 break;
1039 }
1040 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
1041
1042 switch (pci_region) {
1043 case QXL_RAM_RANGE_INDEX:
1044 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1045 break;
1046 case QXL_VRAM_RANGE_INDEX:
1047 case 4 /* vram 64bit */:
1048 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1049 break;
1050 default:
1051 /* should not happen */
1052 abort();
1053 }
1054
1055 memslot.slot_id = slot_id;
1056 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1057 memslot.virt_start = virt_start + (guest_start - pci_start);
1058 memslot.virt_end = virt_start + (guest_end - pci_start);
1059 memslot.addr_delta = memslot.virt_start - delta;
1060 memslot.generation = d->rom->slot_generation = 0;
1061 qxl_rom_set_dirty(d);
1062
1063 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1064 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1065 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1066 d->guest_slots[slot_id].delta = delta;
1067 d->guest_slots[slot_id].active = 1;
1068 }
1069
1070 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1071 {
1072 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1073 d->guest_slots[slot_id].active = 0;
1074 }
1075
1076 static void qxl_reset_memslots(PCIQXLDevice *d)
1077 {
1078 qxl_spice_reset_memslots(d);
1079 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1080 }
1081
1082 static void qxl_reset_surfaces(PCIQXLDevice *d)
1083 {
1084 trace_qxl_reset_surfaces(d->id);
1085 d->mode = QXL_MODE_UNDEFINED;
1086 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1087 }
1088
1089 /* can be also called from spice server thread context */
1090 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1091 {
1092 uint64_t phys = le64_to_cpu(pqxl);
1093 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1094 uint64_t offset = phys & 0xffffffffffff;
1095
1096 switch (group_id) {
1097 case MEMSLOT_GROUP_HOST:
1098 return (void *)(intptr_t)offset;
1099 case MEMSLOT_GROUP_GUEST:
1100 PANIC_ON(slot >= NUM_MEMSLOTS);
1101 PANIC_ON(!qxl->guest_slots[slot].active);
1102 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1103 offset -= qxl->guest_slots[slot].delta;
1104 PANIC_ON(offset > qxl->guest_slots[slot].size)
1105 return qxl->guest_slots[slot].ptr + offset;
1106 default:
1107 PANIC_ON(1);
1108 }
1109 }
1110
1111 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1112 {
1113 /* for local rendering */
1114 qxl_render_resize(qxl);
1115 }
1116
1117 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1118 qxl_async_io async)
1119 {
1120 QXLDevSurfaceCreate surface;
1121 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1122
1123 assert(qxl->mode != QXL_MODE_NATIVE);
1124 qxl_exit_vga_mode(qxl);
1125
1126 surface.format = le32_to_cpu(sc->format);
1127 surface.height = le32_to_cpu(sc->height);
1128 surface.mem = le64_to_cpu(sc->mem);
1129 surface.position = le32_to_cpu(sc->position);
1130 surface.stride = le32_to_cpu(sc->stride);
1131 surface.width = le32_to_cpu(sc->width);
1132 surface.type = le32_to_cpu(sc->type);
1133 surface.flags = le32_to_cpu(sc->flags);
1134 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1135 sc->format, sc->position);
1136 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1137 sc->flags);
1138
1139 surface.mouse_mode = true;
1140 surface.group_id = MEMSLOT_GROUP_GUEST;
1141 if (loadvm) {
1142 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1143 }
1144
1145 qxl->mode = QXL_MODE_NATIVE;
1146 qxl->cmdflags = 0;
1147 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1148
1149 if (async == QXL_SYNC) {
1150 qxl_create_guest_primary_complete(qxl);
1151 }
1152 }
1153
1154 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1155 * done (in QXL_SYNC case), 0 otherwise. */
1156 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1157 {
1158 if (d->mode == QXL_MODE_UNDEFINED) {
1159 return 0;
1160 }
1161 trace_qxl_destroy_primary(d->id);
1162 d->mode = QXL_MODE_UNDEFINED;
1163 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1164 qxl_spice_reset_cursor(d);
1165 return 1;
1166 }
1167
1168 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1169 {
1170 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1171 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1172 QXLMode *mode = d->modes->modes + modenr;
1173 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1174 QXLMemSlot slot = {
1175 .mem_start = start,
1176 .mem_end = end
1177 };
1178 QXLSurfaceCreate surface = {
1179 .width = mode->x_res,
1180 .height = mode->y_res,
1181 .stride = -mode->x_res * 4,
1182 .format = SPICE_SURFACE_FMT_32_xRGB,
1183 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1184 .mouse_mode = true,
1185 .mem = devmem + d->shadow_rom.draw_area_offset,
1186 };
1187
1188 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1189 devmem);
1190 if (!loadvm) {
1191 qxl_hard_reset(d, 0);
1192 }
1193
1194 d->guest_slots[0].slot = slot;
1195 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1196
1197 d->guest_primary.surface = surface;
1198 qxl_create_guest_primary(d, 0, QXL_SYNC);
1199
1200 d->mode = QXL_MODE_COMPAT;
1201 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1202 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1203 if (mode->bits == 16) {
1204 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1205 }
1206 #endif
1207 d->shadow_rom.mode = cpu_to_le32(modenr);
1208 d->rom->mode = cpu_to_le32(modenr);
1209 qxl_rom_set_dirty(d);
1210 }
1211
1212 static void ioport_write(void *opaque, target_phys_addr_t addr,
1213 uint64_t val, unsigned size)
1214 {
1215 PCIQXLDevice *d = opaque;
1216 uint32_t io_port = addr;
1217 qxl_async_io async = QXL_SYNC;
1218 uint32_t orig_io_port = io_port;
1219
1220 switch (io_port) {
1221 case QXL_IO_RESET:
1222 case QXL_IO_SET_MODE:
1223 case QXL_IO_MEMSLOT_ADD:
1224 case QXL_IO_MEMSLOT_DEL:
1225 case QXL_IO_CREATE_PRIMARY:
1226 case QXL_IO_UPDATE_IRQ:
1227 case QXL_IO_LOG:
1228 case QXL_IO_MEMSLOT_ADD_ASYNC:
1229 case QXL_IO_CREATE_PRIMARY_ASYNC:
1230 break;
1231 default:
1232 if (d->mode != QXL_MODE_VGA) {
1233 break;
1234 }
1235 trace_qxl_io_unexpected_vga_mode(d->id,
1236 io_port, io_port_to_string(io_port));
1237 /* be nice to buggy guest drivers */
1238 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1239 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1240 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1241 }
1242 return;
1243 }
1244
1245 /* we change the io_port to avoid ifdeffery in the main switch */
1246 orig_io_port = io_port;
1247 switch (io_port) {
1248 case QXL_IO_UPDATE_AREA_ASYNC:
1249 io_port = QXL_IO_UPDATE_AREA;
1250 goto async_common;
1251 case QXL_IO_MEMSLOT_ADD_ASYNC:
1252 io_port = QXL_IO_MEMSLOT_ADD;
1253 goto async_common;
1254 case QXL_IO_CREATE_PRIMARY_ASYNC:
1255 io_port = QXL_IO_CREATE_PRIMARY;
1256 goto async_common;
1257 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1258 io_port = QXL_IO_DESTROY_PRIMARY;
1259 goto async_common;
1260 case QXL_IO_DESTROY_SURFACE_ASYNC:
1261 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1262 goto async_common;
1263 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1264 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1265 goto async_common;
1266 case QXL_IO_FLUSH_SURFACES_ASYNC:
1267 async_common:
1268 async = QXL_ASYNC;
1269 qemu_mutex_lock(&d->async_lock);
1270 if (d->current_async != QXL_UNDEFINED_IO) {
1271 qxl_guest_bug(d, "%d async started before last (%d) complete",
1272 io_port, d->current_async);
1273 qemu_mutex_unlock(&d->async_lock);
1274 return;
1275 }
1276 d->current_async = orig_io_port;
1277 qemu_mutex_unlock(&d->async_lock);
1278 break;
1279 default:
1280 break;
1281 }
1282 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1283 async);
1284
1285 switch (io_port) {
1286 case QXL_IO_UPDATE_AREA:
1287 {
1288 QXLCookie *cookie = NULL;
1289 QXLRect update = d->ram->update_area;
1290
1291 if (async == QXL_ASYNC) {
1292 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1293 QXL_IO_UPDATE_AREA_ASYNC);
1294 cookie->u.area = update;
1295 }
1296 qxl_spice_update_area(d, d->ram->update_surface,
1297 cookie ? &cookie->u.area : &update,
1298 NULL, 0, 0, async, cookie);
1299 break;
1300 }
1301 case QXL_IO_NOTIFY_CMD:
1302 qemu_spice_wakeup(&d->ssd);
1303 break;
1304 case QXL_IO_NOTIFY_CURSOR:
1305 qemu_spice_wakeup(&d->ssd);
1306 break;
1307 case QXL_IO_UPDATE_IRQ:
1308 qxl_update_irq(d);
1309 break;
1310 case QXL_IO_NOTIFY_OOM:
1311 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1312 break;
1313 }
1314 d->oom_running = 1;
1315 qxl_spice_oom(d);
1316 d->oom_running = 0;
1317 break;
1318 case QXL_IO_SET_MODE:
1319 qxl_set_mode(d, val, 0);
1320 break;
1321 case QXL_IO_LOG:
1322 if (d->guestdebug) {
1323 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1324 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1325 }
1326 break;
1327 case QXL_IO_RESET:
1328 qxl_hard_reset(d, 0);
1329 break;
1330 case QXL_IO_MEMSLOT_ADD:
1331 if (val >= NUM_MEMSLOTS) {
1332 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1333 break;
1334 }
1335 if (d->guest_slots[val].active) {
1336 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1337 break;
1338 }
1339 d->guest_slots[val].slot = d->ram->mem_slot;
1340 qxl_add_memslot(d, val, 0, async);
1341 break;
1342 case QXL_IO_MEMSLOT_DEL:
1343 if (val >= NUM_MEMSLOTS) {
1344 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1345 break;
1346 }
1347 qxl_del_memslot(d, val);
1348 break;
1349 case QXL_IO_CREATE_PRIMARY:
1350 if (val != 0) {
1351 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1352 async);
1353 goto cancel_async;
1354 }
1355 d->guest_primary.surface = d->ram->create_surface;
1356 qxl_create_guest_primary(d, 0, async);
1357 break;
1358 case QXL_IO_DESTROY_PRIMARY:
1359 if (val != 0) {
1360 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1361 async);
1362 goto cancel_async;
1363 }
1364 if (!qxl_destroy_primary(d, async)) {
1365 trace_qxl_io_destroy_primary_ignored(d->id,
1366 qxl_mode_to_string(d->mode));
1367 goto cancel_async;
1368 }
1369 break;
1370 case QXL_IO_DESTROY_SURFACE_WAIT:
1371 if (val >= NUM_SURFACES) {
1372 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1373 "%d >= NUM_SURFACES", async, val);
1374 goto cancel_async;
1375 }
1376 qxl_spice_destroy_surface_wait(d, val, async);
1377 break;
1378 case QXL_IO_FLUSH_RELEASE: {
1379 QXLReleaseRing *ring = &d->ram->release_ring;
1380 if (ring->prod - ring->cons + 1 == ring->num_items) {
1381 fprintf(stderr,
1382 "ERROR: no flush, full release ring [p%d,%dc]\n",
1383 ring->prod, ring->cons);
1384 }
1385 qxl_push_free_res(d, 1 /* flush */);
1386 break;
1387 }
1388 case QXL_IO_FLUSH_SURFACES_ASYNC:
1389 qxl_spice_flush_surfaces_async(d);
1390 break;
1391 case QXL_IO_DESTROY_ALL_SURFACES:
1392 d->mode = QXL_MODE_UNDEFINED;
1393 qxl_spice_destroy_surfaces(d, async);
1394 break;
1395 default:
1396 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1397 abort();
1398 }
1399 return;
1400 cancel_async:
1401 if (async) {
1402 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1403 qemu_mutex_lock(&d->async_lock);
1404 d->current_async = QXL_UNDEFINED_IO;
1405 qemu_mutex_unlock(&d->async_lock);
1406 }
1407 }
1408
1409 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1410 unsigned size)
1411 {
1412 PCIQXLDevice *d = opaque;
1413
1414 trace_qxl_io_read_unexpected(d->id);
1415 return 0xff;
1416 }
1417
1418 static const MemoryRegionOps qxl_io_ops = {
1419 .read = ioport_read,
1420 .write = ioport_write,
1421 .valid = {
1422 .min_access_size = 1,
1423 .max_access_size = 1,
1424 },
1425 };
1426
1427 static void pipe_read(void *opaque)
1428 {
1429 PCIQXLDevice *d = opaque;
1430 char dummy;
1431 int len;
1432
1433 do {
1434 len = read(d->pipe[0], &dummy, sizeof(dummy));
1435 } while (len == sizeof(dummy));
1436 qxl_update_irq(d);
1437 }
1438
1439 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1440 {
1441 uint32_t old_pending;
1442 uint32_t le_events = cpu_to_le32(events);
1443
1444 assert(d->ssd.running);
1445 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1446 if ((old_pending & le_events) == le_events) {
1447 return;
1448 }
1449 if (qemu_thread_is_self(&d->main)) {
1450 qxl_update_irq(d);
1451 } else {
1452 if (write(d->pipe[1], d, 1) != 1) {
1453 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1454 }
1455 }
1456 }
1457
1458 static void init_pipe_signaling(PCIQXLDevice *d)
1459 {
1460 if (pipe(d->pipe) < 0) {
1461 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1462 __FILE__, __func__);
1463 exit(1);
1464 }
1465 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1466 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1467 fcntl(d->pipe[0], F_SETOWN, getpid());
1468
1469 qemu_thread_get_self(&d->main);
1470 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1471 }
1472
1473 /* graphics console */
1474
1475 static void qxl_hw_update(void *opaque)
1476 {
1477 PCIQXLDevice *qxl = opaque;
1478 VGACommonState *vga = &qxl->vga;
1479
1480 switch (qxl->mode) {
1481 case QXL_MODE_VGA:
1482 vga->update(vga);
1483 break;
1484 case QXL_MODE_COMPAT:
1485 case QXL_MODE_NATIVE:
1486 qxl_render_update(qxl);
1487 break;
1488 default:
1489 break;
1490 }
1491 }
1492
1493 static void qxl_hw_invalidate(void *opaque)
1494 {
1495 PCIQXLDevice *qxl = opaque;
1496 VGACommonState *vga = &qxl->vga;
1497
1498 vga->invalidate(vga);
1499 }
1500
1501 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch)
1502 {
1503 PCIQXLDevice *qxl = opaque;
1504 VGACommonState *vga = &qxl->vga;
1505
1506 switch (qxl->mode) {
1507 case QXL_MODE_COMPAT:
1508 case QXL_MODE_NATIVE:
1509 qxl_render_update(qxl);
1510 ppm_save(filename, qxl->ssd.ds->surface);
1511 break;
1512 case QXL_MODE_VGA:
1513 vga->screen_dump(vga, filename, cswitch);
1514 break;
1515 default:
1516 break;
1517 }
1518 }
1519
1520 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1521 {
1522 PCIQXLDevice *qxl = opaque;
1523 VGACommonState *vga = &qxl->vga;
1524
1525 if (qxl->mode == QXL_MODE_VGA) {
1526 vga->text_update(vga, chardata);
1527 return;
1528 }
1529 }
1530
1531 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1532 {
1533 intptr_t vram_start;
1534 int i;
1535
1536 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1537 return;
1538 }
1539
1540 /* dirty the primary surface */
1541 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1542 qxl->shadow_rom.surface0_area_size);
1543
1544 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1545
1546 /* dirty the off-screen surfaces */
1547 for (i = 0; i < NUM_SURFACES; i++) {
1548 QXLSurfaceCmd *cmd;
1549 intptr_t surface_offset;
1550 int surface_size;
1551
1552 if (qxl->guest_surfaces.cmds[i] == 0) {
1553 continue;
1554 }
1555
1556 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1557 MEMSLOT_GROUP_GUEST);
1558 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1559 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1560 cmd->u.surface_create.data,
1561 MEMSLOT_GROUP_GUEST);
1562 surface_offset -= vram_start;
1563 surface_size = cmd->u.surface_create.height *
1564 abs(cmd->u.surface_create.stride);
1565 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1566 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1567 }
1568 }
1569
1570 static void qxl_vm_change_state_handler(void *opaque, int running,
1571 RunState state)
1572 {
1573 PCIQXLDevice *qxl = opaque;
1574 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1575
1576 if (running) {
1577 /*
1578 * if qxl_send_events was called from spice server context before
1579 * migration ended, qxl_update_irq for these events might not have been
1580 * called
1581 */
1582 qxl_update_irq(qxl);
1583 } else {
1584 /* make sure surfaces are saved before migration */
1585 qxl_dirty_surfaces(qxl);
1586 }
1587 }
1588
1589 /* display change listener */
1590
1591 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1592 {
1593 if (qxl0->mode == QXL_MODE_VGA) {
1594 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1595 }
1596 }
1597
1598 static void display_resize(struct DisplayState *ds)
1599 {
1600 if (qxl0->mode == QXL_MODE_VGA) {
1601 qemu_spice_display_resize(&qxl0->ssd);
1602 }
1603 }
1604
1605 static void display_refresh(struct DisplayState *ds)
1606 {
1607 if (qxl0->mode == QXL_MODE_VGA) {
1608 qemu_spice_display_refresh(&qxl0->ssd);
1609 } else {
1610 qemu_mutex_lock(&qxl0->ssd.lock);
1611 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1612 qemu_mutex_unlock(&qxl0->ssd.lock);
1613 }
1614 }
1615
1616 static DisplayChangeListener display_listener = {
1617 .dpy_update = display_update,
1618 .dpy_resize = display_resize,
1619 .dpy_refresh = display_refresh,
1620 };
1621
1622 static void qxl_init_ramsize(PCIQXLDevice *qxl, uint32_t ram_min_mb)
1623 {
1624 /* vga ram (bar 0) */
1625 if (qxl->ram_size_mb != -1) {
1626 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1627 }
1628 if (qxl->vga.vram_size < ram_min_mb * 1024 * 1024) {
1629 qxl->vga.vram_size = ram_min_mb * 1024 * 1024;
1630 }
1631
1632 /* vram32 (surfaces, 32bit, bar 1) */
1633 if (qxl->vram32_size_mb != -1) {
1634 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1635 }
1636 if (qxl->vram32_size < 4096) {
1637 qxl->vram32_size = 4096;
1638 }
1639
1640 /* vram (surfaces, 64bit, bar 4+5) */
1641 if (qxl->vram_size_mb != -1) {
1642 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1643 }
1644 if (qxl->vram_size < qxl->vram32_size) {
1645 qxl->vram_size = qxl->vram32_size;
1646 }
1647
1648 if (qxl->revision == 1) {
1649 qxl->vram32_size = 4096;
1650 qxl->vram_size = 4096;
1651 }
1652 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1653 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1654 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1655 }
1656
1657 static int qxl_init_common(PCIQXLDevice *qxl)
1658 {
1659 uint8_t* config = qxl->pci.config;
1660 uint32_t pci_device_rev;
1661 uint32_t io_size;
1662
1663 qxl->mode = QXL_MODE_UNDEFINED;
1664 qxl->generation = 1;
1665 qxl->num_memslots = NUM_MEMSLOTS;
1666 qxl->num_surfaces = NUM_SURFACES;
1667 qemu_mutex_init(&qxl->track_lock);
1668 qemu_mutex_init(&qxl->async_lock);
1669 qxl->current_async = QXL_UNDEFINED_IO;
1670
1671 switch (qxl->revision) {
1672 case 1: /* spice 0.4 -- qxl-1 */
1673 pci_device_rev = QXL_REVISION_STABLE_V04;
1674 break;
1675 case 2: /* spice 0.6 -- qxl-2 */
1676 pci_device_rev = QXL_REVISION_STABLE_V06;
1677 break;
1678 case 3: /* qxl-3 */
1679 default:
1680 pci_device_rev = QXL_DEFAULT_REVISION;
1681 break;
1682 }
1683
1684 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1685 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1686
1687 qxl->rom_size = qxl_rom_size();
1688 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1689 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1690 init_qxl_rom(qxl);
1691 init_qxl_ram(qxl);
1692
1693 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1694 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1695 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1696 0, qxl->vram32_size);
1697
1698 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1699 if (qxl->revision == 1) {
1700 io_size = 8;
1701 }
1702
1703 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1704 "qxl-ioports", io_size);
1705 if (qxl->id == 0) {
1706 vga_dirty_log_start(&qxl->vga);
1707 }
1708
1709
1710 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1711 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1712
1713 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1714 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1715
1716 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1717 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1718
1719 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1720 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
1721
1722 if (qxl->vram32_size < qxl->vram_size) {
1723 /*
1724 * Make the 64bit vram bar show up only in case it is
1725 * configured to be larger than the 32bit vram bar.
1726 */
1727 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
1728 PCI_BASE_ADDRESS_SPACE_MEMORY |
1729 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1730 PCI_BASE_ADDRESS_MEM_PREFETCH,
1731 &qxl->vram_bar);
1732 }
1733
1734 /* print pci bar details */
1735 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
1736 qxl->id == 0 ? "pri" : "sec",
1737 qxl->vga.vram_size / (1024*1024));
1738 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
1739 qxl->vram32_size / (1024*1024));
1740 dprint(qxl, 1, "vram/64: %d MB %s\n",
1741 qxl->vram_size / (1024*1024),
1742 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
1743
1744 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1745 qxl->ssd.qxl.id = qxl->id;
1746 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1747 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1748
1749 init_pipe_signaling(qxl);
1750 qxl_reset_state(qxl);
1751
1752 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
1753
1754 return 0;
1755 }
1756
1757 static int qxl_init_primary(PCIDevice *dev)
1758 {
1759 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1760 VGACommonState *vga = &qxl->vga;
1761 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1762
1763 qxl->id = 0;
1764 qxl_init_ramsize(qxl, 32);
1765 vga_common_init(vga, qxl->vga.vram_size);
1766 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1767 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1768 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1769
1770 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1771 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1772 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1773
1774 qxl0 = qxl;
1775 register_displaychangelistener(vga->ds, &display_listener);
1776
1777 return qxl_init_common(qxl);
1778 }
1779
1780 static int qxl_init_secondary(PCIDevice *dev)
1781 {
1782 static int device_id = 1;
1783 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1784
1785 qxl->id = device_id++;
1786 qxl_init_ramsize(qxl, 16);
1787 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1788 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
1789 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1790
1791 return qxl_init_common(qxl);
1792 }
1793
1794 static void qxl_pre_save(void *opaque)
1795 {
1796 PCIQXLDevice* d = opaque;
1797 uint8_t *ram_start = d->vga.vram_ptr;
1798
1799 trace_qxl_pre_save(d->id);
1800 if (d->last_release == NULL) {
1801 d->last_release_offset = 0;
1802 } else {
1803 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1804 }
1805 assert(d->last_release_offset < d->vga.vram_size);
1806 }
1807
1808 static int qxl_pre_load(void *opaque)
1809 {
1810 PCIQXLDevice* d = opaque;
1811
1812 trace_qxl_pre_load(d->id);
1813 qxl_hard_reset(d, 1);
1814 qxl_exit_vga_mode(d);
1815 return 0;
1816 }
1817
1818 static void qxl_create_memslots(PCIQXLDevice *d)
1819 {
1820 int i;
1821
1822 for (i = 0; i < NUM_MEMSLOTS; i++) {
1823 if (!d->guest_slots[i].active) {
1824 continue;
1825 }
1826 qxl_add_memslot(d, i, 0, QXL_SYNC);
1827 }
1828 }
1829
1830 static int qxl_post_load(void *opaque, int version)
1831 {
1832 PCIQXLDevice* d = opaque;
1833 uint8_t *ram_start = d->vga.vram_ptr;
1834 QXLCommandExt *cmds;
1835 int in, out, newmode;
1836
1837 assert(d->last_release_offset < d->vga.vram_size);
1838 if (d->last_release_offset == 0) {
1839 d->last_release = NULL;
1840 } else {
1841 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1842 }
1843
1844 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1845
1846 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
1847 newmode = d->mode;
1848 d->mode = QXL_MODE_UNDEFINED;
1849
1850 switch (newmode) {
1851 case QXL_MODE_UNDEFINED:
1852 break;
1853 case QXL_MODE_VGA:
1854 qxl_create_memslots(d);
1855 qxl_enter_vga_mode(d);
1856 break;
1857 case QXL_MODE_NATIVE:
1858 qxl_create_memslots(d);
1859 qxl_create_guest_primary(d, 1, QXL_SYNC);
1860
1861 /* replay surface-create and cursor-set commands */
1862 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1863 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1864 if (d->guest_surfaces.cmds[in] == 0) {
1865 continue;
1866 }
1867 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1868 cmds[out].cmd.type = QXL_CMD_SURFACE;
1869 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1870 out++;
1871 }
1872 if (d->guest_cursor) {
1873 cmds[out].cmd.data = d->guest_cursor;
1874 cmds[out].cmd.type = QXL_CMD_CURSOR;
1875 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1876 out++;
1877 }
1878 qxl_spice_loadvm_commands(d, cmds, out);
1879 g_free(cmds);
1880
1881 break;
1882 case QXL_MODE_COMPAT:
1883 /* note: no need to call qxl_create_memslots, qxl_set_mode
1884 * creates the mem slot. */
1885 qxl_set_mode(d, d->shadow_rom.mode, 1);
1886 break;
1887 }
1888 return 0;
1889 }
1890
1891 #define QXL_SAVE_VERSION 21
1892
1893 static VMStateDescription qxl_memslot = {
1894 .name = "qxl-memslot",
1895 .version_id = QXL_SAVE_VERSION,
1896 .minimum_version_id = QXL_SAVE_VERSION,
1897 .fields = (VMStateField[]) {
1898 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1899 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1900 VMSTATE_UINT32(active, struct guest_slots),
1901 VMSTATE_END_OF_LIST()
1902 }
1903 };
1904
1905 static VMStateDescription qxl_surface = {
1906 .name = "qxl-surface",
1907 .version_id = QXL_SAVE_VERSION,
1908 .minimum_version_id = QXL_SAVE_VERSION,
1909 .fields = (VMStateField[]) {
1910 VMSTATE_UINT32(width, QXLSurfaceCreate),
1911 VMSTATE_UINT32(height, QXLSurfaceCreate),
1912 VMSTATE_INT32(stride, QXLSurfaceCreate),
1913 VMSTATE_UINT32(format, QXLSurfaceCreate),
1914 VMSTATE_UINT32(position, QXLSurfaceCreate),
1915 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1916 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1917 VMSTATE_UINT32(type, QXLSurfaceCreate),
1918 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1919 VMSTATE_END_OF_LIST()
1920 }
1921 };
1922
1923 static VMStateDescription qxl_vmstate = {
1924 .name = "qxl",
1925 .version_id = QXL_SAVE_VERSION,
1926 .minimum_version_id = QXL_SAVE_VERSION,
1927 .pre_save = qxl_pre_save,
1928 .pre_load = qxl_pre_load,
1929 .post_load = qxl_post_load,
1930 .fields = (VMStateField []) {
1931 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1932 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1933 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1934 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1935 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1936 VMSTATE_UINT32(mode, PCIQXLDevice),
1937 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1938 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1939 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1940 qxl_memslot, struct guest_slots),
1941 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1942 qxl_surface, QXLSurfaceCreate),
1943 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1944 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1945 vmstate_info_uint64, uint64_t),
1946 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1947 VMSTATE_END_OF_LIST()
1948 },
1949 };
1950
1951 static Property qxl_properties[] = {
1952 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1953 64 * 1024 * 1024),
1954 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
1955 64 * 1024 * 1024),
1956 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1957 QXL_DEFAULT_REVISION),
1958 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1959 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1960 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1961 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
1962 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, 0),
1963 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, 0),
1964 DEFINE_PROP_END_OF_LIST(),
1965 };
1966
1967 static void qxl_primary_class_init(ObjectClass *klass, void *data)
1968 {
1969 DeviceClass *dc = DEVICE_CLASS(klass);
1970 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1971
1972 k->no_hotplug = 1;
1973 k->init = qxl_init_primary;
1974 k->romfile = "vgabios-qxl.bin";
1975 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1976 k->device_id = QXL_DEVICE_ID_STABLE;
1977 k->class_id = PCI_CLASS_DISPLAY_VGA;
1978 dc->desc = "Spice QXL GPU (primary, vga compatible)";
1979 dc->reset = qxl_reset_handler;
1980 dc->vmsd = &qxl_vmstate;
1981 dc->props = qxl_properties;
1982 }
1983
1984 static TypeInfo qxl_primary_info = {
1985 .name = "qxl-vga",
1986 .parent = TYPE_PCI_DEVICE,
1987 .instance_size = sizeof(PCIQXLDevice),
1988 .class_init = qxl_primary_class_init,
1989 };
1990
1991 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
1992 {
1993 DeviceClass *dc = DEVICE_CLASS(klass);
1994 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1995
1996 k->init = qxl_init_secondary;
1997 k->vendor_id = REDHAT_PCI_VENDOR_ID;
1998 k->device_id = QXL_DEVICE_ID_STABLE;
1999 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2000 dc->desc = "Spice QXL GPU (secondary)";
2001 dc->reset = qxl_reset_handler;
2002 dc->vmsd = &qxl_vmstate;
2003 dc->props = qxl_properties;
2004 }
2005
2006 static TypeInfo qxl_secondary_info = {
2007 .name = "qxl",
2008 .parent = TYPE_PCI_DEVICE,
2009 .instance_size = sizeof(PCIQXLDevice),
2010 .class_init = qxl_secondary_class_init,
2011 };
2012
2013 static void qxl_register_types(void)
2014 {
2015 type_register_static(&qxl_primary_info);
2016 type_register_static(&qxl_secondary_info);
2017 }
2018
2019 type_init(qxl_register_types)
QEmu