2 * QEMU PowerPC 405 shared definitions
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qom/object.h"
29 #include "hw/ppc/ppc4xx.h"
31 #define PPC405EP_SDRAM_BASE 0x00000000
32 #define PPC405EP_NVRAM_BASE 0xF0000000
33 #define PPC405EP_FPGA_BASE 0xF0300000
34 #define PPC405EP_SRAM_BASE 0xFFF00000
35 #define PPC405EP_SRAM_SIZE (512 * KiB)
36 #define PPC405EP_FLASH_BASE 0xFFF80000
38 /* Bootinfo as set-up by u-boot */
39 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t
;
40 struct ppc4xx_bd_info_t
{
43 uint32_t bi_flashstart
;
44 uint32_t bi_flashsize
;
45 uint32_t bi_flashoffset
; /* 0x10 */
46 uint32_t bi_sramstart
;
48 uint32_t bi_bootflags
;
49 uint32_t bi_ipaddr
; /* 0x20 */
50 uint8_t bi_enetaddr
[6];
53 uint32_t bi_busfreq
; /* 0x30 */
55 uint8_t bi_s_version
[4];
56 uint8_t bi_r_version
[32];
58 uint32_t bi_plb_busfreq
;
59 uint32_t bi_pci_busfreq
;
60 uint8_t bi_pci_enetaddr
[6];
61 uint8_t bi_pci_enetaddr2
[6]; /* PPC405EP specific */
63 uint32_t bi_iic_fast
[2];
66 /* PLB to OPB bridge */
67 #define TYPE_PPC405_POB "ppc405-pob"
68 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState
, PPC405_POB
);
69 struct Ppc405PobState
{
70 Ppc4xxDcrDeviceState parent_obj
;
78 #define TYPE_PPC405_OPBA "ppc405-opba"
79 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState
, PPC405_OPBA
);
80 struct Ppc405OpbaState
{
81 SysBusDevice parent_obj
;
89 #define TYPE_PPC405_DMA "ppc405-dma"
90 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState
, PPC405_DMA
);
91 struct Ppc405DmaState
{
92 Ppc4xxDcrDeviceState parent_obj
;
107 #define TYPE_PPC405_GPIO "ppc405-gpio"
108 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState
, PPC405_GPIO
);
109 struct Ppc405GpioState
{
110 SysBusDevice parent_obj
;
127 #define TYPE_PPC405_OCM "ppc405-ocm"
128 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState
, PPC405_OCM
);
129 struct Ppc405OcmState
{
130 Ppc4xxDcrDeviceState parent_obj
;
133 MemoryRegion isarc_ram
;
134 MemoryRegion dsarc_ram
;
141 /* General purpose timers */
142 #define TYPE_PPC405_GPT "ppc405-gpt"
143 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState
, PPC405_GPT
);
144 struct Ppc405GptState
{
145 SysBusDevice parent_obj
;
162 #define TYPE_PPC405_CPC "ppc405-cpc"
163 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState
, PPC405_CPC
);
166 PPC405EP_CPU_CLK
= 0,
167 PPC405EP_PLB_CLK
= 1,
168 PPC405EP_OPB_CLK
= 2,
169 PPC405EP_EBC_CLK
= 3,
170 PPC405EP_MAL_CLK
= 4,
171 PPC405EP_PCI_CLK
= 5,
172 PPC405EP_UART0_CLK
= 6,
173 PPC405EP_UART1_CLK
= 7,
177 struct Ppc405CpcState
{
178 Ppc4xxDcrDeviceState parent_obj
;
181 clk_setup_t clk_setup
[PPC405EP_CLK_NB
];
189 /* Clock and power management */
195 #define TYPE_PPC405_SOC "ppc405-soc"
196 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState
, PPC405_SOC
);
198 struct Ppc405SoCState
{
200 DeviceState parent_obj
;
203 MemoryRegion ram_banks
[2];
204 hwaddr ram_bases
[2], ram_sizes
[2];
207 MemoryRegion
*dram_mr
;
215 Ppc405GpioState gpio
;
218 Ppc405OpbaState opba
;
224 /* PowerPC 405 core */
225 ram_addr_t
ppc405_set_bootinfo(CPUPPCState
*env
, ram_addr_t ram_size
);
227 #endif /* PPC405_H */