hw/ppc/ppc405.h

   1 /*
   2  * QEMU PowerPC 405 shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef PPC405_H
  26 #define PPC405_H
  27
  28 #include "qom/object.h"
  29 #include "hw/ppc/ppc4xx.h"
  30
  31 #define PPC405EP_SDRAM_BASE 0x00000000
  32 #define PPC405EP_NVRAM_BASE 0xF0000000
  33 #define PPC405EP_FPGA_BASE  0xF0300000
  34 #define PPC405EP_SRAM_BASE  0xFFF00000
  35 #define PPC405EP_SRAM_SIZE  (512 * KiB)
  36 #define PPC405EP_FLASH_BASE 0xFFF80000
  37
  38 /* Bootinfo as set-up by u-boot */
  39 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
  40 struct ppc4xx_bd_info_t {
  41     uint32_t bi_memstart;
  42     uint32_t bi_memsize;
  43     uint32_t bi_flashstart;
  44     uint32_t bi_flashsize;
  45     uint32_t bi_flashoffset; /* 0x10 */
  46     uint32_t bi_sramstart;
  47     uint32_t bi_sramsize;
  48     uint32_t bi_bootflags;
  49     uint32_t bi_ipaddr; /* 0x20 */
  50     uint8_t  bi_enetaddr[6];
  51     uint16_t bi_ethspeed;
  52     uint32_t bi_intfreq;
  53     uint32_t bi_busfreq; /* 0x30 */
  54     uint32_t bi_baudrate;
  55     uint8_t  bi_s_version[4];
  56     uint8_t  bi_r_version[32];
  57     uint32_t bi_procfreq;
  58     uint32_t bi_plb_busfreq;
  59     uint32_t bi_pci_busfreq;
  60     uint8_t  bi_pci_enetaddr[6];
  61     uint8_t  bi_pci_enetaddr2[6]; /* PPC405EP specific */
  62     uint32_t bi_opbfreq;
  63     uint32_t bi_iic_fast[2];
  64 };
  65
  66 /* PLB to OPB bridge */
  67 #define TYPE_PPC405_POB "ppc405-pob"
  68 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
  69 struct Ppc405PobState {
  70     Ppc4xxDcrDeviceState parent_obj;
  71
  72     uint32_t bear;
  73     uint32_t besr0;
  74     uint32_t besr1;
  75 };
  76
  77 /* OPB arbitrer */
  78 #define TYPE_PPC405_OPBA "ppc405-opba"
  79 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
  80 struct Ppc405OpbaState {
  81     SysBusDevice parent_obj;
  82
  83     MemoryRegion io;
  84     uint8_t cr;
  85     uint8_t pr;
  86 };
  87
  88 /* DMA controller */
  89 #define TYPE_PPC405_DMA "ppc405-dma"
  90 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
  91 struct Ppc405DmaState {
  92     Ppc4xxDcrDeviceState parent_obj;
  93
  94     qemu_irq irqs[4];
  95     uint32_t cr[4];
  96     uint32_t ct[4];
  97     uint32_t da[4];
  98     uint32_t sa[4];
  99     uint32_t sg[4];
 100     uint32_t sr;
 101     uint32_t sgc;
 102     uint32_t slp;
 103     uint32_t pol;
 104 };
 105
 106 /* GPIO */
 107 #define TYPE_PPC405_GPIO "ppc405-gpio"
 108 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
 109 struct Ppc405GpioState {
 110     SysBusDevice parent_obj;
 111
 112     MemoryRegion io;
 113     uint32_t or;
 114     uint32_t tcr;
 115     uint32_t osrh;
 116     uint32_t osrl;
 117     uint32_t tsrh;
 118     uint32_t tsrl;
 119     uint32_t odr;
 120     uint32_t ir;
 121     uint32_t rr1;
 122     uint32_t isr1h;
 123     uint32_t isr1l;
 124 };
 125
 126 /* On Chip Memory */
 127 #define TYPE_PPC405_OCM "ppc405-ocm"
 128 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
 129 struct Ppc405OcmState {
 130     Ppc4xxDcrDeviceState parent_obj;
 131
 132     MemoryRegion ram;
 133     MemoryRegion isarc_ram;
 134     MemoryRegion dsarc_ram;
 135     uint32_t isarc;
 136     uint32_t isacntl;
 137     uint32_t dsarc;
 138     uint32_t dsacntl;
 139 };
 140
 141 /* General purpose timers */
 142 #define TYPE_PPC405_GPT "ppc405-gpt"
 143 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
 144 struct Ppc405GptState {
 145     SysBusDevice parent_obj;
 146
 147     MemoryRegion iomem;
 148
 149     int64_t tb_offset;
 150     uint32_t tb_freq;
 151     QEMUTimer *timer;
 152     qemu_irq irqs[5];
 153     uint32_t oe;
 154     uint32_t ol;
 155     uint32_t im;
 156     uint32_t is;
 157     uint32_t ie;
 158     uint32_t comp[5];
 159     uint32_t mask[5];
 160 };
 161
 162 #define TYPE_PPC405_CPC "ppc405-cpc"
 163 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
 164
 165 enum {
 166     PPC405EP_CPU_CLK   = 0,
 167     PPC405EP_PLB_CLK   = 1,
 168     PPC405EP_OPB_CLK   = 2,
 169     PPC405EP_EBC_CLK   = 3,
 170     PPC405EP_MAL_CLK   = 4,
 171     PPC405EP_PCI_CLK   = 5,
 172     PPC405EP_UART0_CLK = 6,
 173     PPC405EP_UART1_CLK = 7,
 174     PPC405EP_CLK_NB    = 8,
 175 };
 176
 177 struct Ppc405CpcState {
 178     Ppc4xxDcrDeviceState parent_obj;
 179
 180     uint32_t sysclk;
 181     clk_setup_t clk_setup[PPC405EP_CLK_NB];
 182     uint32_t boot;
 183     uint32_t epctl;
 184     uint32_t pllmr[2];
 185     uint32_t ucr;
 186     uint32_t srr;
 187     uint32_t jtagid;
 188     uint32_t pci;
 189     /* Clock and power management */
 190     uint32_t er;
 191     uint32_t fr;
 192     uint32_t sr;
 193 };
 194
 195 #define TYPE_PPC405_SOC "ppc405-soc"
 196 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
 197
 198 struct Ppc405SoCState {
 199     /* Private */
 200     DeviceState parent_obj;
 201
 202     /* Public */
 203     MemoryRegion ram_banks[2];
 204     hwaddr ram_bases[2], ram_sizes[2];
 205     bool do_dram_init;
 206
 207     MemoryRegion *dram_mr;
 208     hwaddr ram_size;
 209
 210     PowerPCCPU cpu;
 211     DeviceState *uic;
 212     Ppc405CpcState cpc;
 213     Ppc405GptState gpt;
 214     Ppc405OcmState ocm;
 215     Ppc405GpioState gpio;
 216     Ppc405DmaState dma;
 217     Ppc4xxEbcState ebc;
 218     Ppc405OpbaState opba;
 219     Ppc405PobState pob;
 220     Ppc4xxPlbState plb;
 221     Ppc4xxMalState mal;
 222 };
 223
 224 /* PowerPC 405 core */
 225 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
 226
 227 #endif /* PPC405_H */