hw/intc/bcm2835_ic.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Refactoring for Pi2 Copyright (c) 2015, Microsoft. Written by Andrew Baumann.
   4  * This code is licensed under the GNU GPLv2 and later.
   5  * Heavily based on pl190.c, copyright terms below:
   6  *
   7  * Arm PrimeCell PL190 Vector Interrupt Controller
   8  *
   9  * Copyright (c) 2006 CodeSourcery.
  10  * Written by Paul Brook
  11  *
  12  * This code is licensed under the GPL.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "hw/intc/bcm2835_ic.h"
  17
  18 #define GPU_IRQS 64
  19 #define ARM_IRQS 8
  20
  21 #define IRQ_PENDING_BASIC       0x00 /* IRQ basic pending */
  22 #define IRQ_PENDING_1           0x04 /* IRQ pending 1 */
  23 #define IRQ_PENDING_2           0x08 /* IRQ pending 2 */
  24 #define FIQ_CONTROL             0x0C /* FIQ register */
  25 #define IRQ_ENABLE_1            0x10 /* Interrupt enable register 1 */
  26 #define IRQ_ENABLE_2            0x14 /* Interrupt enable register 2 */
  27 #define IRQ_ENABLE_BASIC        0x18 /* Base interrupt enable register */
  28 #define IRQ_DISABLE_1           0x1C /* Interrupt disable register 1 */
  29 #define IRQ_DISABLE_2           0x20 /* Interrupt disable register 2 */
  30 #define IRQ_DISABLE_BASIC       0x24 /* Base interrupt disable register */
  31
  32 /* Update interrupts.  */
  33 static void bcm2835_ic_update(BCM2835ICState *s)
  34 {
  35     bool set = false;
  36
  37     if (s->fiq_enable) {
  38         if (s->fiq_select >= GPU_IRQS) {
  39             /* ARM IRQ */
  40             set = extract32(s->arm_irq_level, s->fiq_select - GPU_IRQS, 1);
  41         } else {
  42             set = extract64(s->gpu_irq_level, s->fiq_select, 1);
  43         }
  44     }
  45     qemu_set_irq(s->fiq, set);
  46
  47     set = (s->gpu_irq_level & s->gpu_irq_enable)
  48         || (s->arm_irq_level & s->arm_irq_enable);
  49     qemu_set_irq(s->irq, set);
  50
  51 }
  52
  53 static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level)
  54 {
  55     BCM2835ICState *s = opaque;
  56
  57     assert(irq >= 0 && irq < 64);
  58     s->gpu_irq_level = deposit64(s->gpu_irq_level, irq, 1, level != 0);
  59     bcm2835_ic_update(s);
  60 }
  61
  62 static void bcm2835_ic_set_arm_irq(void *opaque, int irq, int level)
  63 {
  64     BCM2835ICState *s = opaque;
  65
  66     assert(irq >= 0 && irq < 8);
  67     s->arm_irq_level = deposit32(s->arm_irq_level, irq, 1, level != 0);
  68     bcm2835_ic_update(s);
  69 }
  70
  71 static const int irq_dups[] = { 7, 9, 10, 18, 19, 53, 54, 55, 56, 57, 62 };
  72
  73 static uint64_t bcm2835_ic_read(void *opaque, hwaddr offset, unsigned size)
  74 {
  75     BCM2835ICState *s = opaque;
  76     uint32_t res = 0;
  77     uint64_t gpu_pending = s->gpu_irq_level & s->gpu_irq_enable;
  78     int i;
  79
  80     switch (offset) {
  81     case IRQ_PENDING_BASIC:
  82         /* bits 0-7: ARM irqs */
  83         res = s->arm_irq_level & s->arm_irq_enable;
  84
  85         /* bits 8 & 9: pending registers 1 & 2 */
  86         res |= (((uint32_t)gpu_pending) != 0) << 8;
  87         res |= ((gpu_pending >> 32) != 0) << 9;
  88
  89         /* bits 10-20: selected GPU IRQs */
  90         for (i = 0; i < ARRAY_SIZE(irq_dups); i++) {
  91             res |= extract64(gpu_pending, irq_dups[i], 1) << (i + 10);
  92         }
  93         break;
  94     case IRQ_PENDING_1:
  95         res = gpu_pending;
  96         break;
  97     case IRQ_PENDING_2:
  98         res = gpu_pending >> 32;
  99         break;
 100     case FIQ_CONTROL:
 101         res = (s->fiq_enable << 7) | s->fiq_select;
 102         break;
 103     case IRQ_ENABLE_1:
 104         res = s->gpu_irq_enable;
 105         break;
 106     case IRQ_ENABLE_2:
 107         res = s->gpu_irq_enable >> 32;
 108         break;
 109     case IRQ_ENABLE_BASIC:
 110         res = s->arm_irq_enable;
 111         break;
 112     case IRQ_DISABLE_1:
 113         res = ~s->gpu_irq_enable;
 114         break;
 115     case IRQ_DISABLE_2:
 116         res = ~s->gpu_irq_enable >> 32;
 117         break;
 118     case IRQ_DISABLE_BASIC:
 119         res = ~s->arm_irq_enable;
 120         break;
 121     default:
 122         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 123                       __func__, offset);
 124         return 0;
 125     }
 126
 127     return res;
 128 }
 129
 130 static void bcm2835_ic_write(void *opaque, hwaddr offset, uint64_t val,
 131                              unsigned size)
 132 {
 133     BCM2835ICState *s = opaque;
 134
 135     switch (offset) {
 136     case FIQ_CONTROL:
 137         s->fiq_select = extract32(val, 0, 7);
 138         s->fiq_enable = extract32(val, 7, 1);
 139         break;
 140     case IRQ_ENABLE_1:
 141         s->gpu_irq_enable |= val;
 142         break;
 143     case IRQ_ENABLE_2:
 144         s->gpu_irq_enable |= val << 32;
 145         break;
 146     case IRQ_ENABLE_BASIC:
 147         s->arm_irq_enable |= val & 0xff;
 148         break;
 149     case IRQ_DISABLE_1:
 150         s->gpu_irq_enable &= ~val;
 151         break;
 152     case IRQ_DISABLE_2:
 153         s->gpu_irq_enable &= ~(val << 32);
 154         break;
 155     case IRQ_DISABLE_BASIC:
 156         s->arm_irq_enable &= ~val & 0xff;
 157         break;
 158     default:
 159         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
 160                       __func__, offset);
 161         return;
 162     }
 163     bcm2835_ic_update(s);
 164 }
 165
 166 static const MemoryRegionOps bcm2835_ic_ops = {
 167     .read = bcm2835_ic_read,
 168     .write = bcm2835_ic_write,
 169     .endianness = DEVICE_NATIVE_ENDIAN,
 170     .valid.min_access_size = 4,
 171     .valid.max_access_size = 4,
 172 };
 173
 174 static void bcm2835_ic_reset(DeviceState *d)
 175 {
 176     BCM2835ICState *s = BCM2835_IC(d);
 177
 178     s->gpu_irq_enable = 0;
 179     s->arm_irq_enable = 0;
 180     s->fiq_enable = false;
 181     s->fiq_select = 0;
 182 }
 183
 184 static void bcm2835_ic_init(Object *obj)
 185 {
 186     BCM2835ICState *s = BCM2835_IC(obj);
 187
 188     memory_region_init_io(&s->iomem, obj, &bcm2835_ic_ops, s, TYPE_BCM2835_IC,
 189                           0x200);
 190     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 191
 192     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_gpu_irq,
 193                             BCM2835_IC_GPU_IRQ, GPU_IRQS);
 194     qdev_init_gpio_in_named(DEVICE(s), bcm2835_ic_set_arm_irq,
 195                             BCM2835_IC_ARM_IRQ, ARM_IRQS);
 196
 197     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 198     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->fiq);
 199 }
 200
 201 static const VMStateDescription vmstate_bcm2835_ic = {
 202     .name = TYPE_BCM2835_IC,
 203     .version_id = 1,
 204     .minimum_version_id = 1,
 205     .fields = (VMStateField[]) {
 206         VMSTATE_UINT64(gpu_irq_level, BCM2835ICState),
 207         VMSTATE_UINT64(gpu_irq_enable, BCM2835ICState),
 208         VMSTATE_UINT8(arm_irq_level, BCM2835ICState),
 209         VMSTATE_UINT8(arm_irq_enable, BCM2835ICState),
 210         VMSTATE_BOOL(fiq_enable, BCM2835ICState),
 211         VMSTATE_UINT8(fiq_select, BCM2835ICState),
 212         VMSTATE_END_OF_LIST()
 213     }
 214 };
 215
 216 static void bcm2835_ic_class_init(ObjectClass *klass, void *data)
 217 {
 218     DeviceClass *dc = DEVICE_CLASS(klass);
 219
 220     dc->reset = bcm2835_ic_reset;
 221     dc->vmsd = &vmstate_bcm2835_ic;
 222 }
 223
 224 static TypeInfo bcm2835_ic_info = {
 225     .name          = TYPE_BCM2835_IC,
 226     .parent        = TYPE_SYS_BUS_DEVICE,
 227     .instance_size = sizeof(BCM2835ICState),
 228     .class_init    = bcm2835_ic_class_init,
 229     .instance_init = bcm2835_ic_init,
 230 };
 231
 232 static void bcm2835_ic_register_types(void)
 233 {
 234     type_register_static(&bcm2835_ic_info);
 235 }
 236
 237 type_init(bcm2835_ic_register_types)