hw/dma/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2013 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/mips/mips.h"
  28 #include "hw/sysbus.h"
  29 #include "qemu/timer.h"
  30 #include "exec/address-spaces.h"
  31 #include "trace.h"
  32
  33 /********************************************************/
  34 /* rc4030 emulation                                     */
  35
  36 #define MAX_TL_ENTRIES 512
  37
  38 typedef struct dma_pagetable_entry {
  39     int32_t frame;
  40     int32_t owner;
  41 } QEMU_PACKED dma_pagetable_entry;
  42
  43 #define DMA_PAGESIZE    4096
  44 #define DMA_REG_ENABLE  1
  45 #define DMA_REG_COUNT   2
  46 #define DMA_REG_ADDRESS 3
  47
  48 #define DMA_FLAG_ENABLE     0x0001
  49 #define DMA_FLAG_MEM_TO_DEV 0x0002
  50 #define DMA_FLAG_TC_INTR    0x0100
  51 #define DMA_FLAG_MEM_INTR   0x0200
  52 #define DMA_FLAG_ADDR_INTR  0x0400
  53
  54 #define TYPE_RC4030 "rc4030"
  55 #define RC4030(obj) \
  56     OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
  57
  58 typedef struct rc4030State
  59 {
  60     SysBusDevice parent;
  61
  62     uint32_t config; /* 0x0000: RC4030 config register */
  63     uint32_t revision; /* 0x0008: RC4030 Revision register */
  64     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  65
  66     /* DMA */
  67     uint32_t dma_regs[8][4];
  68     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  69     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  70
  71     /* cache */
  72     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  73     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  74     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  75     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  76     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  77     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  78
  79     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  80     uint32_t memory_refresh_rate; /* 0x0210: memory refresh rate */
  81     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  82     uint32_t rem_speed[16];
  83     uint32_t imr_jazz; /* Local bus int enable mask */
  84     uint32_t isr_jazz; /* Local bus int source */
  85
  86     /* timer */
  87     QEMUTimer *periodic_timer;
  88     uint32_t itr; /* Interval timer reload */
  89
  90     qemu_irq timer_irq;
  91     qemu_irq jazz_bus_irq;
  92
  93     /* biggest translation table */
  94     MemoryRegion dma_tt;
  95     /* translation table memory region alias, added to system RAM */
  96     MemoryRegion dma_tt_alias;
  97     /* whole DMA memory region, root of DMA address space */
  98     MemoryRegion dma_mr;
  99     /* translation table entry aliases, added to DMA memory region */
 100     MemoryRegion dma_mrs[MAX_TL_ENTRIES];
 101     AddressSpace dma_as;
 102
 103     MemoryRegion iomem_chipset;
 104     MemoryRegion iomem_jazzio;
 105 } rc4030State;
 106
 107 static void set_next_tick(rc4030State *s)
 108 {
 109     qemu_irq_lower(s->timer_irq);
 110     uint32_t tm_hz;
 111
 112     tm_hz = 1000 / (s->itr + 1);
 113
 114     timer_mod(s->periodic_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 115                    NANOSECONDS_PER_SECOND / tm_hz);
 116 }
 117
 118 /* called for accesses to rc4030 */
 119 static uint64_t rc4030_read(void *opaque, hwaddr addr, unsigned int size)
 120 {
 121     rc4030State *s = opaque;
 122     uint32_t val;
 123
 124     addr &= 0x3fff;
 125     switch (addr & ~0x3) {
 126     /* Global config register */
 127     case 0x0000:
 128         val = s->config;
 129         break;
 130     /* Revision register */
 131     case 0x0008:
 132         val = s->revision;
 133         break;
 134     /* Invalid Address register */
 135     case 0x0010:
 136         val = s->invalid_address_register;
 137         break;
 138     /* DMA transl. table base */
 139     case 0x0018:
 140         val = s->dma_tl_base;
 141         break;
 142     /* DMA transl. table limit */
 143     case 0x0020:
 144         val = s->dma_tl_limit;
 145         break;
 146     /* Remote Failed Address */
 147     case 0x0038:
 148         val = s->remote_failed_address;
 149         break;
 150     /* Memory Failed Address */
 151     case 0x0040:
 152         val = s->memory_failed_address;
 153         break;
 154     /* I/O Cache Byte Mask */
 155     case 0x0058:
 156         val = s->cache_bmask;
 157         /* HACK */
 158         if (s->cache_bmask == (uint32_t)-1)
 159             s->cache_bmask = 0;
 160         break;
 161     /* Remote Speed Registers */
 162     case 0x0070:
 163     case 0x0078:
 164     case 0x0080:
 165     case 0x0088:
 166     case 0x0090:
 167     case 0x0098:
 168     case 0x00a0:
 169     case 0x00a8:
 170     case 0x00b0:
 171     case 0x00b8:
 172     case 0x00c0:
 173     case 0x00c8:
 174     case 0x00d0:
 175     case 0x00d8:
 176     case 0x00e0:
 177     case 0x00e8:
 178         val = s->rem_speed[(addr - 0x0070) >> 3];
 179         break;
 180     /* DMA channel base address */
 181     case 0x0100:
 182     case 0x0108:
 183     case 0x0110:
 184     case 0x0118:
 185     case 0x0120:
 186     case 0x0128:
 187     case 0x0130:
 188     case 0x0138:
 189     case 0x0140:
 190     case 0x0148:
 191     case 0x0150:
 192     case 0x0158:
 193     case 0x0160:
 194     case 0x0168:
 195     case 0x0170:
 196     case 0x0178:
 197     case 0x0180:
 198     case 0x0188:
 199     case 0x0190:
 200     case 0x0198:
 201     case 0x01a0:
 202     case 0x01a8:
 203     case 0x01b0:
 204     case 0x01b8:
 205     case 0x01c0:
 206     case 0x01c8:
 207     case 0x01d0:
 208     case 0x01d8:
 209     case 0x01e0:
 210     case 0x01e8:
 211     case 0x01f0:
 212     case 0x01f8:
 213         {
 214             int entry = (addr - 0x0100) >> 5;
 215             int idx = (addr & 0x1f) >> 3;
 216             val = s->dma_regs[entry][idx];
 217         }
 218         break;
 219     /* Interrupt source */
 220     case 0x0200:
 221         val = s->nmi_interrupt;
 222         break;
 223     /* Error type */
 224     case 0x0208:
 225         val = 0;
 226         break;
 227     /* Memory refresh rate */
 228     case 0x0210:
 229         val = s->memory_refresh_rate;
 230         break;
 231     /* NV ram protect register */
 232     case 0x0220:
 233         val = s->nvram_protect;
 234         break;
 235     /* Interval timer count */
 236     case 0x0230:
 237         val = 0;
 238         qemu_irq_lower(s->timer_irq);
 239         break;
 240     /* EISA interrupt */
 241     case 0x0238:
 242         val = 7; /* FIXME: should be read from EISA controller */
 243         break;
 244     default:
 245         qemu_log_mask(LOG_GUEST_ERROR,
 246                       "rc4030: invalid read at 0x%x", (int)addr);
 247         val = 0;
 248         break;
 249     }
 250
 251     if ((addr & ~3) != 0x230) {
 252         trace_rc4030_read(addr, val);
 253     }
 254
 255     return val;
 256 }
 257
 258 static void rc4030_dma_as_update_one(rc4030State *s, int index, uint32_t frame)
 259 {
 260     if (index < MAX_TL_ENTRIES) {
 261         memory_region_set_enabled(&s->dma_mrs[index], false);
 262     }
 263
 264     if (!frame) {
 265         return;
 266     }
 267
 268     if (index >= MAX_TL_ENTRIES) {
 269         qemu_log_mask(LOG_UNIMP,
 270                       "rc4030: trying to use too high "
 271                       "translation table entry %d (max allowed=%d)",
 272                       index, MAX_TL_ENTRIES);
 273         return;
 274     }
 275     memory_region_set_alias_offset(&s->dma_mrs[index], frame);
 276     memory_region_set_enabled(&s->dma_mrs[index], true);
 277 }
 278
 279 static void rc4030_dma_tt_write(void *opaque, hwaddr addr, uint64_t data,
 280                                 unsigned int size)
 281 {
 282     rc4030State *s = opaque;
 283
 284     /* write memory */
 285     memcpy(memory_region_get_ram_ptr(&s->dma_tt) + addr, &data, size);
 286
 287     /* update dma address space (only if frame field has been written) */
 288     if (addr % sizeof(dma_pagetable_entry) == 0) {
 289         int index = addr / sizeof(dma_pagetable_entry);
 290         memory_region_transaction_begin();
 291         rc4030_dma_as_update_one(s, index, (uint32_t)data);
 292         memory_region_transaction_commit();
 293     }
 294 }
 295
 296 static const MemoryRegionOps rc4030_dma_tt_ops = {
 297     .write = rc4030_dma_tt_write,
 298     .impl.min_access_size = 4,
 299     .impl.max_access_size = 4,
 300 };
 301
 302 static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base,
 303                                  uint32_t new_tl_limit)
 304 {
 305     int entries, i;
 306     dma_pagetable_entry *dma_tl_contents;
 307
 308     if (s->dma_tl_limit) {
 309         /* write old dma tl table to physical memory */
 310         memory_region_del_subregion(get_system_memory(), &s->dma_tt_alias);
 311         cpu_physical_memory_write(s->dma_tl_limit & 0x7fffffff,
 312                                   memory_region_get_ram_ptr(&s->dma_tt),
 313                                   memory_region_size(&s->dma_tt_alias));
 314     }
 315     object_unparent(OBJECT(&s->dma_tt_alias));
 316
 317     s->dma_tl_base = new_tl_base;
 318     s->dma_tl_limit = new_tl_limit;
 319     new_tl_base &= 0x7fffffff;
 320
 321     if (s->dma_tl_limit) {
 322         uint64_t dma_tt_size;
 323         if (s->dma_tl_limit <= memory_region_size(&s->dma_tt)) {
 324             dma_tt_size = s->dma_tl_limit;
 325         } else {
 326             dma_tt_size = memory_region_size(&s->dma_tt);
 327         }
 328         memory_region_init_alias(&s->dma_tt_alias, OBJECT(s),
 329                                  "dma-table-alias",
 330                                  &s->dma_tt, 0, dma_tt_size);
 331         dma_tl_contents = memory_region_get_ram_ptr(&s->dma_tt);
 332         cpu_physical_memory_read(new_tl_base, dma_tl_contents, dma_tt_size);
 333
 334         memory_region_transaction_begin();
 335         entries = dma_tt_size / sizeof(dma_pagetable_entry);
 336         for (i = 0; i < entries; i++) {
 337             rc4030_dma_as_update_one(s, i, dma_tl_contents[i].frame);
 338         }
 339         memory_region_add_subregion(get_system_memory(), new_tl_base,
 340                                     &s->dma_tt_alias);
 341         memory_region_transaction_commit();
 342     } else {
 343         memory_region_init(&s->dma_tt_alias, OBJECT(s),
 344                            "dma-table-alias", 0);
 345     }
 346 }
 347
 348 static void rc4030_write(void *opaque, hwaddr addr, uint64_t data,
 349                          unsigned int size)
 350 {
 351     rc4030State *s = opaque;
 352     uint32_t val = data;
 353     addr &= 0x3fff;
 354
 355     trace_rc4030_write(addr, val);
 356
 357     switch (addr & ~0x3) {
 358     /* Global config register */
 359     case 0x0000:
 360         s->config = val;
 361         break;
 362     /* DMA transl. table base */
 363     case 0x0018:
 364         rc4030_dma_tt_update(s, val, s->dma_tl_limit);
 365         break;
 366     /* DMA transl. table limit */
 367     case 0x0020:
 368         rc4030_dma_tt_update(s, s->dma_tl_base, val);
 369         break;
 370     /* DMA transl. table invalidated */
 371     case 0x0028:
 372         break;
 373     /* Cache Maintenance */
 374     case 0x0030:
 375         s->cache_maint = val;
 376         break;
 377     /* I/O Cache Physical Tag */
 378     case 0x0048:
 379         s->cache_ptag = val;
 380         break;
 381     /* I/O Cache Logical Tag */
 382     case 0x0050:
 383         s->cache_ltag = val;
 384         break;
 385     /* I/O Cache Byte Mask */
 386     case 0x0058:
 387         s->cache_bmask |= val; /* HACK */
 388         break;
 389     /* I/O Cache Buffer Window */
 390     case 0x0060:
 391         /* HACK */
 392         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 393             hwaddr dest = s->cache_ptag & ~0x1;
 394             dest += (s->cache_maint & 0x3) << 3;
 395             cpu_physical_memory_write(dest, &val, 4);
 396         }
 397         break;
 398     /* Remote Speed Registers */
 399     case 0x0070:
 400     case 0x0078:
 401     case 0x0080:
 402     case 0x0088:
 403     case 0x0090:
 404     case 0x0098:
 405     case 0x00a0:
 406     case 0x00a8:
 407     case 0x00b0:
 408     case 0x00b8:
 409     case 0x00c0:
 410     case 0x00c8:
 411     case 0x00d0:
 412     case 0x00d8:
 413     case 0x00e0:
 414     case 0x00e8:
 415         s->rem_speed[(addr - 0x0070) >> 3] = val;
 416         break;
 417     /* DMA channel base address */
 418     case 0x0100:
 419     case 0x0108:
 420     case 0x0110:
 421     case 0x0118:
 422     case 0x0120:
 423     case 0x0128:
 424     case 0x0130:
 425     case 0x0138:
 426     case 0x0140:
 427     case 0x0148:
 428     case 0x0150:
 429     case 0x0158:
 430     case 0x0160:
 431     case 0x0168:
 432     case 0x0170:
 433     case 0x0178:
 434     case 0x0180:
 435     case 0x0188:
 436     case 0x0190:
 437     case 0x0198:
 438     case 0x01a0:
 439     case 0x01a8:
 440     case 0x01b0:
 441     case 0x01b8:
 442     case 0x01c0:
 443     case 0x01c8:
 444     case 0x01d0:
 445     case 0x01d8:
 446     case 0x01e0:
 447     case 0x01e8:
 448     case 0x01f0:
 449     case 0x01f8:
 450         {
 451             int entry = (addr - 0x0100) >> 5;
 452             int idx = (addr & 0x1f) >> 3;
 453             s->dma_regs[entry][idx] = val;
 454         }
 455         break;
 456     /* Memory refresh rate */
 457     case 0x0210:
 458         s->memory_refresh_rate = val;
 459         break;
 460     /* Interval timer reload */
 461     case 0x0228:
 462         s->itr = val;
 463         qemu_irq_lower(s->timer_irq);
 464         set_next_tick(s);
 465         break;
 466     /* EISA interrupt */
 467     case 0x0238:
 468         break;
 469     default:
 470         qemu_log_mask(LOG_GUEST_ERROR,
 471                       "rc4030: invalid write of 0x%02x at 0x%x",
 472                       val, (int)addr);
 473         break;
 474     }
 475 }
 476
 477 static const MemoryRegionOps rc4030_ops = {
 478     .read = rc4030_read,
 479     .write = rc4030_write,
 480     .impl.min_access_size = 4,
 481     .impl.max_access_size = 4,
 482     .endianness = DEVICE_NATIVE_ENDIAN,
 483 };
 484
 485 static void update_jazz_irq(rc4030State *s)
 486 {
 487     uint16_t pending;
 488
 489     pending = s->isr_jazz & s->imr_jazz;
 490
 491     if (pending != 0)
 492         qemu_irq_raise(s->jazz_bus_irq);
 493     else
 494         qemu_irq_lower(s->jazz_bus_irq);
 495 }
 496
 497 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 498 {
 499     rc4030State *s = opaque;
 500
 501     if (level) {
 502         s->isr_jazz |= 1 << irq;
 503     } else {
 504         s->isr_jazz &= ~(1 << irq);
 505     }
 506
 507     update_jazz_irq(s);
 508 }
 509
 510 static void rc4030_periodic_timer(void *opaque)
 511 {
 512     rc4030State *s = opaque;
 513
 514     set_next_tick(s);
 515     qemu_irq_raise(s->timer_irq);
 516 }
 517
 518 static uint64_t jazzio_read(void *opaque, hwaddr addr, unsigned int size)
 519 {
 520     rc4030State *s = opaque;
 521     uint32_t val;
 522     uint32_t irq;
 523     addr &= 0xfff;
 524
 525     switch (addr) {
 526     /* Local bus int source */
 527     case 0x00: {
 528         uint32_t pending = s->isr_jazz & s->imr_jazz;
 529         val = 0;
 530         irq = 0;
 531         while (pending) {
 532             if (pending & 1) {
 533                 val = (irq + 1) << 2;
 534                 break;
 535             }
 536             irq++;
 537             pending >>= 1;
 538         }
 539         break;
 540     }
 541     /* Local bus int enable mask */
 542     case 0x02:
 543         val = s->imr_jazz;
 544         break;
 545     default:
 546         qemu_log_mask(LOG_GUEST_ERROR,
 547                       "rc4030/jazzio: invalid read at 0x%x", (int)addr);
 548         val = 0;
 549         break;
 550     }
 551
 552     trace_jazzio_read(addr, val);
 553
 554     return val;
 555 }
 556
 557 static void jazzio_write(void *opaque, hwaddr addr, uint64_t data,
 558                          unsigned int size)
 559 {
 560     rc4030State *s = opaque;
 561     uint32_t val = data;
 562     addr &= 0xfff;
 563
 564     trace_jazzio_write(addr, val);
 565
 566     switch (addr) {
 567     /* Local bus int enable mask */
 568     case 0x02:
 569         s->imr_jazz = val;
 570         update_jazz_irq(s);
 571         break;
 572     default:
 573         qemu_log_mask(LOG_GUEST_ERROR,
 574                       "rc4030/jazzio: invalid write of 0x%02x at 0x%x",
 575                       val, (int)addr);
 576         break;
 577     }
 578 }
 579
 580 static const MemoryRegionOps jazzio_ops = {
 581     .read = jazzio_read,
 582     .write = jazzio_write,
 583     .impl.min_access_size = 2,
 584     .impl.max_access_size = 2,
 585     .endianness = DEVICE_NATIVE_ENDIAN,
 586 };
 587
 588 static void rc4030_reset(DeviceState *dev)
 589 {
 590     rc4030State *s = RC4030(dev);
 591     int i;
 592
 593     s->config = 0x410; /* some boards seem to accept 0x104 too */
 594     s->revision = 1;
 595     s->invalid_address_register = 0;
 596
 597     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 598     rc4030_dma_tt_update(s, 0, 0);
 599
 600     s->remote_failed_address = s->memory_failed_address = 0;
 601     s->cache_maint = 0;
 602     s->cache_ptag = s->cache_ltag = 0;
 603     s->cache_bmask = 0;
 604
 605     s->memory_refresh_rate = 0x18186;
 606     s->nvram_protect = 7;
 607     for (i = 0; i < 15; i++)
 608         s->rem_speed[i] = 7;
 609     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 610     s->isr_jazz = 0;
 611
 612     s->itr = 0;
 613
 614     qemu_irq_lower(s->timer_irq);
 615     qemu_irq_lower(s->jazz_bus_irq);
 616 }
 617
 618 static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
 619 {
 620     rc4030State* s = opaque;
 621     int i, j;
 622
 623     if (version_id != 2)
 624         return -EINVAL;
 625
 626     s->config = qemu_get_be32(f);
 627     s->invalid_address_register = qemu_get_be32(f);
 628     for (i = 0; i < 8; i++)
 629         for (j = 0; j < 4; j++)
 630             s->dma_regs[i][j] = qemu_get_be32(f);
 631     s->dma_tl_base = qemu_get_be32(f);
 632     s->dma_tl_limit = qemu_get_be32(f);
 633     s->cache_maint = qemu_get_be32(f);
 634     s->remote_failed_address = qemu_get_be32(f);
 635     s->memory_failed_address = qemu_get_be32(f);
 636     s->cache_ptag = qemu_get_be32(f);
 637     s->cache_ltag = qemu_get_be32(f);
 638     s->cache_bmask = qemu_get_be32(f);
 639     s->memory_refresh_rate = qemu_get_be32(f);
 640     s->nvram_protect = qemu_get_be32(f);
 641     for (i = 0; i < 15; i++)
 642         s->rem_speed[i] = qemu_get_be32(f);
 643     s->imr_jazz = qemu_get_be32(f);
 644     s->isr_jazz = qemu_get_be32(f);
 645     s->itr = qemu_get_be32(f);
 646
 647     set_next_tick(s);
 648     update_jazz_irq(s);
 649
 650     return 0;
 651 }
 652
 653 static void rc4030_save(QEMUFile *f, void *opaque)
 654 {
 655     rc4030State* s = opaque;
 656     int i, j;
 657
 658     qemu_put_be32(f, s->config);
 659     qemu_put_be32(f, s->invalid_address_register);
 660     for (i = 0; i < 8; i++)
 661         for (j = 0; j < 4; j++)
 662             qemu_put_be32(f, s->dma_regs[i][j]);
 663     qemu_put_be32(f, s->dma_tl_base);
 664     qemu_put_be32(f, s->dma_tl_limit);
 665     qemu_put_be32(f, s->cache_maint);
 666     qemu_put_be32(f, s->remote_failed_address);
 667     qemu_put_be32(f, s->memory_failed_address);
 668     qemu_put_be32(f, s->cache_ptag);
 669     qemu_put_be32(f, s->cache_ltag);
 670     qemu_put_be32(f, s->cache_bmask);
 671     qemu_put_be32(f, s->memory_refresh_rate);
 672     qemu_put_be32(f, s->nvram_protect);
 673     for (i = 0; i < 15; i++)
 674         qemu_put_be32(f, s->rem_speed[i]);
 675     qemu_put_be32(f, s->imr_jazz);
 676     qemu_put_be32(f, s->isr_jazz);
 677     qemu_put_be32(f, s->itr);
 678 }
 679
 680 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
 681 {
 682     rc4030State *s = opaque;
 683     hwaddr dma_addr;
 684     int dev_to_mem;
 685
 686     s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 687
 688     /* Check DMA channel consistency */
 689     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 690     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 691         (is_write != dev_to_mem)) {
 692         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 693         s->nmi_interrupt |= 1 << n;
 694         return;
 695     }
 696
 697     /* Get start address and len */
 698     if (len > s->dma_regs[n][DMA_REG_COUNT])
 699         len = s->dma_regs[n][DMA_REG_COUNT];
 700     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 701
 702     /* Read/write data at right place */
 703     address_space_rw(&s->dma_as, dma_addr, MEMTXATTRS_UNSPECIFIED,
 704                      buf, len, is_write);
 705
 706     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 707     s->dma_regs[n][DMA_REG_COUNT] -= len;
 708 }
 709
 710 struct rc4030DMAState {
 711     void *opaque;
 712     int n;
 713 };
 714
 715 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 716 {
 717     rc4030_dma s = dma;
 718     rc4030_do_dma(s->opaque, s->n, buf, len, 0);
 719 }
 720
 721 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 722 {
 723     rc4030_dma s = dma;
 724     rc4030_do_dma(s->opaque, s->n, buf, len, 1);
 725 }
 726
 727 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 728 {
 729     rc4030_dma *s;
 730     struct rc4030DMAState *p;
 731     int i;
 732
 733     s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
 734     p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
 735     for (i = 0; i < n; i++) {
 736         p->opaque = opaque;
 737         p->n = i;
 738         s[i] = p;
 739         p++;
 740     }
 741     return s;
 742 }
 743
 744 static void rc4030_initfn(Object *obj)
 745 {
 746     DeviceState *dev = DEVICE(obj);
 747     rc4030State *s = RC4030(obj);
 748     SysBusDevice *sysbus = SYS_BUS_DEVICE(obj);
 749
 750     qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16);
 751
 752     sysbus_init_irq(sysbus, &s->timer_irq);
 753     sysbus_init_irq(sysbus, &s->jazz_bus_irq);
 754
 755     register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
 756
 757     sysbus_init_mmio(sysbus, &s->iomem_chipset);
 758     sysbus_init_mmio(sysbus, &s->iomem_jazzio);
 759 }
 760
 761 static void rc4030_realize(DeviceState *dev, Error **errp)
 762 {
 763     rc4030State *s = RC4030(dev);
 764     Object *o = OBJECT(dev);
 765     int i;
 766
 767     s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 768                                      rc4030_periodic_timer, s);
 769
 770     memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
 771                           "rc4030.chipset", 0x300);
 772     memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
 773                           "rc4030.jazzio", 0x00001000);
 774
 775     memory_region_init_rom_device(&s->dma_tt, o,
 776                                   &rc4030_dma_tt_ops, s, "dma-table",
 777                                   MAX_TL_ENTRIES * sizeof(dma_pagetable_entry),
 778                                   NULL);
 779     memory_region_init(&s->dma_tt_alias, o, "dma-table-alias", 0);
 780     memory_region_init(&s->dma_mr, o, "dma", INT32_MAX);
 781     for (i = 0; i < MAX_TL_ENTRIES; ++i) {
 782         memory_region_init_alias(&s->dma_mrs[i], o, "dma-alias",
 783                                  get_system_memory(), 0, DMA_PAGESIZE);
 784         memory_region_set_enabled(&s->dma_mrs[i], false);
 785         memory_region_add_subregion(&s->dma_mr, i * DMA_PAGESIZE,
 786                                     &s->dma_mrs[i]);
 787     }
 788     address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma");
 789 }
 790
 791 static void rc4030_unrealize(DeviceState *dev, Error **errp)
 792 {
 793     rc4030State *s = RC4030(dev);
 794     int i;
 795
 796     timer_free(s->periodic_timer);
 797
 798     address_space_destroy(&s->dma_as);
 799     object_unparent(OBJECT(&s->dma_tt));
 800     object_unparent(OBJECT(&s->dma_tt_alias));
 801     object_unparent(OBJECT(&s->dma_mr));
 802     for (i = 0; i < MAX_TL_ENTRIES; ++i) {
 803         memory_region_del_subregion(&s->dma_mr, &s->dma_mrs[i]);
 804         object_unparent(OBJECT(&s->dma_mrs[i]));
 805     }
 806 }
 807
 808 static void rc4030_class_init(ObjectClass *klass, void *class_data)
 809 {
 810     DeviceClass *dc = DEVICE_CLASS(klass);
 811
 812     dc->realize = rc4030_realize;
 813     dc->unrealize = rc4030_unrealize;
 814     dc->reset = rc4030_reset;
 815 }
 816
 817 static const TypeInfo rc4030_info = {
 818     .name = TYPE_RC4030,
 819     .parent = TYPE_SYS_BUS_DEVICE,
 820     .instance_size = sizeof(rc4030State),
 821     .instance_init = rc4030_initfn,
 822     .class_init = rc4030_class_init,
 823 };
 824
 825 static void rc4030_register_types(void)
 826 {
 827     type_register_static(&rc4030_info);
 828 }
 829
 830 type_init(rc4030_register_types)
 831
 832 DeviceState *rc4030_init(rc4030_dma **dmas, MemoryRegion **dma_mr)
 833 {
 834     DeviceState *dev;
 835
 836     dev = qdev_create(NULL, TYPE_RC4030);
 837     qdev_init_nofail(dev);
 838
 839     *dmas = rc4030_allocate_dmas(dev, 4);
 840     *dma_mr = &RC4030(dev)->dma_mr;
 841     return dev;
 842 }