2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "hw/sysbus.h"
14 #include "qemu/timer.h"
15 #include "hw/arm/arm.h"
16 #include "exec/address-spaces.h"
17 #include "gic_internal.h"
27 MemoryRegion sysregmem
;
28 MemoryRegion gic_iomem_alias
;
29 MemoryRegion container
;
33 #define TYPE_NVIC "armv7m_nvic"
36 * @parent_reset: the parent class' reset handler.
38 * A model of the v7M NVIC and System Controller
40 typedef struct NVICClass
{
42 ARMGICClass parent_class
;
44 DeviceRealize parent_realize
;
45 void (*parent_reset
)(DeviceState
*dev
);
48 #define NVIC_CLASS(klass) \
49 OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
50 #define NVIC_GET_CLASS(obj) \
51 OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
53 OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
55 static const uint8_t nvic_id
[] = {
56 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
59 /* qemu timers run at 1GHz. We want something closer to 1MHz. */
60 #define SYSTICK_SCALE 1000ULL
62 #define SYSTICK_ENABLE (1 << 0)
63 #define SYSTICK_TICKINT (1 << 1)
64 #define SYSTICK_CLKSOURCE (1 << 2)
65 #define SYSTICK_COUNTFLAG (1 << 16)
67 int system_clock_scale
;
69 /* Conversion factor from qemu timer to SysTick frequencies. */
70 static inline int64_t systick_scale(nvic_state
*s
)
72 if (s
->systick
.control
& SYSTICK_CLKSOURCE
)
73 return system_clock_scale
;
78 static void systick_reload(nvic_state
*s
, int reset
)
81 s
->systick
.tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
82 s
->systick
.tick
+= (s
->systick
.reload
+ 1) * systick_scale(s
);
83 timer_mod(s
->systick
.timer
, s
->systick
.tick
);
86 static void systick_timer_tick(void * opaque
)
88 nvic_state
*s
= (nvic_state
*)opaque
;
89 s
->systick
.control
|= SYSTICK_COUNTFLAG
;
90 if (s
->systick
.control
& SYSTICK_TICKINT
) {
91 /* Trigger the interrupt. */
92 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
94 if (s
->systick
.reload
== 0) {
95 s
->systick
.control
&= ~SYSTICK_ENABLE
;
101 static void systick_reset(nvic_state
*s
)
103 s
->systick
.control
= 0;
104 s
->systick
.reload
= 0;
106 timer_del(s
->systick
.timer
);
109 /* The external routines use the hardware vector numbering, ie. the first
110 IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
111 void armv7m_nvic_set_pending(void *opaque
, int irq
)
113 nvic_state
*s
= (nvic_state
*)opaque
;
116 gic_set_pending_private(&s
->gic
, 0, irq
);
119 /* Make pending IRQ active. */
120 int armv7m_nvic_acknowledge_irq(void *opaque
)
122 nvic_state
*s
= (nvic_state
*)opaque
;
125 irq
= gic_acknowledge_irq(&s
->gic
, 0);
127 hw_error("Interrupt but no vector\n");
133 void armv7m_nvic_complete_irq(void *opaque
, int irq
)
135 nvic_state
*s
= (nvic_state
*)opaque
;
138 gic_complete_irq(&s
->gic
, 0, irq
);
141 static uint32_t nvic_readl(nvic_state
*s
, uint32_t offset
)
148 case 4: /* Interrupt Control Type. */
149 return (s
->num_irq
/ 32) - 1;
150 case 0x10: /* SysTick Control and Status. */
151 val
= s
->systick
.control
;
152 s
->systick
.control
&= ~SYSTICK_COUNTFLAG
;
154 case 0x14: /* SysTick Reload Value. */
155 return s
->systick
.reload
;
156 case 0x18: /* SysTick Current Value. */
159 if ((s
->systick
.control
& SYSTICK_ENABLE
) == 0)
161 t
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
162 if (t
>= s
->systick
.tick
)
164 val
= ((s
->systick
.tick
- (t
+ 1)) / systick_scale(s
)) + 1;
165 /* The interrupt in triggered when the timer reaches zero.
166 However the counter is not reloaded until the next clock
167 tick. This is a hack to return zero during the first tick. */
168 if (val
> s
->systick
.reload
)
172 case 0x1c: /* SysTick Calibration Value. */
174 case 0xd00: /* CPUID Base. */
175 cpu
= ARM_CPU(current_cpu
);
177 case 0xd04: /* Interrupt Control State. */
179 val
= s
->gic
.running_irq
[0];
182 } else if (val
>= 32) {
186 if (s
->gic
.running_irq
[0] == 1023
187 || s
->gic
.last_active
[s
->gic
.running_irq
[0]][0] == 1023) {
191 if (s
->gic
.current_pending
[0] != 1023)
192 val
|= (s
->gic
.current_pending
[0] << 12);
194 for (irq
= 32; irq
< s
->num_irq
; irq
++) {
195 if (s
->gic
.irq_state
[irq
].pending
) {
201 if (s
->gic
.irq_state
[ARMV7M_EXCP_SYSTICK
].pending
)
204 if (s
->gic
.irq_state
[ARMV7M_EXCP_PENDSV
].pending
)
207 if (s
->gic
.irq_state
[ARMV7M_EXCP_NMI
].pending
)
210 case 0xd08: /* Vector Table Offset. */
211 cpu
= ARM_CPU(current_cpu
);
212 return cpu
->env
.v7m
.vecbase
;
213 case 0xd0c: /* Application Interrupt/Reset Control. */
215 case 0xd10: /* System Control. */
216 /* TODO: Implement SLEEPONEXIT. */
218 case 0xd14: /* Configuration Control. */
219 /* TODO: Implement Configuration Control bits. */
221 case 0xd24: /* System Handler Status. */
223 if (s
->gic
.irq_state
[ARMV7M_EXCP_MEM
].active
) val
|= (1 << 0);
224 if (s
->gic
.irq_state
[ARMV7M_EXCP_BUS
].active
) val
|= (1 << 1);
225 if (s
->gic
.irq_state
[ARMV7M_EXCP_USAGE
].active
) val
|= (1 << 3);
226 if (s
->gic
.irq_state
[ARMV7M_EXCP_SVC
].active
) val
|= (1 << 7);
227 if (s
->gic
.irq_state
[ARMV7M_EXCP_DEBUG
].active
) val
|= (1 << 8);
228 if (s
->gic
.irq_state
[ARMV7M_EXCP_PENDSV
].active
) val
|= (1 << 10);
229 if (s
->gic
.irq_state
[ARMV7M_EXCP_SYSTICK
].active
) val
|= (1 << 11);
230 if (s
->gic
.irq_state
[ARMV7M_EXCP_USAGE
].pending
) val
|= (1 << 12);
231 if (s
->gic
.irq_state
[ARMV7M_EXCP_MEM
].pending
) val
|= (1 << 13);
232 if (s
->gic
.irq_state
[ARMV7M_EXCP_BUS
].pending
) val
|= (1 << 14);
233 if (s
->gic
.irq_state
[ARMV7M_EXCP_SVC
].pending
) val
|= (1 << 15);
234 if (s
->gic
.irq_state
[ARMV7M_EXCP_MEM
].enabled
) val
|= (1 << 16);
235 if (s
->gic
.irq_state
[ARMV7M_EXCP_BUS
].enabled
) val
|= (1 << 17);
236 if (s
->gic
.irq_state
[ARMV7M_EXCP_USAGE
].enabled
) val
|= (1 << 18);
238 case 0xd28: /* Configurable Fault Status. */
239 /* TODO: Implement Fault Status. */
240 qemu_log_mask(LOG_UNIMP
, "Configurable Fault Status unimplemented\n");
242 case 0xd2c: /* Hard Fault Status. */
243 case 0xd30: /* Debug Fault Status. */
244 case 0xd34: /* Mem Manage Address. */
245 case 0xd38: /* Bus Fault Address. */
246 case 0xd3c: /* Aux Fault Status. */
247 /* TODO: Implement fault status registers. */
248 qemu_log_mask(LOG_UNIMP
, "Fault status registers unimplemented\n");
250 case 0xd40: /* PFR0. */
252 case 0xd44: /* PRF1. */
254 case 0xd48: /* DFR0. */
256 case 0xd4c: /* AFR0. */
258 case 0xd50: /* MMFR0. */
260 case 0xd54: /* MMFR1. */
262 case 0xd58: /* MMFR2. */
264 case 0xd5c: /* MMFR3. */
266 case 0xd60: /* ISAR0. */
268 case 0xd64: /* ISAR1. */
270 case 0xd68: /* ISAR2. */
272 case 0xd6c: /* ISAR3. */
274 case 0xd70: /* ISAR4. */
276 /* TODO: Implement debug registers. */
278 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
283 static void nvic_writel(nvic_state
*s
, uint32_t offset
, uint32_t value
)
288 case 0x10: /* SysTick Control and Status. */
289 oldval
= s
->systick
.control
;
290 s
->systick
.control
&= 0xfffffff8;
291 s
->systick
.control
|= value
& 7;
292 if ((oldval
^ value
) & SYSTICK_ENABLE
) {
293 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
294 if (value
& SYSTICK_ENABLE
) {
295 if (s
->systick
.tick
) {
296 s
->systick
.tick
+= now
;
297 timer_mod(s
->systick
.timer
, s
->systick
.tick
);
299 systick_reload(s
, 1);
302 timer_del(s
->systick
.timer
);
303 s
->systick
.tick
-= now
;
304 if (s
->systick
.tick
< 0)
307 } else if ((oldval
^ value
) & SYSTICK_CLKSOURCE
) {
308 /* This is a hack. Force the timer to be reloaded
309 when the reference clock is changed. */
310 systick_reload(s
, 1);
313 case 0x14: /* SysTick Reload Value. */
314 s
->systick
.reload
= value
;
316 case 0x18: /* SysTick Current Value. Writes reload the timer. */
317 systick_reload(s
, 1);
318 s
->systick
.control
&= ~SYSTICK_COUNTFLAG
;
320 case 0xd04: /* Interrupt Control State. */
321 if (value
& (1 << 31)) {
322 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
);
324 if (value
& (1 << 28)) {
325 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
);
326 } else if (value
& (1 << 27)) {
327 s
->gic
.irq_state
[ARMV7M_EXCP_PENDSV
].pending
= 0;
330 if (value
& (1 << 26)) {
331 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
332 } else if (value
& (1 << 25)) {
333 s
->gic
.irq_state
[ARMV7M_EXCP_SYSTICK
].pending
= 0;
337 case 0xd08: /* Vector Table Offset. */
338 cpu
= ARM_CPU(current_cpu
);
339 cpu
->env
.v7m
.vecbase
= value
& 0xffffff80;
341 case 0xd0c: /* Application Interrupt/Reset Control. */
342 if ((value
>> 16) == 0x05fa) {
344 qemu_log_mask(LOG_UNIMP
, "VECTCLRACTIVE unimplemented\n");
347 qemu_log_mask(LOG_UNIMP
, "AIRCR system reset unimplemented\n");
351 case 0xd10: /* System Control. */
352 case 0xd14: /* Configuration Control. */
353 /* TODO: Implement control registers. */
354 qemu_log_mask(LOG_UNIMP
, "NVIC: SCR and CCR unimplemented\n");
356 case 0xd24: /* System Handler Control. */
357 /* TODO: Real hardware allows you to set/clear the active bits
358 under some circumstances. We don't implement this. */
359 s
->gic
.irq_state
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
360 s
->gic
.irq_state
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
361 s
->gic
.irq_state
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
363 case 0xd28: /* Configurable Fault Status. */
364 case 0xd2c: /* Hard Fault Status. */
365 case 0xd30: /* Debug Fault Status. */
366 case 0xd34: /* Mem Manage Address. */
367 case 0xd38: /* Bus Fault Address. */
368 case 0xd3c: /* Aux Fault Status. */
369 qemu_log_mask(LOG_UNIMP
,
370 "NVIC: fault status registers unimplemented\n");
372 case 0xf00: /* Software Triggered Interrupt Register */
373 if ((value
& 0x1ff) < s
->num_irq
) {
374 gic_set_pending_private(&s
->gic
, 0, value
& 0x1ff);
378 qemu_log_mask(LOG_GUEST_ERROR
,
379 "NVIC: Bad write offset 0x%x\n", offset
);
383 static uint64_t nvic_sysreg_read(void *opaque
, hwaddr addr
,
386 nvic_state
*s
= (nvic_state
*)opaque
;
387 uint32_t offset
= addr
;
392 case 0xd18 ... 0xd23: /* System Handler Priority. */
394 for (i
= 0; i
< size
; i
++) {
395 val
|= s
->gic
.priority1
[(offset
- 0xd14) + i
][0] << (i
* 8);
398 case 0xfe0 ... 0xfff: /* ID. */
402 return nvic_id
[(offset
- 0xfe0) >> 2];
405 return nvic_readl(s
, offset
);
407 qemu_log_mask(LOG_GUEST_ERROR
,
408 "NVIC: Bad read of size %d at offset 0x%x\n", size
, offset
);
412 static void nvic_sysreg_write(void *opaque
, hwaddr addr
,
413 uint64_t value
, unsigned size
)
415 nvic_state
*s
= (nvic_state
*)opaque
;
416 uint32_t offset
= addr
;
420 case 0xd18 ... 0xd23: /* System Handler Priority. */
421 for (i
= 0; i
< size
; i
++) {
422 s
->gic
.priority1
[(offset
- 0xd14) + i
][0] =
423 (value
>> (i
* 8)) & 0xff;
429 nvic_writel(s
, offset
, value
);
432 qemu_log_mask(LOG_GUEST_ERROR
,
433 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
436 static const MemoryRegionOps nvic_sysreg_ops
= {
437 .read
= nvic_sysreg_read
,
438 .write
= nvic_sysreg_write
,
439 .endianness
= DEVICE_NATIVE_ENDIAN
,
442 static const VMStateDescription vmstate_nvic
= {
443 .name
= "armv7m_nvic",
445 .minimum_version_id
= 1,
446 .minimum_version_id_old
= 1,
447 .fields
= (VMStateField
[]) {
448 VMSTATE_UINT32(systick
.control
, nvic_state
),
449 VMSTATE_UINT32(systick
.reload
, nvic_state
),
450 VMSTATE_INT64(systick
.tick
, nvic_state
),
451 VMSTATE_TIMER(systick
.timer
, nvic_state
),
452 VMSTATE_END_OF_LIST()
456 static void armv7m_nvic_reset(DeviceState
*dev
)
458 nvic_state
*s
= NVIC(dev
);
459 NVICClass
*nc
= NVIC_GET_CLASS(s
);
460 nc
->parent_reset(dev
);
461 /* Common GIC reset resets to disabled; the NVIC doesn't have
462 * per-CPU interfaces so mark our non-existent CPU interface
463 * as enabled by default, and with a priority mask which allows
464 * all interrupts through.
466 s
->gic
.cpu_enabled
[0] = true;
467 s
->gic
.priority_mask
[0] = 0x100;
468 /* The NVIC as a whole is always enabled. */
469 s
->gic
.enabled
= true;
473 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
475 nvic_state
*s
= NVIC(dev
);
476 NVICClass
*nc
= NVIC_GET_CLASS(s
);
477 Error
*local_err
= NULL
;
479 /* The NVIC always has only one CPU */
481 /* Tell the common code we're an NVIC */
482 s
->gic
.revision
= 0xffffffff;
483 s
->num_irq
= s
->gic
.num_irq
;
484 nc
->parent_realize(dev
, &local_err
);
486 error_propagate(errp
, local_err
);
489 gic_init_irqs_and_distributor(&s
->gic
, s
->num_irq
);
490 /* The NVIC and system controller register area looks like this:
491 * 0..0xff : system control registers, including systick
492 * 0x100..0xcff : GIC-like registers
493 * 0xd00..0xfff : system control registers
494 * We use overlaying to put the GIC like registers
495 * over the top of the system control register region.
497 memory_region_init(&s
->container
, OBJECT(s
), "nvic", 0x1000);
498 /* The system register region goes at the bottom of the priority
499 * stack as it covers the whole page.
501 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
502 "nvic_sysregs", 0x1000);
503 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
504 /* Alias the GIC region so we can get only the section of it
505 * we need, and layer it on top of the system register region.
507 memory_region_init_alias(&s
->gic_iomem_alias
, OBJECT(s
),
508 "nvic-gic", &s
->gic
.iomem
,
510 memory_region_add_subregion_overlap(&s
->container
, 0x100,
511 &s
->gic_iomem_alias
, 1);
512 /* Map the whole thing into system memory at the location required
513 * by the v7M architecture.
515 memory_region_add_subregion(get_system_memory(), 0xe000e000, &s
->container
);
516 s
->systick
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, systick_timer_tick
, s
);
519 static void armv7m_nvic_instance_init(Object
*obj
)
521 /* We have a different default value for the num-irq property
522 * than our superclass. This function runs after qdev init
523 * has set the defaults from the Property array and before
524 * any user-specified property setting, so just modify the
525 * value in the GICState struct.
527 GICState
*s
= ARM_GIC_COMMON(obj
);
528 /* The ARM v7m may have anything from 0 to 496 external interrupt
529 * IRQ lines. We default to 64. Other boards may differ and should
530 * set the num-irq property appropriately.
535 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
537 NVICClass
*nc
= NVIC_CLASS(klass
);
538 DeviceClass
*dc
= DEVICE_CLASS(klass
);
540 nc
->parent_reset
= dc
->reset
;
541 nc
->parent_realize
= dc
->realize
;
542 dc
->vmsd
= &vmstate_nvic
;
543 dc
->reset
= armv7m_nvic_reset
;
544 dc
->realize
= armv7m_nvic_realize
;
547 static const TypeInfo armv7m_nvic_info
= {
549 .parent
= TYPE_ARM_GIC_COMMON
,
550 .instance_init
= armv7m_nvic_instance_init
,
551 .instance_size
= sizeof(nvic_state
),
552 .class_init
= armv7m_nvic_class_init
,
553 .class_size
= sizeof(NVICClass
),
556 static void armv7m_nvic_register_types(void)
558 type_register_static(&armv7m_nvic_info
);
561 type_init(armv7m_nvic_register_types
)