microblaze-dis.c

   1 /* Disassemble Xilinx microblaze instructions.
   2    Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 /*
  19  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms are permitted
  22  * provided that the above copyright notice and this paragraph are
  23  * duplicated in all such forms and that any documentation,
  24  * advertising materials, and other materials related to such
  25  * distribution and use acknowledge that the software was developed
  26  * by Xilinx, Inc.  The name of the Company may not be used to endorse
  27  * or promote products derived from this software without specific prior
  28  * written permission.
  29  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  30  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  31  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  32  *
  33  *      Xilinx, Inc.
  34  */
  35
  36
  37 #include <stdio.h>
  38 #define STATIC_TABLE
  39 #define DEFINE_TABLE
  40
  41 #define TRUE   1
  42 #define FALSE  0
  43
  44 #ifndef MICROBLAZE_OPC
  45 #define MICROBLAZE_OPC
  46 /* Assembler instructions for Xilinx's microblaze processor
  47    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
  48
  49
  50 This program is free software; you can redistribute it and/or modify
  51 it under the terms of the GNU General Public License as published by
  52 the Free Software Foundation; either version 2 of the License, or
  53 (at your option) any later version.
  54
  55 This program is distributed in the hope that it will be useful,
  56 but WITHOUT ANY WARRANTY; without even the implied warranty of
  57 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  58 GNU General Public License for more details.
  59
  60 You should have received a copy of the GNU General Public License
  61 along with this program; if not, write to the Free Software
  62 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  63
  64 /*
  65  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved.
  66  *
  67  * Redistribution and use in source and binary forms are permitted
  68  * provided that the above copyright notice and this paragraph are
  69  * duplicated in all such forms and that any documentation,
  70  * advertising materials, and other materials related to such
  71  * distribution and use acknowledge that the software was developed
  72  * by Xilinx, Inc.  The name of the Company may not be used to endorse
  73  * or promote products derived from this software without specific prior
  74  * written permission.
  75  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  76  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  77  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  78  *
  79  *      Xilinx, Inc.
  80  */
  81
  82
  83 #ifndef MICROBLAZE_OPCM
  84 #define MICROBLAZE_OPCM
  85
  86 /*
  87  * Copyright (c) 2001 Xilinx, Inc.  All rights reserved.
  88  *
  89  * Redistribution and use in source and binary forms are permitted
  90  * provided that the above copyright notice and this paragraph are
  91  * duplicated in all such forms and that any documentation,
  92  * advertising materials, and other materials related to such
  93  * distribution and use acknowledge that the software was developed
  94  * by Xilinx, Inc.  The name of the Company may not be used to endorse
  95  * or promote products derived from this software without specific prior
  96  * written permission.
  97  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  98  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  99  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 100  *
 101  *      Xilinx, Inc.
 102  * $Header:
 103  */
 104
 105 enum microblaze_instr {
 106    add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
 107    addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu,
 108    idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
 109    ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
 110    andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
 111    brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
 112    bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
 113    imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
 114    brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
 115    bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
 116    sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
 117    fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt,
 118    tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
 119    eget, ecget, neget, necget, eput, ecput, neput, necput,
 120    teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
 121    aget, caget, naget, ncaget, aput, caput, naput, ncaput,
 122    taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
 123    eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
 124    teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
 125    getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
 126    putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
 127    egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
 128    eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
 129    agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
 130    aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
 131    eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
 132    eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
 133    invalid_inst } ;
 134
 135 enum microblaze_instr_type {
 136    arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
 137    return_inst, immediate_inst, special_inst, memory_load_inst,
 138    memory_store_inst, barrel_shift_inst, anyware_inst };
 139
 140 #define INST_WORD_SIZE 4
 141
 142 /* gen purpose regs go from 0 to 31 */
 143 /* mask is reg num - max_reg_num, ie reg_num - 32 in this case */
 144
 145 #define REG_PC_MASK 0x8000
 146 #define REG_MSR_MASK 0x8001
 147 #define REG_EAR_MASK 0x8003
 148 #define REG_ESR_MASK 0x8005
 149 #define REG_FSR_MASK 0x8007
 150 #define REG_BTR_MASK 0x800b
 151 #define REG_EDR_MASK 0x800d
 152 #define REG_PVR_MASK 0xa000
 153
 154 #define REG_PID_MASK   0x9000
 155 #define REG_ZPR_MASK   0x9001
 156 #define REG_TLBX_MASK  0x9002
 157 #define REG_TLBLO_MASK 0x9003
 158 #define REG_TLBHI_MASK 0x9004
 159 #define REG_TLBSX_MASK 0x9005
 160
 161 #define MIN_REGNUM 0
 162 #define MAX_REGNUM 31
 163
 164 #define MIN_PVR_REGNUM 0
 165 #define MAX_PVR_REGNUM 15
 166
 167 #define REG_PC  32 /* PC */
 168 #define REG_MSR 33 /* machine status reg */
 169 #define REG_EAR 35 /* Exception reg */
 170 #define REG_ESR 37 /* Exception reg */
 171 #define REG_FSR 39 /* FPU Status reg */
 172 #define REG_BTR 43 /* Branch Target reg */
 173 #define REG_EDR 45 /* Exception reg */
 174 #define REG_PVR 40960 /* Program Verification reg */
 175
 176 #define REG_PID   36864 /* MMU: Process ID reg       */
 177 #define REG_ZPR   36865 /* MMU: Zone Protect reg     */
 178 #define REG_TLBX  36866 /* MMU: TLB Index reg        */
 179 #define REG_TLBLO 36867 /* MMU: TLB Low reg          */
 180 #define REG_TLBHI 36868 /* MMU: TLB High reg         */
 181 #define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
 182
 183 /* alternate names for gen purpose regs */
 184 #define REG_SP  1 /* stack pointer */
 185 #define REG_ROSDP 2 /* read-only small data pointer */
 186 #define REG_RWSDP 13 /* read-write small data pointer */
 187
 188 /* Assembler Register - Used in Delay Slot Optimization */
 189 #define REG_AS    18
 190 #define REG_ZERO  0
 191
 192 #define RD_LOW  21 /* low bit for RD */
 193 #define RA_LOW  16 /* low bit for RA */
 194 #define RB_LOW  11 /* low bit for RB */
 195 #define IMM_LOW  0 /* low bit for immediate */
 196
 197 #define RD_MASK 0x03E00000
 198 #define RA_MASK 0x001F0000
 199 #define RB_MASK 0x0000F800
 200 #define IMM_MASK 0x0000FFFF
 201
 202 // imm mask for barrel shifts
 203 #define IMM5_MASK 0x0000001F
 204
 205
 206 // FSL imm mask for get, put instructions
 207 #define  RFSL_MASK 0x000000F
 208
 209 // imm mask for msrset, msrclr instructions
 210 #define  IMM15_MASK 0x00007FFF
 211
 212 #endif /* MICROBLAZE-OPCM */
 213
 214 #define INST_TYPE_RD_R1_R2 0
 215 #define INST_TYPE_RD_R1_IMM 1
 216 #define INST_TYPE_RD_R1_UNSIGNED_IMM 2
 217 #define INST_TYPE_RD_R1 3
 218 #define INST_TYPE_RD_R2 4
 219 #define INST_TYPE_RD_IMM 5
 220 #define INST_TYPE_R2 6
 221 #define INST_TYPE_R1_R2 7
 222 #define INST_TYPE_R1_IMM 8
 223 #define INST_TYPE_IMM 9
 224 #define INST_TYPE_SPECIAL_R1 10
 225 #define INST_TYPE_RD_SPECIAL 11
 226 #define INST_TYPE_R1 12
 227   // new instn type for barrel shift imms
 228 #define INST_TYPE_RD_R1_IMM5  13
 229 #define INST_TYPE_RD_RFSL    14
 230 #define INST_TYPE_R1_RFSL    15
 231
 232   // new insn type for insn cache
 233 #define INST_TYPE_RD_R1_SPECIAL 16
 234
 235 // new insn type for msrclr, msrset insns.
 236 #define INST_TYPE_RD_IMM15    17
 237
 238 // new insn type for tuqula rd - addik rd, r0, 42
 239 #define INST_TYPE_RD    18
 240
 241 // new insn type for t*put
 242 #define INST_TYPE_RFSL  19
 243
 244 #define INST_TYPE_NONE 25
 245
 246
 247
 248 #define INST_PC_OFFSET 1 /* instructions where the label address is resolved as a PC offset (for branch label)*/
 249 #define INST_NO_OFFSET 0 /* instructions where the label address is resolved as an absolute value (for data mem or abs address)*/
 250
 251 #define IMMVAL_MASK_NON_SPECIAL 0x0000
 252 #define IMMVAL_MASK_MTS 0x4000
 253 #define IMMVAL_MASK_MFS 0x0000
 254
 255 #define OPCODE_MASK_H   0xFC000000 /* High 6 bits only */
 256 #define OPCODE_MASK_H1  0xFFE00000 /* High 11 bits */
 257 #define OPCODE_MASK_H2  0xFC1F0000 /* High 6 and bits 20-16 */
 258 #define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */
 259 #define OPCODE_MASK_H4  0xFC0007FF /* High 6 and low 11 bits */
 260 #define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
 261 #define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
 262 #define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */
 263 #define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */
 264 #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */
 265 #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits */
 266 #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */
 267 #define OPCODE_MASK_H3  0xFC000600 /* High 6 bits and bits 21, 22 */
 268 #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */
 269 #define OPCODE_MASK_H34B   0xFC0000FF /* High 6 bits and low 8 bits */
 270 #define OPCODE_MASK_H34C   0xFC0007E0 /* High 6 bits and bits 21-26 */
 271
 272 // New Mask for msrset, msrclr insns.
 273 #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16 */
 274
 275 #define DELAY_SLOT 1
 276 #define NO_DELAY_SLOT 0
 277
 278 #define MAX_OPCODES 280
 279
 280 struct op_code_struct {
 281   const char *name;
 282   short inst_type; /* registers and immediate values involved */
 283   short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */
 284   short delay_slots; /* info about delay slots needed after this instr. */
 285   short immval_mask;
 286   unsigned long bit_sequence; /* all the fixed bits for the op are set and all the variable bits (reg names, imm vals) are set to 0 */
 287   unsigned long opcode_mask; /* which bits define the opcode */
 288   enum microblaze_instr instr;
 289   enum microblaze_instr_type instr_type;
 290   /* more info about output format here */
 291 } opcodes[MAX_OPCODES] =
 292
 293 {
 294   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
 295   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
 296   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
 297   {"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
 298   {"addk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
 299   {"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
 300   {"cmp",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
 301   {"cmpu",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
 302   {"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
 303   {"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
 304   {"addi",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
 305   {"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
 306   {"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
 307   {"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
 308   {"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
 309   {"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
 310   {"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
 311   {"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
 312   {"mul",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
 313   {"mulh",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
 314   {"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
 315   {"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
 316   {"idiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
 317   {"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
 318   {"bsll",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
 319   {"bsra",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
 320   {"bsrl",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
 321   {"get",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
 322   {"put",   INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
 323   {"nget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
 324   {"nput",  INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
 325   {"cget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
 326   {"cput",  INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
 327   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
 328   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
 329   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
 330   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
 331   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
 332   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
 333   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
 334   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
 335   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
 336   {"andn",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
 337   {"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
 338   {"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
 339   {"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
 340   {"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
 341   {"sra",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
 342   {"src",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
 343   {"srl",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
 344   {"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
 345   {"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
 346   {"wic",   INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
 347   {"wdc",   INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
 348   {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
 349   {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
 350   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
 351   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
 352   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
 353   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
 354   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
 355   {"bra",   INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
 356   {"brad",  INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
 357   {"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
 358   {"brk",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
 359   {"beq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
 360   {"beqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
 361   {"bne",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
 362   {"bned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
 363   {"blt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
 364   {"bltd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
 365   {"ble",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
 366   {"bled",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
 367   {"bgt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
 368   {"bgtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
 369   {"bge",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
 370   {"bged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
 371   {"ori",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
 372   {"andi",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
 373   {"xori",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
 374   {"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
 375   {"imm",   INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
 376   {"rtsd",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
 377   {"rtid",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
 378   {"rtbd",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
 379   {"rted",  INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
 380   {"bri",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
 381   {"brid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
 382   {"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
 383   {"brai",  INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
 384   {"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
 385   {"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
 386   {"brki",  INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
 387   {"beqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
 388   {"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
 389   {"bnei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
 390   {"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
 391   {"blti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
 392   {"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
 393   {"blei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
 394   {"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
 395   {"bgti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
 396   {"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
 397   {"bgei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
 398   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
 399   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
 400   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
 401   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
 402   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
 403   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
 404   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
 405   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
 406   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
 407   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
 408   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
 409   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
 410   {"sbi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
 411   {"shi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
 412   {"swi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
 413   {"nop",   INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0 */
 414   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik */
 415   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42 */
 416   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1 */
 417   {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0 */
 418   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4 */
 419   {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */
 420   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
 421   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
 422   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
 423   {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
 424   {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
 425   {"frsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
 426   {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
 427   {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
 428   {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
 429   {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
 430   {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
 431   {"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
 432   {"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
 433   {"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
 434   {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
 435   {"flt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt,   arithmetic_inst },
 436   {"fint",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint,  arithmetic_inst },
 437   {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
 438   {"tget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget,   anyware_inst },
 439   {"tcget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget,  anyware_inst },
 440   {"tnget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget,  anyware_inst },
 441   {"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
 442   {"tput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput,   anyware_inst },
 443   {"tcput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput,  anyware_inst },
 444   {"tnput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput,  anyware_inst },
 445   {"tncput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
 446
 447   {"eget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget,   anyware_inst },
 448   {"ecget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget,  anyware_inst },
 449   {"neget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget,  anyware_inst },
 450   {"necget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
 451   {"eput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput,   anyware_inst },
 452   {"ecput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput,  anyware_inst },
 453   {"neput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput,  anyware_inst },
 454   {"necput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
 455
 456   {"teget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget,   anyware_inst },
 457   {"tecget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget,  anyware_inst },
 458   {"tneget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget,  anyware_inst },
 459   {"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
 460   {"teput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput,   anyware_inst },
 461   {"tecput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput,  anyware_inst },
 462   {"tneput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput,  anyware_inst },
 463   {"tnecput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
 464
 465   {"aget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget,   anyware_inst },
 466   {"caget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget,  anyware_inst },
 467   {"naget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget,  anyware_inst },
 468   {"ncaget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
 469   {"aput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput,   anyware_inst },
 470   {"caput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput,  anyware_inst },
 471   {"naput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput,  anyware_inst },
 472   {"ncaput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
 473
 474   {"taget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget,   anyware_inst },
 475   {"tcaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget,  anyware_inst },
 476   {"tnaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget,  anyware_inst },
 477   {"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
 478   {"taput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput,   anyware_inst },
 479   {"tcaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput,  anyware_inst },
 480   {"tnaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput,  anyware_inst },
 481   {"tncaput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
 482
 483   {"eaget",   INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget,   anyware_inst },
 484   {"ecaget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget,  anyware_inst },
 485   {"neaget",  INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget,  anyware_inst },
 486   {"necaget", INST_TYPE_RD_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
 487   {"eaput",   INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput,   anyware_inst },
 488   {"ecaput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput,  anyware_inst },
 489   {"neaput",  INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput,  anyware_inst },
 490   {"necaput", INST_TYPE_R1_RFSL,  INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
 491
 492   {"teaget",   INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget,   anyware_inst },
 493   {"tecaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget,  anyware_inst },
 494   {"tneaget",  INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget,  anyware_inst },
 495   {"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
 496   {"teaput",   INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput,   anyware_inst },
 497   {"tecaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput,  anyware_inst },
 498   {"tneaput",  INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput,  anyware_inst },
 499   {"tnecaput", INST_TYPE_RFSL,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
 500
 501   {"getd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd,    anyware_inst },
 502   {"tgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd,   anyware_inst },
 503   {"cgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd,   anyware_inst },
 504   {"tcgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd,  anyware_inst },
 505   {"ngetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd,   anyware_inst },
 506   {"tngetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd,  anyware_inst },
 507   {"ncgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd,  anyware_inst },
 508   {"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
 509   {"putd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd,    anyware_inst },
 510   {"tputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd,   anyware_inst },
 511   {"cputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd,   anyware_inst },
 512   {"tcputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd,  anyware_inst },
 513   {"nputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd,   anyware_inst },
 514   {"tnputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd,  anyware_inst },
 515   {"ncputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd,  anyware_inst },
 516   {"tncputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
 517
 518   {"egetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd,    anyware_inst },
 519   {"tegetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd,   anyware_inst },
 520   {"ecgetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd,   anyware_inst },
 521   {"tecgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd,  anyware_inst },
 522   {"negetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd,   anyware_inst },
 523   {"tnegetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd,  anyware_inst },
 524   {"necgetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd,  anyware_inst },
 525   {"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
 526   {"eputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd,    anyware_inst },
 527   {"teputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd,   anyware_inst },
 528   {"ecputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd,   anyware_inst },
 529   {"tecputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd,  anyware_inst },
 530   {"neputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd,   anyware_inst },
 531   {"tneputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd,  anyware_inst },
 532   {"necputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd,  anyware_inst },
 533   {"tnecputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
 534
 535   {"agetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd,    anyware_inst },
 536   {"tagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd,   anyware_inst },
 537   {"cagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd,   anyware_inst },
 538   {"tcagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd,  anyware_inst },
 539   {"nagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd,   anyware_inst },
 540   {"tnagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd,  anyware_inst },
 541   {"ncagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd,  anyware_inst },
 542   {"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
 543   {"aputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd,    anyware_inst },
 544   {"taputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd,   anyware_inst },
 545   {"caputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd,   anyware_inst },
 546   {"tcaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd,  anyware_inst },
 547   {"naputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd,   anyware_inst },
 548   {"tnaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd,  anyware_inst },
 549   {"ncaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd,  anyware_inst },
 550   {"tncaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
 551
 552   {"eagetd",    INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd,    anyware_inst },
 553   {"teagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd,   anyware_inst },
 554   {"ecagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd,   anyware_inst },
 555   {"tecagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd,  anyware_inst },
 556   {"neagetd",   INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd,   anyware_inst },
 557   {"tneagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd,  anyware_inst },
 558   {"necagetd",  INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd,  anyware_inst },
 559   {"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
 560   {"eaputd",    INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd,    anyware_inst },
 561   {"teaputd",   INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd,   anyware_inst },
 562   {"ecaputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd,   anyware_inst },
 563   {"tecaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd,  anyware_inst },
 564   {"neaputd",   INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd,   anyware_inst },
 565   {"tneaputd",  INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd,  anyware_inst },
 566   {"necaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd,  anyware_inst },
 567   {"tnecaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
 568   {"", 0, 0, 0, 0, 0, 0, 0, 0},
 569 };
 570
 571 /* prefix for register names */
 572 char register_prefix[] = "r";
 573 char special_register_prefix[] = "spr";
 574 char fsl_register_prefix[] = "rfsl";
 575 char pvr_register_prefix[] = "rpvr";
 576
 577
 578 /* #defines for valid immediate range */
 579 #define MIN_IMM  ((int) 0x80000000)
 580 #define MAX_IMM  ((int) 0x7fffffff)
 581
 582 #define MIN_IMM15 ((int) 0x0000)
 583 #define MAX_IMM15 ((int) 0x7fff)
 584
 585 #endif /* MICROBLAZE_OPC */
 586
 587 #include "dis-asm.h"
 588 #include <strings.h>
 589
 590 #define get_field_rd(instr) get_field(instr, RD_MASK, RD_LOW)
 591 #define get_field_r1(instr) get_field(instr, RA_MASK, RA_LOW)
 592 #define get_field_r2(instr) get_field(instr, RB_MASK, RB_LOW)
 593 #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
 594 #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
 595
 596 /* Local function prototypes. */
 597
 598 static char * get_field (long instr, long mask, unsigned short low);
 599 static char * get_field_imm (long instr);
 600 static char * get_field_imm5 (long instr);
 601 static char * get_field_rfsl (long instr);
 602 static char * get_field_imm15 (long instr);
 603 #if 0
 604 static char * get_field_unsigned_imm (long instr);
 605 #endif
 606 char * get_field_special (long instr, struct op_code_struct * op);
 607 unsigned long read_insn_microblaze (bfd_vma memaddr,
 608                       struct disassemble_info *info,
 609                       struct op_code_struct **opr);
 610 enum microblaze_instr get_insn_microblaze (long inst,
 611                      bfd_boolean *isunsignedimm,
 612                      enum microblaze_instr_type *insn_type,
 613                      short *delay_slots);
 614 short get_delay_slots_microblaze (long inst);
 615 enum microblaze_instr microblaze_decode_insn (long insn,
 616                         int *rd,
 617                         int *ra,
 618                         int *rb,
 619                         int *imm);
 620 unsigned long
 621 microblaze_get_target_address (long inst,
 622                                bfd_boolean immfound,
 623                                int immval,
 624                                long pcval,
 625                                long r1val,
 626                                long r2val,
 627                                bfd_boolean *targetvalid,
 628                                bfd_boolean *unconditionalbranch);
 629
 630 static char *
 631 get_field (long instr, long mask, unsigned short low)
 632 {
 633   char tmpstr[25];
 634   sprintf(tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
 635   return(strdup(tmpstr));
 636 }
 637
 638 static char *
 639 get_field_imm (long instr)
 640 {
 641   char tmpstr[25];
 642   sprintf(tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
 643   return(strdup(tmpstr));
 644 }
 645
 646 static char *
 647 get_field_imm5 (long instr)
 648 {
 649   char tmpstr[25];
 650   sprintf(tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
 651   return(strdup(tmpstr));
 652 }
 653
 654 static char *
 655 get_field_rfsl (long instr)
 656 {
 657   char tmpstr[25];
 658   sprintf(tmpstr, "%s%d", fsl_register_prefix, (short)((instr & RFSL_MASK) >> IMM_LOW));
 659   return(strdup(tmpstr));
 660 }
 661
 662 static char *
 663 get_field_imm15 (long instr)
 664 {
 665   char tmpstr[25];
 666   sprintf(tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
 667   return(strdup(tmpstr));
 668 }
 669
 670 #if 0
 671 static char *
 672 get_field_unsigned_imm (long instr)
 673 {
 674   char tmpstr[25];
 675   sprintf(tmpstr, "%d", (int)((instr & IMM_MASK) >> IMM_LOW));
 676   return(strdup(tmpstr));
 677 }
 678 #endif
 679
 680 /*
 681   char *
 682   get_field_special (instr)
 683   long instr;
 684   {
 685   char tmpstr[25];
 686
 687   sprintf(tmpstr, "%s%s", register_prefix, (((instr & IMM_MASK) >> IMM_LOW) & REG_MSR_MASK) == 0 ? "pc" : "msr");
 688
 689   return(strdup(tmpstr));
 690   }
 691 */
 692
 693 char *
 694 get_field_special (long instr, struct op_code_struct * op)
 695 {
 696    char tmpstr[25];
 697    char spr[6];
 698
 699    switch ( (((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ) {
 700
 701    case REG_MSR_MASK :
 702       strcpy(spr, "msr");
 703       break;
 704    case REG_PC_MASK :
 705       strcpy(spr, "pc");
 706       break;
 707    case REG_EAR_MASK :
 708       strcpy(spr, "ear");
 709       break;
 710    case REG_ESR_MASK :
 711       strcpy(spr, "esr");
 712       break;
 713    case REG_FSR_MASK :
 714       strcpy(spr, "fsr");
 715       break;
 716    case REG_BTR_MASK :
 717       strcpy(spr, "btr");
 718       break;
 719    case REG_EDR_MASK :
 720       strcpy(spr, "edr");
 721       break;
 722    case REG_PID_MASK :
 723       strcpy(spr, "pid");
 724       break;
 725    case REG_ZPR_MASK :
 726       strcpy(spr, "zpr");
 727       break;
 728    case REG_TLBX_MASK :
 729       strcpy(spr, "tlbx");
 730       break;
 731    case REG_TLBLO_MASK :
 732       strcpy(spr, "tlblo");
 733       break;
 734    case REG_TLBHI_MASK :
 735       strcpy(spr, "tlbhi");
 736       break;
 737    case REG_TLBSX_MASK :
 738       strcpy(spr, "tlbsx");
 739       break;
 740    default :
 741      {
 742        if ( ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) {
 743          sprintf(tmpstr, "%spvr%d", register_prefix, (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ^ REG_PVR_MASK);
 744          return(strdup(tmpstr));
 745        } else {
 746          strcpy(spr, "pc");
 747        }
 748      }
 749      break;
 750    }
 751
 752    sprintf(tmpstr, "%s%s", register_prefix, spr);
 753    return(strdup(tmpstr));
 754 }
 755
 756 unsigned long
 757 read_insn_microblaze (bfd_vma memaddr,
 758                       struct disassemble_info *info,
 759                       struct op_code_struct **opr)
 760 {
 761   unsigned char       ibytes[4];
 762   int                 status;
 763   struct op_code_struct * op;
 764   unsigned long inst;
 765
 766   status = info->read_memory_func (memaddr, ibytes, 4, info);
 767
 768   if (status != 0)
 769     {
 770       info->memory_error_func (status, memaddr, info);
 771       return 0;
 772     }
 773
 774   if (info->endian == BFD_ENDIAN_BIG)
 775     inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3];
 776   else if (info->endian == BFD_ENDIAN_LITTLE)
 777     inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0];
 778   else
 779     abort ();
 780
 781   /* Just a linear search of the table.  */
 782   for (op = opcodes; op->name != 0; op ++)
 783     if (op->bit_sequence == (inst & op->opcode_mask))
 784       break;
 785
 786   *opr = op;
 787   return inst;
 788 }
 789
 790
 791 int
 792 print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
 793 {
 794   fprintf_ftype       fprintf = info->fprintf_func;
 795   void *              stream = info->stream;
 796   unsigned long       inst, prev_inst;
 797   struct op_code_struct * op, *pop;
 798   int                 immval = 0;
 799   bfd_boolean         immfound = FALSE;
 800   static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */
 801   static int     prev_insn_vma = -1;  /*init the prev insn vma */
 802   int            curr_insn_vma = info->buffer_vma;
 803
 804   info->bytes_per_chunk = 4;
 805
 806   inst = read_insn_microblaze (memaddr, info, &op);
 807   if (inst == 0) {
 808     return -1;
 809   }
 810
 811   if (prev_insn_vma == curr_insn_vma) {
 812   if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) {
 813     prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
 814     if (prev_inst == 0)
 815       return -1;
 816     if (pop->instr == imm) {
 817       immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000;
 818       immfound = TRUE;
 819     }
 820     else {
 821       immval = 0;
 822       immfound = FALSE;
 823     }
 824   }
 825   }
 826   /* make curr insn as prev insn */
 827   prev_insn_addr = memaddr;
 828   prev_insn_vma = curr_insn_vma;
 829
 830   if (op->name == 0) {
 831     fprintf (stream, ".short 0x%04x", inst);
 832   }
 833   else
 834     {
 835       fprintf (stream, "%s", op->name);
 836
 837       switch (op->inst_type)
 838         {
 839   case INST_TYPE_RD_R1_R2:
 840      fprintf(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_r2(inst));
 841      break;
 842         case INST_TYPE_RD_R1_IMM:
 843           fprintf(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm(inst));
 844           if (info->print_address_func && get_int_field_r1(inst) == 0 && info->symbol_at_address_func) {
 845             if (immfound)
 846               immval |= (get_int_field_imm(inst) & 0x0000ffff);
 847             else {
 848               immval = get_int_field_imm(inst);
 849               if (immval & 0x8000)
 850                 immval |= 0xFFFF0000;
 851             }
 852             if (immval > 0 && info->symbol_at_address_func(immval, info)) {
 853               fprintf (stream, "\t// ");
 854               info->print_address_func (immval, info);
 855             }
 856           }
 857           break;
 858         case INST_TYPE_RD_R1_IMM5:
 859           fprintf(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm5(inst));
 860           break;
 861         case INST_TYPE_RD_RFSL:
 862           fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_rfsl(inst));
 863           break;
 864         case INST_TYPE_R1_RFSL:
 865           fprintf(stream, "\t%s, %s", get_field_r1(inst), get_field_rfsl(inst));
 866           break;
 867         case INST_TYPE_RD_SPECIAL:
 868           fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_special(inst, op));
 869           break;
 870         case INST_TYPE_SPECIAL_R1:
 871           fprintf(stream, "\t%s, %s", get_field_special(inst, op), get_field_r1(inst));
 872           break;
 873         case INST_TYPE_RD_R1:
 874           fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_r1(inst));
 875           break;
 876         case INST_TYPE_R1_R2:
 877           fprintf(stream, "\t%s, %s", get_field_r1(inst), get_field_r2(inst));
 878           break;
 879         case INST_TYPE_R1_IMM:
 880           fprintf(stream, "\t%s, %s", get_field_r1(inst), get_field_imm(inst));
 881           /* The non-pc relative instructions are returns, which shouldn't
 882              have a label printed */
 883           if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET && info->symbol_at_address_func) {
 884             if (immfound)
 885               immval |= (get_int_field_imm(inst) & 0x0000ffff);
 886             else {
 887               immval = get_int_field_imm(inst);
 888               if (immval & 0x8000)
 889                 immval |= 0xFFFF0000;
 890             }
 891             immval += memaddr;
 892             if (immval > 0 && info->symbol_at_address_func(immval, info)) {
 893               fprintf (stream, "\t// ");
 894               info->print_address_func (immval, info);
 895             } else {
 896               fprintf (stream, "\t\t// ");
 897               fprintf (stream, "%x", immval);
 898             }
 899           }
 900           break;
 901         case INST_TYPE_RD_IMM:
 902           fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_imm(inst));
 903           if (info->print_address_func && info->symbol_at_address_func) {
 904             if (immfound)
 905               immval |= (get_int_field_imm(inst) & 0x0000ffff);
 906             else {
 907               immval = get_int_field_imm(inst);
 908               if (immval & 0x8000)
 909                 immval |= 0xFFFF0000;
 910             }
 911             if (op->inst_offset_type == INST_PC_OFFSET)
 912               immval += (int) memaddr;
 913             if (info->symbol_at_address_func(immval, info)) {
 914               fprintf (stream, "\t// ");
 915               info->print_address_func (immval, info);
 916             }
 917           }
 918           break;
 919         case INST_TYPE_IMM:
 920           fprintf(stream, "\t%s", get_field_imm(inst));
 921           if (info->print_address_func && info->symbol_at_address_func && op->instr != imm) {
 922             if (immfound)
 923               immval |= (get_int_field_imm(inst) & 0x0000ffff);
 924             else {
 925               immval = get_int_field_imm(inst);
 926               if (immval & 0x8000)
 927                 immval |= 0xFFFF0000;
 928             }
 929             if (op->inst_offset_type == INST_PC_OFFSET)
 930               immval += (int) memaddr;
 931             if (immval > 0 && info->symbol_at_address_func(immval, info)) {
 932               fprintf (stream, "\t// ");
 933               info->print_address_func (immval, info);
 934             } else if (op->inst_offset_type == INST_PC_OFFSET) {
 935               fprintf (stream, "\t\t// ");
 936               fprintf (stream, "%x", immval);
 937             }
 938           }
 939           break;
 940         case INST_TYPE_RD_R2:
 941           fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
 942           break;
 943   case INST_TYPE_R2:
 944      fprintf(stream, "\t%s", get_field_r2(inst));
 945      break;
 946   case INST_TYPE_R1:
 947      fprintf(stream, "\t%s", get_field_r1(inst));
 948      break;
 949   case INST_TYPE_RD_R1_SPECIAL:
 950      fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
 951      break;
 952   case INST_TYPE_RD_IMM15:
 953      fprintf(stream, "\t%s, %s", get_field_rd(inst), get_field_imm15(inst));
 954      break;
 955      /* For tuqula instruction */
 956   case INST_TYPE_RD:
 957      fprintf(stream, "\t%s", get_field_rd(inst));
 958      break;
 959   case INST_TYPE_RFSL:
 960      fprintf(stream, "\t%s", get_field_rfsl(inst));
 961      break;
 962   default:
 963           /* if the disassembler lags the instruction set */
 964           fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
 965           break;
 966         }
 967     }
 968
 969   /* Say how many bytes we consumed? */
 970   return 4;
 971 }
 972
 973 enum microblaze_instr
 974 get_insn_microblaze (long inst,
 975                      bfd_boolean *isunsignedimm,
 976                      enum microblaze_instr_type *insn_type,
 977                      short *delay_slots)
 978 {
 979   struct op_code_struct * op;
 980   *isunsignedimm = FALSE;
 981
 982   /* Just a linear search of the table.  */
 983   for (op = opcodes; op->name != 0; op ++)
 984     if (op->bit_sequence == (inst & op->opcode_mask))
 985       break;
 986
 987   if (op->name == 0)
 988     return invalid_inst;
 989   else {
 990     *isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
 991     *insn_type = op->instr_type;
 992     *delay_slots = op->delay_slots;
 993     return op->instr;
 994   }
 995 }
 996
 997 short
 998 get_delay_slots_microblaze (long inst)
 999 {
1000   bfd_boolean isunsignedimm;
1001   enum microblaze_instr_type insn_type;
1002   enum microblaze_instr op;
1003   short delay_slots;
1004
1005   op = get_insn_microblaze( inst, &isunsignedimm, &insn_type, &delay_slots);
1006   if (op == invalid_inst)
1007     return 0;
1008   else
1009     return delay_slots;
1010 }
1011
1012 enum microblaze_instr
1013 microblaze_decode_insn (long insn,
1014                         int *rd,
1015                         int *ra,
1016                         int *rb,
1017                         int *imm)
1018 {
1019   enum microblaze_instr op;
1020   bfd_boolean t1;
1021   enum microblaze_instr_type t2;
1022   short t3;
1023
1024   op = get_insn_microblaze(insn, &t1, &t2, &t3);
1025   *rd = (insn & RD_MASK) >> RD_LOW;
1026   *ra = (insn & RA_MASK) >> RA_LOW;
1027   *rb = (insn & RB_MASK) >> RB_LOW;
1028   t3 = (insn & IMM_MASK) >> IMM_LOW;
1029   *imm = (int) t3;
1030   return (op);
1031 }
1032
1033 unsigned long
1034 microblaze_get_target_address (long inst,
1035                                bfd_boolean immfound,
1036                                int immval,
1037                                long pcval,
1038                                long r1val,
1039                                long r2val,
1040                                bfd_boolean *targetvalid,
1041                                bfd_boolean *unconditionalbranch)
1042 {
1043   struct op_code_struct * op;
1044   long targetaddr = 0;
1045
1046   *unconditionalbranch = FALSE;
1047   /* Just a linear search of the table.  */
1048   for (op = opcodes; op->name != 0; op ++)
1049     if (op->bit_sequence == (inst & op->opcode_mask))
1050       break;
1051
1052   if (op->name == 0) {
1053     *targetvalid = FALSE;
1054   } else if (op->instr_type == branch_inst) {
1055     switch (op->inst_type) {
1056     case INST_TYPE_R2:
1057       *unconditionalbranch = TRUE;
1058       /* fallthru */
1059     case INST_TYPE_RD_R2:
1060     case INST_TYPE_R1_R2:
1061       targetaddr = r2val;
1062       *targetvalid = TRUE;
1063       if (op->inst_offset_type == INST_PC_OFFSET)
1064         targetaddr += pcval;
1065       break;
1066     case INST_TYPE_IMM:
1067       *unconditionalbranch = TRUE;
1068       /* fallthru */
1069     case INST_TYPE_RD_IMM:
1070     case INST_TYPE_R1_IMM:
1071       if (immfound) {
1072         targetaddr = (immval << 16) & 0xffff0000;
1073         targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
1074       } else {
1075         targetaddr = get_int_field_imm(inst);
1076         if (targetaddr & 0x8000)
1077           targetaddr |= 0xFFFF0000;
1078       }
1079       if (op->inst_offset_type == INST_PC_OFFSET)
1080         targetaddr += pcval;
1081       *targetvalid = TRUE;
1082       break;
1083     default:
1084       *targetvalid = FALSE;
1085       break;
1086     }
1087   } else if (op->instr_type == return_inst) {
1088       if (immfound) {
1089         targetaddr = (immval << 16) & 0xffff0000;
1090         targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
1091       } else {
1092         targetaddr = get_int_field_imm(inst);
1093         if (targetaddr & 0x8000)
1094           targetaddr |= 0xFFFF0000;
1095       }
1096       targetaddr += r1val;
1097       *targetvalid = TRUE;
1098   } else {
1099     *targetvalid = FALSE;
1100   }
1101   return targetaddr;
1102 }