hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "monitor/monitor.h"
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/i386/ioapic.h"
  29 #include "hw/i386/ioapic_internal.h"
  30 #include "include/hw/pci/msi.h"
  31 #include "sysemu/kvm.h"
  32 #include "target-i386/cpu.h"
  33 #include "hw/i386/apic-msidef.h"
  34
  35 //#define DEBUG_IOAPIC
  36
  37 #ifdef DEBUG_IOAPIC
  38 #define DPRINTF(fmt, ...)                                       \
  39     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...)
  42 #endif
  43
  44 #define APIC_DELIVERY_MODE_SHIFT 8
  45 #define APIC_POLARITY_SHIFT 14
  46 #define APIC_TRIG_MODE_SHIFT 15
  47
  48 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  49
  50 /* global variable from ioapic_common.c */
  51 extern int ioapic_no;
  52
  53 static void ioapic_service(IOAPICCommonState *s)
  54 {
  55     AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
  56     uint32_t addr, data;
  57     uint8_t i;
  58     uint8_t trig_mode;
  59     uint8_t vector;
  60     uint8_t delivery_mode;
  61     uint32_t mask;
  62     uint64_t entry;
  63     uint16_t dest_idx;
  64     uint8_t dest_mode;
  65
  66     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  67         mask = 1 << i;
  68         if (s->irr & mask) {
  69             int coalesce = 0;
  70
  71             entry = s->ioredtbl[i];
  72             if (!(entry & IOAPIC_LVT_MASKED)) {
  73                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
  74                 /*
  75                  * By default, this would be dest_id[8] +
  76                  * reserved[8]. When IR is enabled, this would be
  77                  * interrupt_index[15] + interrupt_format[1]. This
  78                  * field never means anything, but only used to
  79                  * generate corresponding MSI.
  80                  */
  81                 dest_idx = entry >> IOAPIC_LVT_DEST_IDX_SHIFT;
  82                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  83                 delivery_mode =
  84                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
  85                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  86                     s->irr &= ~mask;
  87                 } else {
  88                     coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
  89                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
  90                 }
  91                 if (delivery_mode == IOAPIC_DM_EXTINT) {
  92                     vector = pic_read_irq(isa_pic);
  93                 } else {
  94                     vector = entry & IOAPIC_VECTOR_MASK;
  95                 }
  96 #ifdef CONFIG_KVM
  97                 if (kvm_irqchip_is_split()) {
  98                     if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  99                         kvm_set_irq(kvm_state, i, 1);
 100                         kvm_set_irq(kvm_state, i, 0);
 101                     } else {
 102                         if (!coalesce) {
 103                             kvm_set_irq(kvm_state, i, 1);
 104                         }
 105                     }
 106                     continue;
 107                 }
 108 #else
 109                 (void)coalesce;
 110 #endif
 111                 /* No matter whether IR is enabled, we translate
 112                  * the IOAPIC message into a MSI one, and its
 113                  * address space will decide whether we need a
 114                  * translation. */
 115                 addr = APIC_DEFAULT_ADDRESS | \
 116                     (dest_idx << MSI_ADDR_DEST_IDX_SHIFT) |
 117                     (dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
 118                 data = (vector << MSI_DATA_VECTOR_SHIFT) |
 119                     (trig_mode << MSI_DATA_TRIGGER_SHIFT) |
 120                     (delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
 121                 stl_le_phys(ioapic_as, addr, data);
 122             }
 123         }
 124     }
 125 }
 126
 127 static void ioapic_set_irq(void *opaque, int vector, int level)
 128 {
 129     IOAPICCommonState *s = opaque;
 130
 131     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 132      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 133      * the cleanest way of doing it but it should work. */
 134
 135     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 136     if (vector == 0) {
 137         vector = 2;
 138     }
 139     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 140         uint32_t mask = 1 << vector;
 141         uint64_t entry = s->ioredtbl[vector];
 142
 143         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 144             IOAPIC_TRIGGER_LEVEL) {
 145             /* level triggered */
 146             if (level) {
 147                 s->irr |= mask;
 148                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 149                     ioapic_service(s);
 150                 }
 151             } else {
 152                 s->irr &= ~mask;
 153             }
 154         } else {
 155             /* According to the 82093AA manual, we must ignore edge requests
 156              * if the input pin is masked. */
 157             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 158                 s->irr |= mask;
 159                 ioapic_service(s);
 160             }
 161         }
 162     }
 163 }
 164
 165 static void ioapic_update_kvm_routes(IOAPICCommonState *s)
 166 {
 167 #ifdef CONFIG_KVM
 168     int i;
 169
 170     if (kvm_irqchip_is_split()) {
 171         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 172             uint64_t entry = s->ioredtbl[i];
 173             uint8_t trig_mode;
 174             uint8_t delivery_mode;
 175             uint8_t dest;
 176             uint8_t dest_mode;
 177             uint64_t pin_polarity;
 178             MSIMessage msg;
 179
 180             trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
 181             dest = entry >> IOAPIC_LVT_DEST_SHIFT;
 182             dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
 183             pin_polarity = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
 184             delivery_mode =
 185                 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
 186
 187             msg.address = APIC_DEFAULT_ADDRESS;
 188             msg.address |= dest_mode << 2;
 189             msg.address |= dest << 12;
 190
 191             msg.data = entry & IOAPIC_VECTOR_MASK;
 192             msg.data |= delivery_mode << APIC_DELIVERY_MODE_SHIFT;
 193             msg.data |= pin_polarity << APIC_POLARITY_SHIFT;
 194             msg.data |= trig_mode << APIC_TRIG_MODE_SHIFT;
 195
 196             kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
 197         }
 198         kvm_irqchip_commit_routes(kvm_state);
 199     }
 200 #endif
 201 }
 202
 203 void ioapic_eoi_broadcast(int vector)
 204 {
 205     IOAPICCommonState *s;
 206     uint64_t entry;
 207     int i, n;
 208
 209     for (i = 0; i < MAX_IOAPICS; i++) {
 210         s = ioapics[i];
 211         if (!s) {
 212             continue;
 213         }
 214         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 215             entry = s->ioredtbl[n];
 216             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 217                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 218                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 219                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 220                     ioapic_service(s);
 221                 }
 222             }
 223         }
 224     }
 225 }
 226
 227 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 228 {
 229     int i;
 230
 231     for (i = 0; i < MAX_IOAPICS; i++) {
 232         if (ioapics[i] != 0) {
 233             ioapic_print_redtbl(mon, ioapics[i]);
 234         }
 235     }
 236 }
 237
 238 static uint64_t
 239 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 240 {
 241     IOAPICCommonState *s = opaque;
 242     int index;
 243     uint32_t val = 0;
 244
 245     switch (addr & 0xff) {
 246     case IOAPIC_IOREGSEL:
 247         val = s->ioregsel;
 248         break;
 249     case IOAPIC_IOWIN:
 250         if (size != 4) {
 251             break;
 252         }
 253         switch (s->ioregsel) {
 254         case IOAPIC_REG_ID:
 255         case IOAPIC_REG_ARB:
 256             val = s->id << IOAPIC_ID_SHIFT;
 257             break;
 258         case IOAPIC_REG_VER:
 259             val = IOAPIC_VERSION |
 260                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 261             break;
 262         default:
 263             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 264             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 265                 if (s->ioregsel & 1) {
 266                     val = s->ioredtbl[index] >> 32;
 267                 } else {
 268                     val = s->ioredtbl[index] & 0xffffffff;
 269                 }
 270             }
 271         }
 272         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 273         break;
 274     }
 275     return val;
 276 }
 277
 278 /*
 279  * This is to satisfy the hack in Linux kernel. One hack of it is to
 280  * simulate clearing the Remote IRR bit of IOAPIC entry using the
 281  * following:
 282  *
 283  * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
 284  * Otherwise, we simulate the EOI message manually by changing the trigger
 285  * mode to edge and then back to level, with RTE being masked during
 286  * this."
 287  *
 288  * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
 289  *
 290  * This is based on the assumption that, Remote IRR bit will be
 291  * cleared by IOAPIC hardware when configured as edge-triggered
 292  * interrupts.
 293  *
 294  * Without this, level-triggered interrupts in IR mode might fail to
 295  * work correctly.
 296  */
 297 static inline void
 298 ioapic_fix_edge_remote_irr(uint64_t *entry)
 299 {
 300     if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
 301         /* Edge-triggered interrupts, make sure remote IRR is zero */
 302         *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
 303     }
 304 }
 305
 306 static void
 307 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 308                  unsigned int size)
 309 {
 310     IOAPICCommonState *s = opaque;
 311     int index;
 312
 313     switch (addr & 0xff) {
 314     case IOAPIC_IOREGSEL:
 315         s->ioregsel = val;
 316         break;
 317     case IOAPIC_IOWIN:
 318         if (size != 4) {
 319             break;
 320         }
 321         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 322         switch (s->ioregsel) {
 323         case IOAPIC_REG_ID:
 324             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 325             break;
 326         case IOAPIC_REG_VER:
 327         case IOAPIC_REG_ARB:
 328             break;
 329         default:
 330             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 331             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 332                 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
 333                 if (s->ioregsel & 1) {
 334                     s->ioredtbl[index] &= 0xffffffff;
 335                     s->ioredtbl[index] |= (uint64_t)val << 32;
 336                 } else {
 337                     s->ioredtbl[index] &= ~0xffffffffULL;
 338                     s->ioredtbl[index] |= val;
 339                 }
 340                 /* restore RO bits */
 341                 s->ioredtbl[index] &= IOAPIC_RW_BITS;
 342                 s->ioredtbl[index] |= ro_bits;
 343                 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
 344                 ioapic_service(s);
 345             }
 346         }
 347         break;
 348     }
 349
 350     ioapic_update_kvm_routes(s);
 351 }
 352
 353 static const MemoryRegionOps ioapic_io_ops = {
 354     .read = ioapic_mem_read,
 355     .write = ioapic_mem_write,
 356     .endianness = DEVICE_NATIVE_ENDIAN,
 357 };
 358
 359 static void ioapic_realize(DeviceState *dev, Error **errp)
 360 {
 361     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 362
 363     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 364                           "ioapic", 0x1000);
 365
 366     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 367
 368     ioapics[ioapic_no] = s;
 369 }
 370
 371 static void ioapic_class_init(ObjectClass *klass, void *data)
 372 {
 373     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 374     DeviceClass *dc = DEVICE_CLASS(klass);
 375
 376     k->realize = ioapic_realize;
 377     dc->reset = ioapic_reset_common;
 378 }
 379
 380 static const TypeInfo ioapic_info = {
 381     .name          = "ioapic",
 382     .parent        = TYPE_IOAPIC_COMMON,
 383     .instance_size = sizeof(IOAPICCommonState),
 384     .class_init    = ioapic_class_init,
 385 };
 386
 387 static void ioapic_register_types(void)
 388 {
 389     type_register_static(&ioapic_info);
 390 }
 391
 392 type_init(ioapic_register_types)