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target/arm: Implement SVE Integer Compare - Scalars Group
[qemu.git] / target / ppc / translate.c
blob5fe1ba6555990270220a37330ea98fb74d02adb0
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "qemu/host-utils.h"
28 #include "exec/cpu_ldst.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/translator.h"
35 #include "exec/log.h"
36
37
38 #define CPU_SINGLE_STEP 0x1
39 #define CPU_BRANCH_STEP 0x2
40 #define GDBSTUB_SINGLE_STEP 0x4
41
42 /* Include definitions for instructions classes and implementations flags */
43 //#define PPC_DEBUG_DISAS
44 //#define DO_PPC_STATISTICS
45
46 #ifdef PPC_DEBUG_DISAS
47 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DISAS(...) do { } while (0)
50 #endif
51 /*****************************************************************************/
52 /* Code translation helpers */
53
54 /* global register indexes */
55 static char cpu_reg_names[10*3 + 22*4 /* GPR */
56 + 10*4 + 22*5 /* SPE GPRh */
57 + 10*4 + 22*5 /* FPR */
58 + 2*(10*6 + 22*7) /* AVRh, AVRl */
59 + 10*5 + 22*6 /* VSR */
60 + 8*5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i64 cpu_fpr[32];
64 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
65 static TCGv_i64 cpu_vsr[32];
66 static TCGv_i32 cpu_crf[8];
67 static TCGv cpu_nip;
68 static TCGv cpu_msr;
69 static TCGv cpu_ctr;
70 static TCGv cpu_lr;
71 #if defined(TARGET_PPC64)
72 static TCGv cpu_cfar;
73 #endif
74 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
75 static TCGv cpu_reserve;
76 static TCGv cpu_reserve_val;
77 static TCGv cpu_fpscr;
78 static TCGv_i32 cpu_access_type;
79
80 #include "exec/gen-icount.h"
81
82 void ppc_translate_init(void)
83 {
84 int i;
85 char* p;
86 size_t cpu_reg_names_size;
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 snprintf(p, cpu_reg_names_size, "r%dH", i);
106 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gprh[i]), p);
108 p += (i < 10) ? 4 : 5;
109 cpu_reg_names_size -= (i < 10) ? 4 : 5;
110
111 snprintf(p, cpu_reg_names_size, "fp%d", i);
112 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
113 offsetof(CPUPPCState, fpr[i]), p);
114 p += (i < 10) ? 4 : 5;
115 cpu_reg_names_size -= (i < 10) ? 4 : 5;
116
117 snprintf(p, cpu_reg_names_size, "avr%dH", i);
118 #ifdef HOST_WORDS_BIGENDIAN
119 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
120 offsetof(CPUPPCState, avr[i].u64[0]), p);
121 #else
122 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
123 offsetof(CPUPPCState, avr[i].u64[1]), p);
124 #endif
125 p += (i < 10) ? 6 : 7;
126 cpu_reg_names_size -= (i < 10) ? 6 : 7;
127
128 snprintf(p, cpu_reg_names_size, "avr%dL", i);
129 #ifdef HOST_WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
131 offsetof(CPUPPCState, avr[i].u64[1]), p);
132 #else
133 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
134 offsetof(CPUPPCState, avr[i].u64[0]), p);
135 #endif
136 p += (i < 10) ? 6 : 7;
137 cpu_reg_names_size -= (i < 10) ? 6 : 7;
138 snprintf(p, cpu_reg_names_size, "vsr%d", i);
139 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
140 offsetof(CPUPPCState, vsr[i]), p);
141 p += (i < 10) ? 5 : 6;
142 cpu_reg_names_size -= (i < 10) ? 5 : 6;
143 }
144
145 cpu_nip = tcg_global_mem_new(cpu_env,
146 offsetof(CPUPPCState, nip), "nip");
147
148 cpu_msr = tcg_global_mem_new(cpu_env,
149 offsetof(CPUPPCState, msr), "msr");
150
151 cpu_ctr = tcg_global_mem_new(cpu_env,
152 offsetof(CPUPPCState, ctr), "ctr");
153
154 cpu_lr = tcg_global_mem_new(cpu_env,
155 offsetof(CPUPPCState, lr), "lr");
156
157 #if defined(TARGET_PPC64)
158 cpu_cfar = tcg_global_mem_new(cpu_env,
159 offsetof(CPUPPCState, cfar), "cfar");
160 #endif
161
162 cpu_xer = tcg_global_mem_new(cpu_env,
163 offsetof(CPUPPCState, xer), "xer");
164 cpu_so = tcg_global_mem_new(cpu_env,
165 offsetof(CPUPPCState, so), "SO");
166 cpu_ov = tcg_global_mem_new(cpu_env,
167 offsetof(CPUPPCState, ov), "OV");
168 cpu_ca = tcg_global_mem_new(cpu_env,
169 offsetof(CPUPPCState, ca), "CA");
170 cpu_ov32 = tcg_global_mem_new(cpu_env,
171 offsetof(CPUPPCState, ov32), "OV32");
172 cpu_ca32 = tcg_global_mem_new(cpu_env,
173 offsetof(CPUPPCState, ca32), "CA32");
174
175 cpu_reserve = tcg_global_mem_new(cpu_env,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178 cpu_reserve_val = tcg_global_mem_new(cpu_env,
179 offsetof(CPUPPCState, reserve_val),
180 "reserve_val");
181
182 cpu_fpscr = tcg_global_mem_new(cpu_env,
183 offsetof(CPUPPCState, fpscr), "fpscr");
184
185 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
186 offsetof(CPUPPCState, access_type), "access_type");
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 DisasContextBase base;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 bool pr, hv, dr, le_mode;
196 bool lazy_tlb_flush;
197 bool need_access_type;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 bool gtse;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->base.pc_next - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->base.pc_next - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->base.pc_next);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->base.pc_next);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
380 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
381
382 typedef struct opcode_t {
383 unsigned char opc1, opc2, opc3, opc4;
384 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
385 unsigned char pad[4];
386 #endif
387 opc_handler_t handler;
388 const char *oname;
389 } opcode_t;
390
391 /* Helpers for priv. check */
392 #define GEN_PRIV \
393 do { \
394 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
395 } while (0)
396
397 #if defined(CONFIG_USER_ONLY)
398 #define CHK_HV GEN_PRIV
399 #define CHK_SV GEN_PRIV
400 #define CHK_HVRM GEN_PRIV
401 #else
402 #define CHK_HV \
403 do { \
404 if (unlikely(ctx->pr || !ctx->hv)) { \
405 GEN_PRIV; \
406 } \
407 } while (0)
408 #define CHK_SV \
409 do { \
410 if (unlikely(ctx->pr)) { \
411 GEN_PRIV; \
412 } \
413 } while (0)
414 #define CHK_HVRM \
415 do { \
416 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
417 GEN_PRIV; \
418 } \
419 } while (0)
420 #endif
421
422 #define CHK_NONE
423
424 /*****************************************************************************/
425 /* PowerPC instructions table */
426
427 #if defined(DO_PPC_STATISTICS)
428 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
429 { \
430 .opc1 = op1, \
431 .opc2 = op2, \
432 .opc3 = op3, \
433 .opc4 = 0xff, \
434 .handler = { \
435 .inval1 = invl, \
436 .type = _typ, \
437 .type2 = _typ2, \
438 .handler = &gen_##name, \
439 .oname = stringify(name), \
440 }, \
441 .oname = stringify(name), \
442 }
443 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
444 { \
445 .opc1 = op1, \
446 .opc2 = op2, \
447 .opc3 = op3, \
448 .opc4 = 0xff, \
449 .handler = { \
450 .inval1 = invl1, \
451 .inval2 = invl2, \
452 .type = _typ, \
453 .type2 = _typ2, \
454 .handler = &gen_##name, \
455 .oname = stringify(name), \
456 }, \
457 .oname = stringify(name), \
458 }
459 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
460 { \
461 .opc1 = op1, \
462 .opc2 = op2, \
463 .opc3 = op3, \
464 .opc4 = 0xff, \
465 .handler = { \
466 .inval1 = invl, \
467 .type = _typ, \
468 .type2 = _typ2, \
469 .handler = &gen_##name, \
470 .oname = onam, \
471 }, \
472 .oname = onam, \
473 }
474 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
475 { \
476 .opc1 = op1, \
477 .opc2 = op2, \
478 .opc3 = op3, \
479 .opc4 = op4, \
480 .handler = { \
481 .inval1 = invl, \
482 .type = _typ, \
483 .type2 = _typ2, \
484 .handler = &gen_##name, \
485 .oname = stringify(name), \
486 }, \
487 .oname = stringify(name), \
488 }
489 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
490 { \
491 .opc1 = op1, \
492 .opc2 = op2, \
493 .opc3 = op3, \
494 .opc4 = op4, \
495 .handler = { \
496 .inval1 = invl, \
497 .type = _typ, \
498 .type2 = _typ2, \
499 .handler = &gen_##name, \
500 .oname = onam, \
501 }, \
502 .oname = onam, \
503 }
504 #else
505 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
506 { \
507 .opc1 = op1, \
508 .opc2 = op2, \
509 .opc3 = op3, \
510 .opc4 = 0xff, \
511 .handler = { \
512 .inval1 = invl, \
513 .type = _typ, \
514 .type2 = _typ2, \
515 .handler = &gen_##name, \
516 }, \
517 .oname = stringify(name), \
518 }
519 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
520 { \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .opc4 = 0xff, \
525 .handler = { \
526 .inval1 = invl1, \
527 .inval2 = invl2, \
528 .type = _typ, \
529 .type2 = _typ2, \
530 .handler = &gen_##name, \
531 }, \
532 .oname = stringify(name), \
533 }
534 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
535 { \
536 .opc1 = op1, \
537 .opc2 = op2, \
538 .opc3 = op3, \
539 .opc4 = 0xff, \
540 .handler = { \
541 .inval1 = invl, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = onam, \
547 }
548 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
549 { \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .opc4 = op4, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = stringify(name), \
561 }
562 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
563 { \
564 .opc1 = op1, \
565 .opc2 = op2, \
566 .opc3 = op3, \
567 .opc4 = op4, \
568 .handler = { \
569 .inval1 = invl, \
570 .type = _typ, \
571 .type2 = _typ2, \
572 .handler = &gen_##name, \
573 }, \
574 .oname = onam, \
575 }
576 #endif
577
578 /* SPR load/store helpers */
579 static inline void gen_load_spr(TCGv t, int reg)
580 {
581 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
582 }
583
584 static inline void gen_store_spr(int reg, TCGv t)
585 {
586 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
587 }
588
589 /* Invalid instruction */
590 static void gen_invalid(DisasContext *ctx)
591 {
592 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
593 }
594
595 static opc_handler_t invalid_handler = {
596 .inval1 = 0xFFFFFFFF,
597 .inval2 = 0xFFFFFFFF,
598 .type = PPC_NONE,
599 .type2 = PPC_NONE,
600 .handler = gen_invalid,
601 };
602
603 /*** Integer comparison ***/
604
605 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
606 {
607 TCGv t0 = tcg_temp_new();
608 TCGv t1 = tcg_temp_new();
609 TCGv_i32 t = tcg_temp_new_i32();
610
611 tcg_gen_movi_tl(t0, CRF_EQ);
612 tcg_gen_movi_tl(t1, CRF_LT);
613 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1, t0);
614 tcg_gen_movi_tl(t1, CRF_GT);
615 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1, t0);
616
617 tcg_gen_trunc_tl_i32(t, t0);
618 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
619 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
620
621 tcg_temp_free(t0);
622 tcg_temp_free(t1);
623 tcg_temp_free_i32(t);
624 }
625
626 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
627 {
628 TCGv t0 = tcg_const_tl(arg1);
629 gen_op_cmp(arg0, t0, s, crf);
630 tcg_temp_free(t0);
631 }
632
633 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
634 {
635 TCGv t0, t1;
636 t0 = tcg_temp_new();
637 t1 = tcg_temp_new();
638 if (s) {
639 tcg_gen_ext32s_tl(t0, arg0);
640 tcg_gen_ext32s_tl(t1, arg1);
641 } else {
642 tcg_gen_ext32u_tl(t0, arg0);
643 tcg_gen_ext32u_tl(t1, arg1);
644 }
645 gen_op_cmp(t0, t1, s, crf);
646 tcg_temp_free(t1);
647 tcg_temp_free(t0);
648 }
649
650 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
651 {
652 TCGv t0 = tcg_const_tl(arg1);
653 gen_op_cmp32(arg0, t0, s, crf);
654 tcg_temp_free(t0);
655 }
656
657 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
658 {
659 if (NARROW_MODE(ctx)) {
660 gen_op_cmpi32(reg, 0, 1, 0);
661 } else {
662 gen_op_cmpi(reg, 0, 1, 0);
663 }
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
670 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
671 1, crfD(ctx->opcode));
672 } else {
673 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
674 1, crfD(ctx->opcode));
675 }
676 }
677
678 /* cmpi */
679 static void gen_cmpi(DisasContext *ctx)
680 {
681 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
682 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
683 1, crfD(ctx->opcode));
684 } else {
685 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
686 1, crfD(ctx->opcode));
687 }
688 }
689
690 /* cmpl */
691 static void gen_cmpl(DisasContext *ctx)
692 {
693 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
694 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
695 0, crfD(ctx->opcode));
696 } else {
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 }
700 }
701
702 /* cmpli */
703 static void gen_cmpli(DisasContext *ctx)
704 {
705 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
706 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 } else {
709 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
710 0, crfD(ctx->opcode));
711 }
712 }
713
714 /* cmprb - range comparison: isupper, isaplha, islower*/
715 static void gen_cmprb(DisasContext *ctx)
716 {
717 TCGv_i32 src1 = tcg_temp_new_i32();
718 TCGv_i32 src2 = tcg_temp_new_i32();
719 TCGv_i32 src2lo = tcg_temp_new_i32();
720 TCGv_i32 src2hi = tcg_temp_new_i32();
721 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
722
723 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
724 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
725
726 tcg_gen_andi_i32(src1, src1, 0xFF);
727 tcg_gen_ext8u_i32(src2lo, src2);
728 tcg_gen_shri_i32(src2, src2, 8);
729 tcg_gen_ext8u_i32(src2hi, src2);
730
731 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
732 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
733 tcg_gen_and_i32(crf, src2lo, src2hi);
734
735 if (ctx->opcode & 0x00200000) {
736 tcg_gen_shri_i32(src2, src2, 8);
737 tcg_gen_ext8u_i32(src2lo, src2);
738 tcg_gen_shri_i32(src2, src2, 8);
739 tcg_gen_ext8u_i32(src2hi, src2);
740 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
741 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
742 tcg_gen_and_i32(src2lo, src2lo, src2hi);
743 tcg_gen_or_i32(crf, crf, src2lo);
744 }
745 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
746 tcg_temp_free_i32(src1);
747 tcg_temp_free_i32(src2);
748 tcg_temp_free_i32(src2lo);
749 tcg_temp_free_i32(src2hi);
750 }
751
752 #if defined(TARGET_PPC64)
753 /* cmpeqb */
754 static void gen_cmpeqb(DisasContext *ctx)
755 {
756 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
757 cpu_gpr[rB(ctx->opcode)]);
758 }
759 #endif
760
761 /* isel (PowerPC 2.03 specification) */
762 static void gen_isel(DisasContext *ctx)
763 {
764 uint32_t bi = rC(ctx->opcode);
765 uint32_t mask = 0x08 >> (bi & 0x03);
766 TCGv t0 = tcg_temp_new();
767 TCGv zr;
768
769 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
770 tcg_gen_andi_tl(t0, t0, mask);
771
772 zr = tcg_const_tl(0);
773 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
774 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
775 cpu_gpr[rB(ctx->opcode)]);
776 tcg_temp_free(zr);
777 tcg_temp_free(t0);
778 }
779
780 /* cmpb: PowerPC 2.05 specification */
781 static void gen_cmpb(DisasContext *ctx)
782 {
783 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
784 cpu_gpr[rB(ctx->opcode)]);
785 }
786
787 /*** Integer arithmetic ***/
788
789 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
790 TCGv arg1, TCGv arg2, int sub)
791 {
792 TCGv t0 = tcg_temp_new();
793
794 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
795 tcg_gen_xor_tl(t0, arg1, arg2);
796 if (sub) {
797 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
798 } else {
799 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
800 }
801 tcg_temp_free(t0);
802 if (NARROW_MODE(ctx)) {
803 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
804 if (is_isa300(ctx)) {
805 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
806 }
807 } else {
808 if (is_isa300(ctx)) {
809 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
810 }
811 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
812 }
813 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
814 }
815
816 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
817 TCGv res, TCGv arg0, TCGv arg1,
818 int sub)
819 {
820 TCGv t0;
821
822 if (!is_isa300(ctx)) {
823 return;
824 }
825
826 t0 = tcg_temp_new();
827 if (sub) {
828 tcg_gen_eqv_tl(t0, arg0, arg1);
829 } else {
830 tcg_gen_xor_tl(t0, arg0, arg1);
831 }
832 tcg_gen_xor_tl(t0, t0, res);
833 tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
834 tcg_temp_free(t0);
835 }
836
837 /* Common add function */
838 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
839 TCGv arg2, bool add_ca, bool compute_ca,
840 bool compute_ov, bool compute_rc0)
841 {
842 TCGv t0 = ret;
843
844 if (compute_ca || compute_ov) {
845 t0 = tcg_temp_new();
846 }
847
848 if (compute_ca) {
849 if (NARROW_MODE(ctx)) {
850 /* Caution: a non-obvious corner case of the spec is that we
851 must produce the *entire* 64-bit addition, but produce the
852 carry into bit 32. */
853 TCGv t1 = tcg_temp_new();
854 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
855 tcg_gen_add_tl(t0, arg1, arg2);
856 if (add_ca) {
857 tcg_gen_add_tl(t0, t0, cpu_ca);
858 }
859 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
860 tcg_temp_free(t1);
861 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
862 if (is_isa300(ctx)) {
863 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
864 }
865 } else {
866 TCGv zero = tcg_const_tl(0);
867 if (add_ca) {
868 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
869 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
870 } else {
871 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
872 }
873 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 0);
874 tcg_temp_free(zero);
875 }
876 } else {
877 tcg_gen_add_tl(t0, arg1, arg2);
878 if (add_ca) {
879 tcg_gen_add_tl(t0, t0, cpu_ca);
880 }
881 }
882
883 if (compute_ov) {
884 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
885 }
886 if (unlikely(compute_rc0)) {
887 gen_set_Rc0(ctx, t0);
888 }
889
890 if (t0 != ret) {
891 tcg_gen_mov_tl(ret, t0);
892 tcg_temp_free(t0);
893 }
894 }
895 /* Add functions with two operands */
896 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
897 static void glue(gen_, name)(DisasContext *ctx) \
898 { \
899 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
900 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
901 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
902 }
903 /* Add functions with one operand and one immediate */
904 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
905 add_ca, compute_ca, compute_ov) \
906 static void glue(gen_, name)(DisasContext *ctx) \
907 { \
908 TCGv t0 = tcg_const_tl(const_val); \
909 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
910 cpu_gpr[rA(ctx->opcode)], t0, \
911 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
912 tcg_temp_free(t0); \
913 }
914
915 /* add add. addo addo. */
916 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
917 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
918 /* addc addc. addco addco. */
919 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
920 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
921 /* adde adde. addeo addeo. */
922 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
923 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
924 /* addme addme. addmeo addmeo. */
925 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
926 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
927 /* addze addze. addzeo addzeo.*/
928 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
930 /* addi */
931 static void gen_addi(DisasContext *ctx)
932 {
933 target_long simm = SIMM(ctx->opcode);
934
935 if (rA(ctx->opcode) == 0) {
936 /* li case */
937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
938 } else {
939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
940 cpu_gpr[rA(ctx->opcode)], simm);
941 }
942 }
943 /* addic addic.*/
944 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
945 {
946 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
947 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
948 c, 0, 1, 0, compute_rc0);
949 tcg_temp_free(c);
950 }
951
952 static void gen_addic(DisasContext *ctx)
953 {
954 gen_op_addic(ctx, 0);
955 }
956
957 static void gen_addic_(DisasContext *ctx)
958 {
959 gen_op_addic(ctx, 1);
960 }
961
962 /* addis */
963 static void gen_addis(DisasContext *ctx)
964 {
965 target_long simm = SIMM(ctx->opcode);
966
967 if (rA(ctx->opcode) == 0) {
968 /* lis case */
969 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
970 } else {
971 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
972 cpu_gpr[rA(ctx->opcode)], simm << 16);
973 }
974 }
975
976 /* addpcis */
977 static void gen_addpcis(DisasContext *ctx)
978 {
979 target_long d = DX(ctx->opcode);
980
981 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
982 }
983
984 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
985 TCGv arg2, int sign, int compute_ov)
986 {
987 TCGv_i32 t0 = tcg_temp_new_i32();
988 TCGv_i32 t1 = tcg_temp_new_i32();
989 TCGv_i32 t2 = tcg_temp_new_i32();
990 TCGv_i32 t3 = tcg_temp_new_i32();
991
992 tcg_gen_trunc_tl_i32(t0, arg1);
993 tcg_gen_trunc_tl_i32(t1, arg2);
994 if (sign) {
995 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
996 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
997 tcg_gen_and_i32(t2, t2, t3);
998 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
999 tcg_gen_or_i32(t2, t2, t3);
1000 tcg_gen_movi_i32(t3, 0);
1001 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1002 tcg_gen_div_i32(t3, t0, t1);
1003 tcg_gen_extu_i32_tl(ret, t3);
1004 } else {
1005 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1006 tcg_gen_movi_i32(t3, 0);
1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1008 tcg_gen_divu_i32(t3, t0, t1);
1009 tcg_gen_extu_i32_tl(ret, t3);
1010 }
1011 if (compute_ov) {
1012 tcg_gen_extu_i32_tl(cpu_ov, t2);
1013 if (is_isa300(ctx)) {
1014 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1015 }
1016 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1017 }
1018 tcg_temp_free_i32(t0);
1019 tcg_temp_free_i32(t1);
1020 tcg_temp_free_i32(t2);
1021 tcg_temp_free_i32(t3);
1022
1023 if (unlikely(Rc(ctx->opcode) != 0))
1024 gen_set_Rc0(ctx, ret);
1025 }
1026 /* Div functions */
1027 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1028 static void glue(gen_, name)(DisasContext *ctx) \
1029 { \
1030 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1031 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1032 sign, compute_ov); \
1033 }
1034 /* divwu divwu. divwuo divwuo. */
1035 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1036 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1037 /* divw divw. divwo divwo. */
1038 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1039 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1040
1041 /* div[wd]eu[o][.] */
1042 #define GEN_DIVE(name, hlpr, compute_ov) \
1043 static void gen_##name(DisasContext *ctx) \
1044 { \
1045 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1046 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1047 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1048 tcg_temp_free_i32(t0); \
1049 if (unlikely(Rc(ctx->opcode) != 0)) { \
1050 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1051 } \
1052 }
1053
1054 GEN_DIVE(divweu, divweu, 0);
1055 GEN_DIVE(divweuo, divweu, 1);
1056 GEN_DIVE(divwe, divwe, 0);
1057 GEN_DIVE(divweo, divwe, 1);
1058
1059 #if defined(TARGET_PPC64)
1060 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1061 TCGv arg2, int sign, int compute_ov)
1062 {
1063 TCGv_i64 t0 = tcg_temp_new_i64();
1064 TCGv_i64 t1 = tcg_temp_new_i64();
1065 TCGv_i64 t2 = tcg_temp_new_i64();
1066 TCGv_i64 t3 = tcg_temp_new_i64();
1067
1068 tcg_gen_mov_i64(t0, arg1);
1069 tcg_gen_mov_i64(t1, arg2);
1070 if (sign) {
1071 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1072 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1073 tcg_gen_and_i64(t2, t2, t3);
1074 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1075 tcg_gen_or_i64(t2, t2, t3);
1076 tcg_gen_movi_i64(t3, 0);
1077 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1078 tcg_gen_div_i64(ret, t0, t1);
1079 } else {
1080 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1081 tcg_gen_movi_i64(t3, 0);
1082 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1083 tcg_gen_divu_i64(ret, t0, t1);
1084 }
1085 if (compute_ov) {
1086 tcg_gen_mov_tl(cpu_ov, t2);
1087 if (is_isa300(ctx)) {
1088 tcg_gen_mov_tl(cpu_ov32, t2);
1089 }
1090 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1091 }
1092 tcg_temp_free_i64(t0);
1093 tcg_temp_free_i64(t1);
1094 tcg_temp_free_i64(t2);
1095 tcg_temp_free_i64(t3);
1096
1097 if (unlikely(Rc(ctx->opcode) != 0))
1098 gen_set_Rc0(ctx, ret);
1099 }
1100
1101 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1102 static void glue(gen_, name)(DisasContext *ctx) \
1103 { \
1104 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1105 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1106 sign, compute_ov); \
1107 }
1108 /* divdu divdu. divduo divduo. */
1109 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1110 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1111 /* divd divd. divdo divdo. */
1112 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1113 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1114
1115 GEN_DIVE(divdeu, divdeu, 0);
1116 GEN_DIVE(divdeuo, divdeu, 1);
1117 GEN_DIVE(divde, divde, 0);
1118 GEN_DIVE(divdeo, divde, 1);
1119 #endif
1120
1121 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1122 TCGv arg2, int sign)
1123 {
1124 TCGv_i32 t0 = tcg_temp_new_i32();
1125 TCGv_i32 t1 = tcg_temp_new_i32();
1126
1127 tcg_gen_trunc_tl_i32(t0, arg1);
1128 tcg_gen_trunc_tl_i32(t1, arg2);
1129 if (sign) {
1130 TCGv_i32 t2 = tcg_temp_new_i32();
1131 TCGv_i32 t3 = tcg_temp_new_i32();
1132 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1133 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1134 tcg_gen_and_i32(t2, t2, t3);
1135 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1136 tcg_gen_or_i32(t2, t2, t3);
1137 tcg_gen_movi_i32(t3, 0);
1138 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1139 tcg_gen_rem_i32(t3, t0, t1);
1140 tcg_gen_ext_i32_tl(ret, t3);
1141 tcg_temp_free_i32(t2);
1142 tcg_temp_free_i32(t3);
1143 } else {
1144 TCGv_i32 t2 = tcg_const_i32(1);
1145 TCGv_i32 t3 = tcg_const_i32(0);
1146 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1147 tcg_gen_remu_i32(t3, t0, t1);
1148 tcg_gen_extu_i32_tl(ret, t3);
1149 tcg_temp_free_i32(t2);
1150 tcg_temp_free_i32(t3);
1151 }
1152 tcg_temp_free_i32(t0);
1153 tcg_temp_free_i32(t1);
1154 }
1155
1156 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1157 static void glue(gen_, name)(DisasContext *ctx) \
1158 { \
1159 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign); \
1162 }
1163
1164 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1165 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1166
1167 #if defined(TARGET_PPC64)
1168 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1169 TCGv arg2, int sign)
1170 {
1171 TCGv_i64 t0 = tcg_temp_new_i64();
1172 TCGv_i64 t1 = tcg_temp_new_i64();
1173
1174 tcg_gen_mov_i64(t0, arg1);
1175 tcg_gen_mov_i64(t1, arg2);
1176 if (sign) {
1177 TCGv_i64 t2 = tcg_temp_new_i64();
1178 TCGv_i64 t3 = tcg_temp_new_i64();
1179 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1180 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1181 tcg_gen_and_i64(t2, t2, t3);
1182 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1183 tcg_gen_or_i64(t2, t2, t3);
1184 tcg_gen_movi_i64(t3, 0);
1185 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1186 tcg_gen_rem_i64(ret, t0, t1);
1187 tcg_temp_free_i64(t2);
1188 tcg_temp_free_i64(t3);
1189 } else {
1190 TCGv_i64 t2 = tcg_const_i64(1);
1191 TCGv_i64 t3 = tcg_const_i64(0);
1192 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1193 tcg_gen_remu_i64(ret, t0, t1);
1194 tcg_temp_free_i64(t2);
1195 tcg_temp_free_i64(t3);
1196 }
1197 tcg_temp_free_i64(t0);
1198 tcg_temp_free_i64(t1);
1199 }
1200
1201 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1202 static void glue(gen_, name)(DisasContext *ctx) \
1203 { \
1204 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1205 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1206 sign); \
1207 }
1208
1209 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1210 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1211 #endif
1212
1213 /* mulhw mulhw. */
1214 static void gen_mulhw(DisasContext *ctx)
1215 {
1216 TCGv_i32 t0 = tcg_temp_new_i32();
1217 TCGv_i32 t1 = tcg_temp_new_i32();
1218
1219 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1220 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1221 tcg_gen_muls2_i32(t0, t1, t0, t1);
1222 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1223 tcg_temp_free_i32(t0);
1224 tcg_temp_free_i32(t1);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1227 }
1228
1229 /* mulhwu mulhwu. */
1230 static void gen_mulhwu(DisasContext *ctx)
1231 {
1232 TCGv_i32 t0 = tcg_temp_new_i32();
1233 TCGv_i32 t1 = tcg_temp_new_i32();
1234
1235 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1236 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1237 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1238 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1239 tcg_temp_free_i32(t0);
1240 tcg_temp_free_i32(t1);
1241 if (unlikely(Rc(ctx->opcode) != 0))
1242 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1243 }
1244
1245 /* mullw mullw. */
1246 static void gen_mullw(DisasContext *ctx)
1247 {
1248 #if defined(TARGET_PPC64)
1249 TCGv_i64 t0, t1;
1250 t0 = tcg_temp_new_i64();
1251 t1 = tcg_temp_new_i64();
1252 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1253 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1254 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1255 tcg_temp_free(t0);
1256 tcg_temp_free(t1);
1257 #else
1258 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1259 cpu_gpr[rB(ctx->opcode)]);
1260 #endif
1261 if (unlikely(Rc(ctx->opcode) != 0))
1262 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1263 }
1264
1265 /* mullwo mullwo. */
1266 static void gen_mullwo(DisasContext *ctx)
1267 {
1268 TCGv_i32 t0 = tcg_temp_new_i32();
1269 TCGv_i32 t1 = tcg_temp_new_i32();
1270
1271 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1272 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1273 tcg_gen_muls2_i32(t0, t1, t0, t1);
1274 #if defined(TARGET_PPC64)
1275 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1276 #else
1277 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1278 #endif
1279
1280 tcg_gen_sari_i32(t0, t0, 31);
1281 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1282 tcg_gen_extu_i32_tl(cpu_ov, t0);
1283 if (is_isa300(ctx)) {
1284 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1285 }
1286 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1287
1288 tcg_temp_free_i32(t0);
1289 tcg_temp_free_i32(t1);
1290 if (unlikely(Rc(ctx->opcode) != 0))
1291 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1292 }
1293
1294 /* mulli */
1295 static void gen_mulli(DisasContext *ctx)
1296 {
1297 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1298 SIMM(ctx->opcode));
1299 }
1300
1301 #if defined(TARGET_PPC64)
1302 /* mulhd mulhd. */
1303 static void gen_mulhd(DisasContext *ctx)
1304 {
1305 TCGv lo = tcg_temp_new();
1306 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1307 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1308 tcg_temp_free(lo);
1309 if (unlikely(Rc(ctx->opcode) != 0)) {
1310 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1311 }
1312 }
1313
1314 /* mulhdu mulhdu. */
1315 static void gen_mulhdu(DisasContext *ctx)
1316 {
1317 TCGv lo = tcg_temp_new();
1318 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1320 tcg_temp_free(lo);
1321 if (unlikely(Rc(ctx->opcode) != 0)) {
1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1323 }
1324 }
1325
1326 /* mulld mulld. */
1327 static void gen_mulld(DisasContext *ctx)
1328 {
1329 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1330 cpu_gpr[rB(ctx->opcode)]);
1331 if (unlikely(Rc(ctx->opcode) != 0))
1332 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1333 }
1334
1335 /* mulldo mulldo. */
1336 static void gen_mulldo(DisasContext *ctx)
1337 {
1338 TCGv_i64 t0 = tcg_temp_new_i64();
1339 TCGv_i64 t1 = tcg_temp_new_i64();
1340
1341 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1342 cpu_gpr[rB(ctx->opcode)]);
1343 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1344
1345 tcg_gen_sari_i64(t0, t0, 63);
1346 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1347 if (is_isa300(ctx)) {
1348 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1349 }
1350 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1351
1352 tcg_temp_free_i64(t0);
1353 tcg_temp_free_i64(t1);
1354
1355 if (unlikely(Rc(ctx->opcode) != 0)) {
1356 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1357 }
1358 }
1359 #endif
1360
1361 /* Common subf function */
1362 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1363 TCGv arg2, bool add_ca, bool compute_ca,
1364 bool compute_ov, bool compute_rc0)
1365 {
1366 TCGv t0 = ret;
1367
1368 if (compute_ca || compute_ov) {
1369 t0 = tcg_temp_new();
1370 }
1371
1372 if (compute_ca) {
1373 /* dest = ~arg1 + arg2 [+ ca]. */
1374 if (NARROW_MODE(ctx)) {
1375 /* Caution: a non-obvious corner case of the spec is that we
1376 must produce the *entire* 64-bit addition, but produce the
1377 carry into bit 32. */
1378 TCGv inv1 = tcg_temp_new();
1379 TCGv t1 = tcg_temp_new();
1380 tcg_gen_not_tl(inv1, arg1);
1381 if (add_ca) {
1382 tcg_gen_add_tl(t0, arg2, cpu_ca);
1383 } else {
1384 tcg_gen_addi_tl(t0, arg2, 1);
1385 }
1386 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1387 tcg_gen_add_tl(t0, t0, inv1);
1388 tcg_temp_free(inv1);
1389 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1390 tcg_temp_free(t1);
1391 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1392 if (is_isa300(ctx)) {
1393 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1394 }
1395 } else if (add_ca) {
1396 TCGv zero, inv1 = tcg_temp_new();
1397 tcg_gen_not_tl(inv1, arg1);
1398 zero = tcg_const_tl(0);
1399 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1400 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1401 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
1402 tcg_temp_free(zero);
1403 tcg_temp_free(inv1);
1404 } else {
1405 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1406 tcg_gen_sub_tl(t0, arg2, arg1);
1407 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
1408 }
1409 } else if (add_ca) {
1410 /* Since we're ignoring carry-out, we can simplify the
1411 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1412 tcg_gen_sub_tl(t0, arg2, arg1);
1413 tcg_gen_add_tl(t0, t0, cpu_ca);
1414 tcg_gen_subi_tl(t0, t0, 1);
1415 } else {
1416 tcg_gen_sub_tl(t0, arg2, arg1);
1417 }
1418
1419 if (compute_ov) {
1420 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1421 }
1422 if (unlikely(compute_rc0)) {
1423 gen_set_Rc0(ctx, t0);
1424 }
1425
1426 if (t0 != ret) {
1427 tcg_gen_mov_tl(ret, t0);
1428 tcg_temp_free(t0);
1429 }
1430 }
1431 /* Sub functions with Two operands functions */
1432 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1433 static void glue(gen_, name)(DisasContext *ctx) \
1434 { \
1435 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1436 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1437 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1438 }
1439 /* Sub functions with one operand and one immediate */
1440 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1441 add_ca, compute_ca, compute_ov) \
1442 static void glue(gen_, name)(DisasContext *ctx) \
1443 { \
1444 TCGv t0 = tcg_const_tl(const_val); \
1445 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1446 cpu_gpr[rA(ctx->opcode)], t0, \
1447 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1448 tcg_temp_free(t0); \
1449 }
1450 /* subf subf. subfo subfo. */
1451 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1452 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1453 /* subfc subfc. subfco subfco. */
1454 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1455 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1456 /* subfe subfe. subfeo subfo. */
1457 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1458 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1459 /* subfme subfme. subfmeo subfmeo. */
1460 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1461 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1462 /* subfze subfze. subfzeo subfzeo.*/
1463 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1464 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1465
1466 /* subfic */
1467 static void gen_subfic(DisasContext *ctx)
1468 {
1469 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1470 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1471 c, 0, 1, 0, 0);
1472 tcg_temp_free(c);
1473 }
1474
1475 /* neg neg. nego nego. */
1476 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1477 {
1478 TCGv zero = tcg_const_tl(0);
1479 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1480 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1481 tcg_temp_free(zero);
1482 }
1483
1484 static void gen_neg(DisasContext *ctx)
1485 {
1486 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1487 if (unlikely(Rc(ctx->opcode))) {
1488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1489 }
1490 }
1491
1492 static void gen_nego(DisasContext *ctx)
1493 {
1494 gen_op_arith_neg(ctx, 1);
1495 }
1496
1497 /*** Integer logical ***/
1498 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1499 static void glue(gen_, name)(DisasContext *ctx) \
1500 { \
1501 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1502 cpu_gpr[rB(ctx->opcode)]); \
1503 if (unlikely(Rc(ctx->opcode) != 0)) \
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1505 }
1506
1507 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1508 static void glue(gen_, name)(DisasContext *ctx) \
1509 { \
1510 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1511 if (unlikely(Rc(ctx->opcode) != 0)) \
1512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1513 }
1514
1515 /* and & and. */
1516 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1517 /* andc & andc. */
1518 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1519
1520 /* andi. */
1521 static void gen_andi_(DisasContext *ctx)
1522 {
1523 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1524 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1525 }
1526
1527 /* andis. */
1528 static void gen_andis_(DisasContext *ctx)
1529 {
1530 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533
1534 /* cntlzw */
1535 static void gen_cntlzw(DisasContext *ctx)
1536 {
1537 TCGv_i32 t = tcg_temp_new_i32();
1538
1539 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1540 tcg_gen_clzi_i32(t, t, 32);
1541 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1542 tcg_temp_free_i32(t);
1543
1544 if (unlikely(Rc(ctx->opcode) != 0))
1545 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1546 }
1547
1548 /* cnttzw */
1549 static void gen_cnttzw(DisasContext *ctx)
1550 {
1551 TCGv_i32 t = tcg_temp_new_i32();
1552
1553 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1554 tcg_gen_ctzi_i32(t, t, 32);
1555 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1556 tcg_temp_free_i32(t);
1557
1558 if (unlikely(Rc(ctx->opcode) != 0)) {
1559 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1560 }
1561 }
1562
1563 /* eqv & eqv. */
1564 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1565 /* extsb & extsb. */
1566 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1567 /* extsh & extsh. */
1568 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1569 /* nand & nand. */
1570 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1571 /* nor & nor. */
1572 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1573
1574 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1575 static void gen_pause(DisasContext *ctx)
1576 {
1577 TCGv_i32 t0 = tcg_const_i32(0);
1578 tcg_gen_st_i32(t0, cpu_env,
1579 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1580 tcg_temp_free_i32(t0);
1581
1582 /* Stop translation, this gives other CPUs a chance to run */
1583 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1584 }
1585 #endif /* defined(TARGET_PPC64) */
1586
1587 /* or & or. */
1588 static void gen_or(DisasContext *ctx)
1589 {
1590 int rs, ra, rb;
1591
1592 rs = rS(ctx->opcode);
1593 ra = rA(ctx->opcode);
1594 rb = rB(ctx->opcode);
1595 /* Optimisation for mr. ri case */
1596 if (rs != ra || rs != rb) {
1597 if (rs != rb)
1598 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1599 else
1600 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1601 if (unlikely(Rc(ctx->opcode) != 0))
1602 gen_set_Rc0(ctx, cpu_gpr[ra]);
1603 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1604 gen_set_Rc0(ctx, cpu_gpr[rs]);
1605 #if defined(TARGET_PPC64)
1606 } else if (rs != 0) { /* 0 is nop */
1607 int prio = 0;
1608
1609 switch (rs) {
1610 case 1:
1611 /* Set process priority to low */
1612 prio = 2;
1613 break;
1614 case 6:
1615 /* Set process priority to medium-low */
1616 prio = 3;
1617 break;
1618 case 2:
1619 /* Set process priority to normal */
1620 prio = 4;
1621 break;
1622 #if !defined(CONFIG_USER_ONLY)
1623 case 31:
1624 if (!ctx->pr) {
1625 /* Set process priority to very low */
1626 prio = 1;
1627 }
1628 break;
1629 case 5:
1630 if (!ctx->pr) {
1631 /* Set process priority to medium-hight */
1632 prio = 5;
1633 }
1634 break;
1635 case 3:
1636 if (!ctx->pr) {
1637 /* Set process priority to high */
1638 prio = 6;
1639 }
1640 break;
1641 case 7:
1642 if (ctx->hv && !ctx->pr) {
1643 /* Set process priority to very high */
1644 prio = 7;
1645 }
1646 break;
1647 #endif
1648 default:
1649 break;
1650 }
1651 if (prio) {
1652 TCGv t0 = tcg_temp_new();
1653 gen_load_spr(t0, SPR_PPR);
1654 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1655 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1656 gen_store_spr(SPR_PPR, t0);
1657 tcg_temp_free(t0);
1658 }
1659 #if !defined(CONFIG_USER_ONLY)
1660 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1661 * CPU and the kernel hangs. This applies to all encodings other
1662 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1663 * and all currently undefined.
1664 */
1665 gen_pause(ctx);
1666 #endif
1667 #endif
1668 }
1669 }
1670 /* orc & orc. */
1671 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1672
1673 /* xor & xor. */
1674 static void gen_xor(DisasContext *ctx)
1675 {
1676 /* Optimisation for "set to zero" case */
1677 if (rS(ctx->opcode) != rB(ctx->opcode))
1678 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1679 else
1680 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1683 }
1684
1685 /* ori */
1686 static void gen_ori(DisasContext *ctx)
1687 {
1688 target_ulong uimm = UIMM(ctx->opcode);
1689
1690 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1691 return;
1692 }
1693 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1694 }
1695
1696 /* oris */
1697 static void gen_oris(DisasContext *ctx)
1698 {
1699 target_ulong uimm = UIMM(ctx->opcode);
1700
1701 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1702 /* NOP */
1703 return;
1704 }
1705 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1706 }
1707
1708 /* xori */
1709 static void gen_xori(DisasContext *ctx)
1710 {
1711 target_ulong uimm = UIMM(ctx->opcode);
1712
1713 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1714 /* NOP */
1715 return;
1716 }
1717 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1718 }
1719
1720 /* xoris */
1721 static void gen_xoris(DisasContext *ctx)
1722 {
1723 target_ulong uimm = UIMM(ctx->opcode);
1724
1725 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1726 /* NOP */
1727 return;
1728 }
1729 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1730 }
1731
1732 /* popcntb : PowerPC 2.03 specification */
1733 static void gen_popcntb(DisasContext *ctx)
1734 {
1735 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1736 }
1737
1738 static void gen_popcntw(DisasContext *ctx)
1739 {
1740 #if defined(TARGET_PPC64)
1741 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1742 #else
1743 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1744 #endif
1745 }
1746
1747 #if defined(TARGET_PPC64)
1748 /* popcntd: PowerPC 2.06 specification */
1749 static void gen_popcntd(DisasContext *ctx)
1750 {
1751 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1752 }
1753 #endif
1754
1755 /* prtyw: PowerPC 2.05 specification */
1756 static void gen_prtyw(DisasContext *ctx)
1757 {
1758 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1759 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1760 TCGv t0 = tcg_temp_new();
1761 tcg_gen_shri_tl(t0, rs, 16);
1762 tcg_gen_xor_tl(ra, rs, t0);
1763 tcg_gen_shri_tl(t0, ra, 8);
1764 tcg_gen_xor_tl(ra, ra, t0);
1765 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1766 tcg_temp_free(t0);
1767 }
1768
1769 #if defined(TARGET_PPC64)
1770 /* prtyd: PowerPC 2.05 specification */
1771 static void gen_prtyd(DisasContext *ctx)
1772 {
1773 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1774 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1775 TCGv t0 = tcg_temp_new();
1776 tcg_gen_shri_tl(t0, rs, 32);
1777 tcg_gen_xor_tl(ra, rs, t0);
1778 tcg_gen_shri_tl(t0, ra, 16);
1779 tcg_gen_xor_tl(ra, ra, t0);
1780 tcg_gen_shri_tl(t0, ra, 8);
1781 tcg_gen_xor_tl(ra, ra, t0);
1782 tcg_gen_andi_tl(ra, ra, 1);
1783 tcg_temp_free(t0);
1784 }
1785 #endif
1786
1787 #if defined(TARGET_PPC64)
1788 /* bpermd */
1789 static void gen_bpermd(DisasContext *ctx)
1790 {
1791 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1792 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1793 }
1794 #endif
1795
1796 #if defined(TARGET_PPC64)
1797 /* extsw & extsw. */
1798 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1799
1800 /* cntlzd */
1801 static void gen_cntlzd(DisasContext *ctx)
1802 {
1803 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1804 if (unlikely(Rc(ctx->opcode) != 0))
1805 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1806 }
1807
1808 /* cnttzd */
1809 static void gen_cnttzd(DisasContext *ctx)
1810 {
1811 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1812 if (unlikely(Rc(ctx->opcode) != 0)) {
1813 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1814 }
1815 }
1816
1817 /* darn */
1818 static void gen_darn(DisasContext *ctx)
1819 {
1820 int l = L(ctx->opcode);
1821
1822 if (l == 0) {
1823 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1824 } else if (l <= 2) {
1825 /* Return 64-bit random for both CRN and RRN */
1826 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1827 } else {
1828 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1829 }
1830 }
1831 #endif
1832
1833 /*** Integer rotate ***/
1834
1835 /* rlwimi & rlwimi. */
1836 static void gen_rlwimi(DisasContext *ctx)
1837 {
1838 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1839 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1840 uint32_t sh = SH(ctx->opcode);
1841 uint32_t mb = MB(ctx->opcode);
1842 uint32_t me = ME(ctx->opcode);
1843
1844 if (sh == (31-me) && mb <= me) {
1845 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1846 } else {
1847 target_ulong mask;
1848 TCGv t1;
1849
1850 #if defined(TARGET_PPC64)
1851 mb += 32;
1852 me += 32;
1853 #endif
1854 mask = MASK(mb, me);
1855
1856 t1 = tcg_temp_new();
1857 if (mask <= 0xffffffffu) {
1858 TCGv_i32 t0 = tcg_temp_new_i32();
1859 tcg_gen_trunc_tl_i32(t0, t_rs);
1860 tcg_gen_rotli_i32(t0, t0, sh);
1861 tcg_gen_extu_i32_tl(t1, t0);
1862 tcg_temp_free_i32(t0);
1863 } else {
1864 #if defined(TARGET_PPC64)
1865 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1866 tcg_gen_rotli_i64(t1, t1, sh);
1867 #else
1868 g_assert_not_reached();
1869 #endif
1870 }
1871
1872 tcg_gen_andi_tl(t1, t1, mask);
1873 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1874 tcg_gen_or_tl(t_ra, t_ra, t1);
1875 tcg_temp_free(t1);
1876 }
1877 if (unlikely(Rc(ctx->opcode) != 0)) {
1878 gen_set_Rc0(ctx, t_ra);
1879 }
1880 }
1881
1882 /* rlwinm & rlwinm. */
1883 static void gen_rlwinm(DisasContext *ctx)
1884 {
1885 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1886 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1887 int sh = SH(ctx->opcode);
1888 int mb = MB(ctx->opcode);
1889 int me = ME(ctx->opcode);
1890 int len = me - mb + 1;
1891 int rsh = (32 - sh) & 31;
1892
1893 if (sh != 0 && len > 0 && me == (31 - sh)) {
1894 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1895 } else if (me == 31 && rsh + len <= 32) {
1896 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1897 } else {
1898 target_ulong mask;
1899 #if defined(TARGET_PPC64)
1900 mb += 32;
1901 me += 32;
1902 #endif
1903 mask = MASK(mb, me);
1904 if (sh == 0) {
1905 tcg_gen_andi_tl(t_ra, t_rs, mask);
1906 } else if (mask <= 0xffffffffu) {
1907 TCGv_i32 t0 = tcg_temp_new_i32();
1908 tcg_gen_trunc_tl_i32(t0, t_rs);
1909 tcg_gen_rotli_i32(t0, t0, sh);
1910 tcg_gen_andi_i32(t0, t0, mask);
1911 tcg_gen_extu_i32_tl(t_ra, t0);
1912 tcg_temp_free_i32(t0);
1913 } else {
1914 #if defined(TARGET_PPC64)
1915 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1916 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1917 tcg_gen_andi_i64(t_ra, t_ra, mask);
1918 #else
1919 g_assert_not_reached();
1920 #endif
1921 }
1922 }
1923 if (unlikely(Rc(ctx->opcode) != 0)) {
1924 gen_set_Rc0(ctx, t_ra);
1925 }
1926 }
1927
1928 /* rlwnm & rlwnm. */
1929 static void gen_rlwnm(DisasContext *ctx)
1930 {
1931 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1932 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1933 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1934 uint32_t mb = MB(ctx->opcode);
1935 uint32_t me = ME(ctx->opcode);
1936 target_ulong mask;
1937
1938 #if defined(TARGET_PPC64)
1939 mb += 32;
1940 me += 32;
1941 #endif
1942 mask = MASK(mb, me);
1943
1944 if (mask <= 0xffffffffu) {
1945 TCGv_i32 t0 = tcg_temp_new_i32();
1946 TCGv_i32 t1 = tcg_temp_new_i32();
1947 tcg_gen_trunc_tl_i32(t0, t_rb);
1948 tcg_gen_trunc_tl_i32(t1, t_rs);
1949 tcg_gen_andi_i32(t0, t0, 0x1f);
1950 tcg_gen_rotl_i32(t1, t1, t0);
1951 tcg_gen_extu_i32_tl(t_ra, t1);
1952 tcg_temp_free_i32(t0);
1953 tcg_temp_free_i32(t1);
1954 } else {
1955 #if defined(TARGET_PPC64)
1956 TCGv_i64 t0 = tcg_temp_new_i64();
1957 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1958 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1959 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1960 tcg_temp_free_i64(t0);
1961 #else
1962 g_assert_not_reached();
1963 #endif
1964 }
1965
1966 tcg_gen_andi_tl(t_ra, t_ra, mask);
1967
1968 if (unlikely(Rc(ctx->opcode) != 0)) {
1969 gen_set_Rc0(ctx, t_ra);
1970 }
1971 }
1972
1973 #if defined(TARGET_PPC64)
1974 #define GEN_PPC64_R2(name, opc1, opc2) \
1975 static void glue(gen_, name##0)(DisasContext *ctx) \
1976 { \
1977 gen_##name(ctx, 0); \
1978 } \
1979 \
1980 static void glue(gen_, name##1)(DisasContext *ctx) \
1981 { \
1982 gen_##name(ctx, 1); \
1983 }
1984 #define GEN_PPC64_R4(name, opc1, opc2) \
1985 static void glue(gen_, name##0)(DisasContext *ctx) \
1986 { \
1987 gen_##name(ctx, 0, 0); \
1988 } \
1989 \
1990 static void glue(gen_, name##1)(DisasContext *ctx) \
1991 { \
1992 gen_##name(ctx, 0, 1); \
1993 } \
1994 \
1995 static void glue(gen_, name##2)(DisasContext *ctx) \
1996 { \
1997 gen_##name(ctx, 1, 0); \
1998 } \
1999 \
2000 static void glue(gen_, name##3)(DisasContext *ctx) \
2001 { \
2002 gen_##name(ctx, 1, 1); \
2003 }
2004
2005 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2006 {
2007 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2008 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2009 int len = me - mb + 1;
2010 int rsh = (64 - sh) & 63;
2011
2012 if (sh != 0 && len > 0 && me == (63 - sh)) {
2013 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2014 } else if (me == 63 && rsh + len <= 64) {
2015 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2016 } else {
2017 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2018 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2019 }
2020 if (unlikely(Rc(ctx->opcode) != 0)) {
2021 gen_set_Rc0(ctx, t_ra);
2022 }
2023 }
2024
2025 /* rldicl - rldicl. */
2026 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2027 {
2028 uint32_t sh, mb;
2029
2030 sh = SH(ctx->opcode) | (shn << 5);
2031 mb = MB(ctx->opcode) | (mbn << 5);
2032 gen_rldinm(ctx, mb, 63, sh);
2033 }
2034 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2035
2036 /* rldicr - rldicr. */
2037 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2038 {
2039 uint32_t sh, me;
2040
2041 sh = SH(ctx->opcode) | (shn << 5);
2042 me = MB(ctx->opcode) | (men << 5);
2043 gen_rldinm(ctx, 0, me, sh);
2044 }
2045 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2046
2047 /* rldic - rldic. */
2048 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2049 {
2050 uint32_t sh, mb;
2051
2052 sh = SH(ctx->opcode) | (shn << 5);
2053 mb = MB(ctx->opcode) | (mbn << 5);
2054 gen_rldinm(ctx, mb, 63 - sh, sh);
2055 }
2056 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2057
2058 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2059 {
2060 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2061 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2062 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2063 TCGv t0;
2064
2065 t0 = tcg_temp_new();
2066 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2067 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2068 tcg_temp_free(t0);
2069
2070 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2071 if (unlikely(Rc(ctx->opcode) != 0)) {
2072 gen_set_Rc0(ctx, t_ra);
2073 }
2074 }
2075
2076 /* rldcl - rldcl. */
2077 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2078 {
2079 uint32_t mb;
2080
2081 mb = MB(ctx->opcode) | (mbn << 5);
2082 gen_rldnm(ctx, mb, 63);
2083 }
2084 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2085
2086 /* rldcr - rldcr. */
2087 static inline void gen_rldcr(DisasContext *ctx, int men)
2088 {
2089 uint32_t me;
2090
2091 me = MB(ctx->opcode) | (men << 5);
2092 gen_rldnm(ctx, 0, me);
2093 }
2094 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2095
2096 /* rldimi - rldimi. */
2097 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2098 {
2099 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2100 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2101 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2102 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2103 uint32_t me = 63 - sh;
2104
2105 if (mb <= me) {
2106 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2107 } else {
2108 target_ulong mask = MASK(mb, me);
2109 TCGv t1 = tcg_temp_new();
2110
2111 tcg_gen_rotli_tl(t1, t_rs, sh);
2112 tcg_gen_andi_tl(t1, t1, mask);
2113 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2114 tcg_gen_or_tl(t_ra, t_ra, t1);
2115 tcg_temp_free(t1);
2116 }
2117 if (unlikely(Rc(ctx->opcode) != 0)) {
2118 gen_set_Rc0(ctx, t_ra);
2119 }
2120 }
2121 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2122 #endif
2123
2124 /*** Integer shift ***/
2125
2126 /* slw & slw. */
2127 static void gen_slw(DisasContext *ctx)
2128 {
2129 TCGv t0, t1;
2130
2131 t0 = tcg_temp_new();
2132 /* AND rS with a mask that is 0 when rB >= 0x20 */
2133 #if defined(TARGET_PPC64)
2134 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2135 tcg_gen_sari_tl(t0, t0, 0x3f);
2136 #else
2137 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2138 tcg_gen_sari_tl(t0, t0, 0x1f);
2139 #endif
2140 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2141 t1 = tcg_temp_new();
2142 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2143 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2144 tcg_temp_free(t1);
2145 tcg_temp_free(t0);
2146 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2147 if (unlikely(Rc(ctx->opcode) != 0))
2148 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2149 }
2150
2151 /* sraw & sraw. */
2152 static void gen_sraw(DisasContext *ctx)
2153 {
2154 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2155 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2156 if (unlikely(Rc(ctx->opcode) != 0))
2157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2158 }
2159
2160 /* srawi & srawi. */
2161 static void gen_srawi(DisasContext *ctx)
2162 {
2163 int sh = SH(ctx->opcode);
2164 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2165 TCGv src = cpu_gpr[rS(ctx->opcode)];
2166 if (sh == 0) {
2167 tcg_gen_ext32s_tl(dst, src);
2168 tcg_gen_movi_tl(cpu_ca, 0);
2169 if (is_isa300(ctx)) {
2170 tcg_gen_movi_tl(cpu_ca32, 0);
2171 }
2172 } else {
2173 TCGv t0;
2174 tcg_gen_ext32s_tl(dst, src);
2175 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2176 t0 = tcg_temp_new();
2177 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2178 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2179 tcg_temp_free(t0);
2180 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2181 if (is_isa300(ctx)) {
2182 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2183 }
2184 tcg_gen_sari_tl(dst, dst, sh);
2185 }
2186 if (unlikely(Rc(ctx->opcode) != 0)) {
2187 gen_set_Rc0(ctx, dst);
2188 }
2189 }
2190
2191 /* srw & srw. */
2192 static void gen_srw(DisasContext *ctx)
2193 {
2194 TCGv t0, t1;
2195
2196 t0 = tcg_temp_new();
2197 /* AND rS with a mask that is 0 when rB >= 0x20 */
2198 #if defined(TARGET_PPC64)
2199 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2200 tcg_gen_sari_tl(t0, t0, 0x3f);
2201 #else
2202 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2203 tcg_gen_sari_tl(t0, t0, 0x1f);
2204 #endif
2205 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2206 tcg_gen_ext32u_tl(t0, t0);
2207 t1 = tcg_temp_new();
2208 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2209 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2210 tcg_temp_free(t1);
2211 tcg_temp_free(t0);
2212 if (unlikely(Rc(ctx->opcode) != 0))
2213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2214 }
2215
2216 #if defined(TARGET_PPC64)
2217 /* sld & sld. */
2218 static void gen_sld(DisasContext *ctx)
2219 {
2220 TCGv t0, t1;
2221
2222 t0 = tcg_temp_new();
2223 /* AND rS with a mask that is 0 when rB >= 0x40 */
2224 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2225 tcg_gen_sari_tl(t0, t0, 0x3f);
2226 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2227 t1 = tcg_temp_new();
2228 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2229 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2230 tcg_temp_free(t1);
2231 tcg_temp_free(t0);
2232 if (unlikely(Rc(ctx->opcode) != 0))
2233 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2234 }
2235
2236 /* srad & srad. */
2237 static void gen_srad(DisasContext *ctx)
2238 {
2239 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2240 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2241 if (unlikely(Rc(ctx->opcode) != 0))
2242 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2243 }
2244 /* sradi & sradi. */
2245 static inline void gen_sradi(DisasContext *ctx, int n)
2246 {
2247 int sh = SH(ctx->opcode) + (n << 5);
2248 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2249 TCGv src = cpu_gpr[rS(ctx->opcode)];
2250 if (sh == 0) {
2251 tcg_gen_mov_tl(dst, src);
2252 tcg_gen_movi_tl(cpu_ca, 0);
2253 if (is_isa300(ctx)) {
2254 tcg_gen_movi_tl(cpu_ca32, 0);
2255 }
2256 } else {
2257 TCGv t0;
2258 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2259 t0 = tcg_temp_new();
2260 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2261 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2262 tcg_temp_free(t0);
2263 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2264 if (is_isa300(ctx)) {
2265 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2266 }
2267 tcg_gen_sari_tl(dst, src, sh);
2268 }
2269 if (unlikely(Rc(ctx->opcode) != 0)) {
2270 gen_set_Rc0(ctx, dst);
2271 }
2272 }
2273
2274 static void gen_sradi0(DisasContext *ctx)
2275 {
2276 gen_sradi(ctx, 0);
2277 }
2278
2279 static void gen_sradi1(DisasContext *ctx)
2280 {
2281 gen_sradi(ctx, 1);
2282 }
2283
2284 /* extswsli & extswsli. */
2285 static inline void gen_extswsli(DisasContext *ctx, int n)
2286 {
2287 int sh = SH(ctx->opcode) + (n << 5);
2288 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2289 TCGv src = cpu_gpr[rS(ctx->opcode)];
2290
2291 tcg_gen_ext32s_tl(dst, src);
2292 tcg_gen_shli_tl(dst, dst, sh);
2293 if (unlikely(Rc(ctx->opcode) != 0)) {
2294 gen_set_Rc0(ctx, dst);
2295 }
2296 }
2297
2298 static void gen_extswsli0(DisasContext *ctx)
2299 {
2300 gen_extswsli(ctx, 0);
2301 }
2302
2303 static void gen_extswsli1(DisasContext *ctx)
2304 {
2305 gen_extswsli(ctx, 1);
2306 }
2307
2308 /* srd & srd. */
2309 static void gen_srd(DisasContext *ctx)
2310 {
2311 TCGv t0, t1;
2312
2313 t0 = tcg_temp_new();
2314 /* AND rS with a mask that is 0 when rB >= 0x40 */
2315 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2316 tcg_gen_sari_tl(t0, t0, 0x3f);
2317 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2318 t1 = tcg_temp_new();
2319 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2320 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2321 tcg_temp_free(t1);
2322 tcg_temp_free(t0);
2323 if (unlikely(Rc(ctx->opcode) != 0))
2324 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2325 }
2326 #endif
2327
2328 /*** Addressing modes ***/
2329 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2330 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2331 target_long maskl)
2332 {
2333 target_long simm = SIMM(ctx->opcode);
2334
2335 simm &= ~maskl;
2336 if (rA(ctx->opcode) == 0) {
2337 if (NARROW_MODE(ctx)) {
2338 simm = (uint32_t)simm;
2339 }
2340 tcg_gen_movi_tl(EA, simm);
2341 } else if (likely(simm != 0)) {
2342 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2343 if (NARROW_MODE(ctx)) {
2344 tcg_gen_ext32u_tl(EA, EA);
2345 }
2346 } else {
2347 if (NARROW_MODE(ctx)) {
2348 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2349 } else {
2350 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2351 }
2352 }
2353 }
2354
2355 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2356 {
2357 if (rA(ctx->opcode) == 0) {
2358 if (NARROW_MODE(ctx)) {
2359 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2360 } else {
2361 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2362 }
2363 } else {
2364 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 }
2369 }
2370
2371 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2372 {
2373 if (rA(ctx->opcode) == 0) {
2374 tcg_gen_movi_tl(EA, 0);
2375 } else if (NARROW_MODE(ctx)) {
2376 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2377 } else {
2378 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2379 }
2380 }
2381
2382 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2383 target_long val)
2384 {
2385 tcg_gen_addi_tl(ret, arg1, val);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(ret, ret);
2388 }
2389 }
2390
2391 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2392 {
2393 TCGLabel *l1 = gen_new_label();
2394 TCGv t0 = tcg_temp_new();
2395 TCGv_i32 t1, t2;
2396 tcg_gen_andi_tl(t0, EA, mask);
2397 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2398 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2399 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2400 gen_update_nip(ctx, ctx->base.pc_next - 4);
2401 gen_helper_raise_exception_err(cpu_env, t1, t2);
2402 tcg_temp_free_i32(t1);
2403 tcg_temp_free_i32(t2);
2404 gen_set_label(l1);
2405 tcg_temp_free(t0);
2406 }
2407
2408 static inline void gen_align_no_le(DisasContext *ctx)
2409 {
2410 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2411 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2412 }
2413
2414 /*** Integer load ***/
2415 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2416 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2417
2418 #define GEN_QEMU_LOAD_TL(ldop, op) \
2419 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2420 TCGv val, \
2421 TCGv addr) \
2422 { \
2423 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2424 }
2425
2426 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2427 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2428 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2429 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2430 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2431
2432 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2433 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2434
2435 #define GEN_QEMU_LOAD_64(ldop, op) \
2436 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2437 TCGv_i64 val, \
2438 TCGv addr) \
2439 { \
2440 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2441 }
2442
2443 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2444 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2445 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2446 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2447 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2448
2449 #if defined(TARGET_PPC64)
2450 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2451 #endif
2452
2453 #define GEN_QEMU_STORE_TL(stop, op) \
2454 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2455 TCGv val, \
2456 TCGv addr) \
2457 { \
2458 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2459 }
2460
2461 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2462 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2463 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2464
2465 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2466 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2467
2468 #define GEN_QEMU_STORE_64(stop, op) \
2469 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2470 TCGv_i64 val, \
2471 TCGv addr) \
2472 { \
2473 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2474 }
2475
2476 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2477 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2478 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2479 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2480
2481 #if defined(TARGET_PPC64)
2482 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2483 #endif
2484
2485 #define GEN_LD(name, ldop, opc, type) \
2486 static void glue(gen_, name)(DisasContext *ctx) \
2487 { \
2488 TCGv EA; \
2489 gen_set_access_type(ctx, ACCESS_INT); \
2490 EA = tcg_temp_new(); \
2491 gen_addr_imm_index(ctx, EA, 0); \
2492 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2493 tcg_temp_free(EA); \
2494 }
2495
2496 #define GEN_LDU(name, ldop, opc, type) \
2497 static void glue(gen_, name##u)(DisasContext *ctx) \
2498 { \
2499 TCGv EA; \
2500 if (unlikely(rA(ctx->opcode) == 0 || \
2501 rA(ctx->opcode) == rD(ctx->opcode))) { \
2502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2503 return; \
2504 } \
2505 gen_set_access_type(ctx, ACCESS_INT); \
2506 EA = tcg_temp_new(); \
2507 if (type == PPC_64B) \
2508 gen_addr_imm_index(ctx, EA, 0x03); \
2509 else \
2510 gen_addr_imm_index(ctx, EA, 0); \
2511 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2512 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2513 tcg_temp_free(EA); \
2514 }
2515
2516 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2517 static void glue(gen_, name##ux)(DisasContext *ctx) \
2518 { \
2519 TCGv EA; \
2520 if (unlikely(rA(ctx->opcode) == 0 || \
2521 rA(ctx->opcode) == rD(ctx->opcode))) { \
2522 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2523 return; \
2524 } \
2525 gen_set_access_type(ctx, ACCESS_INT); \
2526 EA = tcg_temp_new(); \
2527 gen_addr_reg_index(ctx, EA); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2530 tcg_temp_free(EA); \
2531 }
2532
2533 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2534 static void glue(gen_, name##x)(DisasContext *ctx) \
2535 { \
2536 TCGv EA; \
2537 chk; \
2538 gen_set_access_type(ctx, ACCESS_INT); \
2539 EA = tcg_temp_new(); \
2540 gen_addr_reg_index(ctx, EA); \
2541 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2542 tcg_temp_free(EA); \
2543 }
2544
2545 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2546 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2547
2548 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2549 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2550
2551 #define GEN_LDS(name, ldop, op, type) \
2552 GEN_LD(name, ldop, op | 0x20, type); \
2553 GEN_LDU(name, ldop, op | 0x21, type); \
2554 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2555 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2556
2557 /* lbz lbzu lbzux lbzx */
2558 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2559 /* lha lhau lhaux lhax */
2560 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2561 /* lhz lhzu lhzux lhzx */
2562 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2563 /* lwz lwzu lwzux lwzx */
2564 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2565 #if defined(TARGET_PPC64)
2566 /* lwaux */
2567 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2568 /* lwax */
2569 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2570 /* ldux */
2571 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2572 /* ldx */
2573 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2574
2575 /* CI load/store variants */
2576 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2577 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2578 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2579 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2580
2581 static void gen_ld(DisasContext *ctx)
2582 {
2583 TCGv EA;
2584 if (Rc(ctx->opcode)) {
2585 if (unlikely(rA(ctx->opcode) == 0 ||
2586 rA(ctx->opcode) == rD(ctx->opcode))) {
2587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2588 return;
2589 }
2590 }
2591 gen_set_access_type(ctx, ACCESS_INT);
2592 EA = tcg_temp_new();
2593 gen_addr_imm_index(ctx, EA, 0x03);
2594 if (ctx->opcode & 0x02) {
2595 /* lwa (lwau is undefined) */
2596 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2597 } else {
2598 /* ld - ldu */
2599 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2600 }
2601 if (Rc(ctx->opcode))
2602 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2603 tcg_temp_free(EA);
2604 }
2605
2606 /* lq */
2607 static void gen_lq(DisasContext *ctx)
2608 {
2609 int ra, rd;
2610 TCGv EA;
2611
2612 /* lq is a legal user mode instruction starting in ISA 2.07 */
2613 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2614 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2615
2616 if (!legal_in_user_mode && ctx->pr) {
2617 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2618 return;
2619 }
2620
2621 if (!le_is_supported && ctx->le_mode) {
2622 gen_align_no_le(ctx);
2623 return;
2624 }
2625 ra = rA(ctx->opcode);
2626 rd = rD(ctx->opcode);
2627 if (unlikely((rd & 1) || rd == ra)) {
2628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2629 return;
2630 }
2631
2632 gen_set_access_type(ctx, ACCESS_INT);
2633 EA = tcg_temp_new();
2634 gen_addr_imm_index(ctx, EA, 0x0F);
2635
2636 /* We only need to swap high and low halves. gen_qemu_ld64_i64 does
2637 necessary 64-bit byteswap already. */
2638 if (unlikely(ctx->le_mode)) {
2639 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2640 gen_addr_add(ctx, EA, EA, 8);
2641 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2642 } else {
2643 gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
2644 gen_addr_add(ctx, EA, EA, 8);
2645 gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
2646 }
2647 tcg_temp_free(EA);
2648 }
2649 #endif
2650
2651 /*** Integer store ***/
2652 #define GEN_ST(name, stop, opc, type) \
2653 static void glue(gen_, name)(DisasContext *ctx) \
2654 { \
2655 TCGv EA; \
2656 gen_set_access_type(ctx, ACCESS_INT); \
2657 EA = tcg_temp_new(); \
2658 gen_addr_imm_index(ctx, EA, 0); \
2659 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2660 tcg_temp_free(EA); \
2661 }
2662
2663 #define GEN_STU(name, stop, opc, type) \
2664 static void glue(gen_, stop##u)(DisasContext *ctx) \
2665 { \
2666 TCGv EA; \
2667 if (unlikely(rA(ctx->opcode) == 0)) { \
2668 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2669 return; \
2670 } \
2671 gen_set_access_type(ctx, ACCESS_INT); \
2672 EA = tcg_temp_new(); \
2673 if (type == PPC_64B) \
2674 gen_addr_imm_index(ctx, EA, 0x03); \
2675 else \
2676 gen_addr_imm_index(ctx, EA, 0); \
2677 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2678 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2679 tcg_temp_free(EA); \
2680 }
2681
2682 #define GEN_STUX(name, stop, opc2, opc3, type) \
2683 static void glue(gen_, name##ux)(DisasContext *ctx) \
2684 { \
2685 TCGv EA; \
2686 if (unlikely(rA(ctx->opcode) == 0)) { \
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2688 return; \
2689 } \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 gen_addr_reg_index(ctx, EA); \
2693 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2695 tcg_temp_free(EA); \
2696 }
2697
2698 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2699 static void glue(gen_, name##x)(DisasContext *ctx) \
2700 { \
2701 TCGv EA; \
2702 chk; \
2703 gen_set_access_type(ctx, ACCESS_INT); \
2704 EA = tcg_temp_new(); \
2705 gen_addr_reg_index(ctx, EA); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_temp_free(EA); \
2708 }
2709 #define GEN_STX(name, stop, opc2, opc3, type) \
2710 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2711
2712 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2713 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2714
2715 #define GEN_STS(name, stop, op, type) \
2716 GEN_ST(name, stop, op | 0x20, type); \
2717 GEN_STU(name, stop, op | 0x21, type); \
2718 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2719 GEN_STX(name, stop, 0x17, op | 0x00, type)
2720
2721 /* stb stbu stbux stbx */
2722 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2723 /* sth sthu sthux sthx */
2724 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2725 /* stw stwu stwux stwx */
2726 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2727 #if defined(TARGET_PPC64)
2728 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2729 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2730 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2731 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2732 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2733 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2734
2735 static void gen_std(DisasContext *ctx)
2736 {
2737 int rs;
2738 TCGv EA;
2739
2740 rs = rS(ctx->opcode);
2741 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2742 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2743 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2744
2745 if (!(ctx->insns_flags & PPC_64BX)) {
2746 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2747 }
2748
2749 if (!legal_in_user_mode && ctx->pr) {
2750 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2751 return;
2752 }
2753
2754 if (!le_is_supported && ctx->le_mode) {
2755 gen_align_no_le(ctx);
2756 return;
2757 }
2758
2759 if (unlikely(rs & 1)) {
2760 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2761 return;
2762 }
2763 gen_set_access_type(ctx, ACCESS_INT);
2764 EA = tcg_temp_new();
2765 gen_addr_imm_index(ctx, EA, 0x03);
2766
2767 /* We only need to swap high and low halves. gen_qemu_st64_i64 does
2768 necessary 64-bit byteswap already. */
2769 if (unlikely(ctx->le_mode)) {
2770 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2771 gen_addr_add(ctx, EA, EA, 8);
2772 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2773 } else {
2774 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2775 gen_addr_add(ctx, EA, EA, 8);
2776 gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA);
2777 }
2778 tcg_temp_free(EA);
2779 } else {
2780 /* std / stdu*/
2781 if (Rc(ctx->opcode)) {
2782 if (unlikely(rA(ctx->opcode) == 0)) {
2783 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2784 return;
2785 }
2786 }
2787 gen_set_access_type(ctx, ACCESS_INT);
2788 EA = tcg_temp_new();
2789 gen_addr_imm_index(ctx, EA, 0x03);
2790 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2791 if (Rc(ctx->opcode))
2792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2793 tcg_temp_free(EA);
2794 }
2795 }
2796 #endif
2797 /*** Integer load and store with byte reverse ***/
2798
2799 /* lhbrx */
2800 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2801
2802 /* lwbrx */
2803 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2804
2805 #if defined(TARGET_PPC64)
2806 /* ldbrx */
2807 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2808 /* stdbrx */
2809 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2810 #endif /* TARGET_PPC64 */
2811
2812 /* sthbrx */
2813 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2814 /* stwbrx */
2815 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2816
2817 /*** Integer load and store multiple ***/
2818
2819 /* lmw */
2820 static void gen_lmw(DisasContext *ctx)
2821 {
2822 TCGv t0;
2823 TCGv_i32 t1;
2824
2825 if (ctx->le_mode) {
2826 gen_align_no_le(ctx);
2827 return;
2828 }
2829 gen_set_access_type(ctx, ACCESS_INT);
2830 t0 = tcg_temp_new();
2831 t1 = tcg_const_i32(rD(ctx->opcode));
2832 gen_addr_imm_index(ctx, t0, 0);
2833 gen_helper_lmw(cpu_env, t0, t1);
2834 tcg_temp_free(t0);
2835 tcg_temp_free_i32(t1);
2836 }
2837
2838 /* stmw */
2839 static void gen_stmw(DisasContext *ctx)
2840 {
2841 TCGv t0;
2842 TCGv_i32 t1;
2843
2844 if (ctx->le_mode) {
2845 gen_align_no_le(ctx);
2846 return;
2847 }
2848 gen_set_access_type(ctx, ACCESS_INT);
2849 t0 = tcg_temp_new();
2850 t1 = tcg_const_i32(rS(ctx->opcode));
2851 gen_addr_imm_index(ctx, t0, 0);
2852 gen_helper_stmw(cpu_env, t0, t1);
2853 tcg_temp_free(t0);
2854 tcg_temp_free_i32(t1);
2855 }
2856
2857 /*** Integer load and store strings ***/
2858
2859 /* lswi */
2860 /* PowerPC32 specification says we must generate an exception if
2861 * rA is in the range of registers to be loaded.
2862 * In an other hand, IBM says this is valid, but rA won't be loaded.
2863 * For now, I'll follow the spec...
2864 */
2865 static void gen_lswi(DisasContext *ctx)
2866 {
2867 TCGv t0;
2868 TCGv_i32 t1, t2;
2869 int nb = NB(ctx->opcode);
2870 int start = rD(ctx->opcode);
2871 int ra = rA(ctx->opcode);
2872 int nr;
2873
2874 if (ctx->le_mode) {
2875 gen_align_no_le(ctx);
2876 return;
2877 }
2878 if (nb == 0)
2879 nb = 32;
2880 nr = DIV_ROUND_UP(nb, 4);
2881 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2882 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2883 return;
2884 }
2885 gen_set_access_type(ctx, ACCESS_INT);
2886 t0 = tcg_temp_new();
2887 gen_addr_register(ctx, t0);
2888 t1 = tcg_const_i32(nb);
2889 t2 = tcg_const_i32(start);
2890 gen_helper_lsw(cpu_env, t0, t1, t2);
2891 tcg_temp_free(t0);
2892 tcg_temp_free_i32(t1);
2893 tcg_temp_free_i32(t2);
2894 }
2895
2896 /* lswx */
2897 static void gen_lswx(DisasContext *ctx)
2898 {
2899 TCGv t0;
2900 TCGv_i32 t1, t2, t3;
2901
2902 if (ctx->le_mode) {
2903 gen_align_no_le(ctx);
2904 return;
2905 }
2906 gen_set_access_type(ctx, ACCESS_INT);
2907 t0 = tcg_temp_new();
2908 gen_addr_reg_index(ctx, t0);
2909 t1 = tcg_const_i32(rD(ctx->opcode));
2910 t2 = tcg_const_i32(rA(ctx->opcode));
2911 t3 = tcg_const_i32(rB(ctx->opcode));
2912 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2913 tcg_temp_free(t0);
2914 tcg_temp_free_i32(t1);
2915 tcg_temp_free_i32(t2);
2916 tcg_temp_free_i32(t3);
2917 }
2918
2919 /* stswi */
2920 static void gen_stswi(DisasContext *ctx)
2921 {
2922 TCGv t0;
2923 TCGv_i32 t1, t2;
2924 int nb = NB(ctx->opcode);
2925
2926 if (ctx->le_mode) {
2927 gen_align_no_le(ctx);
2928 return;
2929 }
2930 gen_set_access_type(ctx, ACCESS_INT);
2931 t0 = tcg_temp_new();
2932 gen_addr_register(ctx, t0);
2933 if (nb == 0)
2934 nb = 32;
2935 t1 = tcg_const_i32(nb);
2936 t2 = tcg_const_i32(rS(ctx->opcode));
2937 gen_helper_stsw(cpu_env, t0, t1, t2);
2938 tcg_temp_free(t0);
2939 tcg_temp_free_i32(t1);
2940 tcg_temp_free_i32(t2);
2941 }
2942
2943 /* stswx */
2944 static void gen_stswx(DisasContext *ctx)
2945 {
2946 TCGv t0;
2947 TCGv_i32 t1, t2;
2948
2949 if (ctx->le_mode) {
2950 gen_align_no_le(ctx);
2951 return;
2952 }
2953 gen_set_access_type(ctx, ACCESS_INT);
2954 t0 = tcg_temp_new();
2955 gen_addr_reg_index(ctx, t0);
2956 t1 = tcg_temp_new_i32();
2957 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2958 tcg_gen_andi_i32(t1, t1, 0x7F);
2959 t2 = tcg_const_i32(rS(ctx->opcode));
2960 gen_helper_stsw(cpu_env, t0, t1, t2);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 tcg_temp_free_i32(t2);
2964 }
2965
2966 /*** Memory synchronisation ***/
2967 /* eieio */
2968 static void gen_eieio(DisasContext *ctx)
2969 {
2970 TCGBar bar = TCG_MO_LD_ST;
2971
2972 /*
2973 * POWER9 has a eieio instruction variant using bit 6 as a hint to
2974 * tell the CPU it is a store-forwarding barrier.
2975 */
2976 if (ctx->opcode & 0x2000000) {
2977 /*
2978 * ISA says that "Reserved fields in instructions are ignored
2979 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
2980 * as this is not an instruction software should be using,
2981 * complain to the user.
2982 */
2983 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
2984 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
2985 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
2986 } else {
2987 bar = TCG_MO_ST_LD;
2988 }
2989 }
2990
2991 tcg_gen_mb(bar | TCG_BAR_SC);
2992 }
2993
2994 #if !defined(CONFIG_USER_ONLY)
2995 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
2996 {
2997 TCGv_i32 t;
2998 TCGLabel *l;
2999
3000 if (!ctx->lazy_tlb_flush) {
3001 return;
3002 }
3003 l = gen_new_label();
3004 t = tcg_temp_new_i32();
3005 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3006 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3007 if (global) {
3008 gen_helper_check_tlb_flush_global(cpu_env);
3009 } else {
3010 gen_helper_check_tlb_flush_local(cpu_env);
3011 }
3012 gen_set_label(l);
3013 tcg_temp_free_i32(t);
3014 }
3015 #else
3016 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3017 #endif
3018
3019 /* isync */
3020 static void gen_isync(DisasContext *ctx)
3021 {
3022 /*
3023 * We need to check for a pending TLB flush. This can only happen in
3024 * kernel mode however so check MSR_PR
3025 */
3026 if (!ctx->pr) {
3027 gen_check_tlb_flush(ctx, false);
3028 }
3029 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3030 gen_stop_exception(ctx);
3031 }
3032
3033 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3034
3035 #define LARX(name, memop) \
3036 static void gen_##name(DisasContext *ctx) \
3037 { \
3038 TCGv t0; \
3039 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3040 int len = MEMOP_GET_SIZE(memop); \
3041 gen_set_access_type(ctx, ACCESS_RES); \
3042 t0 = tcg_temp_local_new(); \
3043 gen_addr_reg_index(ctx, t0); \
3044 if ((len) > 1) { \
3045 gen_check_align(ctx, t0, (len)-1); \
3046 } \
3047 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
3048 tcg_gen_mov_tl(cpu_reserve, t0); \
3049 tcg_gen_mov_tl(cpu_reserve_val, gpr); \
3050 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
3051 tcg_temp_free(t0); \
3052 }
3053
3054 /* lwarx */
3055 LARX(lbarx, DEF_MEMOP(MO_UB))
3056 LARX(lharx, DEF_MEMOP(MO_UW))
3057 LARX(lwarx, DEF_MEMOP(MO_UL))
3058
3059 #define LD_ATOMIC(name, memop, tp, op, eop) \
3060 static void gen_##name(DisasContext *ctx) \
3061 { \
3062 int len = MEMOP_GET_SIZE(memop); \
3063 uint32_t gpr_FC = FC(ctx->opcode); \
3064 TCGv EA = tcg_temp_local_new(); \
3065 TCGv_##tp t0, t1; \
3066 \
3067 gen_addr_register(ctx, EA); \
3068 if (len > 1) { \
3069 gen_check_align(ctx, EA, len - 1); \
3070 } \
3071 t0 = tcg_temp_new_##tp(); \
3072 t1 = tcg_temp_new_##tp(); \
3073 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3074 \
3075 switch (gpr_FC) { \
3076 case 0: /* Fetch and add */ \
3077 tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3078 break; \
3079 case 1: /* Fetch and xor */ \
3080 tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3081 break; \
3082 case 2: /* Fetch and or */ \
3083 tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3084 break; \
3085 case 3: /* Fetch and 'and' */ \
3086 tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3087 break; \
3088 case 8: /* Swap */ \
3089 tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3090 break; \
3091 case 4: /* Fetch and max unsigned */ \
3092 case 5: /* Fetch and max signed */ \
3093 case 6: /* Fetch and min unsigned */ \
3094 case 7: /* Fetch and min signed */ \
3095 case 16: /* compare and swap not equal */ \
3096 case 24: /* Fetch and increment bounded */ \
3097 case 25: /* Fetch and increment equal */ \
3098 case 28: /* Fetch and decrement bounded */ \
3099 gen_invalid(ctx); \
3100 break; \
3101 default: \
3102 /* invoke data storage error handler */ \
3103 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3104 } \
3105 tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
3106 tcg_temp_free_##tp(t0); \
3107 tcg_temp_free_##tp(t1); \
3108 tcg_temp_free(EA); \
3109 }
3110
3111 LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
3112 #if defined(TARGET_PPC64)
3113 LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
3114 #endif
3115
3116 #define ST_ATOMIC(name, memop, tp, op) \
3117 static void gen_##name(DisasContext *ctx) \
3118 { \
3119 int len = MEMOP_GET_SIZE(memop); \
3120 uint32_t gpr_FC = FC(ctx->opcode); \
3121 TCGv EA = tcg_temp_local_new(); \
3122 TCGv_##tp t0, t1; \
3123 \
3124 gen_addr_register(ctx, EA); \
3125 if (len > 1) { \
3126 gen_check_align(ctx, EA, len - 1); \
3127 } \
3128 t0 = tcg_temp_new_##tp(); \
3129 t1 = tcg_temp_new_##tp(); \
3130 tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
3131 \
3132 switch (gpr_FC) { \
3133 case 0: /* add and Store */ \
3134 tcg_gen_atomic_add_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3135 break; \
3136 case 1: /* xor and Store */ \
3137 tcg_gen_atomic_xor_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3138 break; \
3139 case 2: /* Or and Store */ \
3140 tcg_gen_atomic_or_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3141 break; \
3142 case 3: /* 'and' and Store */ \
3143 tcg_gen_atomic_and_fetch_##tp(t1, EA, t0, ctx->mem_idx, memop); \
3144 break; \
3145 case 4: /* Store max unsigned */ \
3146 case 5: /* Store max signed */ \
3147 case 6: /* Store min unsigned */ \
3148 case 7: /* Store min signed */ \
3149 case 24: /* Store twin */ \
3150 gen_invalid(ctx); \
3151 break; \
3152 default: \
3153 /* invoke data storage error handler */ \
3154 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
3155 } \
3156 tcg_temp_free_##tp(t0); \
3157 tcg_temp_free_##tp(t1); \
3158 tcg_temp_free(EA); \
3159 }
3160
3161 ST_ATOMIC(stwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32)
3162 #if defined(TARGET_PPC64)
3163 ST_ATOMIC(stdat, DEF_MEMOP(MO_Q), i64, mov_i64)
3164 #endif
3165
3166 #if defined(CONFIG_USER_ONLY)
3167 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3168 int reg, int memop)
3169 {
3170 TCGv t0 = tcg_temp_new();
3171
3172 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3173 tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
3174 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3175 tcg_temp_free(t0);
3176 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3177 }
3178 #else
3179 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3180 int reg, int memop)
3181 {
3182 TCGLabel *l1 = gen_new_label();
3183 TCGLabel *l2 = gen_new_label();
3184 TCGv t0;
3185
3186 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3187
3188 t0 = tcg_temp_new();
3189 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3190 cpu_gpr[reg], ctx->mem_idx,
3191 DEF_MEMOP(memop) | MO_ALIGN);
3192 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3193 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3194 tcg_gen_or_tl(t0, t0, cpu_so);
3195 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3196 tcg_temp_free(t0);
3197 tcg_gen_br(l2);
3198
3199 gen_set_label(l1);
3200
3201 /* Address mismatch implies failure. But we still need to provide the
3202 memory barrier semantics of the instruction. */
3203 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3204 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3205
3206 gen_set_label(l2);
3207 tcg_gen_movi_tl(cpu_reserve, -1);
3208 }
3209 #endif
3210
3211 #define STCX(name, memop) \
3212 static void gen_##name(DisasContext *ctx) \
3213 { \
3214 TCGv t0; \
3215 int len = MEMOP_GET_SIZE(memop); \
3216 gen_set_access_type(ctx, ACCESS_RES); \
3217 t0 = tcg_temp_local_new(); \
3218 gen_addr_reg_index(ctx, t0); \
3219 if (len > 1) { \
3220 gen_check_align(ctx, t0, (len) - 1); \
3221 } \
3222 gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
3223 tcg_temp_free(t0); \
3224 }
3225
3226 STCX(stbcx_, DEF_MEMOP(MO_UB))
3227 STCX(sthcx_, DEF_MEMOP(MO_UW))
3228 STCX(stwcx_, DEF_MEMOP(MO_UL))
3229
3230 #if defined(TARGET_PPC64)
3231 /* ldarx */
3232 LARX(ldarx, DEF_MEMOP(MO_Q))
3233 /* stdcx. */
3234 STCX(stdcx_, DEF_MEMOP(MO_Q))
3235
3236 /* lqarx */
3237 static void gen_lqarx(DisasContext *ctx)
3238 {
3239 TCGv EA;
3240 int rd = rD(ctx->opcode);
3241 TCGv gpr1, gpr2;
3242
3243 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3244 (rd == rB(ctx->opcode)))) {
3245 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3246 return;
3247 }
3248
3249 gen_set_access_type(ctx, ACCESS_RES);
3250 EA = tcg_temp_local_new();
3251 gen_addr_reg_index(ctx, EA);
3252 gen_check_align(ctx, EA, 15);
3253 if (unlikely(ctx->le_mode)) {
3254 gpr1 = cpu_gpr[rd+1];
3255 gpr2 = cpu_gpr[rd];
3256 } else {
3257 gpr1 = cpu_gpr[rd];
3258 gpr2 = cpu_gpr[rd+1];
3259 }
3260 tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3261 tcg_gen_mov_tl(cpu_reserve, EA);
3262 gen_addr_add(ctx, EA, EA, 8);
3263 tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3264
3265 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3266 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3267 tcg_temp_free(EA);
3268 }
3269
3270 /* stqcx. */
3271 static void gen_stqcx_(DisasContext *ctx)
3272 {
3273 TCGv EA;
3274 int reg = rS(ctx->opcode);
3275 int len = 16;
3276 #if !defined(CONFIG_USER_ONLY)
3277 TCGLabel *l1;
3278 TCGv gpr1, gpr2;
3279 #endif
3280
3281 if (unlikely((rD(ctx->opcode) & 1))) {
3282 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3283 return;
3284 }
3285 gen_set_access_type(ctx, ACCESS_RES);
3286 EA = tcg_temp_local_new();
3287 gen_addr_reg_index(ctx, EA);
3288 if (len > 1) {
3289 gen_check_align(ctx, EA, (len) - 1);
3290 }
3291
3292 #if defined(CONFIG_USER_ONLY)
3293 gen_conditional_store(ctx, EA, reg, 16);
3294 #else
3295 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3296 l1 = gen_new_label();
3297 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3298 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3299
3300 if (unlikely(ctx->le_mode)) {
3301 gpr1 = cpu_gpr[reg + 1];
3302 gpr2 = cpu_gpr[reg];
3303 } else {
3304 gpr1 = cpu_gpr[reg];
3305 gpr2 = cpu_gpr[reg + 1];
3306 }
3307 tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3308 gen_addr_add(ctx, EA, EA, 8);
3309 tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q));
3310
3311 gen_set_label(l1);
3312 tcg_gen_movi_tl(cpu_reserve, -1);
3313 #endif
3314 tcg_temp_free(EA);
3315 }
3316
3317 #endif /* defined(TARGET_PPC64) */
3318
3319 /* sync */
3320 static void gen_sync(DisasContext *ctx)
3321 {
3322 uint32_t l = (ctx->opcode >> 21) & 3;
3323
3324 /*
3325 * We may need to check for a pending TLB flush.
3326 *
3327 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3328 *
3329 * Additionally, this can only happen in kernel mode however so
3330 * check MSR_PR as well.
3331 */
3332 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3333 gen_check_tlb_flush(ctx, true);
3334 }
3335 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3336 }
3337
3338 /* wait */
3339 static void gen_wait(DisasContext *ctx)
3340 {
3341 TCGv_i32 t0 = tcg_const_i32(1);
3342 tcg_gen_st_i32(t0, cpu_env,
3343 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3344 tcg_temp_free_i32(t0);
3345 /* Stop translation, as the CPU is supposed to sleep from now */
3346 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3347 }
3348
3349 #if defined(TARGET_PPC64)
3350 static void gen_doze(DisasContext *ctx)
3351 {
3352 #if defined(CONFIG_USER_ONLY)
3353 GEN_PRIV;
3354 #else
3355 TCGv_i32 t;
3356
3357 CHK_HV;
3358 t = tcg_const_i32(PPC_PM_DOZE);
3359 gen_helper_pminsn(cpu_env, t);
3360 tcg_temp_free_i32(t);
3361 gen_stop_exception(ctx);
3362 #endif /* defined(CONFIG_USER_ONLY) */
3363 }
3364
3365 static void gen_nap(DisasContext *ctx)
3366 {
3367 #if defined(CONFIG_USER_ONLY)
3368 GEN_PRIV;
3369 #else
3370 TCGv_i32 t;
3371
3372 CHK_HV;
3373 t = tcg_const_i32(PPC_PM_NAP);
3374 gen_helper_pminsn(cpu_env, t);
3375 tcg_temp_free_i32(t);
3376 gen_stop_exception(ctx);
3377 #endif /* defined(CONFIG_USER_ONLY) */
3378 }
3379
3380 static void gen_stop(DisasContext *ctx)
3381 {
3382 gen_nap(ctx);
3383 }
3384
3385 static void gen_sleep(DisasContext *ctx)
3386 {
3387 #if defined(CONFIG_USER_ONLY)
3388 GEN_PRIV;
3389 #else
3390 TCGv_i32 t;
3391
3392 CHK_HV;
3393 t = tcg_const_i32(PPC_PM_SLEEP);
3394 gen_helper_pminsn(cpu_env, t);
3395 tcg_temp_free_i32(t);
3396 gen_stop_exception(ctx);
3397 #endif /* defined(CONFIG_USER_ONLY) */
3398 }
3399
3400 static void gen_rvwinkle(DisasContext *ctx)
3401 {
3402 #if defined(CONFIG_USER_ONLY)
3403 GEN_PRIV;
3404 #else
3405 TCGv_i32 t;
3406
3407 CHK_HV;
3408 t = tcg_const_i32(PPC_PM_RVWINKLE);
3409 gen_helper_pminsn(cpu_env, t);
3410 tcg_temp_free_i32(t);
3411 gen_stop_exception(ctx);
3412 #endif /* defined(CONFIG_USER_ONLY) */
3413 }
3414 #endif /* #if defined(TARGET_PPC64) */
3415
3416 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3417 {
3418 #if defined(TARGET_PPC64)
3419 if (ctx->has_cfar)
3420 tcg_gen_movi_tl(cpu_cfar, nip);
3421 #endif
3422 }
3423
3424 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3425 {
3426 if (unlikely(ctx->singlestep_enabled)) {
3427 return false;
3428 }
3429
3430 #ifndef CONFIG_USER_ONLY
3431 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3432 #else
3433 return true;
3434 #endif
3435 }
3436
3437 /*** Branch ***/
3438 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3439 {
3440 if (NARROW_MODE(ctx)) {
3441 dest = (uint32_t) dest;
3442 }
3443 if (use_goto_tb(ctx, dest)) {
3444 tcg_gen_goto_tb(n);
3445 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3446 tcg_gen_exit_tb(ctx->base.tb, n);
3447 } else {
3448 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3449 if (unlikely(ctx->singlestep_enabled)) {
3450 if ((ctx->singlestep_enabled &
3451 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3452 (ctx->exception == POWERPC_EXCP_BRANCH ||
3453 ctx->exception == POWERPC_EXCP_TRACE)) {
3454 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3455 }
3456 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3457 gen_debug_exception(ctx);
3458 }
3459 }
3460 tcg_gen_lookup_and_goto_ptr();
3461 }
3462 }
3463
3464 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3465 {
3466 if (NARROW_MODE(ctx)) {
3467 nip = (uint32_t)nip;
3468 }
3469 tcg_gen_movi_tl(cpu_lr, nip);
3470 }
3471
3472 /* b ba bl bla */
3473 static void gen_b(DisasContext *ctx)
3474 {
3475 target_ulong li, target;
3476
3477 ctx->exception = POWERPC_EXCP_BRANCH;
3478 /* sign extend LI */
3479 li = LI(ctx->opcode);
3480 li = (li ^ 0x02000000) - 0x02000000;
3481 if (likely(AA(ctx->opcode) == 0)) {
3482 target = ctx->base.pc_next + li - 4;
3483 } else {
3484 target = li;
3485 }
3486 if (LK(ctx->opcode)) {
3487 gen_setlr(ctx, ctx->base.pc_next);
3488 }
3489 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3490 gen_goto_tb(ctx, 0, target);
3491 }
3492
3493 #define BCOND_IM 0
3494 #define BCOND_LR 1
3495 #define BCOND_CTR 2
3496 #define BCOND_TAR 3
3497
3498 static void gen_bcond(DisasContext *ctx, int type)
3499 {
3500 uint32_t bo = BO(ctx->opcode);
3501 TCGLabel *l1;
3502 TCGv target;
3503
3504 ctx->exception = POWERPC_EXCP_BRANCH;
3505 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3506 target = tcg_temp_local_new();
3507 if (type == BCOND_CTR)
3508 tcg_gen_mov_tl(target, cpu_ctr);
3509 else if (type == BCOND_TAR)
3510 gen_load_spr(target, SPR_TAR);
3511 else
3512 tcg_gen_mov_tl(target, cpu_lr);
3513 } else {
3514 target = NULL;
3515 }
3516 if (LK(ctx->opcode))
3517 gen_setlr(ctx, ctx->base.pc_next);
3518 l1 = gen_new_label();
3519 if ((bo & 0x4) == 0) {
3520 /* Decrement and test CTR */
3521 TCGv temp = tcg_temp_new();
3522 if (unlikely(type == BCOND_CTR)) {
3523 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3524 return;
3525 }
3526 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3527 if (NARROW_MODE(ctx)) {
3528 tcg_gen_ext32u_tl(temp, cpu_ctr);
3529 } else {
3530 tcg_gen_mov_tl(temp, cpu_ctr);
3531 }
3532 if (bo & 0x2) {
3533 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3534 } else {
3535 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3536 }
3537 tcg_temp_free(temp);
3538 }
3539 if ((bo & 0x10) == 0) {
3540 /* Test CR */
3541 uint32_t bi = BI(ctx->opcode);
3542 uint32_t mask = 0x08 >> (bi & 0x03);
3543 TCGv_i32 temp = tcg_temp_new_i32();
3544
3545 if (bo & 0x8) {
3546 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3547 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3548 } else {
3549 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3550 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3551 }
3552 tcg_temp_free_i32(temp);
3553 }
3554 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3555 if (type == BCOND_IM) {
3556 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3557 if (likely(AA(ctx->opcode) == 0)) {
3558 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3559 } else {
3560 gen_goto_tb(ctx, 0, li);
3561 }
3562 } else {
3563 if (NARROW_MODE(ctx)) {
3564 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3565 } else {
3566 tcg_gen_andi_tl(cpu_nip, target, ~3);
3567 }
3568 tcg_gen_lookup_and_goto_ptr();
3569 tcg_temp_free(target);
3570 }
3571 if ((bo & 0x14) != 0x14) {
3572 gen_set_label(l1);
3573 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3574 }
3575 }
3576
3577 static void gen_bc(DisasContext *ctx)
3578 {
3579 gen_bcond(ctx, BCOND_IM);
3580 }
3581
3582 static void gen_bcctr(DisasContext *ctx)
3583 {
3584 gen_bcond(ctx, BCOND_CTR);
3585 }
3586
3587 static void gen_bclr(DisasContext *ctx)
3588 {
3589 gen_bcond(ctx, BCOND_LR);
3590 }
3591
3592 static void gen_bctar(DisasContext *ctx)
3593 {
3594 gen_bcond(ctx, BCOND_TAR);
3595 }
3596
3597 /*** Condition register logical ***/
3598 #define GEN_CRLOGIC(name, tcg_op, opc) \
3599 static void glue(gen_, name)(DisasContext *ctx) \
3600 { \
3601 uint8_t bitmask; \
3602 int sh; \
3603 TCGv_i32 t0, t1; \
3604 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3605 t0 = tcg_temp_new_i32(); \
3606 if (sh > 0) \
3607 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3608 else if (sh < 0) \
3609 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3610 else \
3611 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3612 t1 = tcg_temp_new_i32(); \
3613 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3614 if (sh > 0) \
3615 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3616 else if (sh < 0) \
3617 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3618 else \
3619 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3620 tcg_op(t0, t0, t1); \
3621 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3622 tcg_gen_andi_i32(t0, t0, bitmask); \
3623 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3624 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3625 tcg_temp_free_i32(t0); \
3626 tcg_temp_free_i32(t1); \
3627 }
3628
3629 /* crand */
3630 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3631 /* crandc */
3632 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3633 /* creqv */
3634 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3635 /* crnand */
3636 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3637 /* crnor */
3638 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3639 /* cror */
3640 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3641 /* crorc */
3642 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3643 /* crxor */
3644 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3645
3646 /* mcrf */
3647 static void gen_mcrf(DisasContext *ctx)
3648 {
3649 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3650 }
3651
3652 /*** System linkage ***/
3653
3654 /* rfi (supervisor only) */
3655 static void gen_rfi(DisasContext *ctx)
3656 {
3657 #if defined(CONFIG_USER_ONLY)
3658 GEN_PRIV;
3659 #else
3660 /* This instruction doesn't exist anymore on 64-bit server
3661 * processors compliant with arch 2.x
3662 */
3663 if (ctx->insns_flags & PPC_SEGMENT_64B) {
3664 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3665 return;
3666 }
3667 /* Restore CPU state */
3668 CHK_SV;
3669 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3670 gen_helper_rfi(cpu_env);
3671 gen_sync_exception(ctx);
3672 #endif
3673 }
3674
3675 #if defined(TARGET_PPC64)
3676 static void gen_rfid(DisasContext *ctx)
3677 {
3678 #if defined(CONFIG_USER_ONLY)
3679 GEN_PRIV;
3680 #else
3681 /* Restore CPU state */
3682 CHK_SV;
3683 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3684 gen_helper_rfid(cpu_env);
3685 gen_sync_exception(ctx);
3686 #endif
3687 }
3688
3689 static void gen_hrfid(DisasContext *ctx)
3690 {
3691 #if defined(CONFIG_USER_ONLY)
3692 GEN_PRIV;
3693 #else
3694 /* Restore CPU state */
3695 CHK_HV;
3696 gen_helper_hrfid(cpu_env);
3697 gen_sync_exception(ctx);
3698 #endif
3699 }
3700 #endif
3701
3702 /* sc */
3703 #if defined(CONFIG_USER_ONLY)
3704 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3705 #else
3706 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3707 #endif
3708 static void gen_sc(DisasContext *ctx)
3709 {
3710 uint32_t lev;
3711
3712 lev = (ctx->opcode >> 5) & 0x7F;
3713 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3714 }
3715
3716 /*** Trap ***/
3717
3718 /* Check for unconditional traps (always or never) */
3719 static bool check_unconditional_trap(DisasContext *ctx)
3720 {
3721 /* Trap never */
3722 if (TO(ctx->opcode) == 0) {
3723 return true;
3724 }
3725 /* Trap always */
3726 if (TO(ctx->opcode) == 31) {
3727 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3728 return true;
3729 }
3730 return false;
3731 }
3732
3733 /* tw */
3734 static void gen_tw(DisasContext *ctx)
3735 {
3736 TCGv_i32 t0;
3737
3738 if (check_unconditional_trap(ctx)) {
3739 return;
3740 }
3741 t0 = tcg_const_i32(TO(ctx->opcode));
3742 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3743 t0);
3744 tcg_temp_free_i32(t0);
3745 }
3746
3747 /* twi */
3748 static void gen_twi(DisasContext *ctx)
3749 {
3750 TCGv t0;
3751 TCGv_i32 t1;
3752
3753 if (check_unconditional_trap(ctx)) {
3754 return;
3755 }
3756 t0 = tcg_const_tl(SIMM(ctx->opcode));
3757 t1 = tcg_const_i32(TO(ctx->opcode));
3758 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3759 tcg_temp_free(t0);
3760 tcg_temp_free_i32(t1);
3761 }
3762
3763 #if defined(TARGET_PPC64)
3764 /* td */
3765 static void gen_td(DisasContext *ctx)
3766 {
3767 TCGv_i32 t0;
3768
3769 if (check_unconditional_trap(ctx)) {
3770 return;
3771 }
3772 t0 = tcg_const_i32(TO(ctx->opcode));
3773 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3774 t0);
3775 tcg_temp_free_i32(t0);
3776 }
3777
3778 /* tdi */
3779 static void gen_tdi(DisasContext *ctx)
3780 {
3781 TCGv t0;
3782 TCGv_i32 t1;
3783
3784 if (check_unconditional_trap(ctx)) {
3785 return;
3786 }
3787 t0 = tcg_const_tl(SIMM(ctx->opcode));
3788 t1 = tcg_const_i32(TO(ctx->opcode));
3789 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3790 tcg_temp_free(t0);
3791 tcg_temp_free_i32(t1);
3792 }
3793 #endif
3794
3795 /*** Processor control ***/
3796
3797 static void gen_read_xer(DisasContext *ctx, TCGv dst)
3798 {
3799 TCGv t0 = tcg_temp_new();
3800 TCGv t1 = tcg_temp_new();
3801 TCGv t2 = tcg_temp_new();
3802 tcg_gen_mov_tl(dst, cpu_xer);
3803 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3804 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3805 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3806 tcg_gen_or_tl(t0, t0, t1);
3807 tcg_gen_or_tl(dst, dst, t2);
3808 tcg_gen_or_tl(dst, dst, t0);
3809 if (is_isa300(ctx)) {
3810 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
3811 tcg_gen_or_tl(dst, dst, t0);
3812 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
3813 tcg_gen_or_tl(dst, dst, t0);
3814 }
3815 tcg_temp_free(t0);
3816 tcg_temp_free(t1);
3817 tcg_temp_free(t2);
3818 }
3819
3820 static void gen_write_xer(TCGv src)
3821 {
3822 /* Write all flags, while reading back check for isa300 */
3823 tcg_gen_andi_tl(cpu_xer, src,
3824 ~((1u << XER_SO) |
3825 (1u << XER_OV) | (1u << XER_OV32) |
3826 (1u << XER_CA) | (1u << XER_CA32)));
3827 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
3828 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
3829 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
3830 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
3831 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
3832 }
3833
3834 /* mcrxr */
3835 static void gen_mcrxr(DisasContext *ctx)
3836 {
3837 TCGv_i32 t0 = tcg_temp_new_i32();
3838 TCGv_i32 t1 = tcg_temp_new_i32();
3839 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3840
3841 tcg_gen_trunc_tl_i32(t0, cpu_so);
3842 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3843 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3844 tcg_gen_shli_i32(t0, t0, 3);
3845 tcg_gen_shli_i32(t1, t1, 2);
3846 tcg_gen_shli_i32(dst, dst, 1);
3847 tcg_gen_or_i32(dst, dst, t0);
3848 tcg_gen_or_i32(dst, dst, t1);
3849 tcg_temp_free_i32(t0);
3850 tcg_temp_free_i32(t1);
3851
3852 tcg_gen_movi_tl(cpu_so, 0);
3853 tcg_gen_movi_tl(cpu_ov, 0);
3854 tcg_gen_movi_tl(cpu_ca, 0);
3855 }
3856
3857 #ifdef TARGET_PPC64
3858 /* mcrxrx */
3859 static void gen_mcrxrx(DisasContext *ctx)
3860 {
3861 TCGv t0 = tcg_temp_new();
3862 TCGv t1 = tcg_temp_new();
3863 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3864
3865 /* copy OV and OV32 */
3866 tcg_gen_shli_tl(t0, cpu_ov, 1);
3867 tcg_gen_or_tl(t0, t0, cpu_ov32);
3868 tcg_gen_shli_tl(t0, t0, 2);
3869 /* copy CA and CA32 */
3870 tcg_gen_shli_tl(t1, cpu_ca, 1);
3871 tcg_gen_or_tl(t1, t1, cpu_ca32);
3872 tcg_gen_or_tl(t0, t0, t1);
3873 tcg_gen_trunc_tl_i32(dst, t0);
3874 tcg_temp_free(t0);
3875 tcg_temp_free(t1);
3876 }
3877 #endif
3878
3879 /* mfcr mfocrf */
3880 static void gen_mfcr(DisasContext *ctx)
3881 {
3882 uint32_t crm, crn;
3883
3884 if (likely(ctx->opcode & 0x00100000)) {
3885 crm = CRM(ctx->opcode);
3886 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3887 crn = ctz32 (crm);
3888 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3889 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3890 cpu_gpr[rD(ctx->opcode)], crn * 4);
3891 }
3892 } else {
3893 TCGv_i32 t0 = tcg_temp_new_i32();
3894 tcg_gen_mov_i32(t0, cpu_crf[0]);
3895 tcg_gen_shli_i32(t0, t0, 4);
3896 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3897 tcg_gen_shli_i32(t0, t0, 4);
3898 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3899 tcg_gen_shli_i32(t0, t0, 4);
3900 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3901 tcg_gen_shli_i32(t0, t0, 4);
3902 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3903 tcg_gen_shli_i32(t0, t0, 4);
3904 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3905 tcg_gen_shli_i32(t0, t0, 4);
3906 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3907 tcg_gen_shli_i32(t0, t0, 4);
3908 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3909 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3910 tcg_temp_free_i32(t0);
3911 }
3912 }
3913
3914 /* mfmsr */
3915 static void gen_mfmsr(DisasContext *ctx)
3916 {
3917 CHK_SV;
3918 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3919 }
3920
3921 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3922 {
3923 #if 0
3924 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3925 printf("ERROR: try to access SPR %d !\n", sprn);
3926 #endif
3927 }
3928 #define SPR_NOACCESS (&spr_noaccess)
3929
3930 /* mfspr */
3931 static inline void gen_op_mfspr(DisasContext *ctx)
3932 {
3933 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3934 uint32_t sprn = SPR(ctx->opcode);
3935
3936 #if defined(CONFIG_USER_ONLY)
3937 read_cb = ctx->spr_cb[sprn].uea_read;
3938 #else
3939 if (ctx->pr) {
3940 read_cb = ctx->spr_cb[sprn].uea_read;
3941 } else if (ctx->hv) {
3942 read_cb = ctx->spr_cb[sprn].hea_read;
3943 } else {
3944 read_cb = ctx->spr_cb[sprn].oea_read;
3945 }
3946 #endif
3947 if (likely(read_cb != NULL)) {
3948 if (likely(read_cb != SPR_NOACCESS)) {
3949 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3950 } else {
3951 /* Privilege exception */
3952 /* This is a hack to avoid warnings when running Linux:
3953 * this OS breaks the PowerPC virtualisation model,
3954 * allowing userland application to read the PVR
3955 */
3956 if (sprn != SPR_PVR) {
3957 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
3958 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
3959 ctx->base.pc_next - 4);
3960 }
3961 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3962 }
3963 } else {
3964 /* ISA 2.07 defines these as no-ops */
3965 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3966 (sprn >= 808 && sprn <= 811)) {
3967 /* This is a nop */
3968 return;
3969 }
3970 /* Not defined */
3971 qemu_log_mask(LOG_GUEST_ERROR,
3972 "Trying to read invalid spr %d (0x%03x) at "
3973 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
3974
3975 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3976 * it can generate a priv, a hv emu or a no-op
3977 */
3978 if (sprn & 0x10) {
3979 if (ctx->pr) {
3980 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3981 }
3982 } else {
3983 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3984 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3985 }
3986 }
3987 }
3988 }
3989
3990 static void gen_mfspr(DisasContext *ctx)
3991 {
3992 gen_op_mfspr(ctx);
3993 }
3994
3995 /* mftb */
3996 static void gen_mftb(DisasContext *ctx)
3997 {
3998 gen_op_mfspr(ctx);
3999 }
4000
4001 /* mtcrf mtocrf*/
4002 static void gen_mtcrf(DisasContext *ctx)
4003 {
4004 uint32_t crm, crn;
4005
4006 crm = CRM(ctx->opcode);
4007 if (likely((ctx->opcode & 0x00100000))) {
4008 if (crm && ((crm & (crm - 1)) == 0)) {
4009 TCGv_i32 temp = tcg_temp_new_i32();
4010 crn = ctz32 (crm);
4011 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4012 tcg_gen_shri_i32(temp, temp, crn * 4);
4013 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4014 tcg_temp_free_i32(temp);
4015 }
4016 } else {
4017 TCGv_i32 temp = tcg_temp_new_i32();
4018 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4019 for (crn = 0 ; crn < 8 ; crn++) {
4020 if (crm & (1 << crn)) {
4021 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4022 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4023 }
4024 }
4025 tcg_temp_free_i32(temp);
4026 }
4027 }
4028
4029 /* mtmsr */
4030 #if defined(TARGET_PPC64)
4031 static void gen_mtmsrd(DisasContext *ctx)
4032 {
4033 CHK_SV;
4034
4035 #if !defined(CONFIG_USER_ONLY)
4036 if (ctx->opcode & 0x00010000) {
4037 /* Special form that does not need any synchronisation */
4038 TCGv t0 = tcg_temp_new();
4039 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4040 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4041 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4042 tcg_temp_free(t0);
4043 } else {
4044 /* XXX: we need to update nip before the store
4045 * if we enter power saving mode, we will exit the loop
4046 * directly from ppc_store_msr
4047 */
4048 gen_update_nip(ctx, ctx->base.pc_next);
4049 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4050 /* Must stop the translation as machine state (may have) changed */
4051 /* Note that mtmsr is not always defined as context-synchronizing */
4052 gen_stop_exception(ctx);
4053 }
4054 #endif /* !defined(CONFIG_USER_ONLY) */
4055 }
4056 #endif /* defined(TARGET_PPC64) */
4057
4058 static void gen_mtmsr(DisasContext *ctx)
4059 {
4060 CHK_SV;
4061
4062 #if !defined(CONFIG_USER_ONLY)
4063 if (ctx->opcode & 0x00010000) {
4064 /* Special form that does not need any synchronisation */
4065 TCGv t0 = tcg_temp_new();
4066 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4067 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4068 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4069 tcg_temp_free(t0);
4070 } else {
4071 TCGv msr = tcg_temp_new();
4072
4073 /* XXX: we need to update nip before the store
4074 * if we enter power saving mode, we will exit the loop
4075 * directly from ppc_store_msr
4076 */
4077 gen_update_nip(ctx, ctx->base.pc_next);
4078 #if defined(TARGET_PPC64)
4079 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4080 #else
4081 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4082 #endif
4083 gen_helper_store_msr(cpu_env, msr);
4084 tcg_temp_free(msr);
4085 /* Must stop the translation as machine state (may have) changed */
4086 /* Note that mtmsr is not always defined as context-synchronizing */
4087 gen_stop_exception(ctx);
4088 }
4089 #endif
4090 }
4091
4092 /* mtspr */
4093 static void gen_mtspr(DisasContext *ctx)
4094 {
4095 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4096 uint32_t sprn = SPR(ctx->opcode);
4097
4098 #if defined(CONFIG_USER_ONLY)
4099 write_cb = ctx->spr_cb[sprn].uea_write;
4100 #else
4101 if (ctx->pr) {
4102 write_cb = ctx->spr_cb[sprn].uea_write;
4103 } else if (ctx->hv) {
4104 write_cb = ctx->spr_cb[sprn].hea_write;
4105 } else {
4106 write_cb = ctx->spr_cb[sprn].oea_write;
4107 }
4108 #endif
4109 if (likely(write_cb != NULL)) {
4110 if (likely(write_cb != SPR_NOACCESS)) {
4111 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4112 } else {
4113 /* Privilege exception */
4114 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4115 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4116 ctx->base.pc_next - 4);
4117 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4118 }
4119 } else {
4120 /* ISA 2.07 defines these as no-ops */
4121 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4122 (sprn >= 808 && sprn <= 811)) {
4123 /* This is a nop */
4124 return;
4125 }
4126
4127 /* Not defined */
4128 qemu_log_mask(LOG_GUEST_ERROR,
4129 "Trying to write invalid spr %d (0x%03x) at "
4130 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4131
4132
4133 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4134 * it can generate a priv, a hv emu or a no-op
4135 */
4136 if (sprn & 0x10) {
4137 if (ctx->pr) {
4138 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4139 }
4140 } else {
4141 if (ctx->pr || sprn == 0) {
4142 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4143 }
4144 }
4145 }
4146 }
4147
4148 #if defined(TARGET_PPC64)
4149 /* setb */
4150 static void gen_setb(DisasContext *ctx)
4151 {
4152 TCGv_i32 t0 = tcg_temp_new_i32();
4153 TCGv_i32 t8 = tcg_temp_new_i32();
4154 TCGv_i32 tm1 = tcg_temp_new_i32();
4155 int crf = crfS(ctx->opcode);
4156
4157 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4158 tcg_gen_movi_i32(t8, 8);
4159 tcg_gen_movi_i32(tm1, -1);
4160 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4161 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4162
4163 tcg_temp_free_i32(t0);
4164 tcg_temp_free_i32(t8);
4165 tcg_temp_free_i32(tm1);
4166 }
4167 #endif
4168
4169 /*** Cache management ***/
4170
4171 /* dcbf */
4172 static void gen_dcbf(DisasContext *ctx)
4173 {
4174 /* XXX: specification says this is treated as a load by the MMU */
4175 TCGv t0;
4176 gen_set_access_type(ctx, ACCESS_CACHE);
4177 t0 = tcg_temp_new();
4178 gen_addr_reg_index(ctx, t0);
4179 gen_qemu_ld8u(ctx, t0, t0);
4180 tcg_temp_free(t0);
4181 }
4182
4183 /* dcbi (Supervisor only) */
4184 static void gen_dcbi(DisasContext *ctx)
4185 {
4186 #if defined(CONFIG_USER_ONLY)
4187 GEN_PRIV;
4188 #else
4189 TCGv EA, val;
4190
4191 CHK_SV;
4192 EA = tcg_temp_new();
4193 gen_set_access_type(ctx, ACCESS_CACHE);
4194 gen_addr_reg_index(ctx, EA);
4195 val = tcg_temp_new();
4196 /* XXX: specification says this should be treated as a store by the MMU */
4197 gen_qemu_ld8u(ctx, val, EA);
4198 gen_qemu_st8(ctx, val, EA);
4199 tcg_temp_free(val);
4200 tcg_temp_free(EA);
4201 #endif /* defined(CONFIG_USER_ONLY) */
4202 }
4203
4204 /* dcdst */
4205 static void gen_dcbst(DisasContext *ctx)
4206 {
4207 /* XXX: specification say this is treated as a load by the MMU */
4208 TCGv t0;
4209 gen_set_access_type(ctx, ACCESS_CACHE);
4210 t0 = tcg_temp_new();
4211 gen_addr_reg_index(ctx, t0);
4212 gen_qemu_ld8u(ctx, t0, t0);
4213 tcg_temp_free(t0);
4214 }
4215
4216 /* dcbt */
4217 static void gen_dcbt(DisasContext *ctx)
4218 {
4219 /* interpreted as no-op */
4220 /* XXX: specification say this is treated as a load by the MMU
4221 * but does not generate any exception
4222 */
4223 }
4224
4225 /* dcbtst */
4226 static void gen_dcbtst(DisasContext *ctx)
4227 {
4228 /* interpreted as no-op */
4229 /* XXX: specification say this is treated as a load by the MMU
4230 * but does not generate any exception
4231 */
4232 }
4233
4234 /* dcbtls */
4235 static void gen_dcbtls(DisasContext *ctx)
4236 {
4237 /* Always fails locking the cache */
4238 TCGv t0 = tcg_temp_new();
4239 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4240 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4241 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4242 tcg_temp_free(t0);
4243 }
4244
4245 /* dcbz */
4246 static void gen_dcbz(DisasContext *ctx)
4247 {
4248 TCGv tcgv_addr;
4249 TCGv_i32 tcgv_op;
4250
4251 gen_set_access_type(ctx, ACCESS_CACHE);
4252 tcgv_addr = tcg_temp_new();
4253 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4254 gen_addr_reg_index(ctx, tcgv_addr);
4255 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4256 tcg_temp_free(tcgv_addr);
4257 tcg_temp_free_i32(tcgv_op);
4258 }
4259
4260 /* dst / dstt */
4261 static void gen_dst(DisasContext *ctx)
4262 {
4263 if (rA(ctx->opcode) == 0) {
4264 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4265 } else {
4266 /* interpreted as no-op */
4267 }
4268 }
4269
4270 /* dstst /dststt */
4271 static void gen_dstst(DisasContext *ctx)
4272 {
4273 if (rA(ctx->opcode) == 0) {
4274 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4275 } else {
4276 /* interpreted as no-op */
4277 }
4278
4279 }
4280
4281 /* dss / dssall */
4282 static void gen_dss(DisasContext *ctx)
4283 {
4284 /* interpreted as no-op */
4285 }
4286
4287 /* icbi */
4288 static void gen_icbi(DisasContext *ctx)
4289 {
4290 TCGv t0;
4291 gen_set_access_type(ctx, ACCESS_CACHE);
4292 t0 = tcg_temp_new();
4293 gen_addr_reg_index(ctx, t0);
4294 gen_helper_icbi(cpu_env, t0);
4295 tcg_temp_free(t0);
4296 }
4297
4298 /* Optional: */
4299 /* dcba */
4300 static void gen_dcba(DisasContext *ctx)
4301 {
4302 /* interpreted as no-op */
4303 /* XXX: specification say this is treated as a store by the MMU
4304 * but does not generate any exception
4305 */
4306 }
4307
4308 /*** Segment register manipulation ***/
4309 /* Supervisor only: */
4310
4311 /* mfsr */
4312 static void gen_mfsr(DisasContext *ctx)
4313 {
4314 #if defined(CONFIG_USER_ONLY)
4315 GEN_PRIV;
4316 #else
4317 TCGv t0;
4318
4319 CHK_SV;
4320 t0 = tcg_const_tl(SR(ctx->opcode));
4321 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4322 tcg_temp_free(t0);
4323 #endif /* defined(CONFIG_USER_ONLY) */
4324 }
4325
4326 /* mfsrin */
4327 static void gen_mfsrin(DisasContext *ctx)
4328 {
4329 #if defined(CONFIG_USER_ONLY)
4330 GEN_PRIV;
4331 #else
4332 TCGv t0;
4333
4334 CHK_SV;
4335 t0 = tcg_temp_new();
4336 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4337 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4338 tcg_temp_free(t0);
4339 #endif /* defined(CONFIG_USER_ONLY) */
4340 }
4341
4342 /* mtsr */
4343 static void gen_mtsr(DisasContext *ctx)
4344 {
4345 #if defined(CONFIG_USER_ONLY)
4346 GEN_PRIV;
4347 #else
4348 TCGv t0;
4349
4350 CHK_SV;
4351 t0 = tcg_const_tl(SR(ctx->opcode));
4352 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4353 tcg_temp_free(t0);
4354 #endif /* defined(CONFIG_USER_ONLY) */
4355 }
4356
4357 /* mtsrin */
4358 static void gen_mtsrin(DisasContext *ctx)
4359 {
4360 #if defined(CONFIG_USER_ONLY)
4361 GEN_PRIV;
4362 #else
4363 TCGv t0;
4364 CHK_SV;
4365
4366 t0 = tcg_temp_new();
4367 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4368 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4369 tcg_temp_free(t0);
4370 #endif /* defined(CONFIG_USER_ONLY) */
4371 }
4372
4373 #if defined(TARGET_PPC64)
4374 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4375
4376 /* mfsr */
4377 static void gen_mfsr_64b(DisasContext *ctx)
4378 {
4379 #if defined(CONFIG_USER_ONLY)
4380 GEN_PRIV;
4381 #else
4382 TCGv t0;
4383
4384 CHK_SV;
4385 t0 = tcg_const_tl(SR(ctx->opcode));
4386 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4387 tcg_temp_free(t0);
4388 #endif /* defined(CONFIG_USER_ONLY) */
4389 }
4390
4391 /* mfsrin */
4392 static void gen_mfsrin_64b(DisasContext *ctx)
4393 {
4394 #if defined(CONFIG_USER_ONLY)
4395 GEN_PRIV;
4396 #else
4397 TCGv t0;
4398
4399 CHK_SV;
4400 t0 = tcg_temp_new();
4401 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4402 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4403 tcg_temp_free(t0);
4404 #endif /* defined(CONFIG_USER_ONLY) */
4405 }
4406
4407 /* mtsr */
4408 static void gen_mtsr_64b(DisasContext *ctx)
4409 {
4410 #if defined(CONFIG_USER_ONLY)
4411 GEN_PRIV;
4412 #else
4413 TCGv t0;
4414
4415 CHK_SV;
4416 t0 = tcg_const_tl(SR(ctx->opcode));
4417 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4418 tcg_temp_free(t0);
4419 #endif /* defined(CONFIG_USER_ONLY) */
4420 }
4421
4422 /* mtsrin */
4423 static void gen_mtsrin_64b(DisasContext *ctx)
4424 {
4425 #if defined(CONFIG_USER_ONLY)
4426 GEN_PRIV;
4427 #else
4428 TCGv t0;
4429
4430 CHK_SV;
4431 t0 = tcg_temp_new();
4432 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4433 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4434 tcg_temp_free(t0);
4435 #endif /* defined(CONFIG_USER_ONLY) */
4436 }
4437
4438 /* slbmte */
4439 static void gen_slbmte(DisasContext *ctx)
4440 {
4441 #if defined(CONFIG_USER_ONLY)
4442 GEN_PRIV;
4443 #else
4444 CHK_SV;
4445
4446 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4447 cpu_gpr[rS(ctx->opcode)]);
4448 #endif /* defined(CONFIG_USER_ONLY) */
4449 }
4450
4451 static void gen_slbmfee(DisasContext *ctx)
4452 {
4453 #if defined(CONFIG_USER_ONLY)
4454 GEN_PRIV;
4455 #else
4456 CHK_SV;
4457
4458 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4459 cpu_gpr[rB(ctx->opcode)]);
4460 #endif /* defined(CONFIG_USER_ONLY) */
4461 }
4462
4463 static void gen_slbmfev(DisasContext *ctx)
4464 {
4465 #if defined(CONFIG_USER_ONLY)
4466 GEN_PRIV;
4467 #else
4468 CHK_SV;
4469
4470 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4471 cpu_gpr[rB(ctx->opcode)]);
4472 #endif /* defined(CONFIG_USER_ONLY) */
4473 }
4474
4475 static void gen_slbfee_(DisasContext *ctx)
4476 {
4477 #if defined(CONFIG_USER_ONLY)
4478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4479 #else
4480 TCGLabel *l1, *l2;
4481
4482 if (unlikely(ctx->pr)) {
4483 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4484 return;
4485 }
4486 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4487 cpu_gpr[rB(ctx->opcode)]);
4488 l1 = gen_new_label();
4489 l2 = gen_new_label();
4490 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4491 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4492 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4493 tcg_gen_br(l2);
4494 gen_set_label(l1);
4495 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4496 gen_set_label(l2);
4497 #endif
4498 }
4499 #endif /* defined(TARGET_PPC64) */
4500
4501 /*** Lookaside buffer management ***/
4502 /* Optional & supervisor only: */
4503
4504 /* tlbia */
4505 static void gen_tlbia(DisasContext *ctx)
4506 {
4507 #if defined(CONFIG_USER_ONLY)
4508 GEN_PRIV;
4509 #else
4510 CHK_HV;
4511
4512 gen_helper_tlbia(cpu_env);
4513 #endif /* defined(CONFIG_USER_ONLY) */
4514 }
4515
4516 /* tlbiel */
4517 static void gen_tlbiel(DisasContext *ctx)
4518 {
4519 #if defined(CONFIG_USER_ONLY)
4520 GEN_PRIV;
4521 #else
4522 CHK_SV;
4523
4524 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4525 #endif /* defined(CONFIG_USER_ONLY) */
4526 }
4527
4528 /* tlbie */
4529 static void gen_tlbie(DisasContext *ctx)
4530 {
4531 #if defined(CONFIG_USER_ONLY)
4532 GEN_PRIV;
4533 #else
4534 TCGv_i32 t1;
4535
4536 if (ctx->gtse) {
4537 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4538 } else {
4539 CHK_HV; /* Else hypervisor privileged */
4540 }
4541
4542 if (NARROW_MODE(ctx)) {
4543 TCGv t0 = tcg_temp_new();
4544 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4545 gen_helper_tlbie(cpu_env, t0);
4546 tcg_temp_free(t0);
4547 } else {
4548 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4549 }
4550 t1 = tcg_temp_new_i32();
4551 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4552 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4553 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4554 tcg_temp_free_i32(t1);
4555 #endif /* defined(CONFIG_USER_ONLY) */
4556 }
4557
4558 /* tlbsync */
4559 static void gen_tlbsync(DisasContext *ctx)
4560 {
4561 #if defined(CONFIG_USER_ONLY)
4562 GEN_PRIV;
4563 #else
4564
4565 if (ctx->gtse) {
4566 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4567 } else {
4568 CHK_HV; /* Else hypervisor privileged */
4569 }
4570
4571 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4572 if (ctx->insns_flags & PPC_BOOKE) {
4573 gen_check_tlb_flush(ctx, true);
4574 }
4575 #endif /* defined(CONFIG_USER_ONLY) */
4576 }
4577
4578 #if defined(TARGET_PPC64)
4579 /* slbia */
4580 static void gen_slbia(DisasContext *ctx)
4581 {
4582 #if defined(CONFIG_USER_ONLY)
4583 GEN_PRIV;
4584 #else
4585 CHK_SV;
4586
4587 gen_helper_slbia(cpu_env);
4588 #endif /* defined(CONFIG_USER_ONLY) */
4589 }
4590
4591 /* slbie */
4592 static void gen_slbie(DisasContext *ctx)
4593 {
4594 #if defined(CONFIG_USER_ONLY)
4595 GEN_PRIV;
4596 #else
4597 CHK_SV;
4598
4599 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4600 #endif /* defined(CONFIG_USER_ONLY) */
4601 }
4602
4603 /* slbieg */
4604 static void gen_slbieg(DisasContext *ctx)
4605 {
4606 #if defined(CONFIG_USER_ONLY)
4607 GEN_PRIV;
4608 #else
4609 CHK_SV;
4610
4611 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4612 #endif /* defined(CONFIG_USER_ONLY) */
4613 }
4614
4615 /* slbsync */
4616 static void gen_slbsync(DisasContext *ctx)
4617 {
4618 #if defined(CONFIG_USER_ONLY)
4619 GEN_PRIV;
4620 #else
4621 CHK_SV;
4622 gen_check_tlb_flush(ctx, true);
4623 #endif /* defined(CONFIG_USER_ONLY) */
4624 }
4625
4626 #endif /* defined(TARGET_PPC64) */
4627
4628 /*** External control ***/
4629 /* Optional: */
4630
4631 /* eciwx */
4632 static void gen_eciwx(DisasContext *ctx)
4633 {
4634 TCGv t0;
4635 /* Should check EAR[E] ! */
4636 gen_set_access_type(ctx, ACCESS_EXT);
4637 t0 = tcg_temp_new();
4638 gen_addr_reg_index(ctx, t0);
4639 gen_check_align(ctx, t0, 0x03);
4640 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4641 tcg_temp_free(t0);
4642 }
4643
4644 /* ecowx */
4645 static void gen_ecowx(DisasContext *ctx)
4646 {
4647 TCGv t0;
4648 /* Should check EAR[E] ! */
4649 gen_set_access_type(ctx, ACCESS_EXT);
4650 t0 = tcg_temp_new();
4651 gen_addr_reg_index(ctx, t0);
4652 gen_check_align(ctx, t0, 0x03);
4653 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4654 tcg_temp_free(t0);
4655 }
4656
4657 /* PowerPC 601 specific instructions */
4658
4659 /* abs - abs. */
4660 static void gen_abs(DisasContext *ctx)
4661 {
4662 TCGLabel *l1 = gen_new_label();
4663 TCGLabel *l2 = gen_new_label();
4664 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4665 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4666 tcg_gen_br(l2);
4667 gen_set_label(l1);
4668 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4669 gen_set_label(l2);
4670 if (unlikely(Rc(ctx->opcode) != 0))
4671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4672 }
4673
4674 /* abso - abso. */
4675 static void gen_abso(DisasContext *ctx)
4676 {
4677 TCGLabel *l1 = gen_new_label();
4678 TCGLabel *l2 = gen_new_label();
4679 TCGLabel *l3 = gen_new_label();
4680 /* Start with XER OV disabled, the most likely case */
4681 tcg_gen_movi_tl(cpu_ov, 0);
4682 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4683 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4684 tcg_gen_movi_tl(cpu_ov, 1);
4685 tcg_gen_movi_tl(cpu_so, 1);
4686 tcg_gen_br(l2);
4687 gen_set_label(l1);
4688 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4689 tcg_gen_br(l3);
4690 gen_set_label(l2);
4691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4692 gen_set_label(l3);
4693 if (unlikely(Rc(ctx->opcode) != 0))
4694 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4695 }
4696
4697 /* clcs */
4698 static void gen_clcs(DisasContext *ctx)
4699 {
4700 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4701 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4702 tcg_temp_free_i32(t0);
4703 /* Rc=1 sets CR0 to an undefined state */
4704 }
4705
4706 /* div - div. */
4707 static void gen_div(DisasContext *ctx)
4708 {
4709 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4710 cpu_gpr[rB(ctx->opcode)]);
4711 if (unlikely(Rc(ctx->opcode) != 0))
4712 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4713 }
4714
4715 /* divo - divo. */
4716 static void gen_divo(DisasContext *ctx)
4717 {
4718 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4719 cpu_gpr[rB(ctx->opcode)]);
4720 if (unlikely(Rc(ctx->opcode) != 0))
4721 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4722 }
4723
4724 /* divs - divs. */
4725 static void gen_divs(DisasContext *ctx)
4726 {
4727 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4728 cpu_gpr[rB(ctx->opcode)]);
4729 if (unlikely(Rc(ctx->opcode) != 0))
4730 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4731 }
4732
4733 /* divso - divso. */
4734 static void gen_divso(DisasContext *ctx)
4735 {
4736 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4737 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4738 if (unlikely(Rc(ctx->opcode) != 0))
4739 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4740 }
4741
4742 /* doz - doz. */
4743 static void gen_doz(DisasContext *ctx)
4744 {
4745 TCGLabel *l1 = gen_new_label();
4746 TCGLabel *l2 = gen_new_label();
4747 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4748 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4749 tcg_gen_br(l2);
4750 gen_set_label(l1);
4751 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4752 gen_set_label(l2);
4753 if (unlikely(Rc(ctx->opcode) != 0))
4754 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4755 }
4756
4757 /* dozo - dozo. */
4758 static void gen_dozo(DisasContext *ctx)
4759 {
4760 TCGLabel *l1 = gen_new_label();
4761 TCGLabel *l2 = gen_new_label();
4762 TCGv t0 = tcg_temp_new();
4763 TCGv t1 = tcg_temp_new();
4764 TCGv t2 = tcg_temp_new();
4765 /* Start with XER OV disabled, the most likely case */
4766 tcg_gen_movi_tl(cpu_ov, 0);
4767 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4768 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4769 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4770 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4771 tcg_gen_andc_tl(t1, t1, t2);
4772 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4773 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4774 tcg_gen_movi_tl(cpu_ov, 1);
4775 tcg_gen_movi_tl(cpu_so, 1);
4776 tcg_gen_br(l2);
4777 gen_set_label(l1);
4778 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4779 gen_set_label(l2);
4780 tcg_temp_free(t0);
4781 tcg_temp_free(t1);
4782 tcg_temp_free(t2);
4783 if (unlikely(Rc(ctx->opcode) != 0))
4784 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4785 }
4786
4787 /* dozi */
4788 static void gen_dozi(DisasContext *ctx)
4789 {
4790 target_long simm = SIMM(ctx->opcode);
4791 TCGLabel *l1 = gen_new_label();
4792 TCGLabel *l2 = gen_new_label();
4793 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4794 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4795 tcg_gen_br(l2);
4796 gen_set_label(l1);
4797 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4798 gen_set_label(l2);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4801 }
4802
4803 /* lscbx - lscbx. */
4804 static void gen_lscbx(DisasContext *ctx)
4805 {
4806 TCGv t0 = tcg_temp_new();
4807 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4808 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4809 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4810
4811 gen_addr_reg_index(ctx, t0);
4812 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4813 tcg_temp_free_i32(t1);
4814 tcg_temp_free_i32(t2);
4815 tcg_temp_free_i32(t3);
4816 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4817 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4818 if (unlikely(Rc(ctx->opcode) != 0))
4819 gen_set_Rc0(ctx, t0);
4820 tcg_temp_free(t0);
4821 }
4822
4823 /* maskg - maskg. */
4824 static void gen_maskg(DisasContext *ctx)
4825 {
4826 TCGLabel *l1 = gen_new_label();
4827 TCGv t0 = tcg_temp_new();
4828 TCGv t1 = tcg_temp_new();
4829 TCGv t2 = tcg_temp_new();
4830 TCGv t3 = tcg_temp_new();
4831 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4832 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4833 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4834 tcg_gen_addi_tl(t2, t0, 1);
4835 tcg_gen_shr_tl(t2, t3, t2);
4836 tcg_gen_shr_tl(t3, t3, t1);
4837 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4838 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4839 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4840 gen_set_label(l1);
4841 tcg_temp_free(t0);
4842 tcg_temp_free(t1);
4843 tcg_temp_free(t2);
4844 tcg_temp_free(t3);
4845 if (unlikely(Rc(ctx->opcode) != 0))
4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4847 }
4848
4849 /* maskir - maskir. */
4850 static void gen_maskir(DisasContext *ctx)
4851 {
4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4855 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4856 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4857 tcg_temp_free(t0);
4858 tcg_temp_free(t1);
4859 if (unlikely(Rc(ctx->opcode) != 0))
4860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4861 }
4862
4863 /* mul - mul. */
4864 static void gen_mul(DisasContext *ctx)
4865 {
4866 TCGv_i64 t0 = tcg_temp_new_i64();
4867 TCGv_i64 t1 = tcg_temp_new_i64();
4868 TCGv t2 = tcg_temp_new();
4869 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4870 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4871 tcg_gen_mul_i64(t0, t0, t1);
4872 tcg_gen_trunc_i64_tl(t2, t0);
4873 gen_store_spr(SPR_MQ, t2);
4874 tcg_gen_shri_i64(t1, t0, 32);
4875 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4876 tcg_temp_free_i64(t0);
4877 tcg_temp_free_i64(t1);
4878 tcg_temp_free(t2);
4879 if (unlikely(Rc(ctx->opcode) != 0))
4880 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4881 }
4882
4883 /* mulo - mulo. */
4884 static void gen_mulo(DisasContext *ctx)
4885 {
4886 TCGLabel *l1 = gen_new_label();
4887 TCGv_i64 t0 = tcg_temp_new_i64();
4888 TCGv_i64 t1 = tcg_temp_new_i64();
4889 TCGv t2 = tcg_temp_new();
4890 /* Start with XER OV disabled, the most likely case */
4891 tcg_gen_movi_tl(cpu_ov, 0);
4892 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4893 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4894 tcg_gen_mul_i64(t0, t0, t1);
4895 tcg_gen_trunc_i64_tl(t2, t0);
4896 gen_store_spr(SPR_MQ, t2);
4897 tcg_gen_shri_i64(t1, t0, 32);
4898 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4899 tcg_gen_ext32s_i64(t1, t0);
4900 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4901 tcg_gen_movi_tl(cpu_ov, 1);
4902 tcg_gen_movi_tl(cpu_so, 1);
4903 gen_set_label(l1);
4904 tcg_temp_free_i64(t0);
4905 tcg_temp_free_i64(t1);
4906 tcg_temp_free(t2);
4907 if (unlikely(Rc(ctx->opcode) != 0))
4908 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4909 }
4910
4911 /* nabs - nabs. */
4912 static void gen_nabs(DisasContext *ctx)
4913 {
4914 TCGLabel *l1 = gen_new_label();
4915 TCGLabel *l2 = gen_new_label();
4916 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4917 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4918 tcg_gen_br(l2);
4919 gen_set_label(l1);
4920 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4921 gen_set_label(l2);
4922 if (unlikely(Rc(ctx->opcode) != 0))
4923 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4924 }
4925
4926 /* nabso - nabso. */
4927 static void gen_nabso(DisasContext *ctx)
4928 {
4929 TCGLabel *l1 = gen_new_label();
4930 TCGLabel *l2 = gen_new_label();
4931 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4932 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4933 tcg_gen_br(l2);
4934 gen_set_label(l1);
4935 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4936 gen_set_label(l2);
4937 /* nabs never overflows */
4938 tcg_gen_movi_tl(cpu_ov, 0);
4939 if (unlikely(Rc(ctx->opcode) != 0))
4940 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4941 }
4942
4943 /* rlmi - rlmi. */
4944 static void gen_rlmi(DisasContext *ctx)
4945 {
4946 uint32_t mb = MB(ctx->opcode);
4947 uint32_t me = ME(ctx->opcode);
4948 TCGv t0 = tcg_temp_new();
4949 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4950 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4951 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4952 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4953 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4954 tcg_temp_free(t0);
4955 if (unlikely(Rc(ctx->opcode) != 0))
4956 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4957 }
4958
4959 /* rrib - rrib. */
4960 static void gen_rrib(DisasContext *ctx)
4961 {
4962 TCGv t0 = tcg_temp_new();
4963 TCGv t1 = tcg_temp_new();
4964 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4965 tcg_gen_movi_tl(t1, 0x80000000);
4966 tcg_gen_shr_tl(t1, t1, t0);
4967 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4968 tcg_gen_and_tl(t0, t0, t1);
4969 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4970 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4971 tcg_temp_free(t0);
4972 tcg_temp_free(t1);
4973 if (unlikely(Rc(ctx->opcode) != 0))
4974 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4975 }
4976
4977 /* sle - sle. */
4978 static void gen_sle(DisasContext *ctx)
4979 {
4980 TCGv t0 = tcg_temp_new();
4981 TCGv t1 = tcg_temp_new();
4982 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4983 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4984 tcg_gen_subfi_tl(t1, 32, t1);
4985 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4986 tcg_gen_or_tl(t1, t0, t1);
4987 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4988 gen_store_spr(SPR_MQ, t1);
4989 tcg_temp_free(t0);
4990 tcg_temp_free(t1);
4991 if (unlikely(Rc(ctx->opcode) != 0))
4992 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4993 }
4994
4995 /* sleq - sleq. */
4996 static void gen_sleq(DisasContext *ctx)
4997 {
4998 TCGv t0 = tcg_temp_new();
4999 TCGv t1 = tcg_temp_new();
5000 TCGv t2 = tcg_temp_new();
5001 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5002 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5003 tcg_gen_shl_tl(t2, t2, t0);
5004 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5005 gen_load_spr(t1, SPR_MQ);
5006 gen_store_spr(SPR_MQ, t0);
5007 tcg_gen_and_tl(t0, t0, t2);
5008 tcg_gen_andc_tl(t1, t1, t2);
5009 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5010 tcg_temp_free(t0);
5011 tcg_temp_free(t1);
5012 tcg_temp_free(t2);
5013 if (unlikely(Rc(ctx->opcode) != 0))
5014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5015 }
5016
5017 /* sliq - sliq. */
5018 static void gen_sliq(DisasContext *ctx)
5019 {
5020 int sh = SH(ctx->opcode);
5021 TCGv t0 = tcg_temp_new();
5022 TCGv t1 = tcg_temp_new();
5023 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5024 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5025 tcg_gen_or_tl(t1, t0, t1);
5026 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5027 gen_store_spr(SPR_MQ, t1);
5028 tcg_temp_free(t0);
5029 tcg_temp_free(t1);
5030 if (unlikely(Rc(ctx->opcode) != 0))
5031 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5032 }
5033
5034 /* slliq - slliq. */
5035 static void gen_slliq(DisasContext *ctx)
5036 {
5037 int sh = SH(ctx->opcode);
5038 TCGv t0 = tcg_temp_new();
5039 TCGv t1 = tcg_temp_new();
5040 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5041 gen_load_spr(t1, SPR_MQ);
5042 gen_store_spr(SPR_MQ, t0);
5043 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5044 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5045 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5046 tcg_temp_free(t0);
5047 tcg_temp_free(t1);
5048 if (unlikely(Rc(ctx->opcode) != 0))
5049 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5050 }
5051
5052 /* sllq - sllq. */
5053 static void gen_sllq(DisasContext *ctx)
5054 {
5055 TCGLabel *l1 = gen_new_label();
5056 TCGLabel *l2 = gen_new_label();
5057 TCGv t0 = tcg_temp_local_new();
5058 TCGv t1 = tcg_temp_local_new();
5059 TCGv t2 = tcg_temp_local_new();
5060 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5061 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5062 tcg_gen_shl_tl(t1, t1, t2);
5063 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5064 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5065 gen_load_spr(t0, SPR_MQ);
5066 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5067 tcg_gen_br(l2);
5068 gen_set_label(l1);
5069 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5070 gen_load_spr(t2, SPR_MQ);
5071 tcg_gen_andc_tl(t1, t2, t1);
5072 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5073 gen_set_label(l2);
5074 tcg_temp_free(t0);
5075 tcg_temp_free(t1);
5076 tcg_temp_free(t2);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5079 }
5080
5081 /* slq - slq. */
5082 static void gen_slq(DisasContext *ctx)
5083 {
5084 TCGLabel *l1 = gen_new_label();
5085 TCGv t0 = tcg_temp_new();
5086 TCGv t1 = tcg_temp_new();
5087 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5088 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5089 tcg_gen_subfi_tl(t1, 32, t1);
5090 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5091 tcg_gen_or_tl(t1, t0, t1);
5092 gen_store_spr(SPR_MQ, t1);
5093 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5094 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5095 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5096 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5097 gen_set_label(l1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
5100 if (unlikely(Rc(ctx->opcode) != 0))
5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5102 }
5103
5104 /* sraiq - sraiq. */
5105 static void gen_sraiq(DisasContext *ctx)
5106 {
5107 int sh = SH(ctx->opcode);
5108 TCGLabel *l1 = gen_new_label();
5109 TCGv t0 = tcg_temp_new();
5110 TCGv t1 = tcg_temp_new();
5111 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5112 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5113 tcg_gen_or_tl(t0, t0, t1);
5114 gen_store_spr(SPR_MQ, t0);
5115 tcg_gen_movi_tl(cpu_ca, 0);
5116 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5117 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5118 tcg_gen_movi_tl(cpu_ca, 1);
5119 gen_set_label(l1);
5120 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5121 tcg_temp_free(t0);
5122 tcg_temp_free(t1);
5123 if (unlikely(Rc(ctx->opcode) != 0))
5124 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5125 }
5126
5127 /* sraq - sraq. */
5128 static void gen_sraq(DisasContext *ctx)
5129 {
5130 TCGLabel *l1 = gen_new_label();
5131 TCGLabel *l2 = gen_new_label();
5132 TCGv t0 = tcg_temp_new();
5133 TCGv t1 = tcg_temp_local_new();
5134 TCGv t2 = tcg_temp_local_new();
5135 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5136 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5137 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5138 tcg_gen_subfi_tl(t2, 32, t2);
5139 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_or_tl(t0, t0, t2);
5141 gen_store_spr(SPR_MQ, t0);
5142 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5143 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5144 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5145 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5146 gen_set_label(l1);
5147 tcg_temp_free(t0);
5148 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5149 tcg_gen_movi_tl(cpu_ca, 0);
5150 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5151 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5152 tcg_gen_movi_tl(cpu_ca, 1);
5153 gen_set_label(l2);
5154 tcg_temp_free(t1);
5155 tcg_temp_free(t2);
5156 if (unlikely(Rc(ctx->opcode) != 0))
5157 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5158 }
5159
5160 /* sre - sre. */
5161 static void gen_sre(DisasContext *ctx)
5162 {
5163 TCGv t0 = tcg_temp_new();
5164 TCGv t1 = tcg_temp_new();
5165 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5166 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5167 tcg_gen_subfi_tl(t1, 32, t1);
5168 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5169 tcg_gen_or_tl(t1, t0, t1);
5170 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5171 gen_store_spr(SPR_MQ, t1);
5172 tcg_temp_free(t0);
5173 tcg_temp_free(t1);
5174 if (unlikely(Rc(ctx->opcode) != 0))
5175 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5176 }
5177
5178 /* srea - srea. */
5179 static void gen_srea(DisasContext *ctx)
5180 {
5181 TCGv t0 = tcg_temp_new();
5182 TCGv t1 = tcg_temp_new();
5183 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5184 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5185 gen_store_spr(SPR_MQ, t0);
5186 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5187 tcg_temp_free(t0);
5188 tcg_temp_free(t1);
5189 if (unlikely(Rc(ctx->opcode) != 0))
5190 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5191 }
5192
5193 /* sreq */
5194 static void gen_sreq(DisasContext *ctx)
5195 {
5196 TCGv t0 = tcg_temp_new();
5197 TCGv t1 = tcg_temp_new();
5198 TCGv t2 = tcg_temp_new();
5199 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5200 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5201 tcg_gen_shr_tl(t1, t1, t0);
5202 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5203 gen_load_spr(t2, SPR_MQ);
5204 gen_store_spr(SPR_MQ, t0);
5205 tcg_gen_and_tl(t0, t0, t1);
5206 tcg_gen_andc_tl(t2, t2, t1);
5207 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5208 tcg_temp_free(t0);
5209 tcg_temp_free(t1);
5210 tcg_temp_free(t2);
5211 if (unlikely(Rc(ctx->opcode) != 0))
5212 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5213 }
5214
5215 /* sriq */
5216 static void gen_sriq(DisasContext *ctx)
5217 {
5218 int sh = SH(ctx->opcode);
5219 TCGv t0 = tcg_temp_new();
5220 TCGv t1 = tcg_temp_new();
5221 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5222 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5223 tcg_gen_or_tl(t1, t0, t1);
5224 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5225 gen_store_spr(SPR_MQ, t1);
5226 tcg_temp_free(t0);
5227 tcg_temp_free(t1);
5228 if (unlikely(Rc(ctx->opcode) != 0))
5229 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5230 }
5231
5232 /* srliq */
5233 static void gen_srliq(DisasContext *ctx)
5234 {
5235 int sh = SH(ctx->opcode);
5236 TCGv t0 = tcg_temp_new();
5237 TCGv t1 = tcg_temp_new();
5238 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5239 gen_load_spr(t1, SPR_MQ);
5240 gen_store_spr(SPR_MQ, t0);
5241 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5242 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5243 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5244 tcg_temp_free(t0);
5245 tcg_temp_free(t1);
5246 if (unlikely(Rc(ctx->opcode) != 0))
5247 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5248 }
5249
5250 /* srlq */
5251 static void gen_srlq(DisasContext *ctx)
5252 {
5253 TCGLabel *l1 = gen_new_label();
5254 TCGLabel *l2 = gen_new_label();
5255 TCGv t0 = tcg_temp_local_new();
5256 TCGv t1 = tcg_temp_local_new();
5257 TCGv t2 = tcg_temp_local_new();
5258 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5259 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5260 tcg_gen_shr_tl(t2, t1, t2);
5261 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5262 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5263 gen_load_spr(t0, SPR_MQ);
5264 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5265 tcg_gen_br(l2);
5266 gen_set_label(l1);
5267 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5268 tcg_gen_and_tl(t0, t0, t2);
5269 gen_load_spr(t1, SPR_MQ);
5270 tcg_gen_andc_tl(t1, t1, t2);
5271 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5272 gen_set_label(l2);
5273 tcg_temp_free(t0);
5274 tcg_temp_free(t1);
5275 tcg_temp_free(t2);
5276 if (unlikely(Rc(ctx->opcode) != 0))
5277 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5278 }
5279
5280 /* srq */
5281 static void gen_srq(DisasContext *ctx)
5282 {
5283 TCGLabel *l1 = gen_new_label();
5284 TCGv t0 = tcg_temp_new();
5285 TCGv t1 = tcg_temp_new();
5286 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5287 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5288 tcg_gen_subfi_tl(t1, 32, t1);
5289 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5290 tcg_gen_or_tl(t1, t0, t1);
5291 gen_store_spr(SPR_MQ, t1);
5292 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5293 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5294 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5295 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5296 gen_set_label(l1);
5297 tcg_temp_free(t0);
5298 tcg_temp_free(t1);
5299 if (unlikely(Rc(ctx->opcode) != 0))
5300 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5301 }
5302
5303 /* PowerPC 602 specific instructions */
5304
5305 /* dsa */
5306 static void gen_dsa(DisasContext *ctx)
5307 {
5308 /* XXX: TODO */
5309 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5310 }
5311
5312 /* esa */
5313 static void gen_esa(DisasContext *ctx)
5314 {
5315 /* XXX: TODO */
5316 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5317 }
5318
5319 /* mfrom */
5320 static void gen_mfrom(DisasContext *ctx)
5321 {
5322 #if defined(CONFIG_USER_ONLY)
5323 GEN_PRIV;
5324 #else
5325 CHK_SV;
5326 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5327 #endif /* defined(CONFIG_USER_ONLY) */
5328 }
5329
5330 /* 602 - 603 - G2 TLB management */
5331
5332 /* tlbld */
5333 static void gen_tlbld_6xx(DisasContext *ctx)
5334 {
5335 #if defined(CONFIG_USER_ONLY)
5336 GEN_PRIV;
5337 #else
5338 CHK_SV;
5339 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5340 #endif /* defined(CONFIG_USER_ONLY) */
5341 }
5342
5343 /* tlbli */
5344 static void gen_tlbli_6xx(DisasContext *ctx)
5345 {
5346 #if defined(CONFIG_USER_ONLY)
5347 GEN_PRIV;
5348 #else
5349 CHK_SV;
5350 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5351 #endif /* defined(CONFIG_USER_ONLY) */
5352 }
5353
5354 /* 74xx TLB management */
5355
5356 /* tlbld */
5357 static void gen_tlbld_74xx(DisasContext *ctx)
5358 {
5359 #if defined(CONFIG_USER_ONLY)
5360 GEN_PRIV;
5361 #else
5362 CHK_SV;
5363 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5364 #endif /* defined(CONFIG_USER_ONLY) */
5365 }
5366
5367 /* tlbli */
5368 static void gen_tlbli_74xx(DisasContext *ctx)
5369 {
5370 #if defined(CONFIG_USER_ONLY)
5371 GEN_PRIV;
5372 #else
5373 CHK_SV;
5374 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5375 #endif /* defined(CONFIG_USER_ONLY) */
5376 }
5377
5378 /* POWER instructions not in PowerPC 601 */
5379
5380 /* clf */
5381 static void gen_clf(DisasContext *ctx)
5382 {
5383 /* Cache line flush: implemented as no-op */
5384 }
5385
5386 /* cli */
5387 static void gen_cli(DisasContext *ctx)
5388 {
5389 #if defined(CONFIG_USER_ONLY)
5390 GEN_PRIV;
5391 #else
5392 /* Cache line invalidate: privileged and treated as no-op */
5393 CHK_SV;
5394 #endif /* defined(CONFIG_USER_ONLY) */
5395 }
5396
5397 /* dclst */
5398 static void gen_dclst(DisasContext *ctx)
5399 {
5400 /* Data cache line store: treated as no-op */
5401 }
5402
5403 static void gen_mfsri(DisasContext *ctx)
5404 {
5405 #if defined(CONFIG_USER_ONLY)
5406 GEN_PRIV;
5407 #else
5408 int ra = rA(ctx->opcode);
5409 int rd = rD(ctx->opcode);
5410 TCGv t0;
5411
5412 CHK_SV;
5413 t0 = tcg_temp_new();
5414 gen_addr_reg_index(ctx, t0);
5415 tcg_gen_extract_tl(t0, t0, 28, 4);
5416 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5417 tcg_temp_free(t0);
5418 if (ra != 0 && ra != rd)
5419 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5420 #endif /* defined(CONFIG_USER_ONLY) */
5421 }
5422
5423 static void gen_rac(DisasContext *ctx)
5424 {
5425 #if defined(CONFIG_USER_ONLY)
5426 GEN_PRIV;
5427 #else
5428 TCGv t0;
5429
5430 CHK_SV;
5431 t0 = tcg_temp_new();
5432 gen_addr_reg_index(ctx, t0);
5433 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5434 tcg_temp_free(t0);
5435 #endif /* defined(CONFIG_USER_ONLY) */
5436 }
5437
5438 static void gen_rfsvc(DisasContext *ctx)
5439 {
5440 #if defined(CONFIG_USER_ONLY)
5441 GEN_PRIV;
5442 #else
5443 CHK_SV;
5444
5445 gen_helper_rfsvc(cpu_env);
5446 gen_sync_exception(ctx);
5447 #endif /* defined(CONFIG_USER_ONLY) */
5448 }
5449
5450 /* svc is not implemented for now */
5451
5452 /* BookE specific instructions */
5453
5454 /* XXX: not implemented on 440 ? */
5455 static void gen_mfapidi(DisasContext *ctx)
5456 {
5457 /* XXX: TODO */
5458 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5459 }
5460
5461 /* XXX: not implemented on 440 ? */
5462 static void gen_tlbiva(DisasContext *ctx)
5463 {
5464 #if defined(CONFIG_USER_ONLY)
5465 GEN_PRIV;
5466 #else
5467 TCGv t0;
5468
5469 CHK_SV;
5470 t0 = tcg_temp_new();
5471 gen_addr_reg_index(ctx, t0);
5472 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5473 tcg_temp_free(t0);
5474 #endif /* defined(CONFIG_USER_ONLY) */
5475 }
5476
5477 /* All 405 MAC instructions are translated here */
5478 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5479 int ra, int rb, int rt, int Rc)
5480 {
5481 TCGv t0, t1;
5482
5483 t0 = tcg_temp_local_new();
5484 t1 = tcg_temp_local_new();
5485
5486 switch (opc3 & 0x0D) {
5487 case 0x05:
5488 /* macchw - macchw. - macchwo - macchwo. */
5489 /* macchws - macchws. - macchwso - macchwso. */
5490 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5491 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5492 /* mulchw - mulchw. */
5493 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5494 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5495 tcg_gen_ext16s_tl(t1, t1);
5496 break;
5497 case 0x04:
5498 /* macchwu - macchwu. - macchwuo - macchwuo. */
5499 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5500 /* mulchwu - mulchwu. */
5501 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5502 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5503 tcg_gen_ext16u_tl(t1, t1);
5504 break;
5505 case 0x01:
5506 /* machhw - machhw. - machhwo - machhwo. */
5507 /* machhws - machhws. - machhwso - machhwso. */
5508 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5509 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5510 /* mulhhw - mulhhw. */
5511 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5512 tcg_gen_ext16s_tl(t0, t0);
5513 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5514 tcg_gen_ext16s_tl(t1, t1);
5515 break;
5516 case 0x00:
5517 /* machhwu - machhwu. - machhwuo - machhwuo. */
5518 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5519 /* mulhhwu - mulhhwu. */
5520 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5521 tcg_gen_ext16u_tl(t0, t0);
5522 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5523 tcg_gen_ext16u_tl(t1, t1);
5524 break;
5525 case 0x0D:
5526 /* maclhw - maclhw. - maclhwo - maclhwo. */
5527 /* maclhws - maclhws. - maclhwso - maclhwso. */
5528 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5529 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5530 /* mullhw - mullhw. */
5531 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5532 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5533 break;
5534 case 0x0C:
5535 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5536 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5537 /* mullhwu - mullhwu. */
5538 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5539 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5540 break;
5541 }
5542 if (opc2 & 0x04) {
5543 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5544 tcg_gen_mul_tl(t1, t0, t1);
5545 if (opc2 & 0x02) {
5546 /* nmultiply-and-accumulate (0x0E) */
5547 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5548 } else {
5549 /* multiply-and-accumulate (0x0C) */
5550 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5551 }
5552
5553 if (opc3 & 0x12) {
5554 /* Check overflow and/or saturate */
5555 TCGLabel *l1 = gen_new_label();
5556
5557 if (opc3 & 0x10) {
5558 /* Start with XER OV disabled, the most likely case */
5559 tcg_gen_movi_tl(cpu_ov, 0);
5560 }
5561 if (opc3 & 0x01) {
5562 /* Signed */
5563 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5564 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5565 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5566 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5567 if (opc3 & 0x02) {
5568 /* Saturate */
5569 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5570 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5571 }
5572 } else {
5573 /* Unsigned */
5574 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5575 if (opc3 & 0x02) {
5576 /* Saturate */
5577 tcg_gen_movi_tl(t0, UINT32_MAX);
5578 }
5579 }
5580 if (opc3 & 0x10) {
5581 /* Check overflow */
5582 tcg_gen_movi_tl(cpu_ov, 1);
5583 tcg_gen_movi_tl(cpu_so, 1);
5584 }
5585 gen_set_label(l1);
5586 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5587 }
5588 } else {
5589 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5590 }
5591 tcg_temp_free(t0);
5592 tcg_temp_free(t1);
5593 if (unlikely(Rc) != 0) {
5594 /* Update Rc0 */
5595 gen_set_Rc0(ctx, cpu_gpr[rt]);
5596 }
5597 }
5598
5599 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5600 static void glue(gen_, name)(DisasContext *ctx) \
5601 { \
5602 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5603 rD(ctx->opcode), Rc(ctx->opcode)); \
5604 }
5605
5606 /* macchw - macchw. */
5607 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5608 /* macchwo - macchwo. */
5609 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5610 /* macchws - macchws. */
5611 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5612 /* macchwso - macchwso. */
5613 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5614 /* macchwsu - macchwsu. */
5615 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5616 /* macchwsuo - macchwsuo. */
5617 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5618 /* macchwu - macchwu. */
5619 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5620 /* macchwuo - macchwuo. */
5621 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5622 /* machhw - machhw. */
5623 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5624 /* machhwo - machhwo. */
5625 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5626 /* machhws - machhws. */
5627 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5628 /* machhwso - machhwso. */
5629 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5630 /* machhwsu - machhwsu. */
5631 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5632 /* machhwsuo - machhwsuo. */
5633 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5634 /* machhwu - machhwu. */
5635 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5636 /* machhwuo - machhwuo. */
5637 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5638 /* maclhw - maclhw. */
5639 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5640 /* maclhwo - maclhwo. */
5641 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5642 /* maclhws - maclhws. */
5643 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5644 /* maclhwso - maclhwso. */
5645 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5646 /* maclhwu - maclhwu. */
5647 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5648 /* maclhwuo - maclhwuo. */
5649 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5650 /* maclhwsu - maclhwsu. */
5651 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5652 /* maclhwsuo - maclhwsuo. */
5653 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5654 /* nmacchw - nmacchw. */
5655 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5656 /* nmacchwo - nmacchwo. */
5657 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5658 /* nmacchws - nmacchws. */
5659 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5660 /* nmacchwso - nmacchwso. */
5661 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5662 /* nmachhw - nmachhw. */
5663 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5664 /* nmachhwo - nmachhwo. */
5665 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5666 /* nmachhws - nmachhws. */
5667 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5668 /* nmachhwso - nmachhwso. */
5669 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5670 /* nmaclhw - nmaclhw. */
5671 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5672 /* nmaclhwo - nmaclhwo. */
5673 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5674 /* nmaclhws - nmaclhws. */
5675 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5676 /* nmaclhwso - nmaclhwso. */
5677 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5678
5679 /* mulchw - mulchw. */
5680 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5681 /* mulchwu - mulchwu. */
5682 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5683 /* mulhhw - mulhhw. */
5684 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5685 /* mulhhwu - mulhhwu. */
5686 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5687 /* mullhw - mullhw. */
5688 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5689 /* mullhwu - mullhwu. */
5690 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5691
5692 /* mfdcr */
5693 static void gen_mfdcr(DisasContext *ctx)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 GEN_PRIV;
5697 #else
5698 TCGv dcrn;
5699
5700 CHK_SV;
5701 dcrn = tcg_const_tl(SPR(ctx->opcode));
5702 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5703 tcg_temp_free(dcrn);
5704 #endif /* defined(CONFIG_USER_ONLY) */
5705 }
5706
5707 /* mtdcr */
5708 static void gen_mtdcr(DisasContext *ctx)
5709 {
5710 #if defined(CONFIG_USER_ONLY)
5711 GEN_PRIV;
5712 #else
5713 TCGv dcrn;
5714
5715 CHK_SV;
5716 dcrn = tcg_const_tl(SPR(ctx->opcode));
5717 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5718 tcg_temp_free(dcrn);
5719 #endif /* defined(CONFIG_USER_ONLY) */
5720 }
5721
5722 /* mfdcrx */
5723 /* XXX: not implemented on 440 ? */
5724 static void gen_mfdcrx(DisasContext *ctx)
5725 {
5726 #if defined(CONFIG_USER_ONLY)
5727 GEN_PRIV;
5728 #else
5729 CHK_SV;
5730 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5731 cpu_gpr[rA(ctx->opcode)]);
5732 /* Note: Rc update flag set leads to undefined state of Rc0 */
5733 #endif /* defined(CONFIG_USER_ONLY) */
5734 }
5735
5736 /* mtdcrx */
5737 /* XXX: not implemented on 440 ? */
5738 static void gen_mtdcrx(DisasContext *ctx)
5739 {
5740 #if defined(CONFIG_USER_ONLY)
5741 GEN_PRIV;
5742 #else
5743 CHK_SV;
5744 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5745 cpu_gpr[rS(ctx->opcode)]);
5746 /* Note: Rc update flag set leads to undefined state of Rc0 */
5747 #endif /* defined(CONFIG_USER_ONLY) */
5748 }
5749
5750 /* mfdcrux (PPC 460) : user-mode access to DCR */
5751 static void gen_mfdcrux(DisasContext *ctx)
5752 {
5753 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5754 cpu_gpr[rA(ctx->opcode)]);
5755 /* Note: Rc update flag set leads to undefined state of Rc0 */
5756 }
5757
5758 /* mtdcrux (PPC 460) : user-mode access to DCR */
5759 static void gen_mtdcrux(DisasContext *ctx)
5760 {
5761 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5762 cpu_gpr[rS(ctx->opcode)]);
5763 /* Note: Rc update flag set leads to undefined state of Rc0 */
5764 }
5765
5766 /* dccci */
5767 static void gen_dccci(DisasContext *ctx)
5768 {
5769 CHK_SV;
5770 /* interpreted as no-op */
5771 }
5772
5773 /* dcread */
5774 static void gen_dcread(DisasContext *ctx)
5775 {
5776 #if defined(CONFIG_USER_ONLY)
5777 GEN_PRIV;
5778 #else
5779 TCGv EA, val;
5780
5781 CHK_SV;
5782 gen_set_access_type(ctx, ACCESS_CACHE);
5783 EA = tcg_temp_new();
5784 gen_addr_reg_index(ctx, EA);
5785 val = tcg_temp_new();
5786 gen_qemu_ld32u(ctx, val, EA);
5787 tcg_temp_free(val);
5788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5789 tcg_temp_free(EA);
5790 #endif /* defined(CONFIG_USER_ONLY) */
5791 }
5792
5793 /* icbt */
5794 static void gen_icbt_40x(DisasContext *ctx)
5795 {
5796 /* interpreted as no-op */
5797 /* XXX: specification say this is treated as a load by the MMU
5798 * but does not generate any exception
5799 */
5800 }
5801
5802 /* iccci */
5803 static void gen_iccci(DisasContext *ctx)
5804 {
5805 CHK_SV;
5806 /* interpreted as no-op */
5807 }
5808
5809 /* icread */
5810 static void gen_icread(DisasContext *ctx)
5811 {
5812 CHK_SV;
5813 /* interpreted as no-op */
5814 }
5815
5816 /* rfci (supervisor only) */
5817 static void gen_rfci_40x(DisasContext *ctx)
5818 {
5819 #if defined(CONFIG_USER_ONLY)
5820 GEN_PRIV;
5821 #else
5822 CHK_SV;
5823 /* Restore CPU state */
5824 gen_helper_40x_rfci(cpu_env);
5825 gen_sync_exception(ctx);
5826 #endif /* defined(CONFIG_USER_ONLY) */
5827 }
5828
5829 static void gen_rfci(DisasContext *ctx)
5830 {
5831 #if defined(CONFIG_USER_ONLY)
5832 GEN_PRIV;
5833 #else
5834 CHK_SV;
5835 /* Restore CPU state */
5836 gen_helper_rfci(cpu_env);
5837 gen_sync_exception(ctx);
5838 #endif /* defined(CONFIG_USER_ONLY) */
5839 }
5840
5841 /* BookE specific */
5842
5843 /* XXX: not implemented on 440 ? */
5844 static void gen_rfdi(DisasContext *ctx)
5845 {
5846 #if defined(CONFIG_USER_ONLY)
5847 GEN_PRIV;
5848 #else
5849 CHK_SV;
5850 /* Restore CPU state */
5851 gen_helper_rfdi(cpu_env);
5852 gen_sync_exception(ctx);
5853 #endif /* defined(CONFIG_USER_ONLY) */
5854 }
5855
5856 /* XXX: not implemented on 440 ? */
5857 static void gen_rfmci(DisasContext *ctx)
5858 {
5859 #if defined(CONFIG_USER_ONLY)
5860 GEN_PRIV;
5861 #else
5862 CHK_SV;
5863 /* Restore CPU state */
5864 gen_helper_rfmci(cpu_env);
5865 gen_sync_exception(ctx);
5866 #endif /* defined(CONFIG_USER_ONLY) */
5867 }
5868
5869 /* TLB management - PowerPC 405 implementation */
5870
5871 /* tlbre */
5872 static void gen_tlbre_40x(DisasContext *ctx)
5873 {
5874 #if defined(CONFIG_USER_ONLY)
5875 GEN_PRIV;
5876 #else
5877 CHK_SV;
5878 switch (rB(ctx->opcode)) {
5879 case 0:
5880 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5881 cpu_gpr[rA(ctx->opcode)]);
5882 break;
5883 case 1:
5884 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5885 cpu_gpr[rA(ctx->opcode)]);
5886 break;
5887 default:
5888 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5889 break;
5890 }
5891 #endif /* defined(CONFIG_USER_ONLY) */
5892 }
5893
5894 /* tlbsx - tlbsx. */
5895 static void gen_tlbsx_40x(DisasContext *ctx)
5896 {
5897 #if defined(CONFIG_USER_ONLY)
5898 GEN_PRIV;
5899 #else
5900 TCGv t0;
5901
5902 CHK_SV;
5903 t0 = tcg_temp_new();
5904 gen_addr_reg_index(ctx, t0);
5905 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5906 tcg_temp_free(t0);
5907 if (Rc(ctx->opcode)) {
5908 TCGLabel *l1 = gen_new_label();
5909 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5910 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5911 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5912 gen_set_label(l1);
5913 }
5914 #endif /* defined(CONFIG_USER_ONLY) */
5915 }
5916
5917 /* tlbwe */
5918 static void gen_tlbwe_40x(DisasContext *ctx)
5919 {
5920 #if defined(CONFIG_USER_ONLY)
5921 GEN_PRIV;
5922 #else
5923 CHK_SV;
5924
5925 switch (rB(ctx->opcode)) {
5926 case 0:
5927 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5928 cpu_gpr[rS(ctx->opcode)]);
5929 break;
5930 case 1:
5931 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5932 cpu_gpr[rS(ctx->opcode)]);
5933 break;
5934 default:
5935 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5936 break;
5937 }
5938 #endif /* defined(CONFIG_USER_ONLY) */
5939 }
5940
5941 /* TLB management - PowerPC 440 implementation */
5942
5943 /* tlbre */
5944 static void gen_tlbre_440(DisasContext *ctx)
5945 {
5946 #if defined(CONFIG_USER_ONLY)
5947 GEN_PRIV;
5948 #else
5949 CHK_SV;
5950
5951 switch (rB(ctx->opcode)) {
5952 case 0:
5953 case 1:
5954 case 2:
5955 {
5956 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5957 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5958 t0, cpu_gpr[rA(ctx->opcode)]);
5959 tcg_temp_free_i32(t0);
5960 }
5961 break;
5962 default:
5963 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5964 break;
5965 }
5966 #endif /* defined(CONFIG_USER_ONLY) */
5967 }
5968
5969 /* tlbsx - tlbsx. */
5970 static void gen_tlbsx_440(DisasContext *ctx)
5971 {
5972 #if defined(CONFIG_USER_ONLY)
5973 GEN_PRIV;
5974 #else
5975 TCGv t0;
5976
5977 CHK_SV;
5978 t0 = tcg_temp_new();
5979 gen_addr_reg_index(ctx, t0);
5980 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5981 tcg_temp_free(t0);
5982 if (Rc(ctx->opcode)) {
5983 TCGLabel *l1 = gen_new_label();
5984 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5985 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5986 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5987 gen_set_label(l1);
5988 }
5989 #endif /* defined(CONFIG_USER_ONLY) */
5990 }
5991
5992 /* tlbwe */
5993 static void gen_tlbwe_440(DisasContext *ctx)
5994 {
5995 #if defined(CONFIG_USER_ONLY)
5996 GEN_PRIV;
5997 #else
5998 CHK_SV;
5999 switch (rB(ctx->opcode)) {
6000 case 0:
6001 case 1:
6002 case 2:
6003 {
6004 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6005 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6006 cpu_gpr[rS(ctx->opcode)]);
6007 tcg_temp_free_i32(t0);
6008 }
6009 break;
6010 default:
6011 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6012 break;
6013 }
6014 #endif /* defined(CONFIG_USER_ONLY) */
6015 }
6016
6017 /* TLB management - PowerPC BookE 2.06 implementation */
6018
6019 /* tlbre */
6020 static void gen_tlbre_booke206(DisasContext *ctx)
6021 {
6022 #if defined(CONFIG_USER_ONLY)
6023 GEN_PRIV;
6024 #else
6025 CHK_SV;
6026 gen_helper_booke206_tlbre(cpu_env);
6027 #endif /* defined(CONFIG_USER_ONLY) */
6028 }
6029
6030 /* tlbsx - tlbsx. */
6031 static void gen_tlbsx_booke206(DisasContext *ctx)
6032 {
6033 #if defined(CONFIG_USER_ONLY)
6034 GEN_PRIV;
6035 #else
6036 TCGv t0;
6037
6038 CHK_SV;
6039 if (rA(ctx->opcode)) {
6040 t0 = tcg_temp_new();
6041 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6042 } else {
6043 t0 = tcg_const_tl(0);
6044 }
6045
6046 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6047 gen_helper_booke206_tlbsx(cpu_env, t0);
6048 tcg_temp_free(t0);
6049 #endif /* defined(CONFIG_USER_ONLY) */
6050 }
6051
6052 /* tlbwe */
6053 static void gen_tlbwe_booke206(DisasContext *ctx)
6054 {
6055 #if defined(CONFIG_USER_ONLY)
6056 GEN_PRIV;
6057 #else
6058 CHK_SV;
6059 gen_helper_booke206_tlbwe(cpu_env);
6060 #endif /* defined(CONFIG_USER_ONLY) */
6061 }
6062
6063 static void gen_tlbivax_booke206(DisasContext *ctx)
6064 {
6065 #if defined(CONFIG_USER_ONLY)
6066 GEN_PRIV;
6067 #else
6068 TCGv t0;
6069
6070 CHK_SV;
6071 t0 = tcg_temp_new();
6072 gen_addr_reg_index(ctx, t0);
6073 gen_helper_booke206_tlbivax(cpu_env, t0);
6074 tcg_temp_free(t0);
6075 #endif /* defined(CONFIG_USER_ONLY) */
6076 }
6077
6078 static void gen_tlbilx_booke206(DisasContext *ctx)
6079 {
6080 #if defined(CONFIG_USER_ONLY)
6081 GEN_PRIV;
6082 #else
6083 TCGv t0;
6084
6085 CHK_SV;
6086 t0 = tcg_temp_new();
6087 gen_addr_reg_index(ctx, t0);
6088
6089 switch((ctx->opcode >> 21) & 0x3) {
6090 case 0:
6091 gen_helper_booke206_tlbilx0(cpu_env, t0);
6092 break;
6093 case 1:
6094 gen_helper_booke206_tlbilx1(cpu_env, t0);
6095 break;
6096 case 3:
6097 gen_helper_booke206_tlbilx3(cpu_env, t0);
6098 break;
6099 default:
6100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6101 break;
6102 }
6103
6104 tcg_temp_free(t0);
6105 #endif /* defined(CONFIG_USER_ONLY) */
6106 }
6107
6108
6109 /* wrtee */
6110 static void gen_wrtee(DisasContext *ctx)
6111 {
6112 #if defined(CONFIG_USER_ONLY)
6113 GEN_PRIV;
6114 #else
6115 TCGv t0;
6116
6117 CHK_SV;
6118 t0 = tcg_temp_new();
6119 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6120 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6121 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6122 tcg_temp_free(t0);
6123 /* Stop translation to have a chance to raise an exception
6124 * if we just set msr_ee to 1
6125 */
6126 gen_stop_exception(ctx);
6127 #endif /* defined(CONFIG_USER_ONLY) */
6128 }
6129
6130 /* wrteei */
6131 static void gen_wrteei(DisasContext *ctx)
6132 {
6133 #if defined(CONFIG_USER_ONLY)
6134 GEN_PRIV;
6135 #else
6136 CHK_SV;
6137 if (ctx->opcode & 0x00008000) {
6138 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6139 /* Stop translation to have a chance to raise an exception */
6140 gen_stop_exception(ctx);
6141 } else {
6142 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6143 }
6144 #endif /* defined(CONFIG_USER_ONLY) */
6145 }
6146
6147 /* PowerPC 440 specific instructions */
6148
6149 /* dlmzb */
6150 static void gen_dlmzb(DisasContext *ctx)
6151 {
6152 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6153 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6154 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6155 tcg_temp_free_i32(t0);
6156 }
6157
6158 /* mbar replaces eieio on 440 */
6159 static void gen_mbar(DisasContext *ctx)
6160 {
6161 /* interpreted as no-op */
6162 }
6163
6164 /* msync replaces sync on 440 */
6165 static void gen_msync_4xx(DisasContext *ctx)
6166 {
6167 /* interpreted as no-op */
6168 }
6169
6170 /* icbt */
6171 static void gen_icbt_440(DisasContext *ctx)
6172 {
6173 /* interpreted as no-op */
6174 /* XXX: specification say this is treated as a load by the MMU
6175 * but does not generate any exception
6176 */
6177 }
6178
6179 /* Embedded.Processor Control */
6180
6181 static void gen_msgclr(DisasContext *ctx)
6182 {
6183 #if defined(CONFIG_USER_ONLY)
6184 GEN_PRIV;
6185 #else
6186 CHK_HV;
6187 /* 64-bit server processors compliant with arch 2.x */
6188 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6189 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6190 } else {
6191 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6192 }
6193 #endif /* defined(CONFIG_USER_ONLY) */
6194 }
6195
6196 static void gen_msgsnd(DisasContext *ctx)
6197 {
6198 #if defined(CONFIG_USER_ONLY)
6199 GEN_PRIV;
6200 #else
6201 CHK_HV;
6202 /* 64-bit server processors compliant with arch 2.x */
6203 if (ctx->insns_flags & PPC_SEGMENT_64B) {
6204 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6205 } else {
6206 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6207 }
6208 #endif /* defined(CONFIG_USER_ONLY) */
6209 }
6210
6211 static void gen_msgsync(DisasContext *ctx)
6212 {
6213 #if defined(CONFIG_USER_ONLY)
6214 GEN_PRIV;
6215 #else
6216 CHK_HV;
6217 #endif /* defined(CONFIG_USER_ONLY) */
6218 /* interpreted as no-op */
6219 }
6220
6221 #if defined(TARGET_PPC64)
6222 static void gen_maddld(DisasContext *ctx)
6223 {
6224 TCGv_i64 t1 = tcg_temp_new_i64();
6225
6226 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6227 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6228 tcg_temp_free_i64(t1);
6229 }
6230
6231 /* maddhd maddhdu */
6232 static void gen_maddhd_maddhdu(DisasContext *ctx)
6233 {
6234 TCGv_i64 lo = tcg_temp_new_i64();
6235 TCGv_i64 hi = tcg_temp_new_i64();
6236 TCGv_i64 t1 = tcg_temp_new_i64();
6237
6238 if (Rc(ctx->opcode)) {
6239 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6240 cpu_gpr[rB(ctx->opcode)]);
6241 tcg_gen_movi_i64(t1, 0);
6242 } else {
6243 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6244 cpu_gpr[rB(ctx->opcode)]);
6245 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6246 }
6247 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6248 cpu_gpr[rC(ctx->opcode)], t1);
6249 tcg_temp_free_i64(lo);
6250 tcg_temp_free_i64(hi);
6251 tcg_temp_free_i64(t1);
6252 }
6253 #endif /* defined(TARGET_PPC64) */
6254
6255 static void gen_tbegin(DisasContext *ctx)
6256 {
6257 if (unlikely(!ctx->tm_enabled)) {
6258 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6259 return;
6260 }
6261 gen_helper_tbegin(cpu_env);
6262 }
6263
6264 #define GEN_TM_NOOP(name) \
6265 static inline void gen_##name(DisasContext *ctx) \
6266 { \
6267 if (unlikely(!ctx->tm_enabled)) { \
6268 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6269 return; \
6270 } \
6271 /* Because tbegin always fails in QEMU, these user \
6272 * space instructions all have a simple implementation: \
6273 * \
6274 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6275 * = 0b0 || 0b00 || 0b0 \
6276 */ \
6277 tcg_gen_movi_i32(cpu_crf[0], 0); \
6278 }
6279
6280 GEN_TM_NOOP(tend);
6281 GEN_TM_NOOP(tabort);
6282 GEN_TM_NOOP(tabortwc);
6283 GEN_TM_NOOP(tabortwci);
6284 GEN_TM_NOOP(tabortdc);
6285 GEN_TM_NOOP(tabortdci);
6286 GEN_TM_NOOP(tsr);
6287 static inline void gen_cp_abort(DisasContext *ctx)
6288 {
6289 // Do Nothing
6290 }
6291
6292 #define GEN_CP_PASTE_NOOP(name) \
6293 static inline void gen_##name(DisasContext *ctx) \
6294 { \
6295 /* Generate invalid exception until \
6296 * we have an implementation of the copy \
6297 * paste facility \
6298 */ \
6299 gen_invalid(ctx); \
6300 }
6301
6302 GEN_CP_PASTE_NOOP(copy)
6303 GEN_CP_PASTE_NOOP(paste)
6304
6305 static void gen_tcheck(DisasContext *ctx)
6306 {
6307 if (unlikely(!ctx->tm_enabled)) {
6308 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6309 return;
6310 }
6311 /* Because tbegin always fails, the tcheck implementation
6312 * is simple:
6313 *
6314 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6315 * = 0b1 || 0b00 || 0b0
6316 */
6317 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6318 }
6319
6320 #if defined(CONFIG_USER_ONLY)
6321 #define GEN_TM_PRIV_NOOP(name) \
6322 static inline void gen_##name(DisasContext *ctx) \
6323 { \
6324 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6325 }
6326
6327 #else
6328
6329 #define GEN_TM_PRIV_NOOP(name) \
6330 static inline void gen_##name(DisasContext *ctx) \
6331 { \
6332 CHK_SV; \
6333 if (unlikely(!ctx->tm_enabled)) { \
6334 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6335 return; \
6336 } \
6337 /* Because tbegin always fails, the implementation is \
6338 * simple: \
6339 * \
6340 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6341 * = 0b0 || 0b00 | 0b0 \
6342 */ \
6343 tcg_gen_movi_i32(cpu_crf[0], 0); \
6344 }
6345
6346 #endif
6347
6348 GEN_TM_PRIV_NOOP(treclaim);
6349 GEN_TM_PRIV_NOOP(trechkpt);
6350
6351 #include "translate/fp-impl.inc.c"
6352
6353 #include "translate/vmx-impl.inc.c"
6354
6355 #include "translate/vsx-impl.inc.c"
6356
6357 #include "translate/dfp-impl.inc.c"
6358
6359 #include "translate/spe-impl.inc.c"
6360
6361 /* Handles lfdp, lxsd, lxssp */
6362 static void gen_dform39(DisasContext *ctx)
6363 {
6364 switch (ctx->opcode & 0x3) {
6365 case 0: /* lfdp */
6366 if (ctx->insns_flags2 & PPC2_ISA205) {
6367 return gen_lfdp(ctx);
6368 }
6369 break;
6370 case 2: /* lxsd */
6371 if (ctx->insns_flags2 & PPC2_ISA300) {
6372 return gen_lxsd(ctx);
6373 }
6374 break;
6375 case 3: /* lxssp */
6376 if (ctx->insns_flags2 & PPC2_ISA300) {
6377 return gen_lxssp(ctx);
6378 }
6379 break;
6380 }
6381 return gen_invalid(ctx);
6382 }
6383
6384 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6385 static void gen_dform3D(DisasContext *ctx)
6386 {
6387 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6388 switch (ctx->opcode & 0x7) {
6389 case 1: /* lxv */
6390 if (ctx->insns_flags2 & PPC2_ISA300) {
6391 return gen_lxv(ctx);
6392 }
6393 break;
6394 case 5: /* stxv */
6395 if (ctx->insns_flags2 & PPC2_ISA300) {
6396 return gen_stxv(ctx);
6397 }
6398 break;
6399 }
6400 } else { /* DS-FORM */
6401 switch (ctx->opcode & 0x3) {
6402 case 0: /* stfdp */
6403 if (ctx->insns_flags2 & PPC2_ISA205) {
6404 return gen_stfdp(ctx);
6405 }
6406 break;
6407 case 2: /* stxsd */
6408 if (ctx->insns_flags2 & PPC2_ISA300) {
6409 return gen_stxsd(ctx);
6410 }
6411 break;
6412 case 3: /* stxssp */
6413 if (ctx->insns_flags2 & PPC2_ISA300) {
6414 return gen_stxssp(ctx);
6415 }
6416 break;
6417 }
6418 }
6419 return gen_invalid(ctx);
6420 }
6421
6422 static opcode_t opcodes[] = {
6423 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6424 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6425 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6426 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6427 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6428 #if defined(TARGET_PPC64)
6429 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6430 #endif
6431 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6432 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6433 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6434 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6435 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6436 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6437 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6438 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6439 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6440 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6441 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6442 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6443 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6444 #if defined(TARGET_PPC64)
6445 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6446 #endif
6447 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6448 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6449 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6450 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6451 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6452 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6453 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6454 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6455 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6456 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6457 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6458 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6459 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6460 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6461 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6462 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6463 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6464 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6465 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6466 #if defined(TARGET_PPC64)
6467 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6468 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6469 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6470 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6471 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6472 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6473 #endif
6474 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6475 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6476 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6477 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6478 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6479 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6480 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6481 #if defined(TARGET_PPC64)
6482 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6483 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6484 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6485 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6486 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6487 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6488 PPC_NONE, PPC2_ISA300),
6489 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6490 PPC_NONE, PPC2_ISA300),
6491 #endif
6492 #if defined(TARGET_PPC64)
6493 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6494 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6495 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6496 #endif
6497 /* handles lfdp, lxsd, lxssp */
6498 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6499 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6500 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6501 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6502 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6503 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6504 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6505 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6506 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6507 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6508 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6509 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6510 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6511 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6512 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6513 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6514 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6515 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6516 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6517 #if defined(TARGET_PPC64)
6518 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6519 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6520 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6521 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6522 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6523 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6524 #endif
6525 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6526 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6527 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
6528 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6529 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6530 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6531 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6532 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
6533 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6534 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6535 #if defined(TARGET_PPC64)
6536 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6537 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6538 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6539 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6540 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6541 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6542 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6543 #endif
6544 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6545 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6546 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6547 #if defined(TARGET_PPC64)
6548 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6549 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6550 #endif
6551 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6552 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6553 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6554 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6555 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6556 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6557 #if defined(TARGET_PPC64)
6558 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6559 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6560 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
6561 #endif
6562 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6563 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6564 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6565 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6566 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6567 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6568 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6569 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6570 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6571 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6572 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
6573 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6574 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6575 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6576 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6577 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6578 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6579 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6580 #if defined(TARGET_PPC64)
6581 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6582 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6583 PPC_SEGMENT_64B),
6584 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6585 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6586 PPC_SEGMENT_64B),
6587 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6588 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6589 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6590 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6591 #endif
6592 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6593 /* XXX Those instructions will need to be handled differently for
6594 * different ISA versions */
6595 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6596 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6597 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
6598 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
6599 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6600 #if defined(TARGET_PPC64)
6601 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6602 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6603 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
6604 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6605 #endif
6606 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6607 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6608 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6609 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6610 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6611 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6612 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6613 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6614 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6615 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6616 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6617 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6618 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6619 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6620 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6621 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6622 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6623 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6624 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6625 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6626 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6627 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6628 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6629 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6630 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6631 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6632 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6633 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6634 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6635 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6636 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6637 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6638 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6639 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6640 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6641 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6642 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6643 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6644 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6645 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6646 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6647 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6648 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6649 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6650 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6651 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6652 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6653 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6654 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6655 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6656 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6657 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6658 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6659 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6660 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6661 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6662 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6663 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6664 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6665 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6666 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6667 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6668 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6669 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6670 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6671 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6672 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6673 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6674 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6675 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6676 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6677 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6678 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6679 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6680 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6681 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6682 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6683 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6684 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6685 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6686 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6687 PPC_NONE, PPC2_BOOKE206),
6688 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6689 PPC_NONE, PPC2_BOOKE206),
6690 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6691 PPC_NONE, PPC2_BOOKE206),
6692 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6693 PPC_NONE, PPC2_BOOKE206),
6694 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6695 PPC_NONE, PPC2_BOOKE206),
6696 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6697 PPC_NONE, PPC2_PRCNTL),
6698 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6699 PPC_NONE, PPC2_PRCNTL),
6700 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
6701 PPC_NONE, PPC2_PRCNTL),
6702 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6703 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6704 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6705 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6706 PPC_BOOKE, PPC2_BOOKE206),
6707 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6708 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6709 PPC_BOOKE, PPC2_BOOKE206),
6710 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6711 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6712 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6713 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6714 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6715 #if defined(TARGET_PPC64)
6716 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6717 PPC2_ISA300),
6718 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6719 #endif
6720
6721 #undef GEN_INT_ARITH_ADD
6722 #undef GEN_INT_ARITH_ADD_CONST
6723 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6724 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6725 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6726 add_ca, compute_ca, compute_ov) \
6727 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6728 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6729 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6730 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6731 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6732 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6733 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6734 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6735 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6736 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6737 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6738
6739 #undef GEN_INT_ARITH_DIVW
6740 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6741 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6742 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6743 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6744 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6745 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6746 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6747 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6748 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6749 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6750 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6751 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6752
6753 #if defined(TARGET_PPC64)
6754 #undef GEN_INT_ARITH_DIVD
6755 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6756 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6757 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6758 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6759 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6760 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6761
6762 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6763 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6764 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6765 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6766 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6767 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6768
6769 #undef GEN_INT_ARITH_MUL_HELPER
6770 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6771 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6772 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6773 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6774 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6775 #endif
6776
6777 #undef GEN_INT_ARITH_SUBF
6778 #undef GEN_INT_ARITH_SUBF_CONST
6779 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6780 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6781 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6782 add_ca, compute_ca, compute_ov) \
6783 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6784 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6785 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6786 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6787 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6788 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6789 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6790 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6791 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6792 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6793 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6794
6795 #undef GEN_LOGICAL1
6796 #undef GEN_LOGICAL2
6797 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6798 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6799 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6800 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6801 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6802 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6803 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6804 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6805 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6806 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6807 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6808 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6809 #if defined(TARGET_PPC64)
6810 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6811 #endif
6812
6813 #if defined(TARGET_PPC64)
6814 #undef GEN_PPC64_R2
6815 #undef GEN_PPC64_R4
6816 #define GEN_PPC64_R2(name, opc1, opc2) \
6817 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6818 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6819 PPC_64B)
6820 #define GEN_PPC64_R4(name, opc1, opc2) \
6821 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6822 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6823 PPC_64B), \
6824 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6825 PPC_64B), \
6826 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6827 PPC_64B)
6828 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6829 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6830 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6831 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6832 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6833 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6834 #endif
6835
6836 #undef GEN_LD
6837 #undef GEN_LDU
6838 #undef GEN_LDUX
6839 #undef GEN_LDX_E
6840 #undef GEN_LDS
6841 #define GEN_LD(name, ldop, opc, type) \
6842 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6843 #define GEN_LDU(name, ldop, opc, type) \
6844 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6845 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6846 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6847 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6848 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6849 #define GEN_LDS(name, ldop, op, type) \
6850 GEN_LD(name, ldop, op | 0x20, type) \
6851 GEN_LDU(name, ldop, op | 0x21, type) \
6852 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6853 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6854
6855 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6856 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6857 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6858 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6859 #if defined(TARGET_PPC64)
6860 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6861 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6862 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
6863 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
6864 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6865
6866 /* HV/P7 and later only */
6867 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
6868 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6869 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6870 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6871 #endif
6872 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6873 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6874
6875 #undef GEN_ST
6876 #undef GEN_STU
6877 #undef GEN_STUX
6878 #undef GEN_STX_E
6879 #undef GEN_STS
6880 #define GEN_ST(name, stop, opc, type) \
6881 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6882 #define GEN_STU(name, stop, opc, type) \
6883 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6884 #define GEN_STUX(name, stop, opc2, opc3, type) \
6885 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6886 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6887 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6888 #define GEN_STS(name, stop, op, type) \
6889 GEN_ST(name, stop, op | 0x20, type) \
6890 GEN_STU(name, stop, op | 0x21, type) \
6891 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6892 GEN_STX(name, stop, 0x17, op | 0x00, type)
6893
6894 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6895 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6896 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6897 #if defined(TARGET_PPC64)
6898 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
6899 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
6900 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6901 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
6902 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6903 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6904 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6905 #endif
6906 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6907 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6908
6909 #undef GEN_CRLOGIC
6910 #define GEN_CRLOGIC(name, tcg_op, opc) \
6911 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6912 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6913 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6914 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6915 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6916 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6917 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6918 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6919 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6920
6921 #undef GEN_MAC_HANDLER
6922 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6923 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6924 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6925 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6926 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6927 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6928 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6929 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6930 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6931 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6932 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6933 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6934 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6935 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6936 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6937 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6938 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6939 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6940 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6941 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6942 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6943 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6944 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6945 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6946 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6947 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6948 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6949 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6950 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6951 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6952 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6953 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6954 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6955 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6956 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6957 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6958 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6959 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6960 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6961 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6962 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6963 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6964 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6965 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6966
6967 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6968 PPC_NONE, PPC2_TM),
6969 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6970 PPC_NONE, PPC2_TM),
6971 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6972 PPC_NONE, PPC2_TM),
6973 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6974 PPC_NONE, PPC2_TM),
6975 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6976 PPC_NONE, PPC2_TM),
6977 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6978 PPC_NONE, PPC2_TM),
6979 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6980 PPC_NONE, PPC2_TM),
6981 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6982 PPC_NONE, PPC2_TM),
6983 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6984 PPC_NONE, PPC2_TM),
6985 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6986 PPC_NONE, PPC2_TM),
6987 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6988 PPC_NONE, PPC2_TM),
6989
6990 #include "translate/fp-ops.inc.c"
6991
6992 #include "translate/vmx-ops.inc.c"
6993
6994 #include "translate/vsx-ops.inc.c"
6995
6996 #include "translate/dfp-ops.inc.c"
6997
6998 #include "translate/spe-ops.inc.c"
6999 };
7000
7001 #include "helper_regs.h"
7002 #include "translate_init.inc.c"
7003
7004 /*****************************************************************************/
7005 /* Misc PowerPC helpers */
7006 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
7007 int flags)
7008 {
7009 #define RGPL 4
7010 #define RFPL 4
7011
7012 PowerPCCPU *cpu = POWERPC_CPU(cs);
7013 CPUPPCState *env = &cpu->env;
7014 int i;
7015
7016 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7017 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7018 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7019 cs->cpu_index);
7020 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7021 TARGET_FMT_lx " iidx %d didx %d\n",
7022 env->msr, env->spr[SPR_HID0],
7023 env->hflags, env->immu_idx, env->dmmu_idx);
7024 #if !defined(NO_TIMER_DUMP)
7025 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7026 #if !defined(CONFIG_USER_ONLY)
7027 " DECR %08" PRIu32
7028 #endif
7029 "\n",
7030 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7031 #if !defined(CONFIG_USER_ONLY)
7032 , cpu_ppc_load_decr(env)
7033 #endif
7034 );
7035 #endif
7036 for (i = 0; i < 32; i++) {
7037 if ((i & (RGPL - 1)) == 0)
7038 cpu_fprintf(f, "GPR%02d", i);
7039 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7040 if ((i & (RGPL - 1)) == (RGPL - 1))
7041 cpu_fprintf(f, "\n");
7042 }
7043 cpu_fprintf(f, "CR ");
7044 for (i = 0; i < 8; i++)
7045 cpu_fprintf(f, "%01x", env->crf[i]);
7046 cpu_fprintf(f, " [");
7047 for (i = 0; i < 8; i++) {
7048 char a = '-';
7049 if (env->crf[i] & 0x08)
7050 a = 'L';
7051 else if (env->crf[i] & 0x04)
7052 a = 'G';
7053 else if (env->crf[i] & 0x02)
7054 a = 'E';
7055 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7056 }
7057 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7058 env->reserve_addr);
7059
7060 if (flags & CPU_DUMP_FPU) {
7061 for (i = 0; i < 32; i++) {
7062 if ((i & (RFPL - 1)) == 0) {
7063 cpu_fprintf(f, "FPR%02d", i);
7064 }
7065 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
7066 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7067 cpu_fprintf(f, "\n");
7068 }
7069 }
7070 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7071 }
7072
7073 #if !defined(CONFIG_USER_ONLY)
7074 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7075 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7076 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7077 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7078
7079 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7080 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7081 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7082 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7083
7084 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7085 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7086 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7087 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7088
7089 #if defined(TARGET_PPC64)
7090 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7091 env->excp_model == POWERPC_EXCP_POWER8) {
7092 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7093 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7094 }
7095 #endif
7096 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7097 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7098 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7099 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7100 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7101
7102 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7103 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7104 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7105 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7106
7107 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7108 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7109 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7110 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7111
7112 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7113 " EPR " TARGET_FMT_lx "\n",
7114 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7115 env->spr[SPR_BOOKE_EPR]);
7116
7117 /* FSL-specific */
7118 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7119 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7120 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7121 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7122
7123 /*
7124 * IVORs are left out as they are large and do not change often --
7125 * they can be read with "p $ivor0", "p $ivor1", etc.
7126 */
7127 }
7128
7129 #if defined(TARGET_PPC64)
7130 if (env->flags & POWERPC_FLAG_CFAR) {
7131 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7132 }
7133 #endif
7134
7135 if (env->spr_cb[SPR_LPCR].name)
7136 cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7137
7138 switch (env->mmu_model) {
7139 case POWERPC_MMU_32B:
7140 case POWERPC_MMU_601:
7141 case POWERPC_MMU_SOFT_6xx:
7142 case POWERPC_MMU_SOFT_74xx:
7143 #if defined(TARGET_PPC64)
7144 case POWERPC_MMU_64B:
7145 case POWERPC_MMU_2_03:
7146 case POWERPC_MMU_2_06:
7147 case POWERPC_MMU_2_07:
7148 case POWERPC_MMU_3_00:
7149 #endif
7150 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7151 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7152 }
7153 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7154 cpu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7155 }
7156 cpu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7157 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7158 break;
7159 case POWERPC_MMU_BOOKE206:
7160 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7161 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7162 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7163 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7164
7165 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7166 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7167 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7168 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7169
7170 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7171 " TLB1CFG " TARGET_FMT_lx "\n",
7172 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7173 env->spr[SPR_BOOKE_TLB1CFG]);
7174 break;
7175 default:
7176 break;
7177 }
7178 #endif
7179
7180 #undef RGPL
7181 #undef RFPL
7182 }
7183
7184 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
7185 fprintf_function cpu_fprintf, int flags)
7186 {
7187 #if defined(DO_PPC_STATISTICS)
7188 PowerPCCPU *cpu = POWERPC_CPU(cs);
7189 opc_handler_t **t1, **t2, **t3, *handler;
7190 int op1, op2, op3;
7191
7192 t1 = cpu->env.opcodes;
7193 for (op1 = 0; op1 < 64; op1++) {
7194 handler = t1[op1];
7195 if (is_indirect_opcode(handler)) {
7196 t2 = ind_table(handler);
7197 for (op2 = 0; op2 < 32; op2++) {
7198 handler = t2[op2];
7199 if (is_indirect_opcode(handler)) {
7200 t3 = ind_table(handler);
7201 for (op3 = 0; op3 < 32; op3++) {
7202 handler = t3[op3];
7203 if (handler->count == 0)
7204 continue;
7205 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
7206 "%016" PRIx64 " %" PRId64 "\n",
7207 op1, op2, op3, op1, (op3 << 5) | op2,
7208 handler->oname,
7209 handler->count, handler->count);
7210 }
7211 } else {
7212 if (handler->count == 0)
7213 continue;
7214 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
7215 "%016" PRIx64 " %" PRId64 "\n",
7216 op1, op2, op1, op2, handler->oname,
7217 handler->count, handler->count);
7218 }
7219 }
7220 } else {
7221 if (handler->count == 0)
7222 continue;
7223 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
7224 " %" PRId64 "\n",
7225 op1, op1, handler->oname,
7226 handler->count, handler->count);
7227 }
7228 }
7229 #endif
7230 }
7231
7232 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7233 {
7234 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7235 CPUPPCState *env = cs->env_ptr;
7236 int bound;
7237
7238 ctx->exception = POWERPC_EXCP_NONE;
7239 ctx->spr_cb = env->spr_cb;
7240 ctx->pr = msr_pr;
7241 ctx->mem_idx = env->dmmu_idx;
7242 ctx->dr = msr_dr;
7243 #if !defined(CONFIG_USER_ONLY)
7244 ctx->hv = msr_hv || !env->has_hv_mode;
7245 #endif
7246 ctx->insns_flags = env->insns_flags;
7247 ctx->insns_flags2 = env->insns_flags2;
7248 ctx->access_type = -1;
7249 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7250 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7251 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7252 #if defined(TARGET_PPC64)
7253 ctx->sf_mode = msr_is_64bit(env, env->msr);
7254 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7255 #endif
7256 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7257 || env->mmu_model == POWERPC_MMU_601
7258 || (env->mmu_model & POWERPC_MMU_64B);
7259
7260 ctx->fpu_enabled = !!msr_fp;
7261 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7262 ctx->spe_enabled = !!msr_spe;
7263 else
7264 ctx->spe_enabled = false;
7265 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7266 ctx->altivec_enabled = !!msr_vr;
7267 else
7268 ctx->altivec_enabled = false;
7269 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7270 ctx->vsx_enabled = !!msr_vsx;
7271 } else {
7272 ctx->vsx_enabled = false;
7273 }
7274 #if defined(TARGET_PPC64)
7275 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7276 ctx->tm_enabled = !!msr_tm;
7277 } else {
7278 ctx->tm_enabled = false;
7279 }
7280 #endif
7281 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7282 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7283 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7284 else
7285 ctx->singlestep_enabled = 0;
7286 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7287 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7288 if (unlikely(ctx->base.singlestep_enabled)) {
7289 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7290 }
7291 #if defined (DO_SINGLE_STEP) && 0
7292 /* Single step trace mode */
7293 msr_se = 1;
7294 #endif
7295
7296 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7297 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7298 }
7299
7300 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7301 {
7302 }
7303
7304 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7305 {
7306 tcg_gen_insn_start(dcbase->pc_next);
7307 }
7308
7309 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7310 const CPUBreakpoint *bp)
7311 {
7312 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7313
7314 gen_debug_exception(ctx);
7315 /* The address covered by the breakpoint must be included in
7316 [tb->pc, tb->pc + tb->size) in order to for it to be
7317 properly cleared -- thus we increment the PC here so that
7318 the logic setting tb->size below does the right thing. */
7319 ctx->base.pc_next += 4;
7320 return true;
7321 }
7322
7323 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7324 {
7325 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7326 CPUPPCState *env = cs->env_ptr;
7327 opc_handler_t **table, *handler;
7328
7329 LOG_DISAS("----------------\n");
7330 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7331 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7332
7333 if (unlikely(need_byteswap(ctx))) {
7334 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7335 } else {
7336 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7337 }
7338 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7339 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7340 opc3(ctx->opcode), opc4(ctx->opcode),
7341 ctx->le_mode ? "little" : "big");
7342 ctx->base.pc_next += 4;
7343 table = env->opcodes;
7344 handler = table[opc1(ctx->opcode)];
7345 if (is_indirect_opcode(handler)) {
7346 table = ind_table(handler);
7347 handler = table[opc2(ctx->opcode)];
7348 if (is_indirect_opcode(handler)) {
7349 table = ind_table(handler);
7350 handler = table[opc3(ctx->opcode)];
7351 if (is_indirect_opcode(handler)) {
7352 table = ind_table(handler);
7353 handler = table[opc4(ctx->opcode)];
7354 }
7355 }
7356 }
7357 /* Is opcode *REALLY* valid ? */
7358 if (unlikely(handler->handler == &gen_invalid)) {
7359 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7360 "%02x - %02x - %02x - %02x (%08x) "
7361 TARGET_FMT_lx " %d\n",
7362 opc1(ctx->opcode), opc2(ctx->opcode),
7363 opc3(ctx->opcode), opc4(ctx->opcode),
7364 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7365 } else {
7366 uint32_t inval;
7367
7368 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7369 && Rc(ctx->opcode))) {
7370 inval = handler->inval2;
7371 } else {
7372 inval = handler->inval1;
7373 }
7374
7375 if (unlikely((ctx->opcode & inval) != 0)) {
7376 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7377 "%02x - %02x - %02x - %02x (%08x) "
7378 TARGET_FMT_lx "\n", ctx->opcode & inval,
7379 opc1(ctx->opcode), opc2(ctx->opcode),
7380 opc3(ctx->opcode), opc4(ctx->opcode),
7381 ctx->opcode, ctx->base.pc_next - 4);
7382 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7383 ctx->base.is_jmp = DISAS_NORETURN;
7384 return;
7385 }
7386 }
7387 (*(handler->handler))(ctx);
7388 #if defined(DO_PPC_STATISTICS)
7389 handler->count++;
7390 #endif
7391 /* Check trace mode exceptions */
7392 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7393 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7394 ctx->exception != POWERPC_SYSCALL &&
7395 ctx->exception != POWERPC_EXCP_TRAP &&
7396 ctx->exception != POWERPC_EXCP_BRANCH)) {
7397 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, ctx->base.pc_next);
7398 }
7399
7400 if (tcg_check_temp_count()) {
7401 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7402 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7403 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7404 }
7405
7406 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7407 DISAS_NEXT : DISAS_NORETURN;
7408 }
7409
7410 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7411 {
7412 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7413
7414 if (ctx->exception == POWERPC_EXCP_NONE) {
7415 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7416 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7417 if (unlikely(ctx->base.singlestep_enabled)) {
7418 gen_debug_exception(ctx);
7419 }
7420 /* Generate the return instruction */
7421 tcg_gen_exit_tb(NULL, 0);
7422 }
7423 }
7424
7425 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7426 {
7427 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7428 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7429 }
7430
7431 static const TranslatorOps ppc_tr_ops = {
7432 .init_disas_context = ppc_tr_init_disas_context,
7433 .tb_start = ppc_tr_tb_start,
7434 .insn_start = ppc_tr_insn_start,
7435 .breakpoint_check = ppc_tr_breakpoint_check,
7436 .translate_insn = ppc_tr_translate_insn,
7437 .tb_stop = ppc_tr_tb_stop,
7438 .disas_log = ppc_tr_disas_log,
7439 };
7440
7441 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
7442 {
7443 DisasContext ctx;
7444
7445 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
7446 }
7447
7448 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7449 target_ulong *data)
7450 {
7451 env->nip = data[0];
7452 }
QEmu