2 * Xilinx Versal Virtual board.
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/error-report.h"
15 #include "qapi/error.h"
16 #include "sysemu/device_tree.h"
17 #include "exec/address-spaces.h"
18 #include "hw/boards.h"
19 #include "hw/sysbus.h"
20 #include "hw/arm/sysbus-fdt.h"
21 #include "hw/arm/fdt.h"
23 #include "hw/arm/xlnx-versal.h"
25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
26 #define XLNX_VERSAL_VIRT_MACHINE(obj) \
27 OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
29 typedef struct VersalVirt
{
30 MachineState parent_obj
;
38 uint32_t ethernet_phy
[2];
42 struct arm_boot_info binfo
;
49 static void fdt_create(VersalVirt
*s
)
51 MachineClass
*mc
= MACHINE_GET_CLASS(s
);
54 s
->fdt
= create_device_tree(&s
->fdt_size
);
56 error_report("create_device_tree() failed");
60 /* Allocate all phandles. */
61 s
->phandle
.gic
= qemu_fdt_alloc_phandle(s
->fdt
);
62 for (i
= 0; i
< ARRAY_SIZE(s
->phandle
.ethernet_phy
); i
++) {
63 s
->phandle
.ethernet_phy
[i
] = qemu_fdt_alloc_phandle(s
->fdt
);
65 s
->phandle
.clk_25Mhz
= qemu_fdt_alloc_phandle(s
->fdt
);
66 s
->phandle
.clk_125Mhz
= qemu_fdt_alloc_phandle(s
->fdt
);
68 /* Create /chosen node for load_dtb. */
69 qemu_fdt_add_subnode(s
->fdt
, "/chosen");
72 qemu_fdt_setprop_cell(s
->fdt
, "/", "interrupt-parent", s
->phandle
.gic
);
73 qemu_fdt_setprop_cell(s
->fdt
, "/", "#size-cells", 0x2);
74 qemu_fdt_setprop_cell(s
->fdt
, "/", "#address-cells", 0x2);
75 qemu_fdt_setprop_string(s
->fdt
, "/", "model", mc
->desc
);
76 qemu_fdt_setprop_string(s
->fdt
, "/", "compatible", "xlnx-versal-virt");
79 static void fdt_add_clk_node(VersalVirt
*s
, const char *name
,
80 unsigned int freq_hz
, uint32_t phandle
)
82 qemu_fdt_add_subnode(s
->fdt
, name
);
83 qemu_fdt_setprop_cell(s
->fdt
, name
, "phandle", phandle
);
84 qemu_fdt_setprop_cell(s
->fdt
, name
, "clock-frequency", freq_hz
);
85 qemu_fdt_setprop_cell(s
->fdt
, name
, "#clock-cells", 0x0);
86 qemu_fdt_setprop_string(s
->fdt
, name
, "compatible", "fixed-clock");
87 qemu_fdt_setprop(s
->fdt
, name
, "u-boot,dm-pre-reloc", NULL
, 0);
90 static void fdt_add_cpu_nodes(VersalVirt
*s
, uint32_t psci_conduit
)
94 qemu_fdt_add_subnode(s
->fdt
, "/cpus");
95 qemu_fdt_setprop_cell(s
->fdt
, "/cpus", "#size-cells", 0x0);
96 qemu_fdt_setprop_cell(s
->fdt
, "/cpus", "#address-cells", 1);
98 for (i
= XLNX_VERSAL_NR_ACPUS
- 1; i
>= 0; i
--) {
99 char *name
= g_strdup_printf("/cpus/cpu@%d", i
);
100 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(i
));
102 qemu_fdt_add_subnode(s
->fdt
, name
);
103 qemu_fdt_setprop_cell(s
->fdt
, name
, "reg", armcpu
->mp_affinity
);
104 if (psci_conduit
!= QEMU_PSCI_CONDUIT_DISABLED
) {
105 qemu_fdt_setprop_string(s
->fdt
, name
, "enable-method", "psci");
107 qemu_fdt_setprop_string(s
->fdt
, name
, "device_type", "cpu");
108 qemu_fdt_setprop_string(s
->fdt
, name
, "compatible",
109 armcpu
->dtb_compatible
);
114 static void fdt_add_gic_nodes(VersalVirt
*s
)
118 nodename
= g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN
);
119 qemu_fdt_add_subnode(s
->fdt
, nodename
);
120 qemu_fdt_setprop_cell(s
->fdt
, nodename
, "phandle", s
->phandle
.gic
);
121 qemu_fdt_setprop_cells(s
->fdt
, nodename
, "interrupts",
122 GIC_FDT_IRQ_TYPE_PPI
, VERSAL_GIC_MAINT_IRQ
,
123 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
124 qemu_fdt_setprop(s
->fdt
, nodename
, "interrupt-controller", NULL
, 0);
125 qemu_fdt_setprop_sized_cells(s
->fdt
, nodename
, "reg",
126 2, MM_GIC_APU_DIST_MAIN
,
127 2, MM_GIC_APU_DIST_MAIN_SIZE
,
128 2, MM_GIC_APU_REDIST_0
,
129 2, MM_GIC_APU_REDIST_0_SIZE
);
130 qemu_fdt_setprop_cell(s
->fdt
, nodename
, "#interrupt-cells", 3);
131 qemu_fdt_setprop_string(s
->fdt
, nodename
, "compatible", "arm,gic-v3");
135 static void fdt_add_timer_nodes(VersalVirt
*s
)
137 const char compat
[] = "arm,armv8-timer";
138 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
140 qemu_fdt_add_subnode(s
->fdt
, "/timer");
141 qemu_fdt_setprop_cells(s
->fdt
, "/timer", "interrupts",
142 GIC_FDT_IRQ_TYPE_PPI
, VERSAL_TIMER_S_EL1_IRQ
, irqflags
,
143 GIC_FDT_IRQ_TYPE_PPI
, VERSAL_TIMER_NS_EL1_IRQ
, irqflags
,
144 GIC_FDT_IRQ_TYPE_PPI
, VERSAL_TIMER_VIRT_IRQ
, irqflags
,
145 GIC_FDT_IRQ_TYPE_PPI
, VERSAL_TIMER_NS_EL2_IRQ
, irqflags
);
146 qemu_fdt_setprop(s
->fdt
, "/timer", "compatible",
147 compat
, sizeof(compat
));
150 static void fdt_add_uart_nodes(VersalVirt
*s
)
152 uint64_t addrs
[] = { MM_UART1
, MM_UART0
};
153 unsigned int irqs
[] = { VERSAL_UART1_IRQ_0
, VERSAL_UART0_IRQ_0
};
154 const char compat
[] = "arm,pl011\0arm,sbsa-uart";
155 const char clocknames
[] = "uartclk\0apb_pclk";
158 for (i
= 0; i
< ARRAY_SIZE(addrs
); i
++) {
159 char *name
= g_strdup_printf("/uart@%" PRIx64
, addrs
[i
]);
160 qemu_fdt_add_subnode(s
->fdt
, name
);
161 qemu_fdt_setprop_cell(s
->fdt
, name
, "current-speed", 115200);
162 qemu_fdt_setprop_cells(s
->fdt
, name
, "clocks",
163 s
->phandle
.clk_125Mhz
, s
->phandle
.clk_125Mhz
);
164 qemu_fdt_setprop(s
->fdt
, name
, "clock-names",
165 clocknames
, sizeof(clocknames
));
167 qemu_fdt_setprop_cells(s
->fdt
, name
, "interrupts",
168 GIC_FDT_IRQ_TYPE_SPI
, irqs
[i
],
169 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
170 qemu_fdt_setprop_sized_cells(s
->fdt
, name
, "reg",
171 2, addrs
[i
], 2, 0x1000);
172 qemu_fdt_setprop(s
->fdt
, name
, "compatible",
173 compat
, sizeof(compat
));
174 qemu_fdt_setprop(s
->fdt
, name
, "u-boot,dm-pre-reloc", NULL
, 0);
176 if (addrs
[i
] == MM_UART0
) {
178 qemu_fdt_setprop_string(s
->fdt
, "/chosen", "stdout-path", name
);
184 static void fdt_add_fixed_link_nodes(VersalVirt
*s
, char *gemname
,
187 char *name
= g_strdup_printf("%s/fixed-link", gemname
);
189 qemu_fdt_add_subnode(s
->fdt
, name
);
190 qemu_fdt_setprop_cell(s
->fdt
, name
, "phandle", phandle
);
191 qemu_fdt_setprop(s
->fdt
, name
, "full-duplex", NULL
, 0);
192 qemu_fdt_setprop_cell(s
->fdt
, name
, "speed", 1000);
196 static void fdt_add_gem_nodes(VersalVirt
*s
)
198 uint64_t addrs
[] = { MM_GEM1
, MM_GEM0
};
199 unsigned int irqs
[] = { VERSAL_GEM1_IRQ_0
, VERSAL_GEM0_IRQ_0
};
200 const char clocknames
[] = "pclk\0hclk\0tx_clk\0rx_clk";
201 const char compat_gem
[] = "cdns,zynqmp-gem\0cdns,gem";
204 for (i
= 0; i
< ARRAY_SIZE(addrs
); i
++) {
205 char *name
= g_strdup_printf("/ethernet@%" PRIx64
, addrs
[i
]);
206 qemu_fdt_add_subnode(s
->fdt
, name
);
208 fdt_add_fixed_link_nodes(s
, name
, s
->phandle
.ethernet_phy
[i
]);
209 qemu_fdt_setprop_string(s
->fdt
, name
, "phy-mode", "rgmii-id");
210 qemu_fdt_setprop_cell(s
->fdt
, name
, "phy-handle",
211 s
->phandle
.ethernet_phy
[i
]);
212 qemu_fdt_setprop_cells(s
->fdt
, name
, "clocks",
213 s
->phandle
.clk_25Mhz
, s
->phandle
.clk_25Mhz
,
214 s
->phandle
.clk_25Mhz
, s
->phandle
.clk_25Mhz
);
215 qemu_fdt_setprop(s
->fdt
, name
, "clock-names",
216 clocknames
, sizeof(clocknames
));
217 qemu_fdt_setprop_cells(s
->fdt
, name
, "interrupts",
218 GIC_FDT_IRQ_TYPE_SPI
, irqs
[i
],
219 GIC_FDT_IRQ_FLAGS_LEVEL_HI
,
220 GIC_FDT_IRQ_TYPE_SPI
, irqs
[i
],
221 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
222 qemu_fdt_setprop_sized_cells(s
->fdt
, name
, "reg",
223 2, addrs
[i
], 2, 0x1000);
224 qemu_fdt_setprop(s
->fdt
, name
, "compatible",
225 compat_gem
, sizeof(compat_gem
));
226 qemu_fdt_setprop_cell(s
->fdt
, name
, "#address-cells", 1);
227 qemu_fdt_setprop_cell(s
->fdt
, name
, "#size-cells", 0);
232 static void fdt_nop_memory_nodes(void *fdt
, Error
**errp
)
238 node_path
= qemu_fdt_node_unit_path(fdt
, "memory", &err
);
240 error_propagate(errp
, err
);
243 while (node_path
[n
]) {
244 if (g_str_has_prefix(node_path
[n
], "/memory")) {
245 qemu_fdt_nop_node(fdt
, node_path
[n
]);
249 g_strfreev(node_path
);
252 static void fdt_add_memory_nodes(VersalVirt
*s
, void *fdt
, uint64_t ram_size
)
254 /* Describes the various split DDR access regions. */
255 static const struct {
259 { MM_TOP_DDR
, MM_TOP_DDR_SIZE
},
260 { MM_TOP_DDR_2
, MM_TOP_DDR_2_SIZE
},
261 { MM_TOP_DDR_3
, MM_TOP_DDR_3_SIZE
},
262 { MM_TOP_DDR_4
, MM_TOP_DDR_4_SIZE
}
264 uint64_t mem_reg_prop
[8] = {0};
265 uint64_t size
= ram_size
;
270 fdt_nop_memory_nodes(fdt
, &err
);
272 error_report_err(err
);
276 name
= g_strdup_printf("/memory@%x", MM_TOP_DDR
);
277 for (i
= 0; i
< ARRAY_SIZE(addr_ranges
) && size
; i
++) {
280 mapsize
= size
< addr_ranges
[i
].size
? size
: addr_ranges
[i
].size
;
282 mem_reg_prop
[i
* 2] = addr_ranges
[i
].base
;
283 mem_reg_prop
[i
* 2 + 1] = mapsize
;
286 qemu_fdt_add_subnode(fdt
, name
);
287 qemu_fdt_setprop_string(fdt
, name
, "device_type", "memory");
291 qemu_fdt_setprop_sized_cells(fdt
, name
, "reg",
296 qemu_fdt_setprop_sized_cells(fdt
, name
, "reg",
303 qemu_fdt_setprop_sized_cells(fdt
, name
, "reg",
312 qemu_fdt_setprop_sized_cells(fdt
, name
, "reg",
323 g_assert_not_reached();
328 static void versal_virt_modify_dtb(const struct arm_boot_info
*binfo
,
331 VersalVirt
*s
= container_of(binfo
, VersalVirt
, binfo
);
333 fdt_add_memory_nodes(s
, fdt
, binfo
->ram_size
);
336 static void *versal_virt_get_dtb(const struct arm_boot_info
*binfo
,
339 const VersalVirt
*board
= container_of(binfo
, VersalVirt
, binfo
);
341 *fdt_size
= board
->fdt_size
;
345 #define NUM_VIRTIO_TRANSPORT 8
346 static void create_virtio_regions(VersalVirt
*s
)
348 int virtio_mmio_size
= 0x200;
351 for (i
= 0; i
< NUM_VIRTIO_TRANSPORT
; i
++) {
352 char *name
= g_strdup_printf("virtio%d", i
);
353 hwaddr base
= MM_TOP_RSVD
+ i
* virtio_mmio_size
;
354 int irq
= VERSAL_RSVD_IRQ_FIRST
+ i
;
359 pic_irq
= qdev_get_gpio_in(DEVICE(&s
->soc
.fpd
.apu
.gic
), irq
);
360 dev
= qdev_create(NULL
, "virtio-mmio");
361 object_property_add_child(OBJECT(&s
->soc
), name
, OBJECT(dev
),
363 qdev_init_nofail(dev
);
364 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic_irq
);
365 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
366 memory_region_add_subregion(&s
->soc
.mr_ps
, base
, mr
);
370 for (i
= 0; i
< NUM_VIRTIO_TRANSPORT
; i
++) {
371 hwaddr base
= MM_TOP_RSVD
+ i
* virtio_mmio_size
;
372 int irq
= VERSAL_RSVD_IRQ_FIRST
+ i
;
373 char *name
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
375 qemu_fdt_add_subnode(s
->fdt
, name
);
376 qemu_fdt_setprop(s
->fdt
, name
, "dma-coherent", NULL
, 0);
377 qemu_fdt_setprop_cells(s
->fdt
, name
, "interrupts",
378 GIC_FDT_IRQ_TYPE_SPI
, irq
,
379 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
380 qemu_fdt_setprop_sized_cells(s
->fdt
, name
, "reg",
381 2, base
, 2, virtio_mmio_size
);
382 qemu_fdt_setprop_string(s
->fdt
, name
, "compatible", "virtio,mmio");
387 static void versal_virt_init(MachineState
*machine
)
389 VersalVirt
*s
= XLNX_VERSAL_VIRT_MACHINE(machine
);
390 int psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
393 * If the user provides an Operating System to be loaded, we expect them
394 * to use the -kernel command line option.
396 * Users can load firmware or boot-loaders with the -device loader options.
398 * When loading an OS, we generate a dtb and let arm_load_kernel() select
399 * where it gets loaded. This dtb will be passed to the kernel in x0.
401 * If there's no -kernel option, we generate a DTB and place it at 0x1000
402 * for the bootloaders or firmware to pick up.
404 * If users want to provide their own DTB, they can use the -dtb option.
405 * These dtb's will have their memory nodes modified to match QEMU's
406 * selected ram_size option before they get passed to the kernel or fw.
408 * When loading an OS, we turn on QEMU's PSCI implementation with SMC
409 * as the PSCI conduit. When there's no -kernel, we assume the user
410 * provides EL3 firmware to handle PSCI.
412 if (machine
->kernel_filename
) {
413 psci_conduit
= QEMU_PSCI_CONDUIT_SMC
;
416 sysbus_init_child_obj(OBJECT(machine
), "xlnx-ve", &s
->soc
,
417 sizeof(s
->soc
), TYPE_XLNX_VERSAL
);
418 object_property_set_link(OBJECT(&s
->soc
), OBJECT(machine
->ram
),
419 "ddr", &error_abort
);
420 object_property_set_int(OBJECT(&s
->soc
), psci_conduit
,
421 "psci-conduit", &error_abort
);
422 object_property_set_bool(OBJECT(&s
->soc
), true, "realized", &error_fatal
);
425 create_virtio_regions(s
);
426 fdt_add_gem_nodes(s
);
427 fdt_add_uart_nodes(s
);
428 fdt_add_gic_nodes(s
);
429 fdt_add_timer_nodes(s
);
430 fdt_add_cpu_nodes(s
, psci_conduit
);
431 fdt_add_clk_node(s
, "/clk125", 125000000, s
->phandle
.clk_125Mhz
);
432 fdt_add_clk_node(s
, "/clk25", 25000000, s
->phandle
.clk_25Mhz
);
434 /* Make the APU cpu address space visible to virtio and other
435 * modules unaware of muliple address-spaces. */
436 memory_region_add_subregion_overlap(get_system_memory(),
437 0, &s
->soc
.fpd
.apu
.mr
, 0);
439 s
->binfo
.ram_size
= machine
->ram_size
;
440 s
->binfo
.loader_start
= 0x0;
441 s
->binfo
.get_dtb
= versal_virt_get_dtb
;
442 s
->binfo
.modify_dtb
= versal_virt_modify_dtb
;
443 if (machine
->kernel_filename
) {
444 arm_load_kernel(s
->soc
.fpd
.apu
.cpu
[0], machine
, &s
->binfo
);
446 AddressSpace
*as
= arm_boot_address_space(s
->soc
.fpd
.apu
.cpu
[0],
448 /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
449 * Offset things by 4K. */
450 s
->binfo
.loader_start
= 0x1000;
451 s
->binfo
.dtb_limit
= 0x1000000;
452 if (arm_load_dtb(s
->binfo
.loader_start
,
453 &s
->binfo
, s
->binfo
.dtb_limit
, as
, machine
) < 0) {
459 static void versal_virt_machine_instance_init(Object
*obj
)
463 static void versal_virt_machine_class_init(ObjectClass
*oc
, void *data
)
465 MachineClass
*mc
= MACHINE_CLASS(oc
);
467 mc
->desc
= "Xilinx Versal Virtual development board";
468 mc
->init
= versal_virt_init
;
469 mc
->max_cpus
= XLNX_VERSAL_NR_ACPUS
;
470 mc
->default_cpus
= XLNX_VERSAL_NR_ACPUS
;
472 mc
->default_ram_id
= "ddr";
475 static const TypeInfo versal_virt_machine_init_typeinfo
= {
476 .name
= TYPE_XLNX_VERSAL_VIRT_MACHINE
,
477 .parent
= TYPE_MACHINE
,
478 .class_init
= versal_virt_machine_class_init
,
479 .instance_init
= versal_virt_machine_instance_init
,
480 .instance_size
= sizeof(VersalVirt
),
483 static void versal_virt_machine_init_register_types(void)
485 type_register_static(&versal_virt_machine_init_typeinfo
);
488 type_init(versal_virt_machine_init_register_types
)