hw/ide/microdrive.c

   1 /*
   2  * QEMU IDE Emulation: microdrive (CF / PCMCIA)
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/pc.h>
  27 #include <hw/pcmcia.h>
  28 #include "block.h"
  29 #include "block_int.h"
  30 #include "dma.h"
  31
  32 #include <hw/ide/internal.h>
  33
  34 /***********************************************************/
  35 /* CF-ATA Microdrive */
  36
  37 #define METADATA_SIZE   0x20
  38
  39 /* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */
  40 typedef struct {
  41     IDEBus bus;
  42     PCMCIACardState card;
  43     uint32_t attr_base;
  44     uint32_t io_base;
  45
  46     /* Card state */
  47     uint8_t opt;
  48     uint8_t stat;
  49     uint8_t pins;
  50
  51     uint8_t ctrl;
  52     uint16_t io;
  53     uint8_t cycle;
  54 } MicroDriveState;
  55
  56 /* Register bitfields */
  57 enum md_opt {
  58     OPT_MODE_MMAP       = 0,
  59     OPT_MODE_IOMAP16    = 1,
  60     OPT_MODE_IOMAP1     = 2,
  61     OPT_MODE_IOMAP2     = 3,
  62     OPT_MODE            = 0x3f,
  63     OPT_LEVIREQ         = 0x40,
  64     OPT_SRESET          = 0x80,
  65 };
  66 enum md_cstat {
  67     STAT_INT            = 0x02,
  68     STAT_PWRDWN         = 0x04,
  69     STAT_XE             = 0x10,
  70     STAT_IOIS8          = 0x20,
  71     STAT_SIGCHG         = 0x40,
  72     STAT_CHANGED        = 0x80,
  73 };
  74 enum md_pins {
  75     PINS_MRDY           = 0x02,
  76     PINS_CRDY           = 0x20,
  77 };
  78 enum md_ctrl {
  79     CTRL_IEN            = 0x02,
  80     CTRL_SRST           = 0x04,
  81 };
  82
  83 static inline void md_interrupt_update(MicroDriveState *s)
  84 {
  85     if (!s->card.slot)
  86         return;
  87
  88     qemu_set_irq(s->card.slot->irq,
  89                     !(s->stat & STAT_INT) &&    /* Inverted */
  90                     !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
  91                     !(s->opt & OPT_SRESET));
  92 }
  93
  94 static void md_set_irq(void *opaque, int irq, int level)
  95 {
  96     MicroDriveState *s = opaque;
  97     if (level)
  98         s->stat |= STAT_INT;
  99     else
 100         s->stat &= ~STAT_INT;
 101
 102     md_interrupt_update(s);
 103 }
 104
 105 static void md_reset(MicroDriveState *s)
 106 {
 107     s->opt = OPT_MODE_MMAP;
 108     s->stat = 0;
 109     s->pins = 0;
 110     s->cycle = 0;
 111     s->ctrl = 0;
 112     ide_bus_reset(&s->bus);
 113 }
 114
 115 static uint8_t md_attr_read(void *opaque, uint32_t at)
 116 {
 117     MicroDriveState *s = opaque;
 118     if (at < s->attr_base) {
 119         if (at < s->card.cis_len)
 120             return s->card.cis[at];
 121         else
 122             return 0x00;
 123     }
 124
 125     at -= s->attr_base;
 126
 127     switch (at) {
 128     case 0x00:  /* Configuration Option Register */
 129         return s->opt;
 130     case 0x02:  /* Card Configuration Status Register */
 131         if (s->ctrl & CTRL_IEN)
 132             return s->stat & ~STAT_INT;
 133         else
 134             return s->stat;
 135     case 0x04:  /* Pin Replacement Register */
 136         return (s->pins & PINS_CRDY) | 0x0c;
 137     case 0x06:  /* Socket and Copy Register */
 138         return 0x00;
 139 #ifdef VERBOSE
 140     default:
 141         printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
 142 #endif
 143     }
 144
 145     return 0;
 146 }
 147
 148 static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
 149 {
 150     MicroDriveState *s = opaque;
 151     at -= s->attr_base;
 152
 153     switch (at) {
 154     case 0x00:  /* Configuration Option Register */
 155         s->opt = value & 0xcf;
 156         if (value & OPT_SRESET)
 157             md_reset(s);
 158         md_interrupt_update(s);
 159         break;
 160     case 0x02:  /* Card Configuration Status Register */
 161         if ((s->stat ^ value) & STAT_PWRDWN)
 162             s->pins |= PINS_CRDY;
 163         s->stat &= 0x82;
 164         s->stat |= value & 0x74;
 165         md_interrupt_update(s);
 166         /* Word 170 in Identify Device must be equal to STAT_XE */
 167         break;
 168     case 0x04:  /* Pin Replacement Register */
 169         s->pins &= PINS_CRDY;
 170         s->pins |= value & PINS_MRDY;
 171         break;
 172     case 0x06:  /* Socket and Copy Register */
 173         break;
 174     default:
 175         printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
 176     }
 177 }
 178
 179 static uint16_t md_common_read(void *opaque, uint32_t at)
 180 {
 181     MicroDriveState *s = opaque;
 182     IDEState *ifs;
 183     uint16_t ret;
 184     at -= s->io_base;
 185
 186     switch (s->opt & OPT_MODE) {
 187     case OPT_MODE_MMAP:
 188         if ((at & ~0x3ff) == 0x400)
 189             at = 0;
 190         break;
 191     case OPT_MODE_IOMAP16:
 192         at &= 0xf;
 193         break;
 194     case OPT_MODE_IOMAP1:
 195         if ((at & ~0xf) == 0x3f0)
 196             at -= 0x3e8;
 197         else if ((at & ~0xf) == 0x1f0)
 198             at -= 0x1f0;
 199         break;
 200     case OPT_MODE_IOMAP2:
 201         if ((at & ~0xf) == 0x370)
 202             at -= 0x368;
 203         else if ((at & ~0xf) == 0x170)
 204             at -= 0x170;
 205     }
 206
 207     switch (at) {
 208     case 0x0:   /* Even RD Data */
 209     case 0x8:
 210         return ide_data_readw(&s->bus, 0);
 211
 212         /* TODO: 8-bit accesses */
 213         if (s->cycle)
 214             ret = s->io >> 8;
 215         else {
 216             s->io = ide_data_readw(&s->bus, 0);
 217             ret = s->io & 0xff;
 218         }
 219         s->cycle = !s->cycle;
 220         return ret;
 221     case 0x9:   /* Odd RD Data */
 222         return s->io >> 8;
 223     case 0xd:   /* Error */
 224         return ide_ioport_read(&s->bus, 0x1);
 225     case 0xe:   /* Alternate Status */
 226         ifs = idebus_active_if(&s->bus);
 227         if (ifs->bs)
 228             return ifs->status;
 229         else
 230             return 0;
 231     case 0xf:   /* Device Address */
 232         ifs = idebus_active_if(&s->bus);
 233         return 0xc2 | ((~ifs->select << 2) & 0x3c);
 234     default:
 235         return ide_ioport_read(&s->bus, at);
 236     }
 237
 238     return 0;
 239 }
 240
 241 static void md_common_write(void *opaque, uint32_t at, uint16_t value)
 242 {
 243     MicroDriveState *s = opaque;
 244     at -= s->io_base;
 245
 246     switch (s->opt & OPT_MODE) {
 247     case OPT_MODE_MMAP:
 248         if ((at & ~0x3ff) == 0x400)
 249             at = 0;
 250         break;
 251     case OPT_MODE_IOMAP16:
 252         at &= 0xf;
 253         break;
 254     case OPT_MODE_IOMAP1:
 255         if ((at & ~0xf) == 0x3f0)
 256             at -= 0x3e8;
 257         else if ((at & ~0xf) == 0x1f0)
 258             at -= 0x1f0;
 259         break;
 260     case OPT_MODE_IOMAP2:
 261         if ((at & ~0xf) == 0x370)
 262             at -= 0x368;
 263         else if ((at & ~0xf) == 0x170)
 264             at -= 0x170;
 265     }
 266
 267     switch (at) {
 268     case 0x0:   /* Even WR Data */
 269     case 0x8:
 270         ide_data_writew(&s->bus, 0, value);
 271         break;
 272
 273         /* TODO: 8-bit accesses */
 274         if (s->cycle)
 275             ide_data_writew(&s->bus, 0, s->io | (value << 8));
 276         else
 277             s->io = value & 0xff;
 278         s->cycle = !s->cycle;
 279         break;
 280     case 0x9:
 281         s->io = value & 0xff;
 282         s->cycle = !s->cycle;
 283         break;
 284     case 0xd:   /* Features */
 285         ide_ioport_write(&s->bus, 0x1, value);
 286         break;
 287     case 0xe:   /* Device Control */
 288         s->ctrl = value;
 289         if (value & CTRL_SRST)
 290             md_reset(s);
 291         md_interrupt_update(s);
 292         break;
 293     default:
 294         if (s->stat & STAT_PWRDWN) {
 295             s->pins |= PINS_CRDY;
 296             s->stat &= ~STAT_PWRDWN;
 297         }
 298         ide_ioport_write(&s->bus, at, value);
 299     }
 300 }
 301
 302 static const VMStateDescription vmstate_microdrive = {
 303     .name = "microdrive",
 304     .version_id = 3,
 305     .minimum_version_id = 0,
 306     .minimum_version_id_old = 0,
 307     .fields      = (VMStateField []) {
 308         VMSTATE_UINT8(opt, MicroDriveState),
 309         VMSTATE_UINT8(stat, MicroDriveState),
 310         VMSTATE_UINT8(pins, MicroDriveState),
 311         VMSTATE_UINT8(ctrl, MicroDriveState),
 312         VMSTATE_UINT16(io, MicroDriveState),
 313         VMSTATE_UINT8(cycle, MicroDriveState),
 314         VMSTATE_IDE_BUS(bus, MicroDriveState),
 315         VMSTATE_IDE_DRIVES(bus.ifs, MicroDriveState),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 static const uint8_t dscm1xxxx_cis[0x14a] = {
 321     [0x000] = CISTPL_DEVICE,    /* 5V Device Information */
 322     [0x002] = 0x03,             /* Tuple length = 4 bytes */
 323     [0x004] = 0xdb,             /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
 324     [0x006] = 0x01,             /* Size = 2K bytes */
 325     [0x008] = CISTPL_ENDMARK,
 326
 327     [0x00a] = CISTPL_DEVICE_OC, /* Additional Device Information */
 328     [0x00c] = 0x04,             /* Tuple length = 4 byest */
 329     [0x00e] = 0x03,             /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
 330     [0x010] = 0xdb,             /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
 331     [0x012] = 0x01,             /* Size = 2K bytes */
 332     [0x014] = CISTPL_ENDMARK,
 333
 334     [0x016] = CISTPL_JEDEC_C,   /* JEDEC ID */
 335     [0x018] = 0x02,             /* Tuple length = 2 bytes */
 336     [0x01a] = 0xdf,             /* PC Card ATA with no Vpp required */
 337     [0x01c] = 0x01,
 338
 339     [0x01e] = CISTPL_MANFID,    /* Manufacture ID */
 340     [0x020] = 0x04,             /* Tuple length = 4 bytes */
 341     [0x022] = 0xa4,             /* TPLMID_MANF = 00a4 (IBM) */
 342     [0x024] = 0x00,
 343     [0x026] = 0x00,             /* PLMID_CARD = 0000 */
 344     [0x028] = 0x00,
 345
 346     [0x02a] = CISTPL_VERS_1,    /* Level 1 Version */
 347     [0x02c] = 0x12,             /* Tuple length = 23 bytes */
 348     [0x02e] = 0x04,             /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
 349     [0x030] = 0x01,             /* Minor Version = 1 */
 350     [0x032] = 'I',
 351     [0x034] = 'B',
 352     [0x036] = 'M',
 353     [0x038] = 0x00,
 354     [0x03a] = 'm',
 355     [0x03c] = 'i',
 356     [0x03e] = 'c',
 357     [0x040] = 'r',
 358     [0x042] = 'o',
 359     [0x044] = 'd',
 360     [0x046] = 'r',
 361     [0x048] = 'i',
 362     [0x04a] = 'v',
 363     [0x04c] = 'e',
 364     [0x04e] = 0x00,
 365     [0x050] = CISTPL_ENDMARK,
 366
 367     [0x052] = CISTPL_FUNCID,    /* Function ID */
 368     [0x054] = 0x02,             /* Tuple length = 2 bytes */
 369     [0x056] = 0x04,             /* TPLFID_FUNCTION = Fixed Disk */
 370     [0x058] = 0x01,             /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
 371
 372     [0x05a] = CISTPL_FUNCE,     /* Function Extension */
 373     [0x05c] = 0x02,             /* Tuple length = 2 bytes */
 374     [0x05e] = 0x01,             /* TPLFE_TYPE = Disk Device Interface */
 375     [0x060] = 0x01,             /* TPLFE_DATA = PC Card ATA Interface */
 376
 377     [0x062] = CISTPL_FUNCE,     /* Function Extension */
 378     [0x064] = 0x03,             /* Tuple length = 3 bytes */
 379     [0x066] = 0x02,             /* TPLFE_TYPE = Basic PC Card ATA Interface */
 380     [0x068] = 0x08,             /* TPLFE_DATA: Rotating, Unique, Single */
 381     [0x06a] = 0x0f,             /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
 382
 383     [0x06c] = CISTPL_CONFIG,    /* Configuration */
 384     [0x06e] = 0x05,             /* Tuple length = 5 bytes */
 385     [0x070] = 0x01,             /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
 386     [0x072] = 0x07,             /* TPCC_LAST = 7 */
 387     [0x074] = 0x00,             /* TPCC_RADR = 0200 */
 388     [0x076] = 0x02,
 389     [0x078] = 0x0f,             /* TPCC_RMSK = 200, 202, 204, 206 */
 390
 391     [0x07a] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 392     [0x07c] = 0x0b,             /* Tuple length = 11 bytes */
 393     [0x07e] = 0xc0,             /* TPCE_INDX = Memory Mode, Default, Iface */
 394     [0x080] = 0xc0,             /* TPCE_IF = Memory, no BVDs, no WP, READY */
 395     [0x082] = 0xa1,             /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
 396     [0x084] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 397     [0x086] = 0x55,             /* NomV: 5.0 V */
 398     [0x088] = 0x4d,             /* MinV: 4.5 V */
 399     [0x08a] = 0x5d,             /* MaxV: 5.5 V */
 400     [0x08c] = 0x4e,             /* Peakl: 450 mA */
 401     [0x08e] = 0x08,             /* TPCE_MS = 1 window, 1 byte, Host address */
 402     [0x090] = 0x00,             /* Window descriptor: Window length = 0 */
 403     [0x092] = 0x20,             /* TPCE_MI: support power down mode, RW */
 404
 405     [0x094] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 406     [0x096] = 0x06,             /* Tuple length = 6 bytes */
 407     [0x098] = 0x00,             /* TPCE_INDX = Memory Mode, no Default */
 408     [0x09a] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 409     [0x09c] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 410     [0x09e] = 0xb5,             /* NomV: 3.3 V */
 411     [0x0a0] = 0x1e,
 412     [0x0a2] = 0x3e,             /* Peakl: 350 mA */
 413
 414     [0x0a4] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 415     [0x0a6] = 0x0d,             /* Tuple length = 13 bytes */
 416     [0x0a8] = 0xc1,             /* TPCE_INDX = I/O and Memory Mode, Default */
 417     [0x0aa] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 418     [0x0ac] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 419     [0x0ae] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 420     [0x0b0] = 0x55,             /* NomV: 5.0 V */
 421     [0x0b2] = 0x4d,             /* MinV: 4.5 V */
 422     [0x0b4] = 0x5d,             /* MaxV: 5.5 V */
 423     [0x0b6] = 0x4e,             /* Peakl: 450 mA */
 424     [0x0b8] = 0x64,             /* TPCE_IO = 16-byte boundary, 16/8 accesses */
 425     [0x0ba] = 0xf0,             /* TPCE_IR =  MASK, Level, Pulse, Share */
 426     [0x0bc] = 0xff,             /* IRQ0..IRQ7 supported */
 427     [0x0be] = 0xff,             /* IRQ8..IRQ15 supported */
 428     [0x0c0] = 0x20,             /* TPCE_MI = support power down mode */
 429
 430     [0x0c2] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 431     [0x0c4] = 0x06,             /* Tuple length = 6 bytes */
 432     [0x0c6] = 0x01,             /* TPCE_INDX = I/O and Memory Mode */
 433     [0x0c8] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 434     [0x0ca] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 435     [0x0cc] = 0xb5,             /* NomV: 3.3 V */
 436     [0x0ce] = 0x1e,
 437     [0x0d0] = 0x3e,             /* Peakl: 350 mA */
 438
 439     [0x0d2] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 440     [0x0d4] = 0x12,             /* Tuple length = 18 bytes */
 441     [0x0d6] = 0xc2,             /* TPCE_INDX = I/O Primary Mode */
 442     [0x0d8] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 443     [0x0da] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 444     [0x0dc] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 445     [0x0de] = 0x55,             /* NomV: 5.0 V */
 446     [0x0e0] = 0x4d,             /* MinV: 4.5 V */
 447     [0x0e2] = 0x5d,             /* MaxV: 5.5 V */
 448     [0x0e4] = 0x4e,             /* Peakl: 450 mA */
 449     [0x0e6] = 0xea,             /* TPCE_IO = 1K boundary, 16/8 access, Range */
 450     [0x0e8] = 0x61,             /* Range: 2 fields, 2 bytes addr, 1 byte len */
 451     [0x0ea] = 0xf0,             /* Field 1 address = 0x01f0 */
 452     [0x0ec] = 0x01,
 453     [0x0ee] = 0x07,             /* Address block length = 8 */
 454     [0x0f0] = 0xf6,             /* Field 2 address = 0x03f6 */
 455     [0x0f2] = 0x03,
 456     [0x0f4] = 0x01,             /* Address block length = 2 */
 457     [0x0f6] = 0xee,             /* TPCE_IR = IRQ E, Level, Pulse, Share */
 458     [0x0f8] = 0x20,             /* TPCE_MI = support power down mode */
 459
 460     [0x0fa] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 461     [0x0fc] = 0x06,             /* Tuple length = 6 bytes */
 462     [0x0fe] = 0x02,             /* TPCE_INDX = I/O Primary Mode, no Default */
 463     [0x100] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 464     [0x102] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 465     [0x104] = 0xb5,             /* NomV: 3.3 V */
 466     [0x106] = 0x1e,
 467     [0x108] = 0x3e,             /* Peakl: 350 mA */
 468
 469     [0x10a] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 470     [0x10c] = 0x12,             /* Tuple length = 18 bytes */
 471     [0x10e] = 0xc3,             /* TPCE_INDX = I/O Secondary Mode, Default */
 472     [0x110] = 0x41,             /* TPCE_IF = I/O and Memory, no BVD, no WP */
 473     [0x112] = 0x99,             /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
 474     [0x114] = 0x27,             /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
 475     [0x116] = 0x55,             /* NomV: 5.0 V */
 476     [0x118] = 0x4d,             /* MinV: 4.5 V */
 477     [0x11a] = 0x5d,             /* MaxV: 5.5 V */
 478     [0x11c] = 0x4e,             /* Peakl: 450 mA */
 479     [0x11e] = 0xea,             /* TPCE_IO = 1K boundary, 16/8 access, Range */
 480     [0x120] = 0x61,             /* Range: 2 fields, 2 byte addr, 1 byte len */
 481     [0x122] = 0x70,             /* Field 1 address = 0x0170 */
 482     [0x124] = 0x01,
 483     [0x126] = 0x07,             /* Address block length = 8 */
 484     [0x128] = 0x76,             /* Field 2 address = 0x0376 */
 485     [0x12a] = 0x03,
 486     [0x12c] = 0x01,             /* Address block length = 2 */
 487     [0x12e] = 0xee,             /* TPCE_IR = IRQ E, Level, Pulse, Share */
 488     [0x130] = 0x20,             /* TPCE_MI = support power down mode */
 489
 490     [0x132] = CISTPL_CFTABLE_ENTRY,     /* 16-bit PC Card Configuration */
 491     [0x134] = 0x06,             /* Tuple length = 6 bytes */
 492     [0x136] = 0x03,             /* TPCE_INDX = I/O Secondary Mode */
 493     [0x138] = 0x01,             /* TPCE_FS = Vcc only, no I/O, no Memory */
 494     [0x13a] = 0x21,             /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
 495     [0x13c] = 0xb5,             /* NomV: 3.3 V */
 496     [0x13e] = 0x1e,
 497     [0x140] = 0x3e,             /* Peakl: 350 mA */
 498
 499     [0x142] = CISTPL_NO_LINK,   /* No Link */
 500     [0x144] = 0x00,             /* Tuple length = 0 bytes */
 501
 502     [0x146] = CISTPL_END,       /* Tuple End */
 503 };
 504
 505 static int dscm1xxxx_attach(void *opaque)
 506 {
 507     MicroDriveState *md = opaque;
 508     md->card.attr_read = md_attr_read;
 509     md->card.attr_write = md_attr_write;
 510     md->card.common_read = md_common_read;
 511     md->card.common_write = md_common_write;
 512     md->card.io_read = md_common_read;
 513     md->card.io_write = md_common_write;
 514
 515     md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
 516     md->io_base = 0x0;
 517
 518     md_reset(md);
 519     md_interrupt_update(md);
 520
 521     md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
 522     return 0;
 523 }
 524
 525 static int dscm1xxxx_detach(void *opaque)
 526 {
 527     MicroDriveState *md = opaque;
 528     md_reset(md);
 529     return 0;
 530 }
 531
 532 PCMCIACardState *dscm1xxxx_init(DriveInfo *bdrv)
 533 {
 534     MicroDriveState *md = (MicroDriveState *) g_malloc0(sizeof(MicroDriveState));
 535     md->card.state = md;
 536     md->card.attach = dscm1xxxx_attach;
 537     md->card.detach = dscm1xxxx_detach;
 538     md->card.cis = dscm1xxxx_cis;
 539     md->card.cis_len = sizeof(dscm1xxxx_cis);
 540
 541     ide_init2_with_non_qdev_drives(&md->bus, bdrv, NULL,
 542                                    qemu_allocate_irqs(md_set_irq, md, 1)[0]);
 543     md->bus.ifs[0].drive_kind = IDE_CFATA;
 544     md->bus.ifs[0].mdata_size = METADATA_SIZE;
 545     md->bus.ifs[0].mdata_storage = (uint8_t *) g_malloc0(METADATA_SIZE);
 546
 547     vmstate_register(NULL, -1, &vmstate_microdrive, md);
 548
 549     return &md->card;
 550 }