2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * DEF(name, oargs, iargs, cargs, flags)
30 DEF(end
, 0, 0, 0, TCG_OPF_NOT_PRESENT
) /* must be kept first */
31 DEF(nop
, 0, 0, 0, TCG_OPF_NOT_PRESENT
)
32 DEF(nop1
, 0, 0, 1, TCG_OPF_NOT_PRESENT
)
33 DEF(nop2
, 0, 0, 2, TCG_OPF_NOT_PRESENT
)
34 DEF(nop3
, 0, 0, 3, TCG_OPF_NOT_PRESENT
)
36 /* variable number of parameters */
37 DEF(nopn
, 0, 0, 1, TCG_OPF_NOT_PRESENT
)
39 DEF(discard
, 1, 0, 0, TCG_OPF_NOT_PRESENT
)
40 DEF(set_label
, 0, 0, 1, TCG_OPF_BB_END
| TCG_OPF_NOT_PRESENT
)
42 /* variable number of parameters */
43 DEF(call
, 0, 0, 3, TCG_OPF_CALL_CLOBBER
| TCG_OPF_NOT_PRESENT
)
45 DEF(br
, 0, 0, 1, TCG_OPF_BB_END
)
47 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
48 #if TCG_TARGET_REG_BITS == 32
49 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
51 # define IMPL64 TCG_OPF_64BIT
54 DEF(mov_i32
, 1, 1, 0, TCG_OPF_NOT_PRESENT
)
55 DEF(movi_i32
, 1, 0, 1, TCG_OPF_NOT_PRESENT
)
56 DEF(setcond_i32
, 1, 2, 1, 0)
57 DEF(movcond_i32
, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32
))
59 DEF(ld8u_i32
, 1, 1, 1, 0)
60 DEF(ld8s_i32
, 1, 1, 1, 0)
61 DEF(ld16u_i32
, 1, 1, 1, 0)
62 DEF(ld16s_i32
, 1, 1, 1, 0)
63 DEF(ld_i32
, 1, 1, 1, 0)
64 DEF(st8_i32
, 0, 2, 1, 0)
65 DEF(st16_i32
, 0, 2, 1, 0)
66 DEF(st_i32
, 0, 2, 1, 0)
68 DEF(add_i32
, 1, 2, 0, 0)
69 DEF(sub_i32
, 1, 2, 0, 0)
70 DEF(mul_i32
, 1, 2, 0, 0)
71 DEF(div_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
72 DEF(divu_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32
))
73 DEF(rem_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32
))
74 DEF(remu_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32
))
75 DEF(div2_i32
, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32
))
76 DEF(divu2_i32
, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32
))
77 DEF(and_i32
, 1, 2, 0, 0)
78 DEF(or_i32
, 1, 2, 0, 0)
79 DEF(xor_i32
, 1, 2, 0, 0)
81 DEF(shl_i32
, 1, 2, 0, 0)
82 DEF(shr_i32
, 1, 2, 0, 0)
83 DEF(sar_i32
, 1, 2, 0, 0)
84 DEF(rotl_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32
))
85 DEF(rotr_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32
))
86 DEF(deposit_i32
, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32
))
88 DEF(brcond_i32
, 0, 2, 2, TCG_OPF_BB_END
)
90 DEF(add2_i32
, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32
))
91 DEF(sub2_i32
, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32
))
92 DEF(mulu2_i32
, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32
))
93 DEF(muls2_i32
, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32
))
94 DEF(muluh_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32
))
95 DEF(mulsh_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32
))
96 DEF(brcond2_i32
, 0, 4, 2, TCG_OPF_BB_END
| IMPL(TCG_TARGET_REG_BITS
== 32))
97 DEF(setcond2_i32
, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS
== 32))
99 DEF(ext8s_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32
))
100 DEF(ext16s_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32
))
101 DEF(ext8u_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32
))
102 DEF(ext16u_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32
))
103 DEF(bswap16_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32
))
104 DEF(bswap32_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32
))
105 DEF(not_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32
))
106 DEF(neg_i32
, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32
))
107 DEF(andc_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32
))
108 DEF(orc_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32
))
109 DEF(eqv_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32
))
110 DEF(nand_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32
))
111 DEF(nor_i32
, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32
))
113 DEF(mov_i64
, 1, 1, 0, TCG_OPF_64BIT
| TCG_OPF_NOT_PRESENT
)
114 DEF(movi_i64
, 1, 0, 1, TCG_OPF_64BIT
| TCG_OPF_NOT_PRESENT
)
115 DEF(setcond_i64
, 1, 2, 1, IMPL64
)
116 DEF(movcond_i64
, 1, 4, 1, IMPL64
| IMPL(TCG_TARGET_HAS_movcond_i64
))
118 DEF(ld8u_i64
, 1, 1, 1, IMPL64
)
119 DEF(ld8s_i64
, 1, 1, 1, IMPL64
)
120 DEF(ld16u_i64
, 1, 1, 1, IMPL64
)
121 DEF(ld16s_i64
, 1, 1, 1, IMPL64
)
122 DEF(ld32u_i64
, 1, 1, 1, IMPL64
)
123 DEF(ld32s_i64
, 1, 1, 1, IMPL64
)
124 DEF(ld_i64
, 1, 1, 1, IMPL64
)
125 DEF(st8_i64
, 0, 2, 1, IMPL64
)
126 DEF(st16_i64
, 0, 2, 1, IMPL64
)
127 DEF(st32_i64
, 0, 2, 1, IMPL64
)
128 DEF(st_i64
, 0, 2, 1, IMPL64
)
130 DEF(add_i64
, 1, 2, 0, IMPL64
)
131 DEF(sub_i64
, 1, 2, 0, IMPL64
)
132 DEF(mul_i64
, 1, 2, 0, IMPL64
)
133 DEF(div_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
134 DEF(divu_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div_i64
))
135 DEF(rem_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rem_i64
))
136 DEF(remu_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rem_i64
))
137 DEF(div2_i64
, 2, 3, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div2_i64
))
138 DEF(divu2_i64
, 2, 3, 0, IMPL64
| IMPL(TCG_TARGET_HAS_div2_i64
))
139 DEF(and_i64
, 1, 2, 0, IMPL64
)
140 DEF(or_i64
, 1, 2, 0, IMPL64
)
141 DEF(xor_i64
, 1, 2, 0, IMPL64
)
143 DEF(shl_i64
, 1, 2, 0, IMPL64
)
144 DEF(shr_i64
, 1, 2, 0, IMPL64
)
145 DEF(sar_i64
, 1, 2, 0, IMPL64
)
146 DEF(rotl_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rot_i64
))
147 DEF(rotr_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_rot_i64
))
148 DEF(deposit_i64
, 1, 2, 2, IMPL64
| IMPL(TCG_TARGET_HAS_deposit_i64
))
150 DEF(trunc_shr_i32
, 1, 1, 1,
151 IMPL(TCG_TARGET_HAS_trunc_shr_i32
)
152 | (TCG_TARGET_REG_BITS
== 32 ? TCG_OPF_NOT_PRESENT
: 0))
154 DEF(brcond_i64
, 0, 2, 2, TCG_OPF_BB_END
| IMPL64
)
155 DEF(ext8s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext8s_i64
))
156 DEF(ext16s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext16s_i64
))
157 DEF(ext32s_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext32s_i64
))
158 DEF(ext8u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext8u_i64
))
159 DEF(ext16u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext16u_i64
))
160 DEF(ext32u_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_ext32u_i64
))
161 DEF(bswap16_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap16_i64
))
162 DEF(bswap32_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap32_i64
))
163 DEF(bswap64_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_bswap64_i64
))
164 DEF(not_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_not_i64
))
165 DEF(neg_i64
, 1, 1, 0, IMPL64
| IMPL(TCG_TARGET_HAS_neg_i64
))
166 DEF(andc_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_andc_i64
))
167 DEF(orc_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_orc_i64
))
168 DEF(eqv_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_eqv_i64
))
169 DEF(nand_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_nand_i64
))
170 DEF(nor_i64
, 1, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_nor_i64
))
172 DEF(add2_i64
, 2, 4, 0, IMPL64
| IMPL(TCG_TARGET_HAS_add2_i64
))
173 DEF(sub2_i64
, 2, 4, 0, IMPL64
| IMPL(TCG_TARGET_HAS_sub2_i64
))
174 DEF(mulu2_i64
, 2, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_mulu2_i64
))
175 DEF(muls2_i64
, 2, 2, 0, IMPL64
| IMPL(TCG_TARGET_HAS_muls2_i64
))
176 DEF(muluh_i64
, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64
))
177 DEF(mulsh_i64
, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64
))
180 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
181 DEF(debug_insn_start
, 0, 0, 2, TCG_OPF_NOT_PRESENT
)
183 DEF(debug_insn_start
, 0, 0, 1, TCG_OPF_NOT_PRESENT
)
185 DEF(exit_tb
, 0, 0, 1, TCG_OPF_BB_END
)
186 DEF(goto_tb
, 0, 0, 1, TCG_OPF_BB_END
)
188 #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
189 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
191 DEF(qemu_ld_i32
, 1, TLADDR_ARGS
, 2,
192 TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
193 DEF(qemu_st_i32
, 0, TLADDR_ARGS
+ 1, 2,
194 TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
)
195 DEF(qemu_ld_i64
, DATA64_ARGS
, TLADDR_ARGS
, 2,
196 TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
| TCG_OPF_64BIT
)
197 DEF(qemu_st_i64
, 0, TLADDR_ARGS
+ DATA64_ARGS
, 2,
198 TCG_OPF_CALL_CLOBBER
| TCG_OPF_SIDE_EFFECTS
| TCG_OPF_64BIT
)