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target/ppc: remove 401/403 CPUs
[qemu.git] / target / ppc / cpu_init.c
blob96034889dd0280a56463cb4bc3b096d9f4896518
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "qapi/qapi-commands-machine-target.h"
44
45 #include "helper_regs.h"
46 #include "internal.h"
47 #include "spr_tcg.h"
48
49 /* #define PPC_DEBUG_SPR */
50 /* #define USE_APPLE_GDB */
51
52 static inline void vscr_init(CPUPPCState *env, uint32_t val)
53 {
54 /* Altivec always uses round-to-nearest */
55 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
56 ppc_store_vscr(env, val);
57 }
58
59 /**
60 * _spr_register
61 *
62 * Register an SPR with all the callbacks required for tcg,
63 * and the ID number for KVM.
64 *
65 * The reason for the conditional compilation is that the tcg functions
66 * may be compiled out, and the system kvm header may not be available
67 * for supplying the ID numbers. This is ugly, but the best we can do.
68 */
69
70 #ifdef CONFIG_TCG
71 # define USR_ARG(X) X,
72 # ifdef CONFIG_USER_ONLY
73 # define SYS_ARG(X)
74 # else
75 # define SYS_ARG(X) X,
76 # endif
77 #else
78 # define USR_ARG(X)
79 # define SYS_ARG(X)
80 #endif
81 #ifdef CONFIG_KVM
82 # define KVM_ARG(X) X,
83 #else
84 # define KVM_ARG(X)
85 #endif
86
87 typedef void spr_callback(DisasContext *, int, int);
88
89 static void _spr_register(CPUPPCState *env, int num, const char *name,
90 USR_ARG(spr_callback *uea_read)
91 USR_ARG(spr_callback *uea_write)
92 SYS_ARG(spr_callback *oea_read)
93 SYS_ARG(spr_callback *oea_write)
94 SYS_ARG(spr_callback *hea_read)
95 SYS_ARG(spr_callback *hea_write)
96 KVM_ARG(uint64_t one_reg_id)
97 target_ulong initial_value)
98 {
99 ppc_spr_t *spr = &env->spr_cb[num];
100
101 /* No SPR should be registered twice. */
102 assert(spr->name == NULL);
103 assert(name != NULL);
104
105 spr->name = name;
106 spr->default_value = initial_value;
107 env->spr[num] = initial_value;
108
109 #ifdef CONFIG_TCG
110 spr->uea_read = uea_read;
111 spr->uea_write = uea_write;
112 # ifndef CONFIG_USER_ONLY
113 spr->oea_read = oea_read;
114 spr->oea_write = oea_write;
115 spr->hea_read = hea_read;
116 spr->hea_write = hea_write;
117 # endif
118 #endif
119 #ifdef CONFIG_KVM
120 spr->one_reg_id = one_reg_id;
121 #endif
122 }
123
124 /* spr_register_kvm_hv passes all required arguments. */
125 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
126 oea_read, oea_write, hea_read, hea_write, \
127 one_reg_id, initial_value) \
128 _spr_register(env, num, name, \
129 USR_ARG(uea_read) USR_ARG(uea_write) \
130 SYS_ARG(oea_read) SYS_ARG(oea_write) \
131 SYS_ARG(hea_read) SYS_ARG(hea_write) \
132 KVM_ARG(one_reg_id) initial_value)
133
134 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
135 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
136 oea_read, oea_write, one_reg_id, ival) \
137 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
138 oea_write, oea_read, oea_write, one_reg_id, ival)
139
140 /* spr_register_hv and spr_register are similar, except there is no kvm id. */
141 #define spr_register_hv(env, num, name, uea_read, uea_write, \
142 oea_read, oea_write, hea_read, hea_write, ival) \
143 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
144 oea_write, hea_read, hea_write, 0, ival)
145
146 #define spr_register(env, num, name, uea_read, uea_write, \
147 oea_read, oea_write, ival) \
148 spr_register_kvm(env, num, name, uea_read, uea_write, \
149 oea_read, oea_write, 0, ival)
150
151 /* Generic PowerPC SPRs */
152 static void register_generic_sprs(CPUPPCState *env)
153 {
154 /* Integer processing */
155 spr_register(env, SPR_XER, "XER",
156 &spr_read_xer, &spr_write_xer,
157 &spr_read_xer, &spr_write_xer,
158 0x00000000);
159 /* Branch control */
160 spr_register(env, SPR_LR, "LR",
161 &spr_read_lr, &spr_write_lr,
162 &spr_read_lr, &spr_write_lr,
163 0x00000000);
164 spr_register(env, SPR_CTR, "CTR",
165 &spr_read_ctr, &spr_write_ctr,
166 &spr_read_ctr, &spr_write_ctr,
167 0x00000000);
168 /* Interrupt processing */
169 spr_register(env, SPR_SRR0, "SRR0",
170 SPR_NOACCESS, SPR_NOACCESS,
171 &spr_read_generic, &spr_write_generic,
172 0x00000000);
173 spr_register(env, SPR_SRR1, "SRR1",
174 SPR_NOACCESS, SPR_NOACCESS,
175 &spr_read_generic, &spr_write_generic,
176 0x00000000);
177 /* Processor control */
178 spr_register(env, SPR_SPRG0, "SPRG0",
179 SPR_NOACCESS, SPR_NOACCESS,
180 &spr_read_generic, &spr_write_generic,
181 0x00000000);
182 spr_register(env, SPR_SPRG1, "SPRG1",
183 SPR_NOACCESS, SPR_NOACCESS,
184 &spr_read_generic, &spr_write_generic,
185 0x00000000);
186 spr_register(env, SPR_SPRG2, "SPRG2",
187 SPR_NOACCESS, SPR_NOACCESS,
188 &spr_read_generic, &spr_write_generic,
189 0x00000000);
190 spr_register(env, SPR_SPRG3, "SPRG3",
191 SPR_NOACCESS, SPR_NOACCESS,
192 &spr_read_generic, &spr_write_generic,
193 0x00000000);
194 }
195
196 /* SPR common to all non-embedded PowerPC, including 601 */
197 static void register_ne_601_sprs(CPUPPCState *env)
198 {
199 /* Exception processing */
200 spr_register_kvm(env, SPR_DSISR, "DSISR",
201 SPR_NOACCESS, SPR_NOACCESS,
202 &spr_read_generic, &spr_write_generic,
203 KVM_REG_PPC_DSISR, 0x00000000);
204 spr_register_kvm(env, SPR_DAR, "DAR",
205 SPR_NOACCESS, SPR_NOACCESS,
206 &spr_read_generic, &spr_write_generic,
207 KVM_REG_PPC_DAR, 0x00000000);
208 /* Timer */
209 spr_register(env, SPR_DECR, "DECR",
210 SPR_NOACCESS, SPR_NOACCESS,
211 &spr_read_decr, &spr_write_decr,
212 0x00000000);
213 }
214
215 /* Storage Description Register 1 */
216 static void register_sdr1_sprs(CPUPPCState *env)
217 {
218 #ifndef CONFIG_USER_ONLY
219 if (env->has_hv_mode) {
220 /*
221 * SDR1 is a hypervisor resource on CPUs which have a
222 * hypervisor mode
223 */
224 spr_register_hv(env, SPR_SDR1, "SDR1",
225 SPR_NOACCESS, SPR_NOACCESS,
226 SPR_NOACCESS, SPR_NOACCESS,
227 &spr_read_generic, &spr_write_sdr1,
228 0x00000000);
229 } else {
230 spr_register(env, SPR_SDR1, "SDR1",
231 SPR_NOACCESS, SPR_NOACCESS,
232 &spr_read_generic, &spr_write_sdr1,
233 0x00000000);
234 }
235 #endif
236 }
237
238 /* BATs 0-3 */
239 static void register_low_BATs(CPUPPCState *env)
240 {
241 #if !defined(CONFIG_USER_ONLY)
242 spr_register(env, SPR_IBAT0U, "IBAT0U",
243 SPR_NOACCESS, SPR_NOACCESS,
244 &spr_read_ibat, &spr_write_ibatu,
245 0x00000000);
246 spr_register(env, SPR_IBAT0L, "IBAT0L",
247 SPR_NOACCESS, SPR_NOACCESS,
248 &spr_read_ibat, &spr_write_ibatl,
249 0x00000000);
250 spr_register(env, SPR_IBAT1U, "IBAT1U",
251 SPR_NOACCESS, SPR_NOACCESS,
252 &spr_read_ibat, &spr_write_ibatu,
253 0x00000000);
254 spr_register(env, SPR_IBAT1L, "IBAT1L",
255 SPR_NOACCESS, SPR_NOACCESS,
256 &spr_read_ibat, &spr_write_ibatl,
257 0x00000000);
258 spr_register(env, SPR_IBAT2U, "IBAT2U",
259 SPR_NOACCESS, SPR_NOACCESS,
260 &spr_read_ibat, &spr_write_ibatu,
261 0x00000000);
262 spr_register(env, SPR_IBAT2L, "IBAT2L",
263 SPR_NOACCESS, SPR_NOACCESS,
264 &spr_read_ibat, &spr_write_ibatl,
265 0x00000000);
266 spr_register(env, SPR_IBAT3U, "IBAT3U",
267 SPR_NOACCESS, SPR_NOACCESS,
268 &spr_read_ibat, &spr_write_ibatu,
269 0x00000000);
270 spr_register(env, SPR_IBAT3L, "IBAT3L",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_ibat, &spr_write_ibatl,
273 0x00000000);
274 spr_register(env, SPR_DBAT0U, "DBAT0U",
275 SPR_NOACCESS, SPR_NOACCESS,
276 &spr_read_dbat, &spr_write_dbatu,
277 0x00000000);
278 spr_register(env, SPR_DBAT0L, "DBAT0L",
279 SPR_NOACCESS, SPR_NOACCESS,
280 &spr_read_dbat, &spr_write_dbatl,
281 0x00000000);
282 spr_register(env, SPR_DBAT1U, "DBAT1U",
283 SPR_NOACCESS, SPR_NOACCESS,
284 &spr_read_dbat, &spr_write_dbatu,
285 0x00000000);
286 spr_register(env, SPR_DBAT1L, "DBAT1L",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_dbat, &spr_write_dbatl,
289 0x00000000);
290 spr_register(env, SPR_DBAT2U, "DBAT2U",
291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_dbat, &spr_write_dbatu,
293 0x00000000);
294 spr_register(env, SPR_DBAT2L, "DBAT2L",
295 SPR_NOACCESS, SPR_NOACCESS,
296 &spr_read_dbat, &spr_write_dbatl,
297 0x00000000);
298 spr_register(env, SPR_DBAT3U, "DBAT3U",
299 SPR_NOACCESS, SPR_NOACCESS,
300 &spr_read_dbat, &spr_write_dbatu,
301 0x00000000);
302 spr_register(env, SPR_DBAT3L, "DBAT3L",
303 SPR_NOACCESS, SPR_NOACCESS,
304 &spr_read_dbat, &spr_write_dbatl,
305 0x00000000);
306 env->nb_BATs += 4;
307 #endif
308 }
309
310 /* BATs 4-7 */
311 static void register_high_BATs(CPUPPCState *env)
312 {
313 #if !defined(CONFIG_USER_ONLY)
314 spr_register(env, SPR_IBAT4U, "IBAT4U",
315 SPR_NOACCESS, SPR_NOACCESS,
316 &spr_read_ibat_h, &spr_write_ibatu_h,
317 0x00000000);
318 spr_register(env, SPR_IBAT4L, "IBAT4L",
319 SPR_NOACCESS, SPR_NOACCESS,
320 &spr_read_ibat_h, &spr_write_ibatl_h,
321 0x00000000);
322 spr_register(env, SPR_IBAT5U, "IBAT5U",
323 SPR_NOACCESS, SPR_NOACCESS,
324 &spr_read_ibat_h, &spr_write_ibatu_h,
325 0x00000000);
326 spr_register(env, SPR_IBAT5L, "IBAT5L",
327 SPR_NOACCESS, SPR_NOACCESS,
328 &spr_read_ibat_h, &spr_write_ibatl_h,
329 0x00000000);
330 spr_register(env, SPR_IBAT6U, "IBAT6U",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_ibat_h, &spr_write_ibatu_h,
333 0x00000000);
334 spr_register(env, SPR_IBAT6L, "IBAT6L",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_ibat_h, &spr_write_ibatl_h,
337 0x00000000);
338 spr_register(env, SPR_IBAT7U, "IBAT7U",
339 SPR_NOACCESS, SPR_NOACCESS,
340 &spr_read_ibat_h, &spr_write_ibatu_h,
341 0x00000000);
342 spr_register(env, SPR_IBAT7L, "IBAT7L",
343 SPR_NOACCESS, SPR_NOACCESS,
344 &spr_read_ibat_h, &spr_write_ibatl_h,
345 0x00000000);
346 spr_register(env, SPR_DBAT4U, "DBAT4U",
347 SPR_NOACCESS, SPR_NOACCESS,
348 &spr_read_dbat_h, &spr_write_dbatu_h,
349 0x00000000);
350 spr_register(env, SPR_DBAT4L, "DBAT4L",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_dbat_h, &spr_write_dbatl_h,
353 0x00000000);
354 spr_register(env, SPR_DBAT5U, "DBAT5U",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_dbat_h, &spr_write_dbatu_h,
357 0x00000000);
358 spr_register(env, SPR_DBAT5L, "DBAT5L",
359 SPR_NOACCESS, SPR_NOACCESS,
360 &spr_read_dbat_h, &spr_write_dbatl_h,
361 0x00000000);
362 spr_register(env, SPR_DBAT6U, "DBAT6U",
363 SPR_NOACCESS, SPR_NOACCESS,
364 &spr_read_dbat_h, &spr_write_dbatu_h,
365 0x00000000);
366 spr_register(env, SPR_DBAT6L, "DBAT6L",
367 SPR_NOACCESS, SPR_NOACCESS,
368 &spr_read_dbat_h, &spr_write_dbatl_h,
369 0x00000000);
370 spr_register(env, SPR_DBAT7U, "DBAT7U",
371 SPR_NOACCESS, SPR_NOACCESS,
372 &spr_read_dbat_h, &spr_write_dbatu_h,
373 0x00000000);
374 spr_register(env, SPR_DBAT7L, "DBAT7L",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_dbat_h, &spr_write_dbatl_h,
377 0x00000000);
378 env->nb_BATs += 4;
379 #endif
380 }
381
382 /* Generic PowerPC time base */
383 static void register_tbl(CPUPPCState *env)
384 {
385 spr_register(env, SPR_VTBL, "TBL",
386 &spr_read_tbl, SPR_NOACCESS,
387 &spr_read_tbl, SPR_NOACCESS,
388 0x00000000);
389 spr_register(env, SPR_TBL, "TBL",
390 &spr_read_tbl, SPR_NOACCESS,
391 &spr_read_tbl, &spr_write_tbl,
392 0x00000000);
393 spr_register(env, SPR_VTBU, "TBU",
394 &spr_read_tbu, SPR_NOACCESS,
395 &spr_read_tbu, SPR_NOACCESS,
396 0x00000000);
397 spr_register(env, SPR_TBU, "TBU",
398 &spr_read_tbu, SPR_NOACCESS,
399 &spr_read_tbu, &spr_write_tbu,
400 0x00000000);
401 }
402
403 /* Softare table search registers */
404 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
405 {
406 #if !defined(CONFIG_USER_ONLY)
407 env->nb_tlb = nb_tlbs;
408 env->nb_ways = nb_ways;
409 env->id_tlbs = 1;
410 env->tlb_type = TLB_6XX;
411 spr_register(env, SPR_DMISS, "DMISS",
412 SPR_NOACCESS, SPR_NOACCESS,
413 &spr_read_generic, SPR_NOACCESS,
414 0x00000000);
415 spr_register(env, SPR_DCMP, "DCMP",
416 SPR_NOACCESS, SPR_NOACCESS,
417 &spr_read_generic, SPR_NOACCESS,
418 0x00000000);
419 spr_register(env, SPR_HASH1, "HASH1",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, SPR_NOACCESS,
422 0x00000000);
423 spr_register(env, SPR_HASH2, "HASH2",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, SPR_NOACCESS,
426 0x00000000);
427 spr_register(env, SPR_IMISS, "IMISS",
428 SPR_NOACCESS, SPR_NOACCESS,
429 &spr_read_generic, SPR_NOACCESS,
430 0x00000000);
431 spr_register(env, SPR_ICMP, "ICMP",
432 SPR_NOACCESS, SPR_NOACCESS,
433 &spr_read_generic, SPR_NOACCESS,
434 0x00000000);
435 spr_register(env, SPR_RPA, "RPA",
436 SPR_NOACCESS, SPR_NOACCESS,
437 &spr_read_generic, &spr_write_generic,
438 0x00000000);
439 #endif
440 }
441
442 /* SPR common to MPC755 and G2 */
443 static void register_G2_755_sprs(CPUPPCState *env)
444 {
445 /* SGPRs */
446 spr_register(env, SPR_SPRG4, "SPRG4",
447 SPR_NOACCESS, SPR_NOACCESS,
448 &spr_read_generic, &spr_write_generic,
449 0x00000000);
450 spr_register(env, SPR_SPRG5, "SPRG5",
451 SPR_NOACCESS, SPR_NOACCESS,
452 &spr_read_generic, &spr_write_generic,
453 0x00000000);
454 spr_register(env, SPR_SPRG6, "SPRG6",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458 spr_register(env, SPR_SPRG7, "SPRG7",
459 SPR_NOACCESS, SPR_NOACCESS,
460 &spr_read_generic, &spr_write_generic,
461 0x00000000);
462 }
463
464 /* SPR common to all 7xx PowerPC implementations */
465 static void register_7xx_sprs(CPUPPCState *env)
466 {
467 /* Breakpoints */
468 /* XXX : not implemented */
469 spr_register_kvm(env, SPR_DABR, "DABR",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 KVM_REG_PPC_DABR, 0x00000000);
473 /* XXX : not implemented */
474 spr_register(env, SPR_IABR, "IABR",
475 SPR_NOACCESS, SPR_NOACCESS,
476 &spr_read_generic, &spr_write_generic,
477 0x00000000);
478 /* Cache management */
479 /* XXX : not implemented */
480 spr_register(env, SPR_ICTC, "ICTC",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 /* Performance monitors */
485 /* XXX : not implemented */
486 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
487 SPR_NOACCESS, SPR_NOACCESS,
488 &spr_read_generic, &spr_write_generic,
489 0x00000000);
490 /* XXX : not implemented */
491 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
492 SPR_NOACCESS, SPR_NOACCESS,
493 &spr_read_generic, &spr_write_generic,
494 0x00000000);
495 /* XXX : not implemented */
496 spr_register(env, SPR_7XX_PMC1, "PMC1",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 0x00000000);
500 /* XXX : not implemented */
501 spr_register(env, SPR_7XX_PMC2, "PMC2",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 /* XXX : not implemented */
506 spr_register(env, SPR_7XX_PMC3, "PMC3",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 /* XXX : not implemented */
511 spr_register(env, SPR_7XX_PMC4, "PMC4",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515 /* XXX : not implemented */
516 spr_register(env, SPR_7XX_SIAR, "SIAR",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, SPR_NOACCESS,
519 0x00000000);
520 /* XXX : not implemented */
521 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
522 &spr_read_ureg, SPR_NOACCESS,
523 &spr_read_ureg, SPR_NOACCESS,
524 0x00000000);
525 /* XXX : not implemented */
526 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
527 &spr_read_ureg, SPR_NOACCESS,
528 &spr_read_ureg, SPR_NOACCESS,
529 0x00000000);
530 /* XXX : not implemented */
531 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
532 &spr_read_ureg, SPR_NOACCESS,
533 &spr_read_ureg, SPR_NOACCESS,
534 0x00000000);
535 /* XXX : not implemented */
536 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
537 &spr_read_ureg, SPR_NOACCESS,
538 &spr_read_ureg, SPR_NOACCESS,
539 0x00000000);
540 /* XXX : not implemented */
541 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
542 &spr_read_ureg, SPR_NOACCESS,
543 &spr_read_ureg, SPR_NOACCESS,
544 0x00000000);
545 /* XXX : not implemented */
546 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
547 &spr_read_ureg, SPR_NOACCESS,
548 &spr_read_ureg, SPR_NOACCESS,
549 0x00000000);
550 /* XXX : not implemented */
551 spr_register(env, SPR_7XX_USIAR, "USIAR",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555 /* External access control */
556 /* XXX : not implemented */
557 spr_register(env, SPR_EAR, "EAR",
558 SPR_NOACCESS, SPR_NOACCESS,
559 &spr_read_generic, &spr_write_generic,
560 0x00000000);
561 }
562
563 #ifdef TARGET_PPC64
564 static void register_amr_sprs(CPUPPCState *env)
565 {
566 #ifndef CONFIG_USER_ONLY
567 /*
568 * Virtual Page Class Key protection
569 *
570 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
571 * userspace accessible, 29 is privileged. So we only need to set
572 * the kvm ONE_REG id on one of them, we use 29
573 */
574 spr_register(env, SPR_UAMR, "UAMR",
575 &spr_read_generic, &spr_write_amr,
576 &spr_read_generic, &spr_write_amr,
577 0);
578 spr_register_kvm_hv(env, SPR_AMR, "AMR",
579 SPR_NOACCESS, SPR_NOACCESS,
580 &spr_read_generic, &spr_write_amr,
581 &spr_read_generic, &spr_write_generic,
582 KVM_REG_PPC_AMR, 0);
583 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
584 SPR_NOACCESS, SPR_NOACCESS,
585 &spr_read_generic, &spr_write_uamor,
586 &spr_read_generic, &spr_write_generic,
587 KVM_REG_PPC_UAMOR, 0);
588 spr_register_hv(env, SPR_AMOR, "AMOR",
589 SPR_NOACCESS, SPR_NOACCESS,
590 SPR_NOACCESS, SPR_NOACCESS,
591 &spr_read_generic, &spr_write_generic,
592 0);
593 #endif /* !CONFIG_USER_ONLY */
594 }
595
596 static void register_iamr_sprs(CPUPPCState *env)
597 {
598 #ifndef CONFIG_USER_ONLY
599 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
600 SPR_NOACCESS, SPR_NOACCESS,
601 &spr_read_generic, &spr_write_iamr,
602 &spr_read_generic, &spr_write_generic,
603 KVM_REG_PPC_IAMR, 0);
604 #endif /* !CONFIG_USER_ONLY */
605 }
606 #endif /* TARGET_PPC64 */
607
608 static void register_thrm_sprs(CPUPPCState *env)
609 {
610 /* Thermal management */
611 /* XXX : not implemented */
612 spr_register(env, SPR_THRM1, "THRM1",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_thrm, &spr_write_generic,
615 0x00000000);
616 /* XXX : not implemented */
617 spr_register(env, SPR_THRM2, "THRM2",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_thrm, &spr_write_generic,
620 0x00000000);
621 /* XXX : not implemented */
622 spr_register(env, SPR_THRM3, "THRM3",
623 SPR_NOACCESS, SPR_NOACCESS,
624 &spr_read_thrm, &spr_write_generic,
625 0x00000000);
626 }
627
628 /* SPR specific to PowerPC 604 implementation */
629 static void register_604_sprs(CPUPPCState *env)
630 {
631 /* Processor identification */
632 spr_register(env, SPR_PIR, "PIR",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_generic, &spr_write_pir,
635 0x00000000);
636 /* Breakpoints */
637 /* XXX : not implemented */
638 spr_register(env, SPR_IABR, "IABR",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 /* XXX : not implemented */
643 spr_register_kvm(env, SPR_DABR, "DABR",
644 SPR_NOACCESS, SPR_NOACCESS,
645 &spr_read_generic, &spr_write_generic,
646 KVM_REG_PPC_DABR, 0x00000000);
647 /* Performance counters */
648 /* XXX : not implemented */
649 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
650 SPR_NOACCESS, SPR_NOACCESS,
651 &spr_read_generic, &spr_write_generic,
652 0x00000000);
653 /* XXX : not implemented */
654 spr_register(env, SPR_7XX_PMC1, "PMC1",
655 SPR_NOACCESS, SPR_NOACCESS,
656 &spr_read_generic, &spr_write_generic,
657 0x00000000);
658 /* XXX : not implemented */
659 spr_register(env, SPR_7XX_PMC2, "PMC2",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* XXX : not implemented */
664 spr_register(env, SPR_7XX_SIAR, "SIAR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, SPR_NOACCESS,
667 0x00000000);
668 /* XXX : not implemented */
669 spr_register(env, SPR_SDA, "SDA",
670 SPR_NOACCESS, SPR_NOACCESS,
671 &spr_read_generic, SPR_NOACCESS,
672 0x00000000);
673 /* External access control */
674 /* XXX : not implemented */
675 spr_register(env, SPR_EAR, "EAR",
676 SPR_NOACCESS, SPR_NOACCESS,
677 &spr_read_generic, &spr_write_generic,
678 0x00000000);
679 }
680
681 /* SPR specific to PowerPC 603 implementation */
682 static void register_603_sprs(CPUPPCState *env)
683 {
684 /* External access control */
685 /* XXX : not implemented */
686 spr_register(env, SPR_EAR, "EAR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 0x00000000);
690 /* Breakpoints */
691 /* XXX : not implemented */
692 spr_register(env, SPR_IABR, "IABR",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, &spr_write_generic,
695 0x00000000);
696
697 }
698
699 /* SPR specific to PowerPC G2 implementation */
700 static void register_G2_sprs(CPUPPCState *env)
701 {
702 /* Memory base address */
703 /* MBAR */
704 /* XXX : not implemented */
705 spr_register(env, SPR_MBAR, "MBAR",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 /* Exception processing */
710 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718 /* Breakpoints */
719 /* XXX : not implemented */
720 spr_register(env, SPR_DABR, "DABR",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724 /* XXX : not implemented */
725 spr_register(env, SPR_DABR2, "DABR2",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_generic,
728 0x00000000);
729 /* XXX : not implemented */
730 spr_register(env, SPR_IABR, "IABR",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734 /* XXX : not implemented */
735 spr_register(env, SPR_IABR2, "IABR2",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_generic, &spr_write_generic,
738 0x00000000);
739 /* XXX : not implemented */
740 spr_register(env, SPR_IBCR, "IBCR",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 /* XXX : not implemented */
745 spr_register(env, SPR_DBCR, "DBCR",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_generic, &spr_write_generic,
748 0x00000000);
749 }
750
751 /* SPR specific to PowerPC 602 implementation */
752 static void register_602_sprs(CPUPPCState *env)
753 {
754 /* ESA registers */
755 /* XXX : not implemented */
756 spr_register(env, SPR_SER, "SER",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_generic, &spr_write_generic,
759 0x00000000);
760 /* XXX : not implemented */
761 spr_register(env, SPR_SEBR, "SEBR",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_generic, &spr_write_generic,
764 0x00000000);
765 /* XXX : not implemented */
766 spr_register(env, SPR_ESASRR, "ESASRR",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_generic, &spr_write_generic,
769 0x00000000);
770 /* Floating point status */
771 /* XXX : not implemented */
772 spr_register(env, SPR_SP, "SP",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_generic, &spr_write_generic,
775 0x00000000);
776 /* XXX : not implemented */
777 spr_register(env, SPR_LT, "LT",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_generic, &spr_write_generic,
780 0x00000000);
781 /* Watchdog timer */
782 /* XXX : not implemented */
783 spr_register(env, SPR_TCR, "TCR",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_generic, &spr_write_generic,
786 0x00000000);
787 /* Interrupt base */
788 spr_register(env, SPR_IBR, "IBR",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, &spr_write_generic,
791 0x00000000);
792 /* XXX : not implemented */
793 spr_register(env, SPR_IABR, "IABR",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_generic, &spr_write_generic,
796 0x00000000);
797 }
798
799 /* SPR specific to PowerPC 601 implementation */
800 static void register_601_sprs(CPUPPCState *env)
801 {
802 /* Multiplication/division register */
803 /* MQ */
804 spr_register(env, SPR_MQ, "MQ",
805 &spr_read_generic, &spr_write_generic,
806 &spr_read_generic, &spr_write_generic,
807 0x00000000);
808 /* RTC registers */
809 spr_register(env, SPR_601_RTCU, "RTCU",
810 SPR_NOACCESS, SPR_NOACCESS,
811 SPR_NOACCESS, &spr_write_601_rtcu,
812 0x00000000);
813 spr_register(env, SPR_601_VRTCU, "RTCU",
814 &spr_read_601_rtcu, SPR_NOACCESS,
815 &spr_read_601_rtcu, SPR_NOACCESS,
816 0x00000000);
817 spr_register(env, SPR_601_RTCL, "RTCL",
818 SPR_NOACCESS, SPR_NOACCESS,
819 SPR_NOACCESS, &spr_write_601_rtcl,
820 0x00000000);
821 spr_register(env, SPR_601_VRTCL, "RTCL",
822 &spr_read_601_rtcl, SPR_NOACCESS,
823 &spr_read_601_rtcl, SPR_NOACCESS,
824 0x00000000);
825 /* Timer */
826 #if 0 /* ? */
827 spr_register(env, SPR_601_UDECR, "UDECR",
828 &spr_read_decr, SPR_NOACCESS,
829 &spr_read_decr, SPR_NOACCESS,
830 0x00000000);
831 #endif
832 /* External access control */
833 /* XXX : not implemented */
834 spr_register(env, SPR_EAR, "EAR",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_generic, &spr_write_generic,
837 0x00000000);
838 /* Memory management */
839 #if !defined(CONFIG_USER_ONLY)
840 spr_register(env, SPR_IBAT0U, "IBAT0U",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_601_ubat, &spr_write_601_ubatu,
843 0x00000000);
844 spr_register(env, SPR_IBAT0L, "IBAT0L",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_601_ubat, &spr_write_601_ubatl,
847 0x00000000);
848 spr_register(env, SPR_IBAT1U, "IBAT1U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_601_ubat, &spr_write_601_ubatu,
851 0x00000000);
852 spr_register(env, SPR_IBAT1L, "IBAT1L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_601_ubat, &spr_write_601_ubatl,
855 0x00000000);
856 spr_register(env, SPR_IBAT2U, "IBAT2U",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_601_ubat, &spr_write_601_ubatu,
859 0x00000000);
860 spr_register(env, SPR_IBAT2L, "IBAT2L",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_601_ubat, &spr_write_601_ubatl,
863 0x00000000);
864 spr_register(env, SPR_IBAT3U, "IBAT3U",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_601_ubat, &spr_write_601_ubatu,
867 0x00000000);
868 spr_register(env, SPR_IBAT3L, "IBAT3L",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_601_ubat, &spr_write_601_ubatl,
871 0x00000000);
872 env->nb_BATs = 4;
873 #endif
874 }
875
876 static void register_74xx_sprs(CPUPPCState *env)
877 {
878 /* Processor identification */
879 spr_register(env, SPR_PIR, "PIR",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_pir,
882 0x00000000);
883 /* XXX : not implemented */
884 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 /* XXX : not implemented */
889 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
890 &spr_read_ureg, SPR_NOACCESS,
891 &spr_read_ureg, SPR_NOACCESS,
892 0x00000000);
893 /* XXX: not implemented */
894 spr_register(env, SPR_BAMR, "BAMR",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
898 /* XXX : not implemented */
899 spr_register(env, SPR_MSSCR0, "MSSCR0",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, &spr_write_generic,
902 0x00000000);
903 /* Hardware implementation registers */
904 /* XXX : not implemented */
905 spr_register(env, SPR_HID0, "HID0",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_HID1, "HID1",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* Altivec */
915 spr_register(env, SPR_VRSAVE, "VRSAVE",
916 &spr_read_generic, &spr_write_generic,
917 &spr_read_generic, &spr_write_generic,
918 0x00000000);
919 /* XXX : not implemented */
920 spr_register(env, SPR_L2CR, "L2CR",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, spr_access_nop,
923 0x00000000);
924 }
925
926 static void register_l3_ctrl(CPUPPCState *env)
927 {
928 /* L3CR */
929 /* XXX : not implemented */
930 spr_register(env, SPR_L3CR, "L3CR",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, &spr_write_generic,
933 0x00000000);
934 /* L3ITCR0 */
935 /* XXX : not implemented */
936 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 /* L3PM */
941 /* XXX : not implemented */
942 spr_register(env, SPR_L3PM, "L3PM",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 }
947
948 static void register_usprg3_sprs(CPUPPCState *env)
949 {
950 spr_register(env, SPR_USPRG3, "USPRG3",
951 &spr_read_ureg, SPR_NOACCESS,
952 &spr_read_ureg, SPR_NOACCESS,
953 0x00000000);
954 }
955
956 static void register_usprgh_sprs(CPUPPCState *env)
957 {
958 spr_register(env, SPR_USPRG4, "USPRG4",
959 &spr_read_ureg, SPR_NOACCESS,
960 &spr_read_ureg, SPR_NOACCESS,
961 0x00000000);
962 spr_register(env, SPR_USPRG5, "USPRG5",
963 &spr_read_ureg, SPR_NOACCESS,
964 &spr_read_ureg, SPR_NOACCESS,
965 0x00000000);
966 spr_register(env, SPR_USPRG6, "USPRG6",
967 &spr_read_ureg, SPR_NOACCESS,
968 &spr_read_ureg, SPR_NOACCESS,
969 0x00000000);
970 spr_register(env, SPR_USPRG7, "USPRG7",
971 &spr_read_ureg, SPR_NOACCESS,
972 &spr_read_ureg, SPR_NOACCESS,
973 0x00000000);
974 }
975
976 /* PowerPC BookE SPR */
977 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
978 {
979 const char *ivor_names[64] = {
980 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
981 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
982 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
983 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
984 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
985 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
986 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
987 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
988 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
989 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
990 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
991 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
992 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
993 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
994 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
995 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
996 };
997 #define SPR_BOOKE_IVORxx (-1)
998 int ivor_sprn[64] = {
999 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1000 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1001 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1002 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1003 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1004 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1005 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1006 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1007 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1008 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1009 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1010 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1011 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1012 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1013 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1014 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1015 };
1016 int i;
1017
1018 /* Interrupt processing */
1019 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_generic,
1026 0x00000000);
1027 /* Debug */
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* XXX : not implemented */
1039 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_generic,
1042 0x00000000);
1043 /* XXX : not implemented */
1044 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 /* XXX : not implemented */
1049 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_generic, &spr_write_40x_dbcr0,
1052 0x00000000);
1053 /* XXX : not implemented */
1054 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1064 SPR_NOACCESS, SPR_NOACCESS,
1065 &spr_read_generic, &spr_write_generic,
1066 0x00000000);
1067 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071 /* XXX : not implemented */
1072 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_clear,
1075 0x00000000);
1076 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1077 SPR_NOACCESS, SPR_NOACCESS,
1078 &spr_read_generic, &spr_write_generic,
1079 0x00000000);
1080 spr_register(env, SPR_BOOKE_ESR, "ESR",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1085 SPR_NOACCESS, SPR_NOACCESS,
1086 &spr_read_generic, &spr_write_excp_prefix,
1087 0x00000000);
1088 /* Exception vectors */
1089 for (i = 0; i < 64; i++) {
1090 if (ivor_mask & (1ULL << i)) {
1091 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1092 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1093 exit(1);
1094 }
1095 spr_register(env, ivor_sprn[i], ivor_names[i],
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_excp_vector,
1098 0x00000000);
1099 }
1100 }
1101 spr_register(env, SPR_BOOKE_PID, "PID",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_generic, &spr_write_booke_pid,
1104 0x00000000);
1105 spr_register(env, SPR_BOOKE_TCR, "TCR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_booke_tcr,
1108 0x00000000);
1109 spr_register(env, SPR_BOOKE_TSR, "TSR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_booke_tsr,
1112 0x00000000);
1113 /* Timer */
1114 spr_register(env, SPR_DECR, "DECR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_decr, &spr_write_decr,
1117 0x00000000);
1118 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1119 SPR_NOACCESS, SPR_NOACCESS,
1120 SPR_NOACCESS, &spr_write_generic,
1121 0x00000000);
1122 /* SPRGs */
1123 spr_register(env, SPR_USPRG0, "USPRG0",
1124 &spr_read_generic, &spr_write_generic,
1125 &spr_read_generic, &spr_write_generic,
1126 0x00000000);
1127 spr_register(env, SPR_SPRG4, "SPRG4",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 spr_register(env, SPR_SPRG5, "SPRG5",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 spr_register(env, SPR_SPRG6, "SPRG6",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, &spr_write_generic,
1138 0x00000000);
1139 spr_register(env, SPR_SPRG7, "SPRG7",
1140 SPR_NOACCESS, SPR_NOACCESS,
1141 &spr_read_generic, &spr_write_generic,
1142 0x00000000);
1143 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1144 SPR_NOACCESS, SPR_NOACCESS,
1145 &spr_read_generic, &spr_write_generic,
1146 0x00000000);
1147 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 }
1152
1153 #if !defined(CONFIG_USER_ONLY)
1154 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
1155 uint32_t maxsize, uint32_t flags,
1156 uint32_t nentries)
1157 {
1158 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1159 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1160 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1161 flags | nentries;
1162 }
1163 #endif /* !CONFIG_USER_ONLY */
1164
1165 /* BookE 2.06 storage control registers */
1166 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
1167 uint32_t *tlbncfg, uint32_t mmucfg)
1168 {
1169 #if !defined(CONFIG_USER_ONLY)
1170 const char *mas_names[8] = {
1171 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1172 };
1173 int mas_sprn[8] = {
1174 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1175 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1176 };
1177 int i;
1178
1179 /* TLB assist registers */
1180 /* XXX : not implemented */
1181 for (i = 0; i < 8; i++) {
1182 if (mas_mask & (1 << i)) {
1183 spr_register(env, mas_sprn[i], mas_names[i],
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic,
1186 (i == 2 && (env->insns_flags & PPC_64B))
1187 ? &spr_write_generic : &spr_write_generic32,
1188 0x00000000);
1189 }
1190 }
1191 if (env->nb_pids > 1) {
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_BOOKE_PID1, "PID1",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_booke_pid,
1196 0x00000000);
1197 }
1198 if (env->nb_pids > 2) {
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_BOOKE_PID2, "PID2",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_booke_pid,
1203 0x00000000);
1204 }
1205
1206 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_eplc,
1209 0x00000000);
1210 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_epsc,
1213 0x00000000);
1214
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_MMUCFG, "MMUCFG",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, SPR_NOACCESS,
1219 mmucfg);
1220 switch (env->nb_ways) {
1221 case 4:
1222 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, SPR_NOACCESS,
1225 tlbncfg[3]);
1226 /* Fallthru */
1227 case 3:
1228 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, SPR_NOACCESS,
1231 tlbncfg[2]);
1232 /* Fallthru */
1233 case 2:
1234 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, SPR_NOACCESS,
1237 tlbncfg[1]);
1238 /* Fallthru */
1239 case 1:
1240 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, SPR_NOACCESS,
1243 tlbncfg[0]);
1244 /* Fallthru */
1245 case 0:
1246 default:
1247 break;
1248 }
1249 #endif
1250
1251 register_usprgh_sprs(env);
1252 }
1253
1254 /* SPR specific to PowerPC 440 implementation */
1255 static void register_440_sprs(CPUPPCState *env)
1256 {
1257 /* Cache control */
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_440_DNV0, "DNV0",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_440_DNV1, "DNV1",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_440_DNV2, "DNV2",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_440_DNV3, "DNV3",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 /* XXX : not implemented */
1279 spr_register(env, SPR_440_DTV0, "DTV0",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 0x00000000);
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_440_DTV1, "DTV1",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_440_DTV2, "DTV2",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_440_DTV3, "DTV3",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_440_DVLIM, "DVLIM",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_440_INV0, "INV0",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_440_INV1, "INV1",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_440_INV2, "INV2",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_440_INV3, "INV3",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_440_ITV0, "ITV0",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_440_ITV1, "ITV1",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* XXX : not implemented */
1334 spr_register(env, SPR_440_ITV2, "ITV2",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_440_ITV3, "ITV3",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_440_IVLIM, "IVLIM",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* Cache debug */
1349 /* XXX : not implemented */
1350 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, SPR_NOACCESS,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, SPR_NOACCESS,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, SPR_NOACCESS,
1363 0x00000000);
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, SPR_NOACCESS,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, SPR_NOACCESS,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_440_DBDR, "DBDR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* Processor control */
1380 spr_register(env, SPR_4xx_CCR0, "CCR0",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, SPR_NOACCESS,
1387 0x00000000);
1388 /* Storage control */
1389 spr_register(env, SPR_440_MMUCR, "MMUCR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 }
1394
1395 /* SPR shared between PowerPC 40x implementations */
1396 static void register_40x_sprs(CPUPPCState *env)
1397 {
1398 /* Cache */
1399 /* not emulated, as QEMU do not emulate caches */
1400 spr_register(env, SPR_40x_DCCR, "DCCR",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404 /* not emulated, as QEMU do not emulate caches */
1405 spr_register(env, SPR_40x_ICCR, "ICCR",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_generic,
1408 0x00000000);
1409 /* not emulated, as QEMU do not emulate caches */
1410 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1411 SPR_NOACCESS, SPR_NOACCESS,
1412 &spr_read_generic, SPR_NOACCESS,
1413 0x00000000);
1414 /* Exception */
1415 spr_register(env, SPR_40x_DEAR, "DEAR",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 spr_register(env, SPR_40x_ESR, "ESR",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 spr_register(env, SPR_40x_EVPR, "EVPR",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_generic, &spr_write_excp_prefix,
1426 0x00000000);
1427 spr_register(env, SPR_40x_SRR2, "SRR2",
1428 &spr_read_generic, &spr_write_generic,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431 spr_register(env, SPR_40x_SRR3, "SRR3",
1432 &spr_read_generic, &spr_write_generic,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 /* Timers */
1436 spr_register(env, SPR_40x_PIT, "PIT",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_40x_pit, &spr_write_40x_pit,
1439 0x00000000);
1440 spr_register(env, SPR_40x_TCR, "TCR",
1441 SPR_NOACCESS, SPR_NOACCESS,
1442 &spr_read_generic, &spr_write_booke_tcr,
1443 0x00000000);
1444 spr_register(env, SPR_40x_TSR, "TSR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_booke_tsr,
1447 0x00000000);
1448 }
1449
1450 /* SPR specific to PowerPC 405 implementation */
1451 static void register_405_sprs(CPUPPCState *env)
1452 {
1453 /* MMU */
1454 spr_register(env, SPR_40x_PID, "PID",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 spr_register(env, SPR_4xx_CCR0, "CCR0",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_generic, &spr_write_generic,
1461 0x00700000);
1462 /* Debug interface */
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_40x_dbcr0,
1467 0x00000000);
1468 /* XXX : not implemented */
1469 spr_register(env, SPR_405_DBCR1, "DBCR1",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_40x_DBSR, "DBSR",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_clear,
1477 /* Last reset was system reset */
1478 0x00000300);
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_40x_DAC1, "DAC1",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 spr_register(env, SPR_40x_DAC2, "DAC2",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_405_DVC1, "DVC1",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_405_DVC2, "DVC2",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_generic,
1497 0x00000000);
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_40x_IAC1, "IAC1",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
1503 spr_register(env, SPR_40x_IAC2, "IAC2",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507 /* XXX : not implemented */
1508 spr_register(env, SPR_405_IAC3, "IAC3",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512 /* XXX : not implemented */
1513 spr_register(env, SPR_405_IAC4, "IAC4",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
1517 /* Storage control */
1518 /* XXX: TODO: not implemented */
1519 spr_register(env, SPR_405_SLER, "SLER",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_40x_sler,
1522 0x00000000);
1523 spr_register(env, SPR_40x_ZPR, "ZPR",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_405_SU0R, "SU0R",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* SPRG */
1533 spr_register(env, SPR_USPRG0, "USPRG0",
1534 &spr_read_ureg, SPR_NOACCESS,
1535 &spr_read_ureg, SPR_NOACCESS,
1536 0x00000000);
1537 spr_register(env, SPR_SPRG4, "SPRG4",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 &spr_read_generic, &spr_write_generic,
1540 0x00000000);
1541 spr_register(env, SPR_SPRG5, "SPRG5",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 spr_register(env, SPR_SPRG6, "SPRG6",
1546 SPR_NOACCESS, SPR_NOACCESS,
1547 spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 spr_register(env, SPR_SPRG7, "SPRG7",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 register_usprgh_sprs(env);
1554 }
1555
1556
1557 static void register_5xx_8xx_sprs(CPUPPCState *env)
1558 {
1559 /* Exception processing */
1560 spr_register_kvm(env, SPR_DSISR, "DSISR",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 KVM_REG_PPC_DSISR, 0x00000000);
1564 spr_register_kvm(env, SPR_DAR, "DAR",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_generic,
1567 KVM_REG_PPC_DAR, 0x00000000);
1568 /* Timer */
1569 spr_register(env, SPR_DECR, "DECR",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_decr, &spr_write_decr,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_MPC_EIE, "EIE",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_MPC_EID, "EID",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_generic,
1582 0x00000000);
1583 /* XXX : not implemented */
1584 spr_register(env, SPR_MPC_NRI, "NRI",
1585 SPR_NOACCESS, SPR_NOACCESS,
1586 &spr_read_generic, &spr_write_generic,
1587 0x00000000);
1588 /* XXX : not implemented */
1589 spr_register(env, SPR_MPC_CMPA, "CMPA",
1590 SPR_NOACCESS, SPR_NOACCESS,
1591 &spr_read_generic, &spr_write_generic,
1592 0x00000000);
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_MPC_CMPB, "CMPB",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_MPC_CMPC, "CMPC",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_MPC_CMPD, "CMPD",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 /* XXX : not implemented */
1609 spr_register(env, SPR_MPC_ECR, "ECR",
1610 SPR_NOACCESS, SPR_NOACCESS,
1611 &spr_read_generic, &spr_write_generic,
1612 0x00000000);
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_MPC_DER, "DER",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, &spr_write_generic,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_MPC_CMPE, "CMPE",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_MPC_CMPF, "CMPF",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 /* XXX : not implemented */
1639 spr_register(env, SPR_MPC_CMPG, "CMPG",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* XXX : not implemented */
1644 spr_register(env, SPR_MPC_CMPH, "CMPH",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 /* XXX : not implemented */
1649 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1650 SPR_NOACCESS, SPR_NOACCESS,
1651 &spr_read_generic, &spr_write_generic,
1652 0x00000000);
1653 /* XXX : not implemented */
1654 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1655 SPR_NOACCESS, SPR_NOACCESS,
1656 &spr_read_generic, &spr_write_generic,
1657 0x00000000);
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_MPC_BAR, "BAR",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_MPC_DPDR, "DPDR",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_MPC_IMMR, "IMMR",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 }
1674
1675 static void register_5xx_sprs(CPUPPCState *env)
1676 {
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_generic,
1701 0x00000000);
1702 /* XXX : not implemented */
1703 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1704 SPR_NOACCESS, SPR_NOACCESS,
1705 &spr_read_generic, &spr_write_generic,
1706 0x00000000);
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_generic,
1711 0x00000000);
1712 /* XXX : not implemented */
1713 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 /* XXX : not implemented */
1718 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* XXX : not implemented */
1723 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, &spr_write_generic,
1726 0x00000000);
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 }
1783
1784 static void register_8xx_sprs(CPUPPCState *env)
1785 {
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* XXX : not implemented */
1822 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 /* XXX : not implemented */
1827 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 /* XXX : not implemented */
1847 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1848 SPR_NOACCESS, SPR_NOACCESS,
1849 &spr_read_generic, &spr_write_generic,
1850 0x00000000);
1851 /* XXX : not implemented */
1852 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1853 SPR_NOACCESS, SPR_NOACCESS,
1854 &spr_read_generic, &spr_write_generic,
1855 0x00000000);
1856 /* XXX : not implemented */
1857 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1858 SPR_NOACCESS, SPR_NOACCESS,
1859 &spr_read_generic, &spr_write_generic,
1860 0x00000000);
1861 /* XXX : not implemented */
1862 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 /* XXX : not implemented */
1872 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 /* XXX : not implemented */
1882 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 /* XXX : not implemented */
1897 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_generic,
1900 0x00000000);
1901 /* XXX : not implemented */
1902 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 }
1912
1913 /*
1914 * AMR => SPR 29 (Power 2.04)
1915 * CTRL => SPR 136 (Power 2.04)
1916 * CTRL => SPR 152 (Power 2.04)
1917 * SCOMC => SPR 276 (64 bits ?)
1918 * SCOMD => SPR 277 (64 bits ?)
1919 * TBU40 => SPR 286 (Power 2.04 hypv)
1920 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1921 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1922 * HDSISR => SPR 306 (Power 2.04 hypv)
1923 * HDAR => SPR 307 (Power 2.04 hypv)
1924 * PURR => SPR 309 (Power 2.04 hypv)
1925 * HDEC => SPR 310 (Power 2.04 hypv)
1926 * HIOR => SPR 311 (hypv)
1927 * RMOR => SPR 312 (970)
1928 * HRMOR => SPR 313 (Power 2.04 hypv)
1929 * HSRR0 => SPR 314 (Power 2.04 hypv)
1930 * HSRR1 => SPR 315 (Power 2.04 hypv)
1931 * LPIDR => SPR 317 (970)
1932 * EPR => SPR 702 (Power 2.04 emb)
1933 * perf => 768-783 (Power 2.04)
1934 * perf => 784-799 (Power 2.04)
1935 * PPR => SPR 896 (Power 2.04)
1936 * DABRX => 1015 (Power 2.04 hypv)
1937 * FPECR => SPR 1022 (?)
1938 * ... and more (thermal management, performance counters, ...)
1939 */
1940
1941 /*****************************************************************************/
1942 /* Exception vectors models */
1943 static void init_excp_4xx_softmmu(CPUPPCState *env)
1944 {
1945 #if !defined(CONFIG_USER_ONLY)
1946 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1947 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1948 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1949 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1950 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1951 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1952 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1953 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1954 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1955 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1956 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1957 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1958 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1959 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1960 env->ivor_mask = 0x0000FFF0UL;
1961 env->ivpr_mask = 0xFFFF0000UL;
1962 /* Hardware reset vector */
1963 env->hreset_vector = 0xFFFFFFFCUL;
1964 #endif
1965 }
1966
1967 static void init_excp_MPC5xx(CPUPPCState *env)
1968 {
1969 #if !defined(CONFIG_USER_ONLY)
1970 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1971 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1972 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1973 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1974 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1975 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1976 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1977 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1978 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1979 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1980 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1981 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1983 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1984 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1985 env->ivor_mask = 0x0000FFF0UL;
1986 env->ivpr_mask = 0xFFFF0000UL;
1987 /* Hardware reset vector */
1988 env->hreset_vector = 0x00000100UL;
1989 #endif
1990 }
1991
1992 static void init_excp_MPC8xx(CPUPPCState *env)
1993 {
1994 #if !defined(CONFIG_USER_ONLY)
1995 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1996 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1997 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1998 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1999 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2000 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2001 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2002 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2003 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2004 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2005 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2006 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2007 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2008 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2009 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2010 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2011 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2012 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2013 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2014 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2015 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2016 env->ivor_mask = 0x0000FFF0UL;
2017 env->ivpr_mask = 0xFFFF0000UL;
2018 /* Hardware reset vector */
2019 env->hreset_vector = 0x00000100UL;
2020 #endif
2021 }
2022
2023 static void init_excp_G2(CPUPPCState *env)
2024 {
2025 #if !defined(CONFIG_USER_ONLY)
2026 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2027 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2028 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2029 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2030 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2031 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2032 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2033 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2034 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2035 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2036 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2037 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2038 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2039 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2040 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2041 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2042 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2043 /* Hardware reset vector */
2044 env->hreset_vector = 0x00000100UL;
2045 #endif
2046 }
2047
2048 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2049 {
2050 #if !defined(CONFIG_USER_ONLY)
2051 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2052 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2053 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2054 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2055 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2056 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2057 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2058 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2059 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2060 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2061 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2062 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2063 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2064 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2065 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2066 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2067 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2068 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2069 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2070 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2071 env->ivor_mask = 0x0000FFF7UL;
2072 env->ivpr_mask = ivpr_mask;
2073 /* Hardware reset vector */
2074 env->hreset_vector = 0xFFFFFFFCUL;
2075 #endif
2076 }
2077
2078 static void init_excp_BookE(CPUPPCState *env)
2079 {
2080 #if !defined(CONFIG_USER_ONLY)
2081 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2082 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2083 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2084 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2085 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2086 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2087 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2088 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2089 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2090 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2091 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2092 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2093 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2094 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2095 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2096 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2097 env->ivor_mask = 0x0000FFF0UL;
2098 env->ivpr_mask = 0xFFFF0000UL;
2099 /* Hardware reset vector */
2100 env->hreset_vector = 0xFFFFFFFCUL;
2101 #endif
2102 }
2103
2104 static void init_excp_601(CPUPPCState *env)
2105 {
2106 #if !defined(CONFIG_USER_ONLY)
2107 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2108 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2109 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2110 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2111 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2112 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2113 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2114 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2115 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2116 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2117 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2118 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2119 /* Hardware reset vector */
2120 env->hreset_vector = 0x00000100UL;
2121 #endif
2122 }
2123
2124 static void init_excp_602(CPUPPCState *env)
2125 {
2126 #if !defined(CONFIG_USER_ONLY)
2127 /* XXX: exception prefix has a special behavior on 602 */
2128 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2129 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2130 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2131 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2132 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2133 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2134 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2135 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2136 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2137 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2138 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2139 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2140 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2141 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2142 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2143 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2144 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2145 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2146 /* Hardware reset vector */
2147 env->hreset_vector = 0x00000100UL;
2148 #endif
2149 }
2150
2151 static void init_excp_603(CPUPPCState *env)
2152 {
2153 #if !defined(CONFIG_USER_ONLY)
2154 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2155 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2156 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2157 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2158 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2159 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2160 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2161 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2162 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2163 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2164 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2165 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2166 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2167 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2168 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2169 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2170 /* Hardware reset vector */
2171 env->hreset_vector = 0x00000100UL;
2172 #endif
2173 }
2174
2175 static void init_excp_604(CPUPPCState *env)
2176 {
2177 #if !defined(CONFIG_USER_ONLY)
2178 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2179 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2180 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2181 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2182 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2183 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2184 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2185 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2186 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2187 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2188 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2189 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2190 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2191 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2192 /* Hardware reset vector */
2193 env->hreset_vector = 0x00000100UL;
2194 #endif
2195 }
2196
2197 static void init_excp_7x0(CPUPPCState *env)
2198 {
2199 #if !defined(CONFIG_USER_ONLY)
2200 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2201 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2202 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2203 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2204 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2205 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2206 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2207 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2208 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2212 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2213 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2214 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2215 /* Hardware reset vector */
2216 env->hreset_vector = 0x00000100UL;
2217 #endif
2218 }
2219
2220 static void init_excp_750cl(CPUPPCState *env)
2221 {
2222 #if !defined(CONFIG_USER_ONLY)
2223 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2224 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2225 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2226 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2227 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2228 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2229 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2230 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2231 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2232 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2233 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2234 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2235 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2236 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2237 /* Hardware reset vector */
2238 env->hreset_vector = 0x00000100UL;
2239 #endif
2240 }
2241
2242 static void init_excp_750cx(CPUPPCState *env)
2243 {
2244 #if !defined(CONFIG_USER_ONLY)
2245 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2246 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2247 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2248 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2249 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2250 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2251 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2252 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2253 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2254 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2255 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2256 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2257 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2258 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2259 /* Hardware reset vector */
2260 env->hreset_vector = 0x00000100UL;
2261 #endif
2262 }
2263
2264 /* XXX: Check if this is correct */
2265 static void init_excp_7x5(CPUPPCState *env)
2266 {
2267 #if !defined(CONFIG_USER_ONLY)
2268 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2269 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2270 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2271 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2272 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2273 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2274 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2275 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2276 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2277 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2278 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2279 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2280 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2281 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2282 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2283 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2284 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2285 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2286 /* Hardware reset vector */
2287 env->hreset_vector = 0x00000100UL;
2288 #endif
2289 }
2290
2291 static void init_excp_7400(CPUPPCState *env)
2292 {
2293 #if !defined(CONFIG_USER_ONLY)
2294 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2295 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2296 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2297 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2298 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2299 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2300 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2301 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2302 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2303 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2304 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2305 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2306 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2307 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2308 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2309 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2310 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2311 /* Hardware reset vector */
2312 env->hreset_vector = 0x00000100UL;
2313 #endif
2314 }
2315
2316 static void init_excp_7450(CPUPPCState *env)
2317 {
2318 #if !defined(CONFIG_USER_ONLY)
2319 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2320 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2321 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2322 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2323 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2324 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2325 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2326 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2327 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2328 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2329 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2330 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2331 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2332 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2333 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2334 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2335 /* Hardware reset vector */
2336 env->hreset_vector = 0x00000100UL;
2337 #endif
2338 }
2339
2340 #if defined(TARGET_PPC64)
2341 static void init_excp_970(CPUPPCState *env)
2342 {
2343 #if !defined(CONFIG_USER_ONLY)
2344 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2345 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2346 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2347 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2348 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2349 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2350 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2351 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2352 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2353 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2354 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2355 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2356 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2357 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2358 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2359 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2360 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2361 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2362 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2363 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2364 /* Hardware reset vector */
2365 env->hreset_vector = 0x0000000000000100ULL;
2366 #endif
2367 }
2368
2369 static void init_excp_POWER7(CPUPPCState *env)
2370 {
2371 #if !defined(CONFIG_USER_ONLY)
2372 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2373 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2374 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2375 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2376 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2377 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2378 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2379 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2380 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2381 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2382 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2383 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2384 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2385 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2386 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2387 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2388 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2389 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2390 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2391 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2392 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2393 /* Hardware reset vector */
2394 env->hreset_vector = 0x0000000000000100ULL;
2395 #endif
2396 }
2397
2398 static void init_excp_POWER8(CPUPPCState *env)
2399 {
2400 init_excp_POWER7(env);
2401
2402 #if !defined(CONFIG_USER_ONLY)
2403 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2404 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2405 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2406 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2407 #endif
2408 }
2409
2410 static void init_excp_POWER9(CPUPPCState *env)
2411 {
2412 init_excp_POWER8(env);
2413
2414 #if !defined(CONFIG_USER_ONLY)
2415 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2416 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2417 #endif
2418 }
2419
2420 static void init_excp_POWER10(CPUPPCState *env)
2421 {
2422 init_excp_POWER9(env);
2423 }
2424
2425 #endif
2426
2427 /*****************************************************************************/
2428 /* Power management enable checks */
2429 static int check_pow_none(CPUPPCState *env)
2430 {
2431 return 0;
2432 }
2433
2434 static int check_pow_nocheck(CPUPPCState *env)
2435 {
2436 return 1;
2437 }
2438
2439 static int check_pow_hid0(CPUPPCState *env)
2440 {
2441 if (env->spr[SPR_HID0] & 0x00E00000) {
2442 return 1;
2443 }
2444
2445 return 0;
2446 }
2447
2448 static int check_pow_hid0_74xx(CPUPPCState *env)
2449 {
2450 if (env->spr[SPR_HID0] & 0x00600000) {
2451 return 1;
2452 }
2453
2454 return 0;
2455 }
2456
2457 /*****************************************************************************/
2458 /* PowerPC implementations definitions */
2459
2460 #define POWERPC_FAMILY(_name) \
2461 static void \
2462 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
2463 \
2464 static const TypeInfo \
2465 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
2466 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
2467 .parent = TYPE_POWERPC_CPU, \
2468 .abstract = true, \
2469 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
2470 }; \
2471 \
2472 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
2473 { \
2474 type_register_static( \
2475 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
2476 } \
2477 \
2478 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
2479 \
2480 static void glue(glue(ppc_, _name), _cpu_family_class_init)
2481
2482 static void init_proc_405(CPUPPCState *env)
2483 {
2484 /* Time base */
2485 register_tbl(env);
2486 register_40x_sprs(env);
2487 register_405_sprs(env);
2488 /* Bus access control */
2489 /* not emulated, as QEMU never does speculative access */
2490 spr_register(env, SPR_40x_SGR, "SGR",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0xFFFFFFFF);
2494 /* not emulated, as QEMU do not emulate caches */
2495 spr_register(env, SPR_40x_DCWR, "DCWR",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* Memory management */
2500 #if !defined(CONFIG_USER_ONLY)
2501 env->nb_tlb = 64;
2502 env->nb_ways = 1;
2503 env->id_tlbs = 0;
2504 env->tlb_type = TLB_EMB;
2505 #endif
2506 init_excp_4xx_softmmu(env);
2507 env->dcache_line_size = 32;
2508 env->icache_line_size = 32;
2509 /* Allocate hardware IRQ controller */
2510 ppc40x_irq_init(env_archcpu(env));
2511
2512 SET_FIT_PERIOD(8, 12, 16, 20);
2513 SET_WDT_PERIOD(16, 20, 24, 28);
2514 }
2515
2516 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2517 {
2518 DeviceClass *dc = DEVICE_CLASS(oc);
2519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2520
2521 dc->desc = "PowerPC 405";
2522 pcc->init_proc = init_proc_405;
2523 pcc->check_pow = check_pow_nocheck;
2524 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2525 PPC_DCR | PPC_WRTEE |
2526 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2527 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2528 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2529 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2530 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2531 pcc->msr_mask = (1ull << MSR_POW) |
2532 (1ull << MSR_CE) |
2533 (1ull << MSR_EE) |
2534 (1ull << MSR_PR) |
2535 (1ull << MSR_FP) |
2536 (1ull << MSR_DWE) |
2537 (1ull << MSR_DE) |
2538 (1ull << MSR_IR) |
2539 (1ull << MSR_DR);
2540 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2541 pcc->excp_model = POWERPC_EXCP_40x;
2542 pcc->bus_model = PPC_FLAGS_INPUT_405;
2543 pcc->bfd_mach = bfd_mach_ppc_403;
2544 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2545 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2546 }
2547
2548 static void init_proc_440EP(CPUPPCState *env)
2549 {
2550 /* Time base */
2551 register_tbl(env);
2552 register_BookE_sprs(env, 0x000000000000FFFFULL);
2553 register_440_sprs(env);
2554 register_usprgh_sprs(env);
2555 /* Processor identification */
2556 spr_register(env, SPR_BOOKE_PIR, "PIR",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_pir,
2559 0x00000000);
2560 /* XXX : not implemented */
2561 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2562 SPR_NOACCESS, SPR_NOACCESS,
2563 &spr_read_generic, &spr_write_generic,
2564 0x00000000);
2565 /* XXX : not implemented */
2566 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2567 SPR_NOACCESS, SPR_NOACCESS,
2568 &spr_read_generic, &spr_write_generic,
2569 0x00000000);
2570 /* XXX : not implemented */
2571 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2572 SPR_NOACCESS, SPR_NOACCESS,
2573 &spr_read_generic, &spr_write_generic,
2574 0x00000000);
2575 /* XXX : not implemented */
2576 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2577 SPR_NOACCESS, SPR_NOACCESS,
2578 &spr_read_generic, &spr_write_generic,
2579 0x00000000);
2580 /* XXX : not implemented */
2581 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2582 SPR_NOACCESS, SPR_NOACCESS,
2583 &spr_read_generic, &spr_write_generic,
2584 0x00000000);
2585 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_440_CCR1, "CCR1",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* Memory management */
2599 #if !defined(CONFIG_USER_ONLY)
2600 env->nb_tlb = 64;
2601 env->nb_ways = 1;
2602 env->id_tlbs = 0;
2603 env->tlb_type = TLB_EMB;
2604 #endif
2605 init_excp_BookE(env);
2606 env->dcache_line_size = 32;
2607 env->icache_line_size = 32;
2608 ppc40x_irq_init(env_archcpu(env));
2609
2610 SET_FIT_PERIOD(12, 16, 20, 24);
2611 SET_WDT_PERIOD(20, 24, 28, 32);
2612 }
2613
2614 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2615 {
2616 DeviceClass *dc = DEVICE_CLASS(oc);
2617 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2618
2619 dc->desc = "PowerPC 440 EP";
2620 pcc->init_proc = init_proc_440EP;
2621 pcc->check_pow = check_pow_nocheck;
2622 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2623 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2624 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2625 PPC_FLOAT_STFIWX |
2626 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2627 PPC_CACHE | PPC_CACHE_ICBI |
2628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2629 PPC_MEM_TLBSYNC | PPC_MFTB |
2630 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2631 PPC_440_SPEC;
2632 pcc->msr_mask = (1ull << MSR_POW) |
2633 (1ull << MSR_CE) |
2634 (1ull << MSR_EE) |
2635 (1ull << MSR_PR) |
2636 (1ull << MSR_FP) |
2637 (1ull << MSR_ME) |
2638 (1ull << MSR_FE0) |
2639 (1ull << MSR_DWE) |
2640 (1ull << MSR_DE) |
2641 (1ull << MSR_FE1) |
2642 (1ull << MSR_IR) |
2643 (1ull << MSR_DR);
2644 pcc->mmu_model = POWERPC_MMU_BOOKE;
2645 pcc->excp_model = POWERPC_EXCP_BOOKE;
2646 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2647 pcc->bfd_mach = bfd_mach_ppc_403;
2648 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2649 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2650 }
2651
2652 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2653 {
2654 DeviceClass *dc = DEVICE_CLASS(oc);
2655 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2656
2657 dc->desc = "PowerPC 460 EX";
2658 pcc->init_proc = init_proc_440EP;
2659 pcc->check_pow = check_pow_nocheck;
2660 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2661 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2662 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2663 PPC_FLOAT_STFIWX |
2664 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2665 PPC_CACHE | PPC_CACHE_ICBI |
2666 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2667 PPC_MEM_TLBSYNC | PPC_MFTB |
2668 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2669 PPC_440_SPEC;
2670 pcc->msr_mask = (1ull << MSR_POW) |
2671 (1ull << MSR_CE) |
2672 (1ull << MSR_EE) |
2673 (1ull << MSR_PR) |
2674 (1ull << MSR_FP) |
2675 (1ull << MSR_ME) |
2676 (1ull << MSR_FE0) |
2677 (1ull << MSR_DWE) |
2678 (1ull << MSR_DE) |
2679 (1ull << MSR_FE1) |
2680 (1ull << MSR_IR) |
2681 (1ull << MSR_DR);
2682 pcc->mmu_model = POWERPC_MMU_BOOKE;
2683 pcc->excp_model = POWERPC_EXCP_BOOKE;
2684 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2685 pcc->bfd_mach = bfd_mach_ppc_403;
2686 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2687 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2688 }
2689
2690 static void init_proc_440GP(CPUPPCState *env)
2691 {
2692 /* Time base */
2693 register_tbl(env);
2694 register_BookE_sprs(env, 0x000000000000FFFFULL);
2695 register_440_sprs(env);
2696 register_usprgh_sprs(env);
2697 /* Processor identification */
2698 spr_register(env, SPR_BOOKE_PIR, "PIR",
2699 SPR_NOACCESS, SPR_NOACCESS,
2700 &spr_read_generic, &spr_write_pir,
2701 0x00000000);
2702 /* XXX : not implemented */
2703 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2704 SPR_NOACCESS, SPR_NOACCESS,
2705 &spr_read_generic, &spr_write_generic,
2706 0x00000000);
2707 /* XXX : not implemented */
2708 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2709 SPR_NOACCESS, SPR_NOACCESS,
2710 &spr_read_generic, &spr_write_generic,
2711 0x00000000);
2712 /* XXX : not implemented */
2713 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2714 SPR_NOACCESS, SPR_NOACCESS,
2715 &spr_read_generic, &spr_write_generic,
2716 0x00000000);
2717 /* XXX : not implemented */
2718 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2719 SPR_NOACCESS, SPR_NOACCESS,
2720 &spr_read_generic, &spr_write_generic,
2721 0x00000000);
2722 /* Memory management */
2723 #if !defined(CONFIG_USER_ONLY)
2724 env->nb_tlb = 64;
2725 env->nb_ways = 1;
2726 env->id_tlbs = 0;
2727 env->tlb_type = TLB_EMB;
2728 #endif
2729 init_excp_BookE(env);
2730 env->dcache_line_size = 32;
2731 env->icache_line_size = 32;
2732 /* XXX: TODO: allocate internal IRQ controller */
2733
2734 SET_FIT_PERIOD(12, 16, 20, 24);
2735 SET_WDT_PERIOD(20, 24, 28, 32);
2736 }
2737
2738 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2739 {
2740 DeviceClass *dc = DEVICE_CLASS(oc);
2741 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2742
2743 dc->desc = "PowerPC 440 GP";
2744 pcc->init_proc = init_proc_440GP;
2745 pcc->check_pow = check_pow_nocheck;
2746 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2747 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2748 PPC_CACHE | PPC_CACHE_ICBI |
2749 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2750 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2751 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2752 PPC_440_SPEC;
2753 pcc->msr_mask = (1ull << MSR_POW) |
2754 (1ull << MSR_CE) |
2755 (1ull << MSR_EE) |
2756 (1ull << MSR_PR) |
2757 (1ull << MSR_FP) |
2758 (1ull << MSR_ME) |
2759 (1ull << MSR_FE0) |
2760 (1ull << MSR_DWE) |
2761 (1ull << MSR_DE) |
2762 (1ull << MSR_FE1) |
2763 (1ull << MSR_IR) |
2764 (1ull << MSR_DR);
2765 pcc->mmu_model = POWERPC_MMU_BOOKE;
2766 pcc->excp_model = POWERPC_EXCP_BOOKE;
2767 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2768 pcc->bfd_mach = bfd_mach_ppc_403;
2769 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2770 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2771 }
2772
2773 static void init_proc_440x4(CPUPPCState *env)
2774 {
2775 /* Time base */
2776 register_tbl(env);
2777 register_BookE_sprs(env, 0x000000000000FFFFULL);
2778 register_440_sprs(env);
2779 register_usprgh_sprs(env);
2780 /* Processor identification */
2781 spr_register(env, SPR_BOOKE_PIR, "PIR",
2782 SPR_NOACCESS, SPR_NOACCESS,
2783 &spr_read_generic, &spr_write_pir,
2784 0x00000000);
2785 /* XXX : not implemented */
2786 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2787 SPR_NOACCESS, SPR_NOACCESS,
2788 &spr_read_generic, &spr_write_generic,
2789 0x00000000);
2790 /* XXX : not implemented */
2791 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2792 SPR_NOACCESS, SPR_NOACCESS,
2793 &spr_read_generic, &spr_write_generic,
2794 0x00000000);
2795 /* XXX : not implemented */
2796 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2797 SPR_NOACCESS, SPR_NOACCESS,
2798 &spr_read_generic, &spr_write_generic,
2799 0x00000000);
2800 /* XXX : not implemented */
2801 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2802 SPR_NOACCESS, SPR_NOACCESS,
2803 &spr_read_generic, &spr_write_generic,
2804 0x00000000);
2805 /* Memory management */
2806 #if !defined(CONFIG_USER_ONLY)
2807 env->nb_tlb = 64;
2808 env->nb_ways = 1;
2809 env->id_tlbs = 0;
2810 env->tlb_type = TLB_EMB;
2811 #endif
2812 init_excp_BookE(env);
2813 env->dcache_line_size = 32;
2814 env->icache_line_size = 32;
2815 /* XXX: TODO: allocate internal IRQ controller */
2816
2817 SET_FIT_PERIOD(12, 16, 20, 24);
2818 SET_WDT_PERIOD(20, 24, 28, 32);
2819 }
2820
2821 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
2822 {
2823 DeviceClass *dc = DEVICE_CLASS(oc);
2824 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2825
2826 dc->desc = "PowerPC 440x4";
2827 pcc->init_proc = init_proc_440x4;
2828 pcc->check_pow = check_pow_nocheck;
2829 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2830 PPC_DCR | PPC_WRTEE |
2831 PPC_CACHE | PPC_CACHE_ICBI |
2832 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2833 PPC_MEM_TLBSYNC | PPC_MFTB |
2834 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2835 PPC_440_SPEC;
2836 pcc->msr_mask = (1ull << MSR_POW) |
2837 (1ull << MSR_CE) |
2838 (1ull << MSR_EE) |
2839 (1ull << MSR_PR) |
2840 (1ull << MSR_FP) |
2841 (1ull << MSR_ME) |
2842 (1ull << MSR_FE0) |
2843 (1ull << MSR_DWE) |
2844 (1ull << MSR_DE) |
2845 (1ull << MSR_FE1) |
2846 (1ull << MSR_IR) |
2847 (1ull << MSR_DR);
2848 pcc->mmu_model = POWERPC_MMU_BOOKE;
2849 pcc->excp_model = POWERPC_EXCP_BOOKE;
2850 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2851 pcc->bfd_mach = bfd_mach_ppc_403;
2852 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2853 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2854 }
2855
2856 static void init_proc_440x5(CPUPPCState *env)
2857 {
2858 /* Time base */
2859 register_tbl(env);
2860 register_BookE_sprs(env, 0x000000000000FFFFULL);
2861 register_440_sprs(env);
2862 register_usprgh_sprs(env);
2863 /* Processor identification */
2864 spr_register(env, SPR_BOOKE_PIR, "PIR",
2865 SPR_NOACCESS, SPR_NOACCESS,
2866 &spr_read_generic, &spr_write_pir,
2867 0x00000000);
2868 /* XXX : not implemented */
2869 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2870 SPR_NOACCESS, SPR_NOACCESS,
2871 &spr_read_generic, &spr_write_generic,
2872 0x00000000);
2873 /* XXX : not implemented */
2874 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2875 SPR_NOACCESS, SPR_NOACCESS,
2876 &spr_read_generic, &spr_write_generic,
2877 0x00000000);
2878 /* XXX : not implemented */
2879 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
2880 SPR_NOACCESS, SPR_NOACCESS,
2881 &spr_read_generic, &spr_write_generic,
2882 0x00000000);
2883 /* XXX : not implemented */
2884 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
2885 SPR_NOACCESS, SPR_NOACCESS,
2886 &spr_read_generic, &spr_write_generic,
2887 0x00000000);
2888 /* XXX : not implemented */
2889 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2890 SPR_NOACCESS, SPR_NOACCESS,
2891 &spr_read_generic, &spr_write_generic,
2892 0x00000000);
2893 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2894 SPR_NOACCESS, SPR_NOACCESS,
2895 &spr_read_generic, &spr_write_generic,
2896 0x00000000);
2897 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2898 SPR_NOACCESS, SPR_NOACCESS,
2899 &spr_read_generic, &spr_write_generic,
2900 0x00000000);
2901 /* XXX : not implemented */
2902 spr_register(env, SPR_440_CCR1, "CCR1",
2903 SPR_NOACCESS, SPR_NOACCESS,
2904 &spr_read_generic, &spr_write_generic,
2905 0x00000000);
2906 /* Memory management */
2907 #if !defined(CONFIG_USER_ONLY)
2908 env->nb_tlb = 64;
2909 env->nb_ways = 1;
2910 env->id_tlbs = 0;
2911 env->tlb_type = TLB_EMB;
2912 #endif
2913 init_excp_BookE(env);
2914 env->dcache_line_size = 32;
2915 env->icache_line_size = 32;
2916 ppc40x_irq_init(env_archcpu(env));
2917
2918 SET_FIT_PERIOD(12, 16, 20, 24);
2919 SET_WDT_PERIOD(20, 24, 28, 32);
2920 }
2921
2922 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2923 {
2924 DeviceClass *dc = DEVICE_CLASS(oc);
2925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2926
2927 dc->desc = "PowerPC 440x5";
2928 pcc->init_proc = init_proc_440x5;
2929 pcc->check_pow = check_pow_nocheck;
2930 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2931 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2932 PPC_CACHE | PPC_CACHE_ICBI |
2933 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2934 PPC_MEM_TLBSYNC | PPC_MFTB |
2935 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2936 PPC_440_SPEC;
2937 pcc->msr_mask = (1ull << MSR_POW) |
2938 (1ull << MSR_CE) |
2939 (1ull << MSR_EE) |
2940 (1ull << MSR_PR) |
2941 (1ull << MSR_FP) |
2942 (1ull << MSR_ME) |
2943 (1ull << MSR_FE0) |
2944 (1ull << MSR_DWE) |
2945 (1ull << MSR_DE) |
2946 (1ull << MSR_FE1) |
2947 (1ull << MSR_IR) |
2948 (1ull << MSR_DR);
2949 pcc->mmu_model = POWERPC_MMU_BOOKE;
2950 pcc->excp_model = POWERPC_EXCP_BOOKE;
2951 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2952 pcc->bfd_mach = bfd_mach_ppc_403;
2953 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2954 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2955 }
2956
2957 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2958 {
2959 DeviceClass *dc = DEVICE_CLASS(oc);
2960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2961
2962 dc->desc = "PowerPC 440x5 with double precision FPU";
2963 pcc->init_proc = init_proc_440x5;
2964 pcc->check_pow = check_pow_nocheck;
2965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2966 PPC_FLOAT | PPC_FLOAT_FSQRT |
2967 PPC_FLOAT_STFIWX |
2968 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2969 PPC_CACHE | PPC_CACHE_ICBI |
2970 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2971 PPC_MEM_TLBSYNC | PPC_MFTB |
2972 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2973 PPC_440_SPEC;
2974 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2975 pcc->msr_mask = (1ull << MSR_POW) |
2976 (1ull << MSR_CE) |
2977 (1ull << MSR_EE) |
2978 (1ull << MSR_PR) |
2979 (1ull << MSR_FP) |
2980 (1ull << MSR_ME) |
2981 (1ull << MSR_FE0) |
2982 (1ull << MSR_DWE) |
2983 (1ull << MSR_DE) |
2984 (1ull << MSR_FE1) |
2985 (1ull << MSR_IR) |
2986 (1ull << MSR_DR);
2987 pcc->mmu_model = POWERPC_MMU_BOOKE;
2988 pcc->excp_model = POWERPC_EXCP_BOOKE;
2989 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2990 pcc->bfd_mach = bfd_mach_ppc_403;
2991 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2992 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2993 }
2994
2995 static void init_proc_MPC5xx(CPUPPCState *env)
2996 {
2997 /* Time base */
2998 register_tbl(env);
2999 register_5xx_8xx_sprs(env);
3000 register_5xx_sprs(env);
3001 init_excp_MPC5xx(env);
3002 env->dcache_line_size = 32;
3003 env->icache_line_size = 32;
3004 /* XXX: TODO: allocate internal IRQ controller */
3005 }
3006
3007 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3008 {
3009 DeviceClass *dc = DEVICE_CLASS(oc);
3010 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3011
3012 dc->desc = "Freescale 5xx cores (aka RCPU)";
3013 pcc->init_proc = init_proc_MPC5xx;
3014 pcc->check_pow = check_pow_none;
3015 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3016 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3017 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
3018 PPC_MFTB;
3019 pcc->msr_mask = (1ull << MSR_ILE) |
3020 (1ull << MSR_EE) |
3021 (1ull << MSR_PR) |
3022 (1ull << MSR_FP) |
3023 (1ull << MSR_ME) |
3024 (1ull << MSR_FE0) |
3025 (1ull << MSR_SE) |
3026 (1ull << MSR_DE) |
3027 (1ull << MSR_FE1) |
3028 (1ull << MSR_EP) |
3029 (1ull << MSR_RI) |
3030 (1ull << MSR_LE);
3031 pcc->mmu_model = POWERPC_MMU_REAL;
3032 pcc->excp_model = POWERPC_EXCP_603;
3033 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3034 pcc->bfd_mach = bfd_mach_ppc_505;
3035 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3036 POWERPC_FLAG_BUS_CLK;
3037 }
3038
3039 static void init_proc_MPC8xx(CPUPPCState *env)
3040 {
3041 /* Time base */
3042 register_tbl(env);
3043 register_5xx_8xx_sprs(env);
3044 register_8xx_sprs(env);
3045 init_excp_MPC8xx(env);
3046 env->dcache_line_size = 32;
3047 env->icache_line_size = 32;
3048 /* XXX: TODO: allocate internal IRQ controller */
3049 }
3050
3051 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
3052 {
3053 DeviceClass *dc = DEVICE_CLASS(oc);
3054 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3055
3056 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
3057 pcc->init_proc = init_proc_MPC8xx;
3058 pcc->check_pow = check_pow_none;
3059 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3060 PPC_MEM_EIEIO | PPC_MEM_SYNC |
3061 PPC_CACHE_ICBI | PPC_MFTB;
3062 pcc->msr_mask = (1ull << MSR_ILE) |
3063 (1ull << MSR_EE) |
3064 (1ull << MSR_PR) |
3065 (1ull << MSR_FP) |
3066 (1ull << MSR_ME) |
3067 (1ull << MSR_SE) |
3068 (1ull << MSR_DE) |
3069 (1ull << MSR_EP) |
3070 (1ull << MSR_IR) |
3071 (1ull << MSR_DR) |
3072 (1ull << MSR_RI) |
3073 (1ull << MSR_LE);
3074 pcc->mmu_model = POWERPC_MMU_MPC8xx;
3075 pcc->excp_model = POWERPC_EXCP_603;
3076 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
3077 pcc->bfd_mach = bfd_mach_ppc_860;
3078 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3079 POWERPC_FLAG_BUS_CLK;
3080 }
3081
3082 /* Freescale 82xx cores (aka PowerQUICC-II) */
3083
3084 static void init_proc_G2(CPUPPCState *env)
3085 {
3086 register_ne_601_sprs(env);
3087 register_sdr1_sprs(env);
3088 register_G2_755_sprs(env);
3089 register_G2_sprs(env);
3090 /* Time base */
3091 register_tbl(env);
3092 /* External access control */
3093 /* XXX : not implemented */
3094 spr_register(env, SPR_EAR, "EAR",
3095 SPR_NOACCESS, SPR_NOACCESS,
3096 &spr_read_generic, &spr_write_generic,
3097 0x00000000);
3098 /* Hardware implementation register */
3099 /* XXX : not implemented */
3100 spr_register(env, SPR_HID0, "HID0",
3101 SPR_NOACCESS, SPR_NOACCESS,
3102 &spr_read_generic, &spr_write_generic,
3103 0x00000000);
3104 /* XXX : not implemented */
3105 spr_register(env, SPR_HID1, "HID1",
3106 SPR_NOACCESS, SPR_NOACCESS,
3107 &spr_read_generic, &spr_write_generic,
3108 0x00000000);
3109 /* XXX : not implemented */
3110 spr_register(env, SPR_HID2, "HID2",
3111 SPR_NOACCESS, SPR_NOACCESS,
3112 &spr_read_generic, &spr_write_generic,
3113 0x00000000);
3114 /* Memory management */
3115 register_low_BATs(env);
3116 register_high_BATs(env);
3117 register_6xx_7xx_soft_tlb(env, 64, 2);
3118 init_excp_G2(env);
3119 env->dcache_line_size = 32;
3120 env->icache_line_size = 32;
3121 /* Allocate hardware IRQ controller */
3122 ppc6xx_irq_init(env_archcpu(env));
3123 }
3124
3125 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
3126 {
3127 DeviceClass *dc = DEVICE_CLASS(oc);
3128 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3129
3130 dc->desc = "PowerPC G2";
3131 pcc->init_proc = init_proc_G2;
3132 pcc->check_pow = check_pow_hid0;
3133 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3134 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3135 PPC_FLOAT_STFIWX |
3136 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3137 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3138 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3139 PPC_SEGMENT | PPC_EXTERN;
3140 pcc->msr_mask = (1ull << MSR_POW) |
3141 (1ull << MSR_TGPR) |
3142 (1ull << MSR_EE) |
3143 (1ull << MSR_PR) |
3144 (1ull << MSR_FP) |
3145 (1ull << MSR_ME) |
3146 (1ull << MSR_FE0) |
3147 (1ull << MSR_SE) |
3148 (1ull << MSR_DE) |
3149 (1ull << MSR_FE1) |
3150 (1ull << MSR_AL) |
3151 (1ull << MSR_EP) |
3152 (1ull << MSR_IR) |
3153 (1ull << MSR_DR) |
3154 (1ull << MSR_RI);
3155 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3156 pcc->excp_model = POWERPC_EXCP_G2;
3157 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3158 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3159 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3160 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3161 }
3162
3163 static void init_proc_G2LE(CPUPPCState *env)
3164 {
3165 register_ne_601_sprs(env);
3166 register_sdr1_sprs(env);
3167 register_G2_755_sprs(env);
3168 register_G2_sprs(env);
3169 /* Time base */
3170 register_tbl(env);
3171 /* External access control */
3172 /* XXX : not implemented */
3173 spr_register(env, SPR_EAR, "EAR",
3174 SPR_NOACCESS, SPR_NOACCESS,
3175 &spr_read_generic, &spr_write_generic,
3176 0x00000000);
3177 /* Hardware implementation register */
3178 /* XXX : not implemented */
3179 spr_register(env, SPR_HID0, "HID0",
3180 SPR_NOACCESS, SPR_NOACCESS,
3181 &spr_read_generic, &spr_write_generic,
3182 0x00000000);
3183 /* XXX : not implemented */
3184 spr_register(env, SPR_HID1, "HID1",
3185 SPR_NOACCESS, SPR_NOACCESS,
3186 &spr_read_generic, &spr_write_generic,
3187 0x00000000);
3188 /* XXX : not implemented */
3189 spr_register(env, SPR_HID2, "HID2",
3190 SPR_NOACCESS, SPR_NOACCESS,
3191 &spr_read_generic, &spr_write_generic,
3192 0x00000000);
3193
3194 /* Memory management */
3195 register_low_BATs(env);
3196 register_high_BATs(env);
3197 register_6xx_7xx_soft_tlb(env, 64, 2);
3198 init_excp_G2(env);
3199 env->dcache_line_size = 32;
3200 env->icache_line_size = 32;
3201 /* Allocate hardware IRQ controller */
3202 ppc6xx_irq_init(env_archcpu(env));
3203 }
3204
3205 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
3206 {
3207 DeviceClass *dc = DEVICE_CLASS(oc);
3208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3209
3210 dc->desc = "PowerPC G2LE";
3211 pcc->init_proc = init_proc_G2LE;
3212 pcc->check_pow = check_pow_hid0;
3213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3214 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3215 PPC_FLOAT_STFIWX |
3216 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3217 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3218 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3219 PPC_SEGMENT | PPC_EXTERN;
3220 pcc->msr_mask = (1ull << MSR_POW) |
3221 (1ull << MSR_TGPR) |
3222 (1ull << MSR_ILE) |
3223 (1ull << MSR_EE) |
3224 (1ull << MSR_PR) |
3225 (1ull << MSR_FP) |
3226 (1ull << MSR_ME) |
3227 (1ull << MSR_FE0) |
3228 (1ull << MSR_SE) |
3229 (1ull << MSR_DE) |
3230 (1ull << MSR_FE1) |
3231 (1ull << MSR_AL) |
3232 (1ull << MSR_EP) |
3233 (1ull << MSR_IR) |
3234 (1ull << MSR_DR) |
3235 (1ull << MSR_RI) |
3236 (1ull << MSR_LE);
3237 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3238 pcc->excp_model = POWERPC_EXCP_G2;
3239 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3240 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3241 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3242 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3243 }
3244
3245 static void init_proc_e200(CPUPPCState *env)
3246 {
3247 /* Time base */
3248 register_tbl(env);
3249 register_BookE_sprs(env, 0x000000070000FFFFULL);
3250 /* XXX : not implemented */
3251 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3252 &spr_read_spefscr, &spr_write_spefscr,
3253 &spr_read_spefscr, &spr_write_spefscr,
3254 0x00000000);
3255 /* Memory management */
3256 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
3257 /* XXX : not implemented */
3258 spr_register(env, SPR_HID0, "HID0",
3259 SPR_NOACCESS, SPR_NOACCESS,
3260 &spr_read_generic, &spr_write_generic,
3261 0x00000000);
3262 /* XXX : not implemented */
3263 spr_register(env, SPR_HID1, "HID1",
3264 SPR_NOACCESS, SPR_NOACCESS,
3265 &spr_read_generic, &spr_write_generic,
3266 0x00000000);
3267 /* XXX : not implemented */
3268 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3269 SPR_NOACCESS, SPR_NOACCESS,
3270 &spr_read_generic, &spr_write_generic,
3271 0x00000000);
3272 /* XXX : not implemented */
3273 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3274 SPR_NOACCESS, SPR_NOACCESS,
3275 &spr_read_generic, &spr_write_generic,
3276 0x00000000);
3277 /* XXX : not implemented */
3278 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
3279 SPR_NOACCESS, SPR_NOACCESS,
3280 &spr_read_generic, &spr_write_generic,
3281 0x00000000);
3282 /* XXX : not implemented */
3283 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
3284 SPR_NOACCESS, SPR_NOACCESS,
3285 &spr_read_generic, &spr_write_generic,
3286 0x00000000);
3287 /* XXX : not implemented */
3288 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
3289 SPR_NOACCESS, SPR_NOACCESS,
3290 &spr_read_generic, &spr_write_generic,
3291 0x00000000);
3292 /* XXX : not implemented */
3293 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3294 &spr_read_generic, SPR_NOACCESS,
3295 &spr_read_generic, SPR_NOACCESS,
3296 0x00000000);
3297 /* XXX : not implemented */
3298 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3299 SPR_NOACCESS, SPR_NOACCESS,
3300 &spr_read_generic, &spr_write_generic,
3301 0x00000000);
3302 /* XXX : not implemented */
3303 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
3304 SPR_NOACCESS, SPR_NOACCESS,
3305 &spr_read_generic, &spr_write_generic,
3306 0x00000000);
3307 /* XXX : not implemented */
3308 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
3309 SPR_NOACCESS, SPR_NOACCESS,
3310 &spr_read_generic, &spr_write_generic,
3311 0x00000000);
3312 /* XXX : not implemented */
3313 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
3314 SPR_NOACCESS, SPR_NOACCESS,
3315 &spr_read_generic, &spr_write_generic,
3316 0x00000000);
3317 /* XXX : not implemented */
3318 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3319 SPR_NOACCESS, SPR_NOACCESS,
3320 &spr_read_generic, &spr_write_generic,
3321 0x00000000);
3322 /* XXX : not implemented */
3323 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3324 SPR_NOACCESS, SPR_NOACCESS,
3325 &spr_read_generic, &spr_write_generic,
3326 0x00000000);
3327 /* XXX : not implemented */
3328 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3329 SPR_NOACCESS, SPR_NOACCESS,
3330 &spr_read_generic, &spr_write_generic,
3331 0x00000000); /* TOFIX */
3332 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
3333 SPR_NOACCESS, SPR_NOACCESS,
3334 &spr_read_generic, &spr_write_generic,
3335 0x00000000);
3336 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
3337 SPR_NOACCESS, SPR_NOACCESS,
3338 &spr_read_generic, &spr_write_generic,
3339 0x00000000);
3340 #if !defined(CONFIG_USER_ONLY)
3341 env->nb_tlb = 64;
3342 env->nb_ways = 1;
3343 env->id_tlbs = 0;
3344 env->tlb_type = TLB_EMB;
3345 #endif
3346 init_excp_e200(env, 0xFFFF0000UL);
3347 env->dcache_line_size = 32;
3348 env->icache_line_size = 32;
3349 /* XXX: TODO: allocate internal IRQ controller */
3350 }
3351
3352 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
3353 {
3354 DeviceClass *dc = DEVICE_CLASS(oc);
3355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3356
3357 dc->desc = "e200 core";
3358 pcc->init_proc = init_proc_e200;
3359 pcc->check_pow = check_pow_hid0;
3360 /*
3361 * XXX: unimplemented instructions:
3362 * dcblc
3363 * dcbtlst
3364 * dcbtstls
3365 * icblc
3366 * icbtls
3367 * tlbivax
3368 * all SPE multiply-accumulate instructions
3369 */
3370 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3371 PPC_SPE | PPC_SPE_SINGLE |
3372 PPC_WRTEE | PPC_RFDI |
3373 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3374 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3375 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
3376 PPC_BOOKE;
3377 pcc->msr_mask = (1ull << MSR_UCLE) |
3378 (1ull << MSR_SPE) |
3379 (1ull << MSR_POW) |
3380 (1ull << MSR_CE) |
3381 (1ull << MSR_EE) |
3382 (1ull << MSR_PR) |
3383 (1ull << MSR_FP) |
3384 (1ull << MSR_ME) |
3385 (1ull << MSR_FE0) |
3386 (1ull << MSR_DWE) |
3387 (1ull << MSR_DE) |
3388 (1ull << MSR_FE1) |
3389 (1ull << MSR_IR) |
3390 (1ull << MSR_DR);
3391 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3392 pcc->excp_model = POWERPC_EXCP_BOOKE;
3393 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3394 pcc->bfd_mach = bfd_mach_ppc_860;
3395 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3396 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3397 POWERPC_FLAG_BUS_CLK;
3398 }
3399
3400 static void init_proc_e300(CPUPPCState *env)
3401 {
3402 register_ne_601_sprs(env);
3403 register_sdr1_sprs(env);
3404 register_603_sprs(env);
3405 /* Time base */
3406 register_tbl(env);
3407 /* hardware implementation registers */
3408 /* XXX : not implemented */
3409 spr_register(env, SPR_HID0, "HID0",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0x00000000);
3413 /* XXX : not implemented */
3414 spr_register(env, SPR_HID1, "HID1",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* XXX : not implemented */
3419 spr_register(env, SPR_HID2, "HID2",
3420 SPR_NOACCESS, SPR_NOACCESS,
3421 &spr_read_generic, &spr_write_generic,
3422 0x00000000);
3423 /* Breakpoints */
3424 /* XXX : not implemented */
3425 spr_register(env, SPR_DABR, "DABR",
3426 SPR_NOACCESS, SPR_NOACCESS,
3427 &spr_read_generic, &spr_write_generic,
3428 0x00000000);
3429 /* XXX : not implemented */
3430 spr_register(env, SPR_DABR2, "DABR2",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_generic,
3433 0x00000000);
3434 /* XXX : not implemented */
3435 spr_register(env, SPR_IABR2, "IABR2",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_generic,
3438 0x00000000);
3439 /* XXX : not implemented */
3440 spr_register(env, SPR_IBCR, "IBCR",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 /* XXX : not implemented */
3445 spr_register(env, SPR_DBCR, "DBCR",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_generic,
3448 0x00000000);
3449 /* Memory management */
3450 register_low_BATs(env);
3451 register_high_BATs(env);
3452 register_6xx_7xx_soft_tlb(env, 64, 2);
3453 init_excp_603(env);
3454 env->dcache_line_size = 32;
3455 env->icache_line_size = 32;
3456 /* Allocate hardware IRQ controller */
3457 ppc6xx_irq_init(env_archcpu(env));
3458 }
3459
3460 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3461 {
3462 DeviceClass *dc = DEVICE_CLASS(oc);
3463 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3464
3465 dc->desc = "e300 core";
3466 pcc->init_proc = init_proc_e300;
3467 pcc->check_pow = check_pow_hid0;
3468 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3469 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3470 PPC_FLOAT_STFIWX |
3471 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3472 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3473 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3474 PPC_SEGMENT | PPC_EXTERN;
3475 pcc->msr_mask = (1ull << MSR_POW) |
3476 (1ull << MSR_TGPR) |
3477 (1ull << MSR_ILE) |
3478 (1ull << MSR_EE) |
3479 (1ull << MSR_PR) |
3480 (1ull << MSR_FP) |
3481 (1ull << MSR_ME) |
3482 (1ull << MSR_FE0) |
3483 (1ull << MSR_SE) |
3484 (1ull << MSR_DE) |
3485 (1ull << MSR_FE1) |
3486 (1ull << MSR_AL) |
3487 (1ull << MSR_EP) |
3488 (1ull << MSR_IR) |
3489 (1ull << MSR_DR) |
3490 (1ull << MSR_RI) |
3491 (1ull << MSR_LE);
3492 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3493 pcc->excp_model = POWERPC_EXCP_603;
3494 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3495 pcc->bfd_mach = bfd_mach_ppc_603;
3496 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3497 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3498 }
3499
3500 enum fsl_e500_version {
3501 fsl_e500v1,
3502 fsl_e500v2,
3503 fsl_e500mc,
3504 fsl_e5500,
3505 fsl_e6500,
3506 };
3507
3508 static void init_proc_e500(CPUPPCState *env, int version)
3509 {
3510 uint32_t tlbncfg[2];
3511 uint64_t ivor_mask;
3512 uint64_t ivpr_mask = 0xFFFF0000ULL;
3513 uint32_t l1cfg0 = 0x3800 /* 8 ways */
3514 | 0x0020; /* 32 kb */
3515 uint32_t l1cfg1 = 0x3800 /* 8 ways */
3516 | 0x0020; /* 32 kb */
3517 uint32_t mmucfg = 0;
3518 #if !defined(CONFIG_USER_ONLY)
3519 int i;
3520 #endif
3521
3522 /* Time base */
3523 register_tbl(env);
3524 /*
3525 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
3526 * complain when accessing them.
3527 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
3528 */
3529 switch (version) {
3530 case fsl_e500v1:
3531 case fsl_e500v2:
3532 default:
3533 ivor_mask = 0x0000000F0000FFFFULL;
3534 break;
3535 case fsl_e500mc:
3536 case fsl_e5500:
3537 ivor_mask = 0x000003FE0000FFFFULL;
3538 break;
3539 case fsl_e6500:
3540 ivor_mask = 0x000003FF0000FFFFULL;
3541 break;
3542 }
3543 register_BookE_sprs(env, ivor_mask);
3544 register_usprg3_sprs(env);
3545 /* Processor identification */
3546 spr_register(env, SPR_BOOKE_PIR, "PIR",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_pir,
3549 0x00000000);
3550 /* XXX : not implemented */
3551 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3552 &spr_read_spefscr, &spr_write_spefscr,
3553 &spr_read_spefscr, &spr_write_spefscr,
3554 0x00000000);
3555 #if !defined(CONFIG_USER_ONLY)
3556 /* Memory management */
3557 env->nb_pids = 3;
3558 env->nb_ways = 2;
3559 env->id_tlbs = 0;
3560 switch (version) {
3561 case fsl_e500v1:
3562 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
3563 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3564 break;
3565 case fsl_e500v2:
3566 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3567 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
3568 break;
3569 case fsl_e500mc:
3570 case fsl_e5500:
3571 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
3572 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
3573 break;
3574 case fsl_e6500:
3575 mmucfg = 0x6510B45;
3576 env->nb_pids = 1;
3577 tlbncfg[0] = 0x08052400;
3578 tlbncfg[1] = 0x40028040;
3579 break;
3580 default:
3581 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3582 env->spr[SPR_PVR]);
3583 }
3584 #endif
3585 /* Cache sizes */
3586 switch (version) {
3587 case fsl_e500v1:
3588 case fsl_e500v2:
3589 env->dcache_line_size = 32;
3590 env->icache_line_size = 32;
3591 break;
3592 case fsl_e500mc:
3593 case fsl_e5500:
3594 env->dcache_line_size = 64;
3595 env->icache_line_size = 64;
3596 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
3597 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
3598 break;
3599 case fsl_e6500:
3600 env->dcache_line_size = 32;
3601 env->icache_line_size = 32;
3602 l1cfg0 |= 0x0F83820;
3603 l1cfg1 |= 0x0B83820;
3604 break;
3605 default:
3606 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
3607 env->spr[SPR_PVR]);
3608 }
3609 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
3610 /* XXX : not implemented */
3611 spr_register(env, SPR_HID0, "HID0",
3612 SPR_NOACCESS, SPR_NOACCESS,
3613 &spr_read_generic, &spr_write_generic,
3614 0x00000000);
3615 /* XXX : not implemented */
3616 spr_register(env, SPR_HID1, "HID1",
3617 SPR_NOACCESS, SPR_NOACCESS,
3618 &spr_read_generic, &spr_write_generic,
3619 0x00000000);
3620 /* XXX : not implemented */
3621 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 /* XXX : not implemented */
3626 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
3627 SPR_NOACCESS, SPR_NOACCESS,
3628 &spr_read_generic, &spr_write_generic,
3629 0x00000000);
3630 /* XXX : not implemented */
3631 spr_register(env, SPR_Exxx_MCAR, "MCAR",
3632 SPR_NOACCESS, SPR_NOACCESS,
3633 &spr_read_generic, &spr_write_generic,
3634 0x00000000);
3635 /* XXX : not implemented */
3636 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3637 SPR_NOACCESS, SPR_NOACCESS,
3638 &spr_read_generic, &spr_write_generic,
3639 0x00000000);
3640 /* XXX : not implemented */
3641 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
3642 SPR_NOACCESS, SPR_NOACCESS,
3643 &spr_read_generic, &spr_write_generic,
3644 0x00000000);
3645 /* XXX : not implemented */
3646 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3647 SPR_NOACCESS, SPR_NOACCESS,
3648 &spr_read_generic, &spr_write_generic,
3649 0x00000000);
3650 /* XXX : not implemented */
3651 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
3652 &spr_read_generic, SPR_NOACCESS,
3653 &spr_read_generic, SPR_NOACCESS,
3654 l1cfg0);
3655 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
3656 &spr_read_generic, SPR_NOACCESS,
3657 &spr_read_generic, SPR_NOACCESS,
3658 l1cfg1);
3659 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
3660 SPR_NOACCESS, SPR_NOACCESS,
3661 &spr_read_generic, &spr_write_e500_l1csr0,
3662 0x00000000);
3663 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_e500_l1csr1,
3666 0x00000000);
3667 if (version != fsl_e500v1 && version != fsl_e500v2) {
3668 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_e500_l2csr0,
3671 0x00000000);
3672 }
3673 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3674 SPR_NOACCESS, SPR_NOACCESS,
3675 &spr_read_generic, &spr_write_generic,
3676 0x00000000);
3677 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_booke206_mmucsr0,
3684 0x00000000);
3685 spr_register(env, SPR_BOOKE_EPR, "EPR",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, SPR_NOACCESS,
3688 0x00000000);
3689 /* XXX better abstract into Emb.xxx features */
3690 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3691 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
3695 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3696 SPR_NOACCESS, SPR_NOACCESS,
3697 &spr_read_mas73, &spr_write_mas73,
3698 0x00000000);
3699 ivpr_mask = (target_ulong)~0xFFFFULL;
3700 }
3701
3702 if (version == fsl_e6500) {
3703 /* Thread identification */
3704 spr_register(env, SPR_TIR, "TIR",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, SPR_NOACCESS,
3707 0x00000000);
3708 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3709 SPR_NOACCESS, SPR_NOACCESS,
3710 &spr_read_generic, SPR_NOACCESS,
3711 0x00000004);
3712 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3713 SPR_NOACCESS, SPR_NOACCESS,
3714 &spr_read_generic, SPR_NOACCESS,
3715 0x7FFFFFFC);
3716 }
3717
3718 #if !defined(CONFIG_USER_ONLY)
3719 env->nb_tlb = 0;
3720 env->tlb_type = TLB_MAS;
3721 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3722 env->nb_tlb += booke206_tlb_size(env, i);
3723 }
3724 #endif
3725
3726 init_excp_e200(env, ivpr_mask);
3727 /* Allocate hardware IRQ controller */
3728 ppce500_irq_init(env_archcpu(env));
3729 }
3730
3731 static void init_proc_e500v1(CPUPPCState *env)
3732 {
3733 init_proc_e500(env, fsl_e500v1);
3734 }
3735
3736 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3737 {
3738 DeviceClass *dc = DEVICE_CLASS(oc);
3739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3740
3741 dc->desc = "e500v1 core";
3742 pcc->init_proc = init_proc_e500v1;
3743 pcc->check_pow = check_pow_hid0;
3744 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3745 PPC_SPE | PPC_SPE_SINGLE |
3746 PPC_WRTEE | PPC_RFDI |
3747 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3748 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3749 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3750 pcc->insns_flags2 = PPC2_BOOKE206;
3751 pcc->msr_mask = (1ull << MSR_UCLE) |
3752 (1ull << MSR_SPE) |
3753 (1ull << MSR_POW) |
3754 (1ull << MSR_CE) |
3755 (1ull << MSR_EE) |
3756 (1ull << MSR_PR) |
3757 (1ull << MSR_FP) |
3758 (1ull << MSR_ME) |
3759 (1ull << MSR_FE0) |
3760 (1ull << MSR_DWE) |
3761 (1ull << MSR_DE) |
3762 (1ull << MSR_FE1) |
3763 (1ull << MSR_IR) |
3764 (1ull << MSR_DR);
3765 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3766 pcc->excp_model = POWERPC_EXCP_BOOKE;
3767 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3768 pcc->bfd_mach = bfd_mach_ppc_860;
3769 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3770 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3771 POWERPC_FLAG_BUS_CLK;
3772 }
3773
3774 static void init_proc_e500v2(CPUPPCState *env)
3775 {
3776 init_proc_e500(env, fsl_e500v2);
3777 }
3778
3779 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3780 {
3781 DeviceClass *dc = DEVICE_CLASS(oc);
3782 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3783
3784 dc->desc = "e500v2 core";
3785 pcc->init_proc = init_proc_e500v2;
3786 pcc->check_pow = check_pow_hid0;
3787 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3788 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3789 PPC_WRTEE | PPC_RFDI |
3790 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3791 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3792 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3793 pcc->insns_flags2 = PPC2_BOOKE206;
3794 pcc->msr_mask = (1ull << MSR_UCLE) |
3795 (1ull << MSR_SPE) |
3796 (1ull << MSR_POW) |
3797 (1ull << MSR_CE) |
3798 (1ull << MSR_EE) |
3799 (1ull << MSR_PR) |
3800 (1ull << MSR_FP) |
3801 (1ull << MSR_ME) |
3802 (1ull << MSR_FE0) |
3803 (1ull << MSR_DWE) |
3804 (1ull << MSR_DE) |
3805 (1ull << MSR_FE1) |
3806 (1ull << MSR_IR) |
3807 (1ull << MSR_DR);
3808 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3809 pcc->excp_model = POWERPC_EXCP_BOOKE;
3810 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3811 pcc->bfd_mach = bfd_mach_ppc_860;
3812 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3813 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3814 POWERPC_FLAG_BUS_CLK;
3815 }
3816
3817 static void init_proc_e500mc(CPUPPCState *env)
3818 {
3819 init_proc_e500(env, fsl_e500mc);
3820 }
3821
3822 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3823 {
3824 DeviceClass *dc = DEVICE_CLASS(oc);
3825 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3826
3827 dc->desc = "e500mc core";
3828 pcc->init_proc = init_proc_e500mc;
3829 pcc->check_pow = check_pow_none;
3830 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3831 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3832 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3833 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3834 PPC_FLOAT | PPC_FLOAT_FRES |
3835 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3836 PPC_FLOAT_STFIWX | PPC_WAIT |
3837 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3838 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3839 pcc->msr_mask = (1ull << MSR_GS) |
3840 (1ull << MSR_UCLE) |
3841 (1ull << MSR_CE) |
3842 (1ull << MSR_EE) |
3843 (1ull << MSR_PR) |
3844 (1ull << MSR_FP) |
3845 (1ull << MSR_ME) |
3846 (1ull << MSR_FE0) |
3847 (1ull << MSR_DE) |
3848 (1ull << MSR_FE1) |
3849 (1ull << MSR_IR) |
3850 (1ull << MSR_DR) |
3851 (1ull << MSR_PX) |
3852 (1ull << MSR_RI);
3853 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3854 pcc->excp_model = POWERPC_EXCP_BOOKE;
3855 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3856 /* FIXME: figure out the correct flag for e500mc */
3857 pcc->bfd_mach = bfd_mach_ppc_e500;
3858 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3859 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3860 }
3861
3862 #ifdef TARGET_PPC64
3863 static void init_proc_e5500(CPUPPCState *env)
3864 {
3865 init_proc_e500(env, fsl_e5500);
3866 }
3867
3868 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3869 {
3870 DeviceClass *dc = DEVICE_CLASS(oc);
3871 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3872
3873 dc->desc = "e5500 core";
3874 pcc->init_proc = init_proc_e5500;
3875 pcc->check_pow = check_pow_none;
3876 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3877 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3878 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3879 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3880 PPC_FLOAT | PPC_FLOAT_FRES |
3881 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3882 PPC_FLOAT_STFIWX | PPC_WAIT |
3883 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3884 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3885 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3886 PPC2_FP_CVT_S64;
3887 pcc->msr_mask = (1ull << MSR_CM) |
3888 (1ull << MSR_GS) |
3889 (1ull << MSR_UCLE) |
3890 (1ull << MSR_CE) |
3891 (1ull << MSR_EE) |
3892 (1ull << MSR_PR) |
3893 (1ull << MSR_FP) |
3894 (1ull << MSR_ME) |
3895 (1ull << MSR_FE0) |
3896 (1ull << MSR_DE) |
3897 (1ull << MSR_FE1) |
3898 (1ull << MSR_IR) |
3899 (1ull << MSR_DR) |
3900 (1ull << MSR_PX) |
3901 (1ull << MSR_RI);
3902 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3903 pcc->excp_model = POWERPC_EXCP_BOOKE;
3904 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3905 /* FIXME: figure out the correct flag for e5500 */
3906 pcc->bfd_mach = bfd_mach_ppc_e500;
3907 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3908 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3909 }
3910
3911 static void init_proc_e6500(CPUPPCState *env)
3912 {
3913 init_proc_e500(env, fsl_e6500);
3914 }
3915
3916 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3917 {
3918 DeviceClass *dc = DEVICE_CLASS(oc);
3919 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3920
3921 dc->desc = "e6500 core";
3922 pcc->init_proc = init_proc_e6500;
3923 pcc->check_pow = check_pow_none;
3924 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3925 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3926 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3927 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3928 PPC_FLOAT | PPC_FLOAT_FRES |
3929 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3930 PPC_FLOAT_STFIWX | PPC_WAIT |
3931 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3932 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3933 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3934 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3935 pcc->msr_mask = (1ull << MSR_CM) |
3936 (1ull << MSR_GS) |
3937 (1ull << MSR_UCLE) |
3938 (1ull << MSR_CE) |
3939 (1ull << MSR_EE) |
3940 (1ull << MSR_PR) |
3941 (1ull << MSR_FP) |
3942 (1ull << MSR_ME) |
3943 (1ull << MSR_FE0) |
3944 (1ull << MSR_DE) |
3945 (1ull << MSR_FE1) |
3946 (1ull << MSR_IS) |
3947 (1ull << MSR_DS) |
3948 (1ull << MSR_PX) |
3949 (1ull << MSR_RI) |
3950 (1ull << MSR_VR);
3951 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3952 pcc->excp_model = POWERPC_EXCP_BOOKE;
3953 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3954 pcc->bfd_mach = bfd_mach_ppc_e500;
3955 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3956 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3957 }
3958
3959 #endif
3960
3961 /* Non-embedded PowerPC */
3962
3963 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
3964
3965 static void init_proc_601(CPUPPCState *env)
3966 {
3967 register_ne_601_sprs(env);
3968 register_sdr1_sprs(env);
3969 register_601_sprs(env);
3970 /* Hardware implementation registers */
3971 /* XXX : not implemented */
3972 spr_register(env, SPR_HID0, "HID0",
3973 SPR_NOACCESS, SPR_NOACCESS,
3974 &spr_read_generic, &spr_write_hid0_601,
3975 0x80010080);
3976 /* XXX : not implemented */
3977 spr_register(env, SPR_HID1, "HID1",
3978 SPR_NOACCESS, SPR_NOACCESS,
3979 &spr_read_generic, &spr_write_generic,
3980 0x00000000);
3981 /* XXX : not implemented */
3982 spr_register(env, SPR_601_HID2, "HID2",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
3986 /* XXX : not implemented */
3987 spr_register(env, SPR_601_HID5, "HID5",
3988 SPR_NOACCESS, SPR_NOACCESS,
3989 &spr_read_generic, &spr_write_generic,
3990 0x00000000);
3991 /* Memory management */
3992 init_excp_601(env);
3993 /*
3994 * XXX: beware that dcache line size is 64
3995 * but dcbz uses 32 bytes "sectors"
3996 * XXX: this breaks clcs instruction !
3997 */
3998 env->dcache_line_size = 32;
3999 env->icache_line_size = 64;
4000 /* Allocate hardware IRQ controller */
4001 ppc6xx_irq_init(env_archcpu(env));
4002 }
4003
4004 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4005 {
4006 DeviceClass *dc = DEVICE_CLASS(oc);
4007 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4008
4009 dc->desc = "PowerPC 601";
4010 pcc->init_proc = init_proc_601;
4011 pcc->check_pow = check_pow_none;
4012 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4013 PPC_FLOAT |
4014 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4015 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4016 PPC_SEGMENT | PPC_EXTERN;
4017 pcc->msr_mask = (1ull << MSR_EE) |
4018 (1ull << MSR_PR) |
4019 (1ull << MSR_FP) |
4020 (1ull << MSR_ME) |
4021 (1ull << MSR_FE0) |
4022 (1ull << MSR_SE) |
4023 (1ull << MSR_FE1) |
4024 (1ull << MSR_EP) |
4025 (1ull << MSR_IR) |
4026 (1ull << MSR_DR);
4027 pcc->mmu_model = POWERPC_MMU_601;
4028 pcc->excp_model = POWERPC_EXCP_601;
4029 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4030 pcc->bfd_mach = bfd_mach_ppc_601;
4031 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4032 }
4033
4034 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4035
4036 static void init_proc_601v(CPUPPCState *env)
4037 {
4038 init_proc_601(env);
4039 /* XXX : not implemented */
4040 spr_register(env, SPR_601_HID15, "HID15",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_generic,
4043 0x00000000);
4044 }
4045
4046 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4047 {
4048 DeviceClass *dc = DEVICE_CLASS(oc);
4049 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4050
4051 dc->desc = "PowerPC 601v";
4052 pcc->init_proc = init_proc_601v;
4053 pcc->check_pow = check_pow_none;
4054 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4055 PPC_FLOAT |
4056 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4057 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4058 PPC_SEGMENT | PPC_EXTERN;
4059 pcc->msr_mask = (1ull << MSR_EE) |
4060 (1ull << MSR_PR) |
4061 (1ull << MSR_FP) |
4062 (1ull << MSR_ME) |
4063 (1ull << MSR_FE0) |
4064 (1ull << MSR_SE) |
4065 (1ull << MSR_FE1) |
4066 (1ull << MSR_EP) |
4067 (1ull << MSR_IR) |
4068 (1ull << MSR_DR);
4069 pcc->mmu_model = POWERPC_MMU_601;
4070 pcc->excp_model = POWERPC_EXCP_601;
4071 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4072 pcc->bfd_mach = bfd_mach_ppc_601;
4073 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE;
4074 }
4075
4076 static void init_proc_602(CPUPPCState *env)
4077 {
4078 register_ne_601_sprs(env);
4079 register_sdr1_sprs(env);
4080 register_602_sprs(env);
4081 /* Time base */
4082 register_tbl(env);
4083 /* hardware implementation registers */
4084 /* XXX : not implemented */
4085 spr_register(env, SPR_HID0, "HID0",
4086 SPR_NOACCESS, SPR_NOACCESS,
4087 &spr_read_generic, &spr_write_generic,
4088 0x00000000);
4089 /* XXX : not implemented */
4090 spr_register(env, SPR_HID1, "HID1",
4091 SPR_NOACCESS, SPR_NOACCESS,
4092 &spr_read_generic, &spr_write_generic,
4093 0x00000000);
4094 /* Memory management */
4095 register_low_BATs(env);
4096 register_6xx_7xx_soft_tlb(env, 64, 2);
4097 init_excp_602(env);
4098 env->dcache_line_size = 32;
4099 env->icache_line_size = 32;
4100 /* Allocate hardware IRQ controller */
4101 ppc6xx_irq_init(env_archcpu(env));
4102 }
4103
4104 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4105 {
4106 DeviceClass *dc = DEVICE_CLASS(oc);
4107 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4108
4109 dc->desc = "PowerPC 602";
4110 pcc->init_proc = init_proc_602;
4111 pcc->check_pow = check_pow_hid0;
4112 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4113 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4114 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4115 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4116 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4117 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4118 PPC_SEGMENT | PPC_602_SPEC;
4119 pcc->msr_mask = (1ull << MSR_VSX) |
4120 (1ull << MSR_SA) |
4121 (1ull << MSR_POW) |
4122 (1ull << MSR_TGPR) |
4123 (1ull << MSR_ILE) |
4124 (1ull << MSR_EE) |
4125 (1ull << MSR_PR) |
4126 (1ull << MSR_FP) |
4127 (1ull << MSR_ME) |
4128 (1ull << MSR_FE0) |
4129 (1ull << MSR_SE) |
4130 (1ull << MSR_DE) |
4131 (1ull << MSR_FE1) |
4132 (1ull << MSR_EP) |
4133 (1ull << MSR_IR) |
4134 (1ull << MSR_DR) |
4135 (1ull << MSR_RI) |
4136 (1ull << MSR_LE);
4137 /* XXX: 602 MMU is quite specific. Should add a special case */
4138 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4139 pcc->excp_model = POWERPC_EXCP_602;
4140 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4141 pcc->bfd_mach = bfd_mach_ppc_602;
4142 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4143 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4144 }
4145
4146 static void init_proc_603(CPUPPCState *env)
4147 {
4148 register_ne_601_sprs(env);
4149 register_sdr1_sprs(env);
4150 register_603_sprs(env);
4151 /* Time base */
4152 register_tbl(env);
4153 /* hardware implementation registers */
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_HID0, "HID0",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID1, "HID1",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* Memory management */
4165 register_low_BATs(env);
4166 register_6xx_7xx_soft_tlb(env, 64, 2);
4167 init_excp_603(env);
4168 env->dcache_line_size = 32;
4169 env->icache_line_size = 32;
4170 /* Allocate hardware IRQ controller */
4171 ppc6xx_irq_init(env_archcpu(env));
4172 }
4173
4174 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4175 {
4176 DeviceClass *dc = DEVICE_CLASS(oc);
4177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4178
4179 dc->desc = "PowerPC 603";
4180 pcc->init_proc = init_proc_603;
4181 pcc->check_pow = check_pow_hid0;
4182 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4183 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4184 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4185 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4186 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4187 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4188 PPC_SEGMENT | PPC_EXTERN;
4189 pcc->msr_mask = (1ull << MSR_POW) |
4190 (1ull << MSR_TGPR) |
4191 (1ull << MSR_ILE) |
4192 (1ull << MSR_EE) |
4193 (1ull << MSR_PR) |
4194 (1ull << MSR_FP) |
4195 (1ull << MSR_ME) |
4196 (1ull << MSR_FE0) |
4197 (1ull << MSR_SE) |
4198 (1ull << MSR_DE) |
4199 (1ull << MSR_FE1) |
4200 (1ull << MSR_EP) |
4201 (1ull << MSR_IR) |
4202 (1ull << MSR_DR) |
4203 (1ull << MSR_RI) |
4204 (1ull << MSR_LE);
4205 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4206 pcc->excp_model = POWERPC_EXCP_603;
4207 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4208 pcc->bfd_mach = bfd_mach_ppc_603;
4209 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4210 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4211 }
4212
4213 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4214 {
4215 DeviceClass *dc = DEVICE_CLASS(oc);
4216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4217
4218 dc->desc = "PowerPC 603e";
4219 pcc->init_proc = init_proc_603;
4220 pcc->check_pow = check_pow_hid0;
4221 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4222 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4223 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4224 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4225 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4226 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4227 PPC_SEGMENT | PPC_EXTERN;
4228 pcc->msr_mask = (1ull << MSR_POW) |
4229 (1ull << MSR_TGPR) |
4230 (1ull << MSR_ILE) |
4231 (1ull << MSR_EE) |
4232 (1ull << MSR_PR) |
4233 (1ull << MSR_FP) |
4234 (1ull << MSR_ME) |
4235 (1ull << MSR_FE0) |
4236 (1ull << MSR_SE) |
4237 (1ull << MSR_DE) |
4238 (1ull << MSR_FE1) |
4239 (1ull << MSR_EP) |
4240 (1ull << MSR_IR) |
4241 (1ull << MSR_DR) |
4242 (1ull << MSR_RI) |
4243 (1ull << MSR_LE);
4244 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4245 pcc->excp_model = POWERPC_EXCP_603;
4246 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4247 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4248 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4249 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4250 }
4251
4252 static void init_proc_604(CPUPPCState *env)
4253 {
4254 register_ne_601_sprs(env);
4255 register_sdr1_sprs(env);
4256 register_604_sprs(env);
4257 /* Time base */
4258 register_tbl(env);
4259 /* Hardware implementation registers */
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_HID0, "HID0",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* Memory management */
4266 register_low_BATs(env);
4267 init_excp_604(env);
4268 env->dcache_line_size = 32;
4269 env->icache_line_size = 32;
4270 /* Allocate hardware IRQ controller */
4271 ppc6xx_irq_init(env_archcpu(env));
4272 }
4273
4274 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
4275 {
4276 DeviceClass *dc = DEVICE_CLASS(oc);
4277 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4278
4279 dc->desc = "PowerPC 604";
4280 pcc->init_proc = init_proc_604;
4281 pcc->check_pow = check_pow_nocheck;
4282 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4283 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4284 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4285 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4286 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4287 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4288 PPC_SEGMENT | PPC_EXTERN;
4289 pcc->msr_mask = (1ull << MSR_POW) |
4290 (1ull << MSR_ILE) |
4291 (1ull << MSR_EE) |
4292 (1ull << MSR_PR) |
4293 (1ull << MSR_FP) |
4294 (1ull << MSR_ME) |
4295 (1ull << MSR_FE0) |
4296 (1ull << MSR_SE) |
4297 (1ull << MSR_DE) |
4298 (1ull << MSR_FE1) |
4299 (1ull << MSR_EP) |
4300 (1ull << MSR_IR) |
4301 (1ull << MSR_DR) |
4302 (1ull << MSR_PMM) |
4303 (1ull << MSR_RI) |
4304 (1ull << MSR_LE);
4305 pcc->mmu_model = POWERPC_MMU_32B;
4306 pcc->excp_model = POWERPC_EXCP_604;
4307 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4308 pcc->bfd_mach = bfd_mach_ppc_604;
4309 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4310 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4311 }
4312
4313 static void init_proc_604E(CPUPPCState *env)
4314 {
4315 register_ne_601_sprs(env);
4316 register_sdr1_sprs(env);
4317 register_604_sprs(env);
4318 /* XXX : not implemented */
4319 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
4320 SPR_NOACCESS, SPR_NOACCESS,
4321 &spr_read_generic, &spr_write_generic,
4322 0x00000000);
4323 /* XXX : not implemented */
4324 spr_register(env, SPR_7XX_PMC3, "PMC3",
4325 SPR_NOACCESS, SPR_NOACCESS,
4326 &spr_read_generic, &spr_write_generic,
4327 0x00000000);
4328 /* XXX : not implemented */
4329 spr_register(env, SPR_7XX_PMC4, "PMC4",
4330 SPR_NOACCESS, SPR_NOACCESS,
4331 &spr_read_generic, &spr_write_generic,
4332 0x00000000);
4333 /* Time base */
4334 register_tbl(env);
4335 /* Hardware implementation registers */
4336 /* XXX : not implemented */
4337 spr_register(env, SPR_HID0, "HID0",
4338 SPR_NOACCESS, SPR_NOACCESS,
4339 &spr_read_generic, &spr_write_generic,
4340 0x00000000);
4341 /* XXX : not implemented */
4342 spr_register(env, SPR_HID1, "HID1",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346 /* Memory management */
4347 register_low_BATs(env);
4348 init_excp_604(env);
4349 env->dcache_line_size = 32;
4350 env->icache_line_size = 32;
4351 /* Allocate hardware IRQ controller */
4352 ppc6xx_irq_init(env_archcpu(env));
4353 }
4354
4355 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
4356 {
4357 DeviceClass *dc = DEVICE_CLASS(oc);
4358 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4359
4360 dc->desc = "PowerPC 604E";
4361 pcc->init_proc = init_proc_604E;
4362 pcc->check_pow = check_pow_nocheck;
4363 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4364 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4365 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4366 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4367 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4368 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4369 PPC_SEGMENT | PPC_EXTERN;
4370 pcc->msr_mask = (1ull << MSR_POW) |
4371 (1ull << MSR_ILE) |
4372 (1ull << MSR_EE) |
4373 (1ull << MSR_PR) |
4374 (1ull << MSR_FP) |
4375 (1ull << MSR_ME) |
4376 (1ull << MSR_FE0) |
4377 (1ull << MSR_SE) |
4378 (1ull << MSR_DE) |
4379 (1ull << MSR_FE1) |
4380 (1ull << MSR_EP) |
4381 (1ull << MSR_IR) |
4382 (1ull << MSR_DR) |
4383 (1ull << MSR_PMM) |
4384 (1ull << MSR_RI) |
4385 (1ull << MSR_LE);
4386 pcc->mmu_model = POWERPC_MMU_32B;
4387 pcc->excp_model = POWERPC_EXCP_604;
4388 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4389 pcc->bfd_mach = bfd_mach_ppc_604;
4390 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4391 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4392 }
4393
4394 static void init_proc_740(CPUPPCState *env)
4395 {
4396 register_ne_601_sprs(env);
4397 register_sdr1_sprs(env);
4398 register_7xx_sprs(env);
4399 /* Time base */
4400 register_tbl(env);
4401 /* Thermal management */
4402 register_thrm_sprs(env);
4403 /* Hardware implementation registers */
4404 /* XXX : not implemented */
4405 spr_register(env, SPR_HID0, "HID0",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409 /* XXX : not implemented */
4410 spr_register(env, SPR_HID1, "HID1",
4411 SPR_NOACCESS, SPR_NOACCESS,
4412 &spr_read_generic, &spr_write_generic,
4413 0x00000000);
4414 /* Memory management */
4415 register_low_BATs(env);
4416 init_excp_7x0(env);
4417 env->dcache_line_size = 32;
4418 env->icache_line_size = 32;
4419 /* Allocate hardware IRQ controller */
4420 ppc6xx_irq_init(env_archcpu(env));
4421 }
4422
4423 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
4424 {
4425 DeviceClass *dc = DEVICE_CLASS(oc);
4426 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4427
4428 dc->desc = "PowerPC 740";
4429 pcc->init_proc = init_proc_740;
4430 pcc->check_pow = check_pow_hid0;
4431 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4432 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4433 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4434 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4435 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4436 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4437 PPC_SEGMENT | PPC_EXTERN;
4438 pcc->msr_mask = (1ull << MSR_POW) |
4439 (1ull << MSR_ILE) |
4440 (1ull << MSR_EE) |
4441 (1ull << MSR_PR) |
4442 (1ull << MSR_FP) |
4443 (1ull << MSR_ME) |
4444 (1ull << MSR_FE0) |
4445 (1ull << MSR_SE) |
4446 (1ull << MSR_DE) |
4447 (1ull << MSR_FE1) |
4448 (1ull << MSR_EP) |
4449 (1ull << MSR_IR) |
4450 (1ull << MSR_DR) |
4451 (1ull << MSR_PMM) |
4452 (1ull << MSR_RI) |
4453 (1ull << MSR_LE);
4454 pcc->mmu_model = POWERPC_MMU_32B;
4455 pcc->excp_model = POWERPC_EXCP_7x0;
4456 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4457 pcc->bfd_mach = bfd_mach_ppc_750;
4458 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4459 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4460 }
4461
4462 static void init_proc_750(CPUPPCState *env)
4463 {
4464 register_ne_601_sprs(env);
4465 register_sdr1_sprs(env);
4466 register_7xx_sprs(env);
4467 /* XXX : not implemented */
4468 spr_register(env, SPR_L2CR, "L2CR",
4469 SPR_NOACCESS, SPR_NOACCESS,
4470 &spr_read_generic, spr_access_nop,
4471 0x00000000);
4472 /* Time base */
4473 register_tbl(env);
4474 /* Thermal management */
4475 register_thrm_sprs(env);
4476 /* Hardware implementation registers */
4477 /* XXX : not implemented */
4478 spr_register(env, SPR_HID0, "HID0",
4479 SPR_NOACCESS, SPR_NOACCESS,
4480 &spr_read_generic, &spr_write_generic,
4481 0x00000000);
4482 /* XXX : not implemented */
4483 spr_register(env, SPR_HID1, "HID1",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 /* Memory management */
4488 register_low_BATs(env);
4489 /*
4490 * XXX: high BATs are also present but are known to be bugged on
4491 * die version 1.x
4492 */
4493 init_excp_7x0(env);
4494 env->dcache_line_size = 32;
4495 env->icache_line_size = 32;
4496 /* Allocate hardware IRQ controller */
4497 ppc6xx_irq_init(env_archcpu(env));
4498 }
4499
4500 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
4501 {
4502 DeviceClass *dc = DEVICE_CLASS(oc);
4503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4504
4505 dc->desc = "PowerPC 750";
4506 pcc->init_proc = init_proc_750;
4507 pcc->check_pow = check_pow_hid0;
4508 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4509 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4510 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4511 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4512 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4514 PPC_SEGMENT | PPC_EXTERN;
4515 pcc->msr_mask = (1ull << MSR_POW) |
4516 (1ull << MSR_ILE) |
4517 (1ull << MSR_EE) |
4518 (1ull << MSR_PR) |
4519 (1ull << MSR_FP) |
4520 (1ull << MSR_ME) |
4521 (1ull << MSR_FE0) |
4522 (1ull << MSR_SE) |
4523 (1ull << MSR_DE) |
4524 (1ull << MSR_FE1) |
4525 (1ull << MSR_EP) |
4526 (1ull << MSR_IR) |
4527 (1ull << MSR_DR) |
4528 (1ull << MSR_PMM) |
4529 (1ull << MSR_RI) |
4530 (1ull << MSR_LE);
4531 pcc->mmu_model = POWERPC_MMU_32B;
4532 pcc->excp_model = POWERPC_EXCP_7x0;
4533 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4534 pcc->bfd_mach = bfd_mach_ppc_750;
4535 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4536 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4537 }
4538
4539 static void init_proc_750cl(CPUPPCState *env)
4540 {
4541 register_ne_601_sprs(env);
4542 register_sdr1_sprs(env);
4543 register_7xx_sprs(env);
4544 /* XXX : not implemented */
4545 spr_register(env, SPR_L2CR, "L2CR",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, spr_access_nop,
4548 0x00000000);
4549 /* Time base */
4550 register_tbl(env);
4551 /* Thermal management */
4552 /* Those registers are fake on 750CL */
4553 spr_register(env, SPR_THRM1, "THRM1",
4554 SPR_NOACCESS, SPR_NOACCESS,
4555 &spr_read_generic, &spr_write_generic,
4556 0x00000000);
4557 spr_register(env, SPR_THRM2, "THRM2",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 spr_register(env, SPR_THRM3, "THRM3",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565 /* XXX: not implemented */
4566 spr_register(env, SPR_750_TDCL, "TDCL",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_generic, &spr_write_generic,
4569 0x00000000);
4570 spr_register(env, SPR_750_TDCH, "TDCH",
4571 SPR_NOACCESS, SPR_NOACCESS,
4572 &spr_read_generic, &spr_write_generic,
4573 0x00000000);
4574 /* DMA */
4575 /* XXX : not implemented */
4576 spr_register(env, SPR_750_WPAR, "WPAR",
4577 SPR_NOACCESS, SPR_NOACCESS,
4578 &spr_read_generic, &spr_write_generic,
4579 0x00000000);
4580 spr_register(env, SPR_750_DMAL, "DMAL",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 spr_register(env, SPR_750_DMAU, "DMAU",
4585 SPR_NOACCESS, SPR_NOACCESS,
4586 &spr_read_generic, &spr_write_generic,
4587 0x00000000);
4588 /* Hardware implementation registers */
4589 /* XXX : not implemented */
4590 spr_register(env, SPR_HID0, "HID0",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594 /* XXX : not implemented */
4595 spr_register(env, SPR_HID1, "HID1",
4596 SPR_NOACCESS, SPR_NOACCESS,
4597 &spr_read_generic, &spr_write_generic,
4598 0x00000000);
4599 /* XXX : not implemented */
4600 spr_register(env, SPR_750CL_HID2, "HID2",
4601 SPR_NOACCESS, SPR_NOACCESS,
4602 &spr_read_generic, &spr_write_generic,
4603 0x00000000);
4604 /* XXX : not implemented */
4605 spr_register(env, SPR_750CL_HID4, "HID4",
4606 SPR_NOACCESS, SPR_NOACCESS,
4607 &spr_read_generic, &spr_write_generic,
4608 0x00000000);
4609 /* Quantization registers */
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_750_GQR0, "GQR0",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_750_GQR1, "GQR1",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
4620 /* XXX : not implemented */
4621 spr_register(env, SPR_750_GQR2, "GQR2",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625 /* XXX : not implemented */
4626 spr_register(env, SPR_750_GQR3, "GQR3",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630 /* XXX : not implemented */
4631 spr_register(env, SPR_750_GQR4, "GQR4",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 /* XXX : not implemented */
4636 spr_register(env, SPR_750_GQR5, "GQR5",
4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
4640 /* XXX : not implemented */
4641 spr_register(env, SPR_750_GQR6, "GQR6",
4642 SPR_NOACCESS, SPR_NOACCESS,
4643 &spr_read_generic, &spr_write_generic,
4644 0x00000000);
4645 /* XXX : not implemented */
4646 spr_register(env, SPR_750_GQR7, "GQR7",
4647 SPR_NOACCESS, SPR_NOACCESS,
4648 &spr_read_generic, &spr_write_generic,
4649 0x00000000);
4650 /* Memory management */
4651 register_low_BATs(env);
4652 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4653 register_high_BATs(env);
4654 init_excp_750cl(env);
4655 env->dcache_line_size = 32;
4656 env->icache_line_size = 32;
4657 /* Allocate hardware IRQ controller */
4658 ppc6xx_irq_init(env_archcpu(env));
4659 }
4660
4661 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
4662 {
4663 DeviceClass *dc = DEVICE_CLASS(oc);
4664 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4665
4666 dc->desc = "PowerPC 750 CL";
4667 pcc->init_proc = init_proc_750cl;
4668 pcc->check_pow = check_pow_hid0;
4669 /*
4670 * XXX: not implemented:
4671 * cache lock instructions:
4672 * dcbz_l
4673 * floating point paired instructions
4674 * psq_lux
4675 * psq_lx
4676 * psq_stux
4677 * psq_stx
4678 * ps_abs
4679 * ps_add
4680 * ps_cmpo0
4681 * ps_cmpo1
4682 * ps_cmpu0
4683 * ps_cmpu1
4684 * ps_div
4685 * ps_madd
4686 * ps_madds0
4687 * ps_madds1
4688 * ps_merge00
4689 * ps_merge01
4690 * ps_merge10
4691 * ps_merge11
4692 * ps_mr
4693 * ps_msub
4694 * ps_mul
4695 * ps_muls0
4696 * ps_muls1
4697 * ps_nabs
4698 * ps_neg
4699 * ps_nmadd
4700 * ps_nmsub
4701 * ps_res
4702 * ps_rsqrte
4703 * ps_sel
4704 * ps_sub
4705 * ps_sum0
4706 * ps_sum1
4707 */
4708 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4709 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4710 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4711 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4712 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4713 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4714 PPC_SEGMENT | PPC_EXTERN;
4715 pcc->msr_mask = (1ull << MSR_POW) |
4716 (1ull << MSR_ILE) |
4717 (1ull << MSR_EE) |
4718 (1ull << MSR_PR) |
4719 (1ull << MSR_FP) |
4720 (1ull << MSR_ME) |
4721 (1ull << MSR_FE0) |
4722 (1ull << MSR_SE) |
4723 (1ull << MSR_DE) |
4724 (1ull << MSR_FE1) |
4725 (1ull << MSR_EP) |
4726 (1ull << MSR_IR) |
4727 (1ull << MSR_DR) |
4728 (1ull << MSR_PMM) |
4729 (1ull << MSR_RI) |
4730 (1ull << MSR_LE);
4731 pcc->mmu_model = POWERPC_MMU_32B;
4732 pcc->excp_model = POWERPC_EXCP_7x0;
4733 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4734 pcc->bfd_mach = bfd_mach_ppc_750;
4735 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4736 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4737 }
4738
4739 static void init_proc_750cx(CPUPPCState *env)
4740 {
4741 register_ne_601_sprs(env);
4742 register_sdr1_sprs(env);
4743 register_7xx_sprs(env);
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_L2CR, "L2CR",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, spr_access_nop,
4748 0x00000000);
4749 /* Time base */
4750 register_tbl(env);
4751 /* Thermal management */
4752 register_thrm_sprs(env);
4753 /* This register is not implemented but is present for compatibility */
4754 spr_register(env, SPR_SDA, "SDA",
4755 SPR_NOACCESS, SPR_NOACCESS,
4756 &spr_read_generic, &spr_write_generic,
4757 0x00000000);
4758 /* Hardware implementation registers */
4759 /* XXX : not implemented */
4760 spr_register(env, SPR_HID0, "HID0",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_generic,
4763 0x00000000);
4764 /* XXX : not implemented */
4765 spr_register(env, SPR_HID1, "HID1",
4766 SPR_NOACCESS, SPR_NOACCESS,
4767 &spr_read_generic, &spr_write_generic,
4768 0x00000000);
4769 /* Memory management */
4770 register_low_BATs(env);
4771 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
4772 register_high_BATs(env);
4773 init_excp_750cx(env);
4774 env->dcache_line_size = 32;
4775 env->icache_line_size = 32;
4776 /* Allocate hardware IRQ controller */
4777 ppc6xx_irq_init(env_archcpu(env));
4778 }
4779
4780 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
4781 {
4782 DeviceClass *dc = DEVICE_CLASS(oc);
4783 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4784
4785 dc->desc = "PowerPC 750CX";
4786 pcc->init_proc = init_proc_750cx;
4787 pcc->check_pow = check_pow_hid0;
4788 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4789 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4790 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4791 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4792 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4794 PPC_SEGMENT | PPC_EXTERN;
4795 pcc->msr_mask = (1ull << MSR_POW) |
4796 (1ull << MSR_ILE) |
4797 (1ull << MSR_EE) |
4798 (1ull << MSR_PR) |
4799 (1ull << MSR_FP) |
4800 (1ull << MSR_ME) |
4801 (1ull << MSR_FE0) |
4802 (1ull << MSR_SE) |
4803 (1ull << MSR_DE) |
4804 (1ull << MSR_FE1) |
4805 (1ull << MSR_EP) |
4806 (1ull << MSR_IR) |
4807 (1ull << MSR_DR) |
4808 (1ull << MSR_PMM) |
4809 (1ull << MSR_RI) |
4810 (1ull << MSR_LE);
4811 pcc->mmu_model = POWERPC_MMU_32B;
4812 pcc->excp_model = POWERPC_EXCP_7x0;
4813 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4814 pcc->bfd_mach = bfd_mach_ppc_750;
4815 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4816 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4817 }
4818
4819 static void init_proc_750fx(CPUPPCState *env)
4820 {
4821 register_ne_601_sprs(env);
4822 register_sdr1_sprs(env);
4823 register_7xx_sprs(env);
4824 /* XXX : not implemented */
4825 spr_register(env, SPR_L2CR, "L2CR",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, spr_access_nop,
4828 0x00000000);
4829 /* Time base */
4830 register_tbl(env);
4831 /* Thermal management */
4832 register_thrm_sprs(env);
4833 /* XXX : not implemented */
4834 spr_register(env, SPR_750_THRM4, "THRM4",
4835 SPR_NOACCESS, SPR_NOACCESS,
4836 &spr_read_generic, &spr_write_generic,
4837 0x00000000);
4838 /* Hardware implementation registers */
4839 /* XXX : not implemented */
4840 spr_register(env, SPR_HID0, "HID0",
4841 SPR_NOACCESS, SPR_NOACCESS,
4842 &spr_read_generic, &spr_write_generic,
4843 0x00000000);
4844 /* XXX : not implemented */
4845 spr_register(env, SPR_HID1, "HID1",
4846 SPR_NOACCESS, SPR_NOACCESS,
4847 &spr_read_generic, &spr_write_generic,
4848 0x00000000);
4849 /* XXX : not implemented */
4850 spr_register(env, SPR_750FX_HID2, "HID2",
4851 SPR_NOACCESS, SPR_NOACCESS,
4852 &spr_read_generic, &spr_write_generic,
4853 0x00000000);
4854 /* Memory management */
4855 register_low_BATs(env);
4856 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4857 register_high_BATs(env);
4858 init_excp_7x0(env);
4859 env->dcache_line_size = 32;
4860 env->icache_line_size = 32;
4861 /* Allocate hardware IRQ controller */
4862 ppc6xx_irq_init(env_archcpu(env));
4863 }
4864
4865 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
4866 {
4867 DeviceClass *dc = DEVICE_CLASS(oc);
4868 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4869
4870 dc->desc = "PowerPC 750FX";
4871 pcc->init_proc = init_proc_750fx;
4872 pcc->check_pow = check_pow_hid0;
4873 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4874 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4875 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4876 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4877 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4878 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4879 PPC_SEGMENT | PPC_EXTERN;
4880 pcc->msr_mask = (1ull << MSR_POW) |
4881 (1ull << MSR_ILE) |
4882 (1ull << MSR_EE) |
4883 (1ull << MSR_PR) |
4884 (1ull << MSR_FP) |
4885 (1ull << MSR_ME) |
4886 (1ull << MSR_FE0) |
4887 (1ull << MSR_SE) |
4888 (1ull << MSR_DE) |
4889 (1ull << MSR_FE1) |
4890 (1ull << MSR_EP) |
4891 (1ull << MSR_IR) |
4892 (1ull << MSR_DR) |
4893 (1ull << MSR_PMM) |
4894 (1ull << MSR_RI) |
4895 (1ull << MSR_LE);
4896 pcc->mmu_model = POWERPC_MMU_32B;
4897 pcc->excp_model = POWERPC_EXCP_7x0;
4898 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4899 pcc->bfd_mach = bfd_mach_ppc_750;
4900 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4901 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4902 }
4903
4904 static void init_proc_750gx(CPUPPCState *env)
4905 {
4906 register_ne_601_sprs(env);
4907 register_sdr1_sprs(env);
4908 register_7xx_sprs(env);
4909 /* XXX : not implemented (XXX: different from 750fx) */
4910 spr_register(env, SPR_L2CR, "L2CR",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, spr_access_nop,
4913 0x00000000);
4914 /* Time base */
4915 register_tbl(env);
4916 /* Thermal management */
4917 register_thrm_sprs(env);
4918 /* XXX : not implemented */
4919 spr_register(env, SPR_750_THRM4, "THRM4",
4920 SPR_NOACCESS, SPR_NOACCESS,
4921 &spr_read_generic, &spr_write_generic,
4922 0x00000000);
4923 /* Hardware implementation registers */
4924 /* XXX : not implemented (XXX: different from 750fx) */
4925 spr_register(env, SPR_HID0, "HID0",
4926 SPR_NOACCESS, SPR_NOACCESS,
4927 &spr_read_generic, &spr_write_generic,
4928 0x00000000);
4929 /* XXX : not implemented */
4930 spr_register(env, SPR_HID1, "HID1",
4931 SPR_NOACCESS, SPR_NOACCESS,
4932 &spr_read_generic, &spr_write_generic,
4933 0x00000000);
4934 /* XXX : not implemented (XXX: different from 750fx) */
4935 spr_register(env, SPR_750FX_HID2, "HID2",
4936 SPR_NOACCESS, SPR_NOACCESS,
4937 &spr_read_generic, &spr_write_generic,
4938 0x00000000);
4939 /* Memory management */
4940 register_low_BATs(env);
4941 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4942 register_high_BATs(env);
4943 init_excp_7x0(env);
4944 env->dcache_line_size = 32;
4945 env->icache_line_size = 32;
4946 /* Allocate hardware IRQ controller */
4947 ppc6xx_irq_init(env_archcpu(env));
4948 }
4949
4950 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
4951 {
4952 DeviceClass *dc = DEVICE_CLASS(oc);
4953 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4954
4955 dc->desc = "PowerPC 750GX";
4956 pcc->init_proc = init_proc_750gx;
4957 pcc->check_pow = check_pow_hid0;
4958 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4959 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4960 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4961 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4962 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4963 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4964 PPC_SEGMENT | PPC_EXTERN;
4965 pcc->msr_mask = (1ull << MSR_POW) |
4966 (1ull << MSR_ILE) |
4967 (1ull << MSR_EE) |
4968 (1ull << MSR_PR) |
4969 (1ull << MSR_FP) |
4970 (1ull << MSR_ME) |
4971 (1ull << MSR_FE0) |
4972 (1ull << MSR_SE) |
4973 (1ull << MSR_DE) |
4974 (1ull << MSR_FE1) |
4975 (1ull << MSR_EP) |
4976 (1ull << MSR_IR) |
4977 (1ull << MSR_DR) |
4978 (1ull << MSR_PMM) |
4979 (1ull << MSR_RI) |
4980 (1ull << MSR_LE);
4981 pcc->mmu_model = POWERPC_MMU_32B;
4982 pcc->excp_model = POWERPC_EXCP_7x0;
4983 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4984 pcc->bfd_mach = bfd_mach_ppc_750;
4985 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4986 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4987 }
4988
4989 static void init_proc_745(CPUPPCState *env)
4990 {
4991 register_ne_601_sprs(env);
4992 register_sdr1_sprs(env);
4993 register_7xx_sprs(env);
4994 register_G2_755_sprs(env);
4995 /* Time base */
4996 register_tbl(env);
4997 /* Thermal management */
4998 register_thrm_sprs(env);
4999 /* Hardware implementation registers */
5000 /* XXX : not implemented */
5001 spr_register(env, SPR_HID0, "HID0",
5002 SPR_NOACCESS, SPR_NOACCESS,
5003 &spr_read_generic, &spr_write_generic,
5004 0x00000000);
5005 /* XXX : not implemented */
5006 spr_register(env, SPR_HID1, "HID1",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 /* XXX : not implemented */
5011 spr_register(env, SPR_HID2, "HID2",
5012 SPR_NOACCESS, SPR_NOACCESS,
5013 &spr_read_generic, &spr_write_generic,
5014 0x00000000);
5015 /* Memory management */
5016 register_low_BATs(env);
5017 register_high_BATs(env);
5018 register_6xx_7xx_soft_tlb(env, 64, 2);
5019 init_excp_7x5(env);
5020 env->dcache_line_size = 32;
5021 env->icache_line_size = 32;
5022 /* Allocate hardware IRQ controller */
5023 ppc6xx_irq_init(env_archcpu(env));
5024 }
5025
5026 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5027 {
5028 DeviceClass *dc = DEVICE_CLASS(oc);
5029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5030
5031 dc->desc = "PowerPC 745";
5032 pcc->init_proc = init_proc_745;
5033 pcc->check_pow = check_pow_hid0;
5034 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5035 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5036 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5037 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5038 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5039 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5040 PPC_SEGMENT | PPC_EXTERN;
5041 pcc->msr_mask = (1ull << MSR_POW) |
5042 (1ull << MSR_ILE) |
5043 (1ull << MSR_EE) |
5044 (1ull << MSR_PR) |
5045 (1ull << MSR_FP) |
5046 (1ull << MSR_ME) |
5047 (1ull << MSR_FE0) |
5048 (1ull << MSR_SE) |
5049 (1ull << MSR_DE) |
5050 (1ull << MSR_FE1) |
5051 (1ull << MSR_EP) |
5052 (1ull << MSR_IR) |
5053 (1ull << MSR_DR) |
5054 (1ull << MSR_PMM) |
5055 (1ull << MSR_RI) |
5056 (1ull << MSR_LE);
5057 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5058 pcc->excp_model = POWERPC_EXCP_7x5;
5059 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5060 pcc->bfd_mach = bfd_mach_ppc_750;
5061 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5062 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5063 }
5064
5065 static void init_proc_755(CPUPPCState *env)
5066 {
5067 register_ne_601_sprs(env);
5068 register_sdr1_sprs(env);
5069 register_7xx_sprs(env);
5070 register_G2_755_sprs(env);
5071 /* Time base */
5072 register_tbl(env);
5073 /* L2 cache control */
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_L2CR, "L2CR",
5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, spr_access_nop,
5078 0x00000000);
5079 /* XXX : not implemented */
5080 spr_register(env, SPR_L2PMCR, "L2PMCR",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 /* Thermal management */
5085 register_thrm_sprs(env);
5086 /* Hardware implementation registers */
5087 /* XXX : not implemented */
5088 spr_register(env, SPR_HID0, "HID0",
5089 SPR_NOACCESS, SPR_NOACCESS,
5090 &spr_read_generic, &spr_write_generic,
5091 0x00000000);
5092 /* XXX : not implemented */
5093 spr_register(env, SPR_HID1, "HID1",
5094 SPR_NOACCESS, SPR_NOACCESS,
5095 &spr_read_generic, &spr_write_generic,
5096 0x00000000);
5097 /* XXX : not implemented */
5098 spr_register(env, SPR_HID2, "HID2",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_generic,
5101 0x00000000);
5102 /* Memory management */
5103 register_low_BATs(env);
5104 register_high_BATs(env);
5105 register_6xx_7xx_soft_tlb(env, 64, 2);
5106 init_excp_7x5(env);
5107 env->dcache_line_size = 32;
5108 env->icache_line_size = 32;
5109 /* Allocate hardware IRQ controller */
5110 ppc6xx_irq_init(env_archcpu(env));
5111 }
5112
5113 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5114 {
5115 DeviceClass *dc = DEVICE_CLASS(oc);
5116 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5117
5118 dc->desc = "PowerPC 755";
5119 pcc->init_proc = init_proc_755;
5120 pcc->check_pow = check_pow_hid0;
5121 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5122 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5123 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5124 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5125 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5126 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5127 PPC_SEGMENT | PPC_EXTERN;
5128 pcc->msr_mask = (1ull << MSR_POW) |
5129 (1ull << MSR_ILE) |
5130 (1ull << MSR_EE) |
5131 (1ull << MSR_PR) |
5132 (1ull << MSR_FP) |
5133 (1ull << MSR_ME) |
5134 (1ull << MSR_FE0) |
5135 (1ull << MSR_SE) |
5136 (1ull << MSR_DE) |
5137 (1ull << MSR_FE1) |
5138 (1ull << MSR_EP) |
5139 (1ull << MSR_IR) |
5140 (1ull << MSR_DR) |
5141 (1ull << MSR_PMM) |
5142 (1ull << MSR_RI) |
5143 (1ull << MSR_LE);
5144 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5145 pcc->excp_model = POWERPC_EXCP_7x5;
5146 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5147 pcc->bfd_mach = bfd_mach_ppc_750;
5148 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5149 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5150 }
5151
5152 static void init_proc_7400(CPUPPCState *env)
5153 {
5154 register_ne_601_sprs(env);
5155 register_sdr1_sprs(env);
5156 register_7xx_sprs(env);
5157 /* Time base */
5158 register_tbl(env);
5159 /* 74xx specific SPR */
5160 register_74xx_sprs(env);
5161 vscr_init(env, 0x00010000);
5162 /* XXX : not implemented */
5163 spr_register(env, SPR_UBAMR, "UBAMR",
5164 &spr_read_ureg, SPR_NOACCESS,
5165 &spr_read_ureg, SPR_NOACCESS,
5166 0x00000000);
5167 /* XXX: this seems not implemented on all revisions. */
5168 /* XXX : not implemented */
5169 spr_register(env, SPR_MSSCR1, "MSSCR1",
5170 SPR_NOACCESS, SPR_NOACCESS,
5171 &spr_read_generic, &spr_write_generic,
5172 0x00000000);
5173 /* Thermal management */
5174 register_thrm_sprs(env);
5175 /* Memory management */
5176 register_low_BATs(env);
5177 init_excp_7400(env);
5178 env->dcache_line_size = 32;
5179 env->icache_line_size = 32;
5180 /* Allocate hardware IRQ controller */
5181 ppc6xx_irq_init(env_archcpu(env));
5182 }
5183
5184 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5185 {
5186 DeviceClass *dc = DEVICE_CLASS(oc);
5187 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5188
5189 dc->desc = "PowerPC 7400 (aka G4)";
5190 pcc->init_proc = init_proc_7400;
5191 pcc->check_pow = check_pow_hid0;
5192 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5193 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5194 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5195 PPC_FLOAT_STFIWX |
5196 PPC_CACHE | PPC_CACHE_ICBI |
5197 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5198 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5199 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5200 PPC_MEM_TLBIA |
5201 PPC_SEGMENT | PPC_EXTERN |
5202 PPC_ALTIVEC;
5203 pcc->msr_mask = (1ull << MSR_VR) |
5204 (1ull << MSR_POW) |
5205 (1ull << MSR_ILE) |
5206 (1ull << MSR_EE) |
5207 (1ull << MSR_PR) |
5208 (1ull << MSR_FP) |
5209 (1ull << MSR_ME) |
5210 (1ull << MSR_FE0) |
5211 (1ull << MSR_SE) |
5212 (1ull << MSR_DE) |
5213 (1ull << MSR_FE1) |
5214 (1ull << MSR_EP) |
5215 (1ull << MSR_IR) |
5216 (1ull << MSR_DR) |
5217 (1ull << MSR_PMM) |
5218 (1ull << MSR_RI) |
5219 (1ull << MSR_LE);
5220 pcc->mmu_model = POWERPC_MMU_32B;
5221 pcc->excp_model = POWERPC_EXCP_74xx;
5222 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5223 pcc->bfd_mach = bfd_mach_ppc_7400;
5224 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5225 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5226 POWERPC_FLAG_BUS_CLK;
5227 }
5228
5229 static void init_proc_7410(CPUPPCState *env)
5230 {
5231 register_ne_601_sprs(env);
5232 register_sdr1_sprs(env);
5233 register_7xx_sprs(env);
5234 /* Time base */
5235 register_tbl(env);
5236 /* 74xx specific SPR */
5237 register_74xx_sprs(env);
5238 vscr_init(env, 0x00010000);
5239 /* XXX : not implemented */
5240 spr_register(env, SPR_UBAMR, "UBAMR",
5241 &spr_read_ureg, SPR_NOACCESS,
5242 &spr_read_ureg, SPR_NOACCESS,
5243 0x00000000);
5244 /* Thermal management */
5245 register_thrm_sprs(env);
5246 /* L2PMCR */
5247 /* XXX : not implemented */
5248 spr_register(env, SPR_L2PMCR, "L2PMCR",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 0x00000000);
5252 /* LDSTDB */
5253 /* XXX : not implemented */
5254 spr_register(env, SPR_LDSTDB, "LDSTDB",
5255 SPR_NOACCESS, SPR_NOACCESS,
5256 &spr_read_generic, &spr_write_generic,
5257 0x00000000);
5258 /* Memory management */
5259 register_low_BATs(env);
5260 init_excp_7400(env);
5261 env->dcache_line_size = 32;
5262 env->icache_line_size = 32;
5263 /* Allocate hardware IRQ controller */
5264 ppc6xx_irq_init(env_archcpu(env));
5265 }
5266
5267 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5268 {
5269 DeviceClass *dc = DEVICE_CLASS(oc);
5270 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5271
5272 dc->desc = "PowerPC 7410 (aka G4)";
5273 pcc->init_proc = init_proc_7410;
5274 pcc->check_pow = check_pow_hid0;
5275 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5276 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5277 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5278 PPC_FLOAT_STFIWX |
5279 PPC_CACHE | PPC_CACHE_ICBI |
5280 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5281 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5282 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5283 PPC_MEM_TLBIA |
5284 PPC_SEGMENT | PPC_EXTERN |
5285 PPC_ALTIVEC;
5286 pcc->msr_mask = (1ull << MSR_VR) |
5287 (1ull << MSR_POW) |
5288 (1ull << MSR_ILE) |
5289 (1ull << MSR_EE) |
5290 (1ull << MSR_PR) |
5291 (1ull << MSR_FP) |
5292 (1ull << MSR_ME) |
5293 (1ull << MSR_FE0) |
5294 (1ull << MSR_SE) |
5295 (1ull << MSR_DE) |
5296 (1ull << MSR_FE1) |
5297 (1ull << MSR_EP) |
5298 (1ull << MSR_IR) |
5299 (1ull << MSR_DR) |
5300 (1ull << MSR_PMM) |
5301 (1ull << MSR_RI) |
5302 (1ull << MSR_LE);
5303 pcc->mmu_model = POWERPC_MMU_32B;
5304 pcc->excp_model = POWERPC_EXCP_74xx;
5305 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5306 pcc->bfd_mach = bfd_mach_ppc_7400;
5307 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5308 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5309 POWERPC_FLAG_BUS_CLK;
5310 }
5311
5312 static void init_proc_7440(CPUPPCState *env)
5313 {
5314 register_ne_601_sprs(env);
5315 register_sdr1_sprs(env);
5316 register_7xx_sprs(env);
5317 /* Time base */
5318 register_tbl(env);
5319 /* 74xx specific SPR */
5320 register_74xx_sprs(env);
5321 vscr_init(env, 0x00010000);
5322 /* XXX : not implemented */
5323 spr_register(env, SPR_UBAMR, "UBAMR",
5324 &spr_read_ureg, SPR_NOACCESS,
5325 &spr_read_ureg, SPR_NOACCESS,
5326 0x00000000);
5327 /* LDSTCR */
5328 /* XXX : not implemented */
5329 spr_register(env, SPR_LDSTCR, "LDSTCR",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333 /* ICTRL */
5334 /* XXX : not implemented */
5335 spr_register(env, SPR_ICTRL, "ICTRL",
5336 SPR_NOACCESS, SPR_NOACCESS,
5337 &spr_read_generic, &spr_write_generic,
5338 0x00000000);
5339 /* MSSSR0 */
5340 /* XXX : not implemented */
5341 spr_register(env, SPR_MSSSR0, "MSSSR0",
5342 SPR_NOACCESS, SPR_NOACCESS,
5343 &spr_read_generic, &spr_write_generic,
5344 0x00000000);
5345 /* PMC */
5346 /* XXX : not implemented */
5347 spr_register(env, SPR_7XX_PMC5, "PMC5",
5348 SPR_NOACCESS, SPR_NOACCESS,
5349 &spr_read_generic, &spr_write_generic,
5350 0x00000000);
5351 /* XXX : not implemented */
5352 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5353 &spr_read_ureg, SPR_NOACCESS,
5354 &spr_read_ureg, SPR_NOACCESS,
5355 0x00000000);
5356 /* XXX : not implemented */
5357 spr_register(env, SPR_7XX_PMC6, "PMC6",
5358 SPR_NOACCESS, SPR_NOACCESS,
5359 &spr_read_generic, &spr_write_generic,
5360 0x00000000);
5361 /* XXX : not implemented */
5362 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5363 &spr_read_ureg, SPR_NOACCESS,
5364 &spr_read_ureg, SPR_NOACCESS,
5365 0x00000000);
5366 /* Memory management */
5367 register_low_BATs(env);
5368 init_excp_7450(env);
5369 env->dcache_line_size = 32;
5370 env->icache_line_size = 32;
5371 /* Allocate hardware IRQ controller */
5372 ppc6xx_irq_init(env_archcpu(env));
5373 }
5374
5375 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5376 {
5377 DeviceClass *dc = DEVICE_CLASS(oc);
5378 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5379
5380 dc->desc = "PowerPC 7440 (aka G4)";
5381 pcc->init_proc = init_proc_7440;
5382 pcc->check_pow = check_pow_hid0_74xx;
5383 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5384 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5385 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5386 PPC_FLOAT_STFIWX |
5387 PPC_CACHE | PPC_CACHE_ICBI |
5388 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5391 PPC_MEM_TLBIA |
5392 PPC_SEGMENT | PPC_EXTERN |
5393 PPC_ALTIVEC;
5394 pcc->msr_mask = (1ull << MSR_VR) |
5395 (1ull << MSR_POW) |
5396 (1ull << MSR_ILE) |
5397 (1ull << MSR_EE) |
5398 (1ull << MSR_PR) |
5399 (1ull << MSR_FP) |
5400 (1ull << MSR_ME) |
5401 (1ull << MSR_FE0) |
5402 (1ull << MSR_SE) |
5403 (1ull << MSR_DE) |
5404 (1ull << MSR_FE1) |
5405 (1ull << MSR_EP) |
5406 (1ull << MSR_IR) |
5407 (1ull << MSR_DR) |
5408 (1ull << MSR_PMM) |
5409 (1ull << MSR_RI) |
5410 (1ull << MSR_LE);
5411 pcc->mmu_model = POWERPC_MMU_32B;
5412 pcc->excp_model = POWERPC_EXCP_74xx;
5413 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5414 pcc->bfd_mach = bfd_mach_ppc_7400;
5415 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5416 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5417 POWERPC_FLAG_BUS_CLK;
5418 }
5419
5420 static void init_proc_7450(CPUPPCState *env)
5421 {
5422 register_ne_601_sprs(env);
5423 register_sdr1_sprs(env);
5424 register_7xx_sprs(env);
5425 /* Time base */
5426 register_tbl(env);
5427 /* 74xx specific SPR */
5428 register_74xx_sprs(env);
5429 vscr_init(env, 0x00010000);
5430 /* Level 3 cache control */
5431 register_l3_ctrl(env);
5432 /* L3ITCR1 */
5433 /* XXX : not implemented */
5434 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
5438 /* L3ITCR2 */
5439 /* XXX : not implemented */
5440 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5441 SPR_NOACCESS, SPR_NOACCESS,
5442 &spr_read_generic, &spr_write_generic,
5443 0x00000000);
5444 /* L3ITCR3 */
5445 /* XXX : not implemented */
5446 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 &spr_read_generic, &spr_write_generic,
5449 0x00000000);
5450 /* L3OHCR */
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_L3OHCR, "L3OHCR",
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_generic, &spr_write_generic,
5455 0x00000000);
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_UBAMR, "UBAMR",
5458 &spr_read_ureg, SPR_NOACCESS,
5459 &spr_read_ureg, SPR_NOACCESS,
5460 0x00000000);
5461 /* LDSTCR */
5462 /* XXX : not implemented */
5463 spr_register(env, SPR_LDSTCR, "LDSTCR",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 /* ICTRL */
5468 /* XXX : not implemented */
5469 spr_register(env, SPR_ICTRL, "ICTRL",
5470 SPR_NOACCESS, SPR_NOACCESS,
5471 &spr_read_generic, &spr_write_generic,
5472 0x00000000);
5473 /* MSSSR0 */
5474 /* XXX : not implemented */
5475 spr_register(env, SPR_MSSSR0, "MSSSR0",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 &spr_read_generic, &spr_write_generic,
5478 0x00000000);
5479 /* PMC */
5480 /* XXX : not implemented */
5481 spr_register(env, SPR_7XX_PMC5, "PMC5",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 /* XXX : not implemented */
5486 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5487 &spr_read_ureg, SPR_NOACCESS,
5488 &spr_read_ureg, SPR_NOACCESS,
5489 0x00000000);
5490 /* XXX : not implemented */
5491 spr_register(env, SPR_7XX_PMC6, "PMC6",
5492 SPR_NOACCESS, SPR_NOACCESS,
5493 &spr_read_generic, &spr_write_generic,
5494 0x00000000);
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5497 &spr_read_ureg, SPR_NOACCESS,
5498 &spr_read_ureg, SPR_NOACCESS,
5499 0x00000000);
5500 /* Memory management */
5501 register_low_BATs(env);
5502 init_excp_7450(env);
5503 env->dcache_line_size = 32;
5504 env->icache_line_size = 32;
5505 /* Allocate hardware IRQ controller */
5506 ppc6xx_irq_init(env_archcpu(env));
5507 }
5508
5509 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
5510 {
5511 DeviceClass *dc = DEVICE_CLASS(oc);
5512 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5513
5514 dc->desc = "PowerPC 7450 (aka G4)";
5515 pcc->init_proc = init_proc_7450;
5516 pcc->check_pow = check_pow_hid0_74xx;
5517 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5518 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5519 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5520 PPC_FLOAT_STFIWX |
5521 PPC_CACHE | PPC_CACHE_ICBI |
5522 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5523 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5524 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5525 PPC_MEM_TLBIA |
5526 PPC_SEGMENT | PPC_EXTERN |
5527 PPC_ALTIVEC;
5528 pcc->msr_mask = (1ull << MSR_VR) |
5529 (1ull << MSR_POW) |
5530 (1ull << MSR_ILE) |
5531 (1ull << MSR_EE) |
5532 (1ull << MSR_PR) |
5533 (1ull << MSR_FP) |
5534 (1ull << MSR_ME) |
5535 (1ull << MSR_FE0) |
5536 (1ull << MSR_SE) |
5537 (1ull << MSR_DE) |
5538 (1ull << MSR_FE1) |
5539 (1ull << MSR_EP) |
5540 (1ull << MSR_IR) |
5541 (1ull << MSR_DR) |
5542 (1ull << MSR_PMM) |
5543 (1ull << MSR_RI) |
5544 (1ull << MSR_LE);
5545 pcc->mmu_model = POWERPC_MMU_32B;
5546 pcc->excp_model = POWERPC_EXCP_74xx;
5547 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5548 pcc->bfd_mach = bfd_mach_ppc_7400;
5549 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5550 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5551 POWERPC_FLAG_BUS_CLK;
5552 }
5553
5554 static void init_proc_7445(CPUPPCState *env)
5555 {
5556 register_ne_601_sprs(env);
5557 register_sdr1_sprs(env);
5558 register_7xx_sprs(env);
5559 /* Time base */
5560 register_tbl(env);
5561 /* 74xx specific SPR */
5562 register_74xx_sprs(env);
5563 vscr_init(env, 0x00010000);
5564 /* LDSTCR */
5565 /* XXX : not implemented */
5566 spr_register(env, SPR_LDSTCR, "LDSTCR",
5567 SPR_NOACCESS, SPR_NOACCESS,
5568 &spr_read_generic, &spr_write_generic,
5569 0x00000000);
5570 /* ICTRL */
5571 /* XXX : not implemented */
5572 spr_register(env, SPR_ICTRL, "ICTRL",
5573 SPR_NOACCESS, SPR_NOACCESS,
5574 &spr_read_generic, &spr_write_generic,
5575 0x00000000);
5576 /* MSSSR0 */
5577 /* XXX : not implemented */
5578 spr_register(env, SPR_MSSSR0, "MSSSR0",
5579 SPR_NOACCESS, SPR_NOACCESS,
5580 &spr_read_generic, &spr_write_generic,
5581 0x00000000);
5582 /* PMC */
5583 /* XXX : not implemented */
5584 spr_register(env, SPR_7XX_PMC5, "PMC5",
5585 SPR_NOACCESS, SPR_NOACCESS,
5586 &spr_read_generic, &spr_write_generic,
5587 0x00000000);
5588 /* XXX : not implemented */
5589 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5590 &spr_read_ureg, SPR_NOACCESS,
5591 &spr_read_ureg, SPR_NOACCESS,
5592 0x00000000);
5593 /* XXX : not implemented */
5594 spr_register(env, SPR_7XX_PMC6, "PMC6",
5595 SPR_NOACCESS, SPR_NOACCESS,
5596 &spr_read_generic, &spr_write_generic,
5597 0x00000000);
5598 /* XXX : not implemented */
5599 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5600 &spr_read_ureg, SPR_NOACCESS,
5601 &spr_read_ureg, SPR_NOACCESS,
5602 0x00000000);
5603 /* SPRGs */
5604 spr_register(env, SPR_SPRG4, "SPRG4",
5605 SPR_NOACCESS, SPR_NOACCESS,
5606 &spr_read_generic, &spr_write_generic,
5607 0x00000000);
5608 spr_register(env, SPR_USPRG4, "USPRG4",
5609 &spr_read_ureg, SPR_NOACCESS,
5610 &spr_read_ureg, SPR_NOACCESS,
5611 0x00000000);
5612 spr_register(env, SPR_SPRG5, "SPRG5",
5613 SPR_NOACCESS, SPR_NOACCESS,
5614 &spr_read_generic, &spr_write_generic,
5615 0x00000000);
5616 spr_register(env, SPR_USPRG5, "USPRG5",
5617 &spr_read_ureg, SPR_NOACCESS,
5618 &spr_read_ureg, SPR_NOACCESS,
5619 0x00000000);
5620 spr_register(env, SPR_SPRG6, "SPRG6",
5621 SPR_NOACCESS, SPR_NOACCESS,
5622 &spr_read_generic, &spr_write_generic,
5623 0x00000000);
5624 spr_register(env, SPR_USPRG6, "USPRG6",
5625 &spr_read_ureg, SPR_NOACCESS,
5626 &spr_read_ureg, SPR_NOACCESS,
5627 0x00000000);
5628 spr_register(env, SPR_SPRG7, "SPRG7",
5629 SPR_NOACCESS, SPR_NOACCESS,
5630 &spr_read_generic, &spr_write_generic,
5631 0x00000000);
5632 spr_register(env, SPR_USPRG7, "USPRG7",
5633 &spr_read_ureg, SPR_NOACCESS,
5634 &spr_read_ureg, SPR_NOACCESS,
5635 0x00000000);
5636 /* Memory management */
5637 register_low_BATs(env);
5638 register_high_BATs(env);
5639 init_excp_7450(env);
5640 env->dcache_line_size = 32;
5641 env->icache_line_size = 32;
5642 /* Allocate hardware IRQ controller */
5643 ppc6xx_irq_init(env_archcpu(env));
5644 }
5645
5646 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
5647 {
5648 DeviceClass *dc = DEVICE_CLASS(oc);
5649 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5650
5651 dc->desc = "PowerPC 7445 (aka G4)";
5652 pcc->init_proc = init_proc_7445;
5653 pcc->check_pow = check_pow_hid0_74xx;
5654 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5655 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5656 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5657 PPC_FLOAT_STFIWX |
5658 PPC_CACHE | PPC_CACHE_ICBI |
5659 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5660 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5661 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5662 PPC_MEM_TLBIA |
5663 PPC_SEGMENT | PPC_EXTERN |
5664 PPC_ALTIVEC;
5665 pcc->msr_mask = (1ull << MSR_VR) |
5666 (1ull << MSR_POW) |
5667 (1ull << MSR_ILE) |
5668 (1ull << MSR_EE) |
5669 (1ull << MSR_PR) |
5670 (1ull << MSR_FP) |
5671 (1ull << MSR_ME) |
5672 (1ull << MSR_FE0) |
5673 (1ull << MSR_SE) |
5674 (1ull << MSR_DE) |
5675 (1ull << MSR_FE1) |
5676 (1ull << MSR_EP) |
5677 (1ull << MSR_IR) |
5678 (1ull << MSR_DR) |
5679 (1ull << MSR_PMM) |
5680 (1ull << MSR_RI) |
5681 (1ull << MSR_LE);
5682 pcc->mmu_model = POWERPC_MMU_32B;
5683 pcc->excp_model = POWERPC_EXCP_74xx;
5684 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5685 pcc->bfd_mach = bfd_mach_ppc_7400;
5686 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5687 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5688 POWERPC_FLAG_BUS_CLK;
5689 }
5690
5691 static void init_proc_7455(CPUPPCState *env)
5692 {
5693 register_ne_601_sprs(env);
5694 register_sdr1_sprs(env);
5695 register_7xx_sprs(env);
5696 /* Time base */
5697 register_tbl(env);
5698 /* 74xx specific SPR */
5699 register_74xx_sprs(env);
5700 vscr_init(env, 0x00010000);
5701 /* Level 3 cache control */
5702 register_l3_ctrl(env);
5703 /* LDSTCR */
5704 /* XXX : not implemented */
5705 spr_register(env, SPR_LDSTCR, "LDSTCR",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_generic, &spr_write_generic,
5708 0x00000000);
5709 /* ICTRL */
5710 /* XXX : not implemented */
5711 spr_register(env, SPR_ICTRL, "ICTRL",
5712 SPR_NOACCESS, SPR_NOACCESS,
5713 &spr_read_generic, &spr_write_generic,
5714 0x00000000);
5715 /* MSSSR0 */
5716 /* XXX : not implemented */
5717 spr_register(env, SPR_MSSSR0, "MSSSR0",
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_generic, &spr_write_generic,
5720 0x00000000);
5721 /* PMC */
5722 /* XXX : not implemented */
5723 spr_register(env, SPR_7XX_PMC5, "PMC5",
5724 SPR_NOACCESS, SPR_NOACCESS,
5725 &spr_read_generic, &spr_write_generic,
5726 0x00000000);
5727 /* XXX : not implemented */
5728 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5729 &spr_read_ureg, SPR_NOACCESS,
5730 &spr_read_ureg, SPR_NOACCESS,
5731 0x00000000);
5732 /* XXX : not implemented */
5733 spr_register(env, SPR_7XX_PMC6, "PMC6",
5734 SPR_NOACCESS, SPR_NOACCESS,
5735 &spr_read_generic, &spr_write_generic,
5736 0x00000000);
5737 /* XXX : not implemented */
5738 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5739 &spr_read_ureg, SPR_NOACCESS,
5740 &spr_read_ureg, SPR_NOACCESS,
5741 0x00000000);
5742 /* SPRGs */
5743 spr_register(env, SPR_SPRG4, "SPRG4",
5744 SPR_NOACCESS, SPR_NOACCESS,
5745 &spr_read_generic, &spr_write_generic,
5746 0x00000000);
5747 spr_register(env, SPR_USPRG4, "USPRG4",
5748 &spr_read_ureg, SPR_NOACCESS,
5749 &spr_read_ureg, SPR_NOACCESS,
5750 0x00000000);
5751 spr_register(env, SPR_SPRG5, "SPRG5",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 &spr_read_generic, &spr_write_generic,
5754 0x00000000);
5755 spr_register(env, SPR_USPRG5, "USPRG5",
5756 &spr_read_ureg, SPR_NOACCESS,
5757 &spr_read_ureg, SPR_NOACCESS,
5758 0x00000000);
5759 spr_register(env, SPR_SPRG6, "SPRG6",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 spr_register(env, SPR_USPRG6, "USPRG6",
5764 &spr_read_ureg, SPR_NOACCESS,
5765 &spr_read_ureg, SPR_NOACCESS,
5766 0x00000000);
5767 spr_register(env, SPR_SPRG7, "SPRG7",
5768 SPR_NOACCESS, SPR_NOACCESS,
5769 &spr_read_generic, &spr_write_generic,
5770 0x00000000);
5771 spr_register(env, SPR_USPRG7, "USPRG7",
5772 &spr_read_ureg, SPR_NOACCESS,
5773 &spr_read_ureg, SPR_NOACCESS,
5774 0x00000000);
5775 /* Memory management */
5776 register_low_BATs(env);
5777 register_high_BATs(env);
5778 init_excp_7450(env);
5779 env->dcache_line_size = 32;
5780 env->icache_line_size = 32;
5781 /* Allocate hardware IRQ controller */
5782 ppc6xx_irq_init(env_archcpu(env));
5783 }
5784
5785 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
5786 {
5787 DeviceClass *dc = DEVICE_CLASS(oc);
5788 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5789
5790 dc->desc = "PowerPC 7455 (aka G4)";
5791 pcc->init_proc = init_proc_7455;
5792 pcc->check_pow = check_pow_hid0_74xx;
5793 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5794 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5795 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5796 PPC_FLOAT_STFIWX |
5797 PPC_CACHE | PPC_CACHE_ICBI |
5798 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5799 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5801 PPC_MEM_TLBIA |
5802 PPC_SEGMENT | PPC_EXTERN |
5803 PPC_ALTIVEC;
5804 pcc->msr_mask = (1ull << MSR_VR) |
5805 (1ull << MSR_POW) |
5806 (1ull << MSR_ILE) |
5807 (1ull << MSR_EE) |
5808 (1ull << MSR_PR) |
5809 (1ull << MSR_FP) |
5810 (1ull << MSR_ME) |
5811 (1ull << MSR_FE0) |
5812 (1ull << MSR_SE) |
5813 (1ull << MSR_DE) |
5814 (1ull << MSR_FE1) |
5815 (1ull << MSR_EP) |
5816 (1ull << MSR_IR) |
5817 (1ull << MSR_DR) |
5818 (1ull << MSR_PMM) |
5819 (1ull << MSR_RI) |
5820 (1ull << MSR_LE);
5821 pcc->mmu_model = POWERPC_MMU_32B;
5822 pcc->excp_model = POWERPC_EXCP_74xx;
5823 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5824 pcc->bfd_mach = bfd_mach_ppc_7400;
5825 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5826 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5827 POWERPC_FLAG_BUS_CLK;
5828 }
5829
5830 static void init_proc_7457(CPUPPCState *env)
5831 {
5832 register_ne_601_sprs(env);
5833 register_sdr1_sprs(env);
5834 register_7xx_sprs(env);
5835 /* Time base */
5836 register_tbl(env);
5837 /* 74xx specific SPR */
5838 register_74xx_sprs(env);
5839 vscr_init(env, 0x00010000);
5840 /* Level 3 cache control */
5841 register_l3_ctrl(env);
5842 /* L3ITCR1 */
5843 /* XXX : not implemented */
5844 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 0x00000000);
5848 /* L3ITCR2 */
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* L3ITCR3 */
5855 /* XXX : not implemented */
5856 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5857 SPR_NOACCESS, SPR_NOACCESS,
5858 &spr_read_generic, &spr_write_generic,
5859 0x00000000);
5860 /* L3OHCR */
5861 /* XXX : not implemented */
5862 spr_register(env, SPR_L3OHCR, "L3OHCR",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 /* LDSTCR */
5867 /* XXX : not implemented */
5868 spr_register(env, SPR_LDSTCR, "LDSTCR",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 /* ICTRL */
5873 /* XXX : not implemented */
5874 spr_register(env, SPR_ICTRL, "ICTRL",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 /* MSSSR0 */
5879 /* XXX : not implemented */
5880 spr_register(env, SPR_MSSSR0, "MSSSR0",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 /* PMC */
5885 /* XXX : not implemented */
5886 spr_register(env, SPR_7XX_PMC5, "PMC5",
5887 SPR_NOACCESS, SPR_NOACCESS,
5888 &spr_read_generic, &spr_write_generic,
5889 0x00000000);
5890 /* XXX : not implemented */
5891 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
5892 &spr_read_ureg, SPR_NOACCESS,
5893 &spr_read_ureg, SPR_NOACCESS,
5894 0x00000000);
5895 /* XXX : not implemented */
5896 spr_register(env, SPR_7XX_PMC6, "PMC6",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 /* XXX : not implemented */
5901 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
5902 &spr_read_ureg, SPR_NOACCESS,
5903 &spr_read_ureg, SPR_NOACCESS,
5904 0x00000000);
5905 /* SPRGs */
5906 spr_register(env, SPR_SPRG4, "SPRG4",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000);
5910 spr_register(env, SPR_USPRG4, "USPRG4",
5911 &spr_read_ureg, SPR_NOACCESS,
5912 &spr_read_ureg, SPR_NOACCESS,
5913 0x00000000);
5914 spr_register(env, SPR_SPRG5, "SPRG5",
5915 SPR_NOACCESS, SPR_NOACCESS,
5916 &spr_read_generic, &spr_write_generic,
5917 0x00000000);
5918 spr_register(env, SPR_USPRG5, "USPRG5",
5919 &spr_read_ureg, SPR_NOACCESS,
5920 &spr_read_ureg, SPR_NOACCESS,
5921 0x00000000);
5922 spr_register(env, SPR_SPRG6, "SPRG6",
5923 SPR_NOACCESS, SPR_NOACCESS,
5924 &spr_read_generic, &spr_write_generic,
5925 0x00000000);
5926 spr_register(env, SPR_USPRG6, "USPRG6",
5927 &spr_read_ureg, SPR_NOACCESS,
5928 &spr_read_ureg, SPR_NOACCESS,
5929 0x00000000);
5930 spr_register(env, SPR_SPRG7, "SPRG7",
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 &spr_read_generic, &spr_write_generic,
5933 0x00000000);
5934 spr_register(env, SPR_USPRG7, "USPRG7",
5935 &spr_read_ureg, SPR_NOACCESS,
5936 &spr_read_ureg, SPR_NOACCESS,
5937 0x00000000);
5938 /* Memory management */
5939 register_low_BATs(env);
5940 register_high_BATs(env);
5941 init_excp_7450(env);
5942 env->dcache_line_size = 32;
5943 env->icache_line_size = 32;
5944 /* Allocate hardware IRQ controller */
5945 ppc6xx_irq_init(env_archcpu(env));
5946 }
5947
5948 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
5949 {
5950 DeviceClass *dc = DEVICE_CLASS(oc);
5951 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5952
5953 dc->desc = "PowerPC 7457 (aka G4)";
5954 pcc->init_proc = init_proc_7457;
5955 pcc->check_pow = check_pow_hid0_74xx;
5956 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5957 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5958 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5959 PPC_FLOAT_STFIWX |
5960 PPC_CACHE | PPC_CACHE_ICBI |
5961 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5962 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5963 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5964 PPC_MEM_TLBIA |
5965 PPC_SEGMENT | PPC_EXTERN |
5966 PPC_ALTIVEC;
5967 pcc->msr_mask = (1ull << MSR_VR) |
5968 (1ull << MSR_POW) |
5969 (1ull << MSR_ILE) |
5970 (1ull << MSR_EE) |
5971 (1ull << MSR_PR) |
5972 (1ull << MSR_FP) |
5973 (1ull << MSR_ME) |
5974 (1ull << MSR_FE0) |
5975 (1ull << MSR_SE) |
5976 (1ull << MSR_DE) |
5977 (1ull << MSR_FE1) |
5978 (1ull << MSR_EP) |
5979 (1ull << MSR_IR) |
5980 (1ull << MSR_DR) |
5981 (1ull << MSR_PMM) |
5982 (1ull << MSR_RI) |
5983 (1ull << MSR_LE);
5984 pcc->mmu_model = POWERPC_MMU_32B;
5985 pcc->excp_model = POWERPC_EXCP_74xx;
5986 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5987 pcc->bfd_mach = bfd_mach_ppc_7400;
5988 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5989 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5990 POWERPC_FLAG_BUS_CLK;
5991 }
5992
5993 static void init_proc_e600(CPUPPCState *env)
5994 {
5995 register_ne_601_sprs(env);
5996 register_sdr1_sprs(env);
5997 register_7xx_sprs(env);
5998 /* Time base */
5999 register_tbl(env);
6000 /* 74xx specific SPR */
6001 register_74xx_sprs(env);
6002 vscr_init(env, 0x00010000);
6003 /* XXX : not implemented */
6004 spr_register(env, SPR_UBAMR, "UBAMR",
6005 &spr_read_ureg, SPR_NOACCESS,
6006 &spr_read_ureg, SPR_NOACCESS,
6007 0x00000000);
6008 /* XXX : not implemented */
6009 spr_register(env, SPR_LDSTCR, "LDSTCR",
6010 SPR_NOACCESS, SPR_NOACCESS,
6011 &spr_read_generic, &spr_write_generic,
6012 0x00000000);
6013 /* XXX : not implemented */
6014 spr_register(env, SPR_ICTRL, "ICTRL",
6015 SPR_NOACCESS, SPR_NOACCESS,
6016 &spr_read_generic, &spr_write_generic,
6017 0x00000000);
6018 /* XXX : not implemented */
6019 spr_register(env, SPR_MSSSR0, "MSSSR0",
6020 SPR_NOACCESS, SPR_NOACCESS,
6021 &spr_read_generic, &spr_write_generic,
6022 0x00000000);
6023 /* XXX : not implemented */
6024 spr_register(env, SPR_7XX_PMC5, "PMC5",
6025 SPR_NOACCESS, SPR_NOACCESS,
6026 &spr_read_generic, &spr_write_generic,
6027 0x00000000);
6028 /* XXX : not implemented */
6029 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6030 &spr_read_ureg, SPR_NOACCESS,
6031 &spr_read_ureg, SPR_NOACCESS,
6032 0x00000000);
6033 /* XXX : not implemented */
6034 spr_register(env, SPR_7XX_PMC6, "PMC6",
6035 SPR_NOACCESS, SPR_NOACCESS,
6036 &spr_read_generic, &spr_write_generic,
6037 0x00000000);
6038 /* XXX : not implemented */
6039 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6040 &spr_read_ureg, SPR_NOACCESS,
6041 &spr_read_ureg, SPR_NOACCESS,
6042 0x00000000);
6043 /* SPRGs */
6044 spr_register(env, SPR_SPRG4, "SPRG4",
6045 SPR_NOACCESS, SPR_NOACCESS,
6046 &spr_read_generic, &spr_write_generic,
6047 0x00000000);
6048 spr_register(env, SPR_USPRG4, "USPRG4",
6049 &spr_read_ureg, SPR_NOACCESS,
6050 &spr_read_ureg, SPR_NOACCESS,
6051 0x00000000);
6052 spr_register(env, SPR_SPRG5, "SPRG5",
6053 SPR_NOACCESS, SPR_NOACCESS,
6054 &spr_read_generic, &spr_write_generic,
6055 0x00000000);
6056 spr_register(env, SPR_USPRG5, "USPRG5",
6057 &spr_read_ureg, SPR_NOACCESS,
6058 &spr_read_ureg, SPR_NOACCESS,
6059 0x00000000);
6060 spr_register(env, SPR_SPRG6, "SPRG6",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 spr_register(env, SPR_USPRG6, "USPRG6",
6065 &spr_read_ureg, SPR_NOACCESS,
6066 &spr_read_ureg, SPR_NOACCESS,
6067 0x00000000);
6068 spr_register(env, SPR_SPRG7, "SPRG7",
6069 SPR_NOACCESS, SPR_NOACCESS,
6070 &spr_read_generic, &spr_write_generic,
6071 0x00000000);
6072 spr_register(env, SPR_USPRG7, "USPRG7",
6073 &spr_read_ureg, SPR_NOACCESS,
6074 &spr_read_ureg, SPR_NOACCESS,
6075 0x00000000);
6076 /* Memory management */
6077 register_low_BATs(env);
6078 register_high_BATs(env);
6079 init_excp_7450(env);
6080 env->dcache_line_size = 32;
6081 env->icache_line_size = 32;
6082 /* Allocate hardware IRQ controller */
6083 ppc6xx_irq_init(env_archcpu(env));
6084 }
6085
6086 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6087 {
6088 DeviceClass *dc = DEVICE_CLASS(oc);
6089 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6090
6091 dc->desc = "PowerPC e600";
6092 pcc->init_proc = init_proc_e600;
6093 pcc->check_pow = check_pow_hid0_74xx;
6094 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6095 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6096 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6097 PPC_FLOAT_STFIWX |
6098 PPC_CACHE | PPC_CACHE_ICBI |
6099 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6100 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6102 PPC_MEM_TLBIA |
6103 PPC_SEGMENT | PPC_EXTERN |
6104 PPC_ALTIVEC;
6105 pcc->insns_flags2 = PPC_NONE;
6106 pcc->msr_mask = (1ull << MSR_VR) |
6107 (1ull << MSR_POW) |
6108 (1ull << MSR_ILE) |
6109 (1ull << MSR_EE) |
6110 (1ull << MSR_PR) |
6111 (1ull << MSR_FP) |
6112 (1ull << MSR_ME) |
6113 (1ull << MSR_FE0) |
6114 (1ull << MSR_SE) |
6115 (1ull << MSR_DE) |
6116 (1ull << MSR_FE1) |
6117 (1ull << MSR_EP) |
6118 (1ull << MSR_IR) |
6119 (1ull << MSR_DR) |
6120 (1ull << MSR_PMM) |
6121 (1ull << MSR_RI) |
6122 (1ull << MSR_LE);
6123 pcc->mmu_model = POWERPC_MMU_32B;
6124 pcc->excp_model = POWERPC_EXCP_74xx;
6125 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6126 pcc->bfd_mach = bfd_mach_ppc_7400;
6127 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6128 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6129 POWERPC_FLAG_BUS_CLK;
6130 }
6131
6132 #if defined(TARGET_PPC64)
6133 #if defined(CONFIG_USER_ONLY)
6134 #define POWERPC970_HID5_INIT 0x00000080
6135 #else
6136 #define POWERPC970_HID5_INIT 0x00000000
6137 #endif
6138
6139 static int check_pow_970(CPUPPCState *env)
6140 {
6141 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
6142 return 1;
6143 }
6144
6145 return 0;
6146 }
6147
6148 static void register_970_hid_sprs(CPUPPCState *env)
6149 {
6150 /* Hardware implementation registers */
6151 /* XXX : not implemented */
6152 spr_register(env, SPR_HID0, "HID0",
6153 SPR_NOACCESS, SPR_NOACCESS,
6154 &spr_read_generic, &spr_write_clear,
6155 0x60000000);
6156 spr_register(env, SPR_HID1, "HID1",
6157 SPR_NOACCESS, SPR_NOACCESS,
6158 &spr_read_generic, &spr_write_generic,
6159 0x00000000);
6160 spr_register(env, SPR_970_HID5, "HID5",
6161 SPR_NOACCESS, SPR_NOACCESS,
6162 &spr_read_generic, &spr_write_generic,
6163 POWERPC970_HID5_INIT);
6164 }
6165
6166 static void register_970_hior_sprs(CPUPPCState *env)
6167 {
6168 spr_register(env, SPR_HIOR, "SPR_HIOR",
6169 SPR_NOACCESS, SPR_NOACCESS,
6170 &spr_read_hior, &spr_write_hior,
6171 0x00000000);
6172 }
6173
6174 static void register_book3s_ctrl_sprs(CPUPPCState *env)
6175 {
6176 spr_register(env, SPR_CTRL, "SPR_CTRL",
6177 SPR_NOACCESS, SPR_NOACCESS,
6178 SPR_NOACCESS, &spr_write_generic,
6179 0x00000000);
6180 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6181 &spr_read_ureg, SPR_NOACCESS,
6182 &spr_read_ureg, SPR_NOACCESS,
6183 0x00000000);
6184 }
6185
6186 static void register_book3s_altivec_sprs(CPUPPCState *env)
6187 {
6188 if (!(env->insns_flags & PPC_ALTIVEC)) {
6189 return;
6190 }
6191
6192 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
6193 &spr_read_generic, &spr_write_generic,
6194 &spr_read_generic, &spr_write_generic,
6195 KVM_REG_PPC_VRSAVE, 0x00000000);
6196
6197 }
6198
6199 static void register_book3s_dbg_sprs(CPUPPCState *env)
6200 {
6201 /*
6202 * TODO: different specs define different scopes for these,
6203 * will have to address this:
6204 * 970: super/write and super/read
6205 * powerisa 2.03..2.04: hypv/write and super/read.
6206 * powerisa 2.05 and newer: hypv/write and hypv/read.
6207 */
6208 spr_register_kvm(env, SPR_DABR, "DABR",
6209 SPR_NOACCESS, SPR_NOACCESS,
6210 &spr_read_generic, &spr_write_generic,
6211 KVM_REG_PPC_DABR, 0x00000000);
6212 spr_register_kvm(env, SPR_DABRX, "DABRX",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 KVM_REG_PPC_DABRX, 0x00000000);
6216 }
6217
6218 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
6219 {
6220 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
6221 SPR_NOACCESS, SPR_NOACCESS,
6222 SPR_NOACCESS, SPR_NOACCESS,
6223 &spr_read_generic, &spr_write_generic,
6224 KVM_REG_PPC_DAWR, 0x00000000);
6225 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
6226 SPR_NOACCESS, SPR_NOACCESS,
6227 SPR_NOACCESS, SPR_NOACCESS,
6228 &spr_read_generic, &spr_write_generic,
6229 KVM_REG_PPC_DAWRX, 0x00000000);
6230 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
6231 SPR_NOACCESS, SPR_NOACCESS,
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_generic,
6234 KVM_REG_PPC_CIABR, 0x00000000);
6235 }
6236
6237 static void register_970_dbg_sprs(CPUPPCState *env)
6238 {
6239 /* Breakpoints */
6240 spr_register(env, SPR_IABR, "IABR",
6241 SPR_NOACCESS, SPR_NOACCESS,
6242 &spr_read_generic, &spr_write_generic,
6243 0x00000000);
6244 }
6245
6246 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
6247 {
6248 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
6249 SPR_NOACCESS, SPR_NOACCESS,
6250 &spr_read_generic, &spr_write_generic,
6251 KVM_REG_PPC_MMCR0, 0x00000000);
6252 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
6253 SPR_NOACCESS, SPR_NOACCESS,
6254 &spr_read_generic, &spr_write_generic,
6255 KVM_REG_PPC_MMCR1, 0x00000000);
6256 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
6257 SPR_NOACCESS, SPR_NOACCESS,
6258 &spr_read_generic, &spr_write_generic,
6259 KVM_REG_PPC_MMCRA, 0x00000000);
6260 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
6261 SPR_NOACCESS, SPR_NOACCESS,
6262 &spr_read_generic, &spr_write_generic,
6263 KVM_REG_PPC_PMC1, 0x00000000);
6264 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 KVM_REG_PPC_PMC2, 0x00000000);
6268 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_generic, &spr_write_generic,
6271 KVM_REG_PPC_PMC3, 0x00000000);
6272 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
6273 SPR_NOACCESS, SPR_NOACCESS,
6274 &spr_read_generic, &spr_write_generic,
6275 KVM_REG_PPC_PMC4, 0x00000000);
6276 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
6277 SPR_NOACCESS, SPR_NOACCESS,
6278 &spr_read_generic, &spr_write_generic,
6279 KVM_REG_PPC_PMC5, 0x00000000);
6280 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
6281 SPR_NOACCESS, SPR_NOACCESS,
6282 &spr_read_generic, &spr_write_generic,
6283 KVM_REG_PPC_PMC6, 0x00000000);
6284 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
6285 SPR_NOACCESS, SPR_NOACCESS,
6286 &spr_read_generic, &spr_write_generic,
6287 KVM_REG_PPC_SIAR, 0x00000000);
6288 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 KVM_REG_PPC_SDAR, 0x00000000);
6292 }
6293
6294 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
6295 {
6296 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
6297 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
6298 &spr_read_ureg, &spr_write_ureg,
6299 0x00000000);
6300 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
6301 &spr_read_ureg, SPR_NOACCESS,
6302 &spr_read_ureg, &spr_write_ureg,
6303 0x00000000);
6304 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
6305 &spr_read_ureg, SPR_NOACCESS,
6306 &spr_read_ureg, &spr_write_ureg,
6307 0x00000000);
6308 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
6309 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6310 &spr_read_ureg, &spr_write_ureg,
6311 0x00000000);
6312 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
6313 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6314 &spr_read_ureg, &spr_write_ureg,
6315 0x00000000);
6316 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
6317 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6318 &spr_read_ureg, &spr_write_ureg,
6319 0x00000000);
6320 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
6321 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
6322 &spr_read_ureg, &spr_write_ureg,
6323 0x00000000);
6324 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
6325 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
6326 &spr_read_ureg, &spr_write_ureg,
6327 0x00000000);
6328 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
6329 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
6330 &spr_read_ureg, &spr_write_ureg,
6331 0x00000000);
6332 spr_register(env, SPR_POWER_USIAR, "USIAR",
6333 &spr_read_ureg, SPR_NOACCESS,
6334 &spr_read_ureg, &spr_write_ureg,
6335 0x00000000);
6336 spr_register(env, SPR_POWER_USDAR, "USDAR",
6337 &spr_read_ureg, SPR_NOACCESS,
6338 &spr_read_ureg, &spr_write_ureg,
6339 0x00000000);
6340 }
6341
6342 static void register_970_pmu_sup_sprs(CPUPPCState *env)
6343 {
6344 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
6345 SPR_NOACCESS, SPR_NOACCESS,
6346 &spr_read_generic, &spr_write_generic,
6347 KVM_REG_PPC_PMC7, 0x00000000);
6348 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
6349 SPR_NOACCESS, SPR_NOACCESS,
6350 &spr_read_generic, &spr_write_generic,
6351 KVM_REG_PPC_PMC8, 0x00000000);
6352 }
6353
6354 static void register_970_pmu_user_sprs(CPUPPCState *env)
6355 {
6356 spr_register(env, SPR_970_UPMC7, "UPMC7",
6357 &spr_read_ureg, SPR_NOACCESS,
6358 &spr_read_ureg, &spr_write_ureg,
6359 0x00000000);
6360 spr_register(env, SPR_970_UPMC8, "UPMC8",
6361 &spr_read_ureg, SPR_NOACCESS,
6362 &spr_read_ureg, &spr_write_ureg,
6363 0x00000000);
6364 }
6365
6366 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
6367 {
6368 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
6369 SPR_NOACCESS, SPR_NOACCESS,
6370 &spr_read_generic, &spr_write_generic,
6371 KVM_REG_PPC_MMCR2, 0x00000000);
6372 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
6373 SPR_NOACCESS, SPR_NOACCESS,
6374 &spr_read_generic, &spr_write_generic,
6375 KVM_REG_PPC_MMCRS, 0x00000000);
6376 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
6377 SPR_NOACCESS, SPR_NOACCESS,
6378 &spr_read_generic, &spr_write_generic,
6379 KVM_REG_PPC_SIER, 0x00000000);
6380 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
6381 SPR_NOACCESS, SPR_NOACCESS,
6382 &spr_read_generic, &spr_write_generic,
6383 KVM_REG_PPC_SPMC1, 0x00000000);
6384 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
6385 SPR_NOACCESS, SPR_NOACCESS,
6386 &spr_read_generic, &spr_write_generic,
6387 KVM_REG_PPC_SPMC2, 0x00000000);
6388 spr_register_kvm(env, SPR_TACR, "TACR",
6389 SPR_NOACCESS, SPR_NOACCESS,
6390 &spr_read_generic, &spr_write_generic,
6391 KVM_REG_PPC_TACR, 0x00000000);
6392 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
6393 SPR_NOACCESS, SPR_NOACCESS,
6394 &spr_read_generic, &spr_write_generic,
6395 KVM_REG_PPC_TCSCR, 0x00000000);
6396 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
6397 SPR_NOACCESS, SPR_NOACCESS,
6398 &spr_read_generic, &spr_write_generic,
6399 KVM_REG_PPC_CSIGR, 0x00000000);
6400 }
6401
6402 static void register_power8_pmu_user_sprs(CPUPPCState *env)
6403 {
6404 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
6405 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
6406 &spr_read_ureg, &spr_write_ureg,
6407 0x00000000);
6408 spr_register(env, SPR_POWER_USIER, "USIER",
6409 &spr_read_generic, SPR_NOACCESS,
6410 &spr_read_generic, &spr_write_generic,
6411 0x00000000);
6412 }
6413
6414 static void register_power5p_ear_sprs(CPUPPCState *env)
6415 {
6416 /* External access control */
6417 spr_register(env, SPR_EAR, "EAR",
6418 SPR_NOACCESS, SPR_NOACCESS,
6419 &spr_read_generic, &spr_write_generic,
6420 0x00000000);
6421 }
6422
6423 static void register_power5p_tb_sprs(CPUPPCState *env)
6424 {
6425 /* TBU40 (High 40 bits of the Timebase register */
6426 spr_register_hv(env, SPR_TBU40, "TBU40",
6427 SPR_NOACCESS, SPR_NOACCESS,
6428 SPR_NOACCESS, SPR_NOACCESS,
6429 SPR_NOACCESS, &spr_write_tbu40,
6430 0x00000000);
6431 }
6432
6433 static void register_970_lpar_sprs(CPUPPCState *env)
6434 {
6435 #if !defined(CONFIG_USER_ONLY)
6436 /*
6437 * PPC970: HID4 covers things later controlled by the LPCR and
6438 * RMOR in later CPUs, but with a different encoding. We only
6439 * support the 970 in "Apple mode" which has all hypervisor
6440 * facilities disabled by strapping, so we can basically just
6441 * ignore it
6442 */
6443 spr_register(env, SPR_970_HID4, "HID4",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 0x00000000);
6447 #endif
6448 }
6449
6450 static void register_power5p_lpar_sprs(CPUPPCState *env)
6451 {
6452 #if !defined(CONFIG_USER_ONLY)
6453 /* Logical partitionning */
6454 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
6455 SPR_NOACCESS, SPR_NOACCESS,
6456 SPR_NOACCESS, SPR_NOACCESS,
6457 &spr_read_generic, &spr_write_lpcr,
6458 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
6459 spr_register_hv(env, SPR_HDEC, "HDEC",
6460 SPR_NOACCESS, SPR_NOACCESS,
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_hdecr, &spr_write_hdecr, 0);
6463 #endif
6464 }
6465
6466 static void register_book3s_ids_sprs(CPUPPCState *env)
6467 {
6468 /* FIXME: Will need to deal with thread vs core only SPRs */
6469
6470 /* Processor identification */
6471 spr_register_hv(env, SPR_PIR, "PIR",
6472 SPR_NOACCESS, SPR_NOACCESS,
6473 &spr_read_generic, SPR_NOACCESS,
6474 &spr_read_generic, NULL,
6475 0x00000000);
6476 spr_register_hv(env, SPR_HID0, "HID0",
6477 SPR_NOACCESS, SPR_NOACCESS,
6478 SPR_NOACCESS, SPR_NOACCESS,
6479 &spr_read_generic, &spr_write_generic,
6480 0x00000000);
6481 spr_register_hv(env, SPR_TSCR, "TSCR",
6482 SPR_NOACCESS, SPR_NOACCESS,
6483 SPR_NOACCESS, SPR_NOACCESS,
6484 &spr_read_generic, &spr_write_generic,
6485 0x00000000);
6486 spr_register_hv(env, SPR_HMER, "HMER",
6487 SPR_NOACCESS, SPR_NOACCESS,
6488 SPR_NOACCESS, SPR_NOACCESS,
6489 &spr_read_generic, &spr_write_hmer,
6490 0x00000000);
6491 spr_register_hv(env, SPR_HMEER, "HMEER",
6492 SPR_NOACCESS, SPR_NOACCESS,
6493 SPR_NOACCESS, SPR_NOACCESS,
6494 &spr_read_generic, &spr_write_generic,
6495 0x00000000);
6496 spr_register_hv(env, SPR_TFMR, "TFMR",
6497 SPR_NOACCESS, SPR_NOACCESS,
6498 SPR_NOACCESS, SPR_NOACCESS,
6499 &spr_read_generic, &spr_write_generic,
6500 0x00000000);
6501 spr_register_hv(env, SPR_LPIDR, "LPIDR",
6502 SPR_NOACCESS, SPR_NOACCESS,
6503 SPR_NOACCESS, SPR_NOACCESS,
6504 &spr_read_generic, &spr_write_lpidr,
6505 0x00000000);
6506 spr_register_hv(env, SPR_HFSCR, "HFSCR",
6507 SPR_NOACCESS, SPR_NOACCESS,
6508 SPR_NOACCESS, SPR_NOACCESS,
6509 &spr_read_generic, &spr_write_generic,
6510 0x00000000);
6511 spr_register_hv(env, SPR_MMCRC, "MMCRC",
6512 SPR_NOACCESS, SPR_NOACCESS,
6513 SPR_NOACCESS, SPR_NOACCESS,
6514 &spr_read_generic, &spr_write_generic,
6515 0x00000000);
6516 spr_register_hv(env, SPR_MMCRH, "MMCRH",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 SPR_NOACCESS, SPR_NOACCESS,
6519 &spr_read_generic, &spr_write_generic,
6520 0x00000000);
6521 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
6522 SPR_NOACCESS, SPR_NOACCESS,
6523 SPR_NOACCESS, SPR_NOACCESS,
6524 &spr_read_generic, &spr_write_generic,
6525 0x00000000);
6526 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
6527 SPR_NOACCESS, SPR_NOACCESS,
6528 SPR_NOACCESS, SPR_NOACCESS,
6529 &spr_read_generic, &spr_write_generic,
6530 0x00000000);
6531 spr_register_hv(env, SPR_HSRR0, "HSRR0",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 SPR_NOACCESS, SPR_NOACCESS,
6534 &spr_read_generic, &spr_write_generic,
6535 0x00000000);
6536 spr_register_hv(env, SPR_HSRR1, "HSRR1",
6537 SPR_NOACCESS, SPR_NOACCESS,
6538 SPR_NOACCESS, SPR_NOACCESS,
6539 &spr_read_generic, &spr_write_generic,
6540 0x00000000);
6541 spr_register_hv(env, SPR_HDAR, "HDAR",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 SPR_NOACCESS, SPR_NOACCESS,
6544 &spr_read_generic, &spr_write_generic,
6545 0x00000000);
6546 spr_register_hv(env, SPR_HDSISR, "HDSISR",
6547 SPR_NOACCESS, SPR_NOACCESS,
6548 SPR_NOACCESS, SPR_NOACCESS,
6549 &spr_read_generic, &spr_write_generic,
6550 0x00000000);
6551 spr_register_hv(env, SPR_HRMOR, "HRMOR",
6552 SPR_NOACCESS, SPR_NOACCESS,
6553 SPR_NOACCESS, SPR_NOACCESS,
6554 &spr_read_generic, &spr_write_generic,
6555 0x00000000);
6556 }
6557
6558 static void register_rmor_sprs(CPUPPCState *env)
6559 {
6560 spr_register_hv(env, SPR_RMOR, "RMOR",
6561 SPR_NOACCESS, SPR_NOACCESS,
6562 SPR_NOACCESS, SPR_NOACCESS,
6563 &spr_read_generic, &spr_write_generic,
6564 0x00000000);
6565 }
6566
6567 static void register_power8_ids_sprs(CPUPPCState *env)
6568 {
6569 /* Thread identification */
6570 spr_register(env, SPR_TIR, "TIR",
6571 SPR_NOACCESS, SPR_NOACCESS,
6572 &spr_read_generic, SPR_NOACCESS,
6573 0x00000000);
6574 }
6575
6576 static void register_book3s_purr_sprs(CPUPPCState *env)
6577 {
6578 #if !defined(CONFIG_USER_ONLY)
6579 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6580 spr_register_kvm_hv(env, SPR_PURR, "PURR",
6581 &spr_read_purr, SPR_NOACCESS,
6582 &spr_read_purr, SPR_NOACCESS,
6583 &spr_read_purr, &spr_write_purr,
6584 KVM_REG_PPC_PURR, 0x00000000);
6585 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
6586 &spr_read_purr, SPR_NOACCESS,
6587 &spr_read_purr, SPR_NOACCESS,
6588 &spr_read_purr, &spr_write_purr,
6589 KVM_REG_PPC_SPURR, 0x00000000);
6590 #endif
6591 }
6592
6593 static void register_power6_dbg_sprs(CPUPPCState *env)
6594 {
6595 #if !defined(CONFIG_USER_ONLY)
6596 spr_register(env, SPR_CFAR, "SPR_CFAR",
6597 SPR_NOACCESS, SPR_NOACCESS,
6598 &spr_read_cfar, &spr_write_cfar,
6599 0x00000000);
6600 #endif
6601 }
6602
6603 static void register_power5p_common_sprs(CPUPPCState *env)
6604 {
6605 spr_register_kvm(env, SPR_PPR, "PPR",
6606 &spr_read_generic, &spr_write_generic,
6607 &spr_read_generic, &spr_write_generic,
6608 KVM_REG_PPC_PPR, 0x00000000);
6609 }
6610
6611 static void register_power6_common_sprs(CPUPPCState *env)
6612 {
6613 #if !defined(CONFIG_USER_ONLY)
6614 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6615 SPR_NOACCESS, SPR_NOACCESS,
6616 &spr_read_generic, &spr_write_generic,
6617 KVM_REG_PPC_DSCR, 0x00000000);
6618 #endif
6619 /*
6620 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6621 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
6622 */
6623 spr_register_hv(env, SPR_PCR, "PCR",
6624 SPR_NOACCESS, SPR_NOACCESS,
6625 SPR_NOACCESS, SPR_NOACCESS,
6626 &spr_read_generic, &spr_write_pcr,
6627 0x00000000);
6628 }
6629
6630 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
6631 {
6632 spr_register_kvm(env, SPR_TAR, "TAR",
6633 &spr_read_tar, &spr_write_tar,
6634 &spr_read_generic, &spr_write_generic,
6635 KVM_REG_PPC_TAR, 0x00000000);
6636 }
6637
6638 static void register_power8_tm_sprs(CPUPPCState *env)
6639 {
6640 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
6641 &spr_read_tm, &spr_write_tm,
6642 &spr_read_tm, &spr_write_tm,
6643 KVM_REG_PPC_TFHAR, 0x00000000);
6644 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
6645 &spr_read_tm, &spr_write_tm,
6646 &spr_read_tm, &spr_write_tm,
6647 KVM_REG_PPC_TFIAR, 0x00000000);
6648 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
6649 &spr_read_tm, &spr_write_tm,
6650 &spr_read_tm, &spr_write_tm,
6651 KVM_REG_PPC_TEXASR, 0x00000000);
6652 spr_register(env, SPR_TEXASRU, "TEXASRU",
6653 &spr_read_tm_upper32, &spr_write_tm_upper32,
6654 &spr_read_tm_upper32, &spr_write_tm_upper32,
6655 0x00000000);
6656 }
6657
6658 static void register_power8_ebb_sprs(CPUPPCState *env)
6659 {
6660 spr_register(env, SPR_BESCRS, "BESCRS",
6661 &spr_read_ebb, &spr_write_ebb,
6662 &spr_read_generic, &spr_write_generic,
6663 0x00000000);
6664 spr_register(env, SPR_BESCRSU, "BESCRSU",
6665 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6666 &spr_read_prev_upper32, &spr_write_prev_upper32,
6667 0x00000000);
6668 spr_register(env, SPR_BESCRR, "BESCRR",
6669 &spr_read_ebb, &spr_write_ebb,
6670 &spr_read_generic, &spr_write_generic,
6671 0x00000000);
6672 spr_register(env, SPR_BESCRRU, "BESCRRU",
6673 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
6674 &spr_read_prev_upper32, &spr_write_prev_upper32,
6675 0x00000000);
6676 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
6677 &spr_read_ebb, &spr_write_ebb,
6678 &spr_read_generic, &spr_write_generic,
6679 KVM_REG_PPC_EBBHR, 0x00000000);
6680 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
6681 &spr_read_ebb, &spr_write_ebb,
6682 &spr_read_generic, &spr_write_generic,
6683 KVM_REG_PPC_EBBRR, 0x00000000);
6684 spr_register_kvm(env, SPR_BESCR, "BESCR",
6685 &spr_read_ebb, &spr_write_ebb,
6686 &spr_read_generic, &spr_write_generic,
6687 KVM_REG_PPC_BESCR, 0x00000000);
6688 }
6689
6690 /* Virtual Time Base */
6691 static void register_vtb_sprs(CPUPPCState *env)
6692 {
6693 spr_register_kvm_hv(env, SPR_VTB, "VTB",
6694 SPR_NOACCESS, SPR_NOACCESS,
6695 &spr_read_vtb, SPR_NOACCESS,
6696 &spr_read_vtb, &spr_write_vtb,
6697 KVM_REG_PPC_VTB, 0x00000000);
6698 }
6699
6700 static void register_power8_fscr_sprs(CPUPPCState *env)
6701 {
6702 #if defined(CONFIG_USER_ONLY)
6703 target_ulong initval = 1ULL << FSCR_TAR;
6704 #else
6705 target_ulong initval = 0;
6706 #endif
6707 spr_register_kvm(env, SPR_FSCR, "FSCR",
6708 SPR_NOACCESS, SPR_NOACCESS,
6709 &spr_read_generic, &spr_write_generic,
6710 KVM_REG_PPC_FSCR, initval);
6711 }
6712
6713 static void register_power8_pspb_sprs(CPUPPCState *env)
6714 {
6715 spr_register_kvm(env, SPR_PSPB, "PSPB",
6716 SPR_NOACCESS, SPR_NOACCESS,
6717 &spr_read_generic, &spr_write_generic32,
6718 KVM_REG_PPC_PSPB, 0);
6719 }
6720
6721 static void register_power8_dpdes_sprs(CPUPPCState *env)
6722 {
6723 #if !defined(CONFIG_USER_ONLY)
6724 /* Directed Privileged Door-bell Exception State, used for IPI */
6725 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
6726 SPR_NOACCESS, SPR_NOACCESS,
6727 &spr_read_dpdes, SPR_NOACCESS,
6728 &spr_read_dpdes, &spr_write_dpdes,
6729 KVM_REG_PPC_DPDES, 0x00000000);
6730 #endif
6731 }
6732
6733 static void register_power8_ic_sprs(CPUPPCState *env)
6734 {
6735 #if !defined(CONFIG_USER_ONLY)
6736 spr_register_hv(env, SPR_IC, "IC",
6737 SPR_NOACCESS, SPR_NOACCESS,
6738 &spr_read_generic, SPR_NOACCESS,
6739 &spr_read_generic, &spr_write_generic,
6740 0);
6741 #endif
6742 }
6743
6744 static void register_power8_book4_sprs(CPUPPCState *env)
6745 {
6746 /* Add a number of P8 book4 registers */
6747 #if !defined(CONFIG_USER_ONLY)
6748 spr_register_kvm(env, SPR_ACOP, "ACOP",
6749 SPR_NOACCESS, SPR_NOACCESS,
6750 &spr_read_generic, &spr_write_generic,
6751 KVM_REG_PPC_ACOP, 0);
6752 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6753 SPR_NOACCESS, SPR_NOACCESS,
6754 &spr_read_generic, &spr_write_pidr,
6755 KVM_REG_PPC_PID, 0);
6756 spr_register_kvm(env, SPR_WORT, "WORT",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 KVM_REG_PPC_WORT, 0);
6760 #endif
6761 }
6762
6763 static void register_power7_book4_sprs(CPUPPCState *env)
6764 {
6765 /* Add a number of P7 book4 registers */
6766 #if !defined(CONFIG_USER_ONLY)
6767 spr_register_kvm(env, SPR_ACOP, "ACOP",
6768 SPR_NOACCESS, SPR_NOACCESS,
6769 &spr_read_generic, &spr_write_generic,
6770 KVM_REG_PPC_ACOP, 0);
6771 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
6772 SPR_NOACCESS, SPR_NOACCESS,
6773 &spr_read_generic, &spr_write_generic,
6774 KVM_REG_PPC_PID, 0);
6775 #endif
6776 }
6777
6778 static void register_power8_rpr_sprs(CPUPPCState *env)
6779 {
6780 #if !defined(CONFIG_USER_ONLY)
6781 spr_register_hv(env, SPR_RPR, "RPR",
6782 SPR_NOACCESS, SPR_NOACCESS,
6783 SPR_NOACCESS, SPR_NOACCESS,
6784 &spr_read_generic, &spr_write_generic,
6785 0x00000103070F1F3F);
6786 #endif
6787 }
6788
6789 static void register_power9_mmu_sprs(CPUPPCState *env)
6790 {
6791 #if !defined(CONFIG_USER_ONLY)
6792 /* Partition Table Control */
6793 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
6794 SPR_NOACCESS, SPR_NOACCESS,
6795 SPR_NOACCESS, SPR_NOACCESS,
6796 &spr_read_generic, &spr_write_ptcr,
6797 KVM_REG_PPC_PTCR, 0x00000000);
6798 /* Address Segment Descriptor Register */
6799 spr_register_hv(env, SPR_ASDR, "ASDR",
6800 SPR_NOACCESS, SPR_NOACCESS,
6801 SPR_NOACCESS, SPR_NOACCESS,
6802 &spr_read_generic, &spr_write_generic,
6803 0x0000000000000000);
6804 #endif
6805 }
6806
6807 static void init_proc_book3s_common(CPUPPCState *env)
6808 {
6809 register_ne_601_sprs(env);
6810 register_tbl(env);
6811 register_usprg3_sprs(env);
6812 register_book3s_altivec_sprs(env);
6813 register_book3s_pmu_sup_sprs(env);
6814 register_book3s_pmu_user_sprs(env);
6815 register_book3s_ctrl_sprs(env);
6816 /*
6817 * Can't find information on what this should be on reset. This
6818 * value is the one used by 74xx processors.
6819 */
6820 vscr_init(env, 0x00010000);
6821 }
6822
6823 static void init_proc_970(CPUPPCState *env)
6824 {
6825 /* Common Registers */
6826 init_proc_book3s_common(env);
6827 register_sdr1_sprs(env);
6828 register_book3s_dbg_sprs(env);
6829
6830 /* 970 Specific Registers */
6831 register_970_hid_sprs(env);
6832 register_970_hior_sprs(env);
6833 register_low_BATs(env);
6834 register_970_pmu_sup_sprs(env);
6835 register_970_pmu_user_sprs(env);
6836 register_970_lpar_sprs(env);
6837 register_970_dbg_sprs(env);
6838
6839 /* env variables */
6840 env->dcache_line_size = 128;
6841 env->icache_line_size = 128;
6842
6843 /* Allocate hardware IRQ controller */
6844 init_excp_970(env);
6845 ppc970_irq_init(env_archcpu(env));
6846 }
6847
6848 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6849 {
6850 DeviceClass *dc = DEVICE_CLASS(oc);
6851 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6852
6853 dc->desc = "PowerPC 970";
6854 pcc->init_proc = init_proc_970;
6855 pcc->check_pow = check_pow_970;
6856 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6857 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6858 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6859 PPC_FLOAT_STFIWX |
6860 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6861 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6862 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6863 PPC_64B | PPC_ALTIVEC |
6864 PPC_SEGMENT_64B | PPC_SLBI;
6865 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6866 pcc->msr_mask = (1ull << MSR_SF) |
6867 (1ull << MSR_VR) |
6868 (1ull << MSR_POW) |
6869 (1ull << MSR_EE) |
6870 (1ull << MSR_PR) |
6871 (1ull << MSR_FP) |
6872 (1ull << MSR_ME) |
6873 (1ull << MSR_FE0) |
6874 (1ull << MSR_SE) |
6875 (1ull << MSR_DE) |
6876 (1ull << MSR_FE1) |
6877 (1ull << MSR_IR) |
6878 (1ull << MSR_DR) |
6879 (1ull << MSR_PMM) |
6880 (1ull << MSR_RI);
6881 pcc->mmu_model = POWERPC_MMU_64B;
6882 #if defined(CONFIG_SOFTMMU)
6883 pcc->hash64_opts = &ppc_hash64_opts_basic;
6884 #endif
6885 pcc->excp_model = POWERPC_EXCP_970;
6886 pcc->bus_model = PPC_FLAGS_INPUT_970;
6887 pcc->bfd_mach = bfd_mach_ppc64;
6888 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6889 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6890 POWERPC_FLAG_BUS_CLK;
6891 pcc->l1_dcache_size = 0x8000;
6892 pcc->l1_icache_size = 0x10000;
6893 }
6894
6895 static void init_proc_power5plus(CPUPPCState *env)
6896 {
6897 /* Common Registers */
6898 init_proc_book3s_common(env);
6899 register_sdr1_sprs(env);
6900 register_book3s_dbg_sprs(env);
6901
6902 /* POWER5+ Specific Registers */
6903 register_970_hid_sprs(env);
6904 register_970_hior_sprs(env);
6905 register_low_BATs(env);
6906 register_970_pmu_sup_sprs(env);
6907 register_970_pmu_user_sprs(env);
6908 register_power5p_common_sprs(env);
6909 register_power5p_lpar_sprs(env);
6910 register_power5p_ear_sprs(env);
6911 register_power5p_tb_sprs(env);
6912
6913 /* env variables */
6914 env->dcache_line_size = 128;
6915 env->icache_line_size = 128;
6916
6917 /* Allocate hardware IRQ controller */
6918 init_excp_970(env);
6919 ppc970_irq_init(env_archcpu(env));
6920 }
6921
6922 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6923 {
6924 DeviceClass *dc = DEVICE_CLASS(oc);
6925 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6926
6927 dc->fw_name = "PowerPC,POWER5";
6928 dc->desc = "POWER5+";
6929 pcc->init_proc = init_proc_power5plus;
6930 pcc->check_pow = check_pow_970;
6931 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6932 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6933 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6934 PPC_FLOAT_STFIWX |
6935 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6936 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6937 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6938 PPC_64B |
6939 PPC_SEGMENT_64B | PPC_SLBI;
6940 pcc->insns_flags2 = PPC2_FP_CVT_S64;
6941 pcc->msr_mask = (1ull << MSR_SF) |
6942 (1ull << MSR_VR) |
6943 (1ull << MSR_POW) |
6944 (1ull << MSR_EE) |
6945 (1ull << MSR_PR) |
6946 (1ull << MSR_FP) |
6947 (1ull << MSR_ME) |
6948 (1ull << MSR_FE0) |
6949 (1ull << MSR_SE) |
6950 (1ull << MSR_DE) |
6951 (1ull << MSR_FE1) |
6952 (1ull << MSR_IR) |
6953 (1ull << MSR_DR) |
6954 (1ull << MSR_PMM) |
6955 (1ull << MSR_RI);
6956 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6957 LPCR_RMI | LPCR_HDICE;
6958 pcc->mmu_model = POWERPC_MMU_2_03;
6959 #if defined(CONFIG_SOFTMMU)
6960 pcc->hash64_opts = &ppc_hash64_opts_basic;
6961 pcc->lrg_decr_bits = 32;
6962 #endif
6963 pcc->excp_model = POWERPC_EXCP_970;
6964 pcc->bus_model = PPC_FLAGS_INPUT_970;
6965 pcc->bfd_mach = bfd_mach_ppc64;
6966 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6967 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6968 POWERPC_FLAG_BUS_CLK;
6969 pcc->l1_dcache_size = 0x8000;
6970 pcc->l1_icache_size = 0x10000;
6971 }
6972
6973 static void init_proc_POWER7(CPUPPCState *env)
6974 {
6975 /* Common Registers */
6976 init_proc_book3s_common(env);
6977 register_sdr1_sprs(env);
6978 register_book3s_dbg_sprs(env);
6979
6980 /* POWER7 Specific Registers */
6981 register_book3s_ids_sprs(env);
6982 register_rmor_sprs(env);
6983 register_amr_sprs(env);
6984 register_book3s_purr_sprs(env);
6985 register_power5p_common_sprs(env);
6986 register_power5p_lpar_sprs(env);
6987 register_power5p_ear_sprs(env);
6988 register_power5p_tb_sprs(env);
6989 register_power6_common_sprs(env);
6990 register_power6_dbg_sprs(env);
6991 register_power7_book4_sprs(env);
6992
6993 /* env variables */
6994 env->dcache_line_size = 128;
6995 env->icache_line_size = 128;
6996
6997 /* Allocate hardware IRQ controller */
6998 init_excp_POWER7(env);
6999 ppcPOWER7_irq_init(env_archcpu(env));
7000 }
7001
7002 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
7003 {
7004 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
7005 return true;
7006 }
7007 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
7008 return true;
7009 }
7010 return false;
7011 }
7012
7013 static bool cpu_has_work_POWER7(CPUState *cs)
7014 {
7015 PowerPCCPU *cpu = POWERPC_CPU(cs);
7016 CPUPPCState *env = &cpu->env;
7017
7018 if (cs->halted) {
7019 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7020 return false;
7021 }
7022 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7023 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
7024 return true;
7025 }
7026 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7027 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
7028 return true;
7029 }
7030 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7031 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7032 return true;
7033 }
7034 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7035 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
7036 return true;
7037 }
7038 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7039 return true;
7040 }
7041 return false;
7042 } else {
7043 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7044 }
7045 }
7046
7047 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7048 {
7049 DeviceClass *dc = DEVICE_CLASS(oc);
7050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7051 CPUClass *cc = CPU_CLASS(oc);
7052
7053 dc->fw_name = "PowerPC,POWER7";
7054 dc->desc = "POWER7";
7055 pcc->pvr_match = ppc_pvr_match_power7;
7056 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
7057 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7058 pcc->init_proc = init_proc_POWER7;
7059 pcc->check_pow = check_pow_nocheck;
7060 cc->has_work = cpu_has_work_POWER7;
7061 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7062 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7063 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7064 PPC_FLOAT_FRSQRTES |
7065 PPC_FLOAT_STFIWX |
7066 PPC_FLOAT_EXT |
7067 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7068 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7069 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7070 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7071 PPC_SEGMENT_64B | PPC_SLBI |
7072 PPC_POPCNTB | PPC_POPCNTWD |
7073 PPC_CILDST;
7074 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7075 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7076 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7077 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
7078 PPC2_PM_ISA206;
7079 pcc->msr_mask = (1ull << MSR_SF) |
7080 (1ull << MSR_VR) |
7081 (1ull << MSR_VSX) |
7082 (1ull << MSR_EE) |
7083 (1ull << MSR_PR) |
7084 (1ull << MSR_FP) |
7085 (1ull << MSR_ME) |
7086 (1ull << MSR_FE0) |
7087 (1ull << MSR_SE) |
7088 (1ull << MSR_DE) |
7089 (1ull << MSR_FE1) |
7090 (1ull << MSR_IR) |
7091 (1ull << MSR_DR) |
7092 (1ull << MSR_PMM) |
7093 (1ull << MSR_RI) |
7094 (1ull << MSR_LE);
7095 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
7096 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7097 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
7098 LPCR_MER | LPCR_TC |
7099 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
7100 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
7101 pcc->mmu_model = POWERPC_MMU_2_06;
7102 #if defined(CONFIG_SOFTMMU)
7103 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7104 pcc->lrg_decr_bits = 32;
7105 #endif
7106 pcc->excp_model = POWERPC_EXCP_POWER7;
7107 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7108 pcc->bfd_mach = bfd_mach_ppc64;
7109 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7110 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7111 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7112 POWERPC_FLAG_VSX;
7113 pcc->l1_dcache_size = 0x8000;
7114 pcc->l1_icache_size = 0x8000;
7115 }
7116
7117 static void init_proc_POWER8(CPUPPCState *env)
7118 {
7119 /* Common Registers */
7120 init_proc_book3s_common(env);
7121 register_sdr1_sprs(env);
7122 register_book3s_207_dbg_sprs(env);
7123
7124 /* POWER8 Specific Registers */
7125 register_book3s_ids_sprs(env);
7126 register_rmor_sprs(env);
7127 register_amr_sprs(env);
7128 register_iamr_sprs(env);
7129 register_book3s_purr_sprs(env);
7130 register_power5p_common_sprs(env);
7131 register_power5p_lpar_sprs(env);
7132 register_power5p_ear_sprs(env);
7133 register_power5p_tb_sprs(env);
7134 register_power6_common_sprs(env);
7135 register_power6_dbg_sprs(env);
7136 register_power8_tce_address_control_sprs(env);
7137 register_power8_ids_sprs(env);
7138 register_power8_ebb_sprs(env);
7139 register_power8_fscr_sprs(env);
7140 register_power8_pmu_sup_sprs(env);
7141 register_power8_pmu_user_sprs(env);
7142 register_power8_tm_sprs(env);
7143 register_power8_pspb_sprs(env);
7144 register_power8_dpdes_sprs(env);
7145 register_vtb_sprs(env);
7146 register_power8_ic_sprs(env);
7147 register_power8_book4_sprs(env);
7148 register_power8_rpr_sprs(env);
7149
7150 /* env variables */
7151 env->dcache_line_size = 128;
7152 env->icache_line_size = 128;
7153
7154 /* Allocate hardware IRQ controller */
7155 init_excp_POWER8(env);
7156 ppcPOWER7_irq_init(env_archcpu(env));
7157 }
7158
7159 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
7160 {
7161 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
7162 return true;
7163 }
7164 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
7165 return true;
7166 }
7167 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
7168 return true;
7169 }
7170 return false;
7171 }
7172
7173 static bool cpu_has_work_POWER8(CPUState *cs)
7174 {
7175 PowerPCCPU *cpu = POWERPC_CPU(cs);
7176 CPUPPCState *env = &cpu->env;
7177
7178 if (cs->halted) {
7179 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7180 return false;
7181 }
7182 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7183 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
7184 return true;
7185 }
7186 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7187 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
7188 return true;
7189 }
7190 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
7191 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7192 return true;
7193 }
7194 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
7195 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
7196 return true;
7197 }
7198 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7199 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
7200 return true;
7201 }
7202 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7203 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
7204 return true;
7205 }
7206 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7207 return true;
7208 }
7209 return false;
7210 } else {
7211 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7212 }
7213 }
7214
7215 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7216 {
7217 DeviceClass *dc = DEVICE_CLASS(oc);
7218 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7219 CPUClass *cc = CPU_CLASS(oc);
7220
7221 dc->fw_name = "PowerPC,POWER8";
7222 dc->desc = "POWER8";
7223 pcc->pvr_match = ppc_pvr_match_power8;
7224 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7225 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7226 pcc->init_proc = init_proc_POWER8;
7227 pcc->check_pow = check_pow_nocheck;
7228 cc->has_work = cpu_has_work_POWER8;
7229 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7231 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7232 PPC_FLOAT_FRSQRTES |
7233 PPC_FLOAT_STFIWX |
7234 PPC_FLOAT_EXT |
7235 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7236 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7237 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7238 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7239 PPC_SEGMENT_64B | PPC_SLBI |
7240 PPC_POPCNTB | PPC_POPCNTWD |
7241 PPC_CILDST;
7242 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7243 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7244 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7245 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7246 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7247 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7248 PPC2_TM | PPC2_PM_ISA206;
7249 pcc->msr_mask = (1ull << MSR_SF) |
7250 (1ull << MSR_HV) |
7251 (1ull << MSR_TM) |
7252 (1ull << MSR_VR) |
7253 (1ull << MSR_VSX) |
7254 (1ull << MSR_EE) |
7255 (1ull << MSR_PR) |
7256 (1ull << MSR_FP) |
7257 (1ull << MSR_ME) |
7258 (1ull << MSR_FE0) |
7259 (1ull << MSR_SE) |
7260 (1ull << MSR_DE) |
7261 (1ull << MSR_FE1) |
7262 (1ull << MSR_IR) |
7263 (1ull << MSR_DR) |
7264 (1ull << MSR_PMM) |
7265 (1ull << MSR_RI) |
7266 (1ull << MSR_TS0) |
7267 (1ull << MSR_TS1) |
7268 (1ull << MSR_LE);
7269 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
7270 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
7271 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
7272 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
7273 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
7274 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
7275 LPCR_P8_PECE3 | LPCR_P8_PECE4;
7276 pcc->mmu_model = POWERPC_MMU_2_07;
7277 #if defined(CONFIG_SOFTMMU)
7278 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7279 pcc->lrg_decr_bits = 32;
7280 pcc->n_host_threads = 8;
7281 #endif
7282 pcc->excp_model = POWERPC_EXCP_POWER8;
7283 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7284 pcc->bfd_mach = bfd_mach_ppc64;
7285 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7286 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7287 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7288 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
7289 pcc->l1_dcache_size = 0x8000;
7290 pcc->l1_icache_size = 0x8000;
7291 }
7292
7293 #ifdef CONFIG_SOFTMMU
7294 /*
7295 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7296 * Encoded as array of int_32s in the form:
7297 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7298 * x -> AP encoding
7299 * y -> radix mode supported page size (encoded as a shift)
7300 */
7301 static struct ppc_radix_page_info POWER9_radix_page_info = {
7302 .count = 4,
7303 .entries = {
7304 0x0000000c, /* 4K - enc: 0x0 */
7305 0xa0000010, /* 64K - enc: 0x5 */
7306 0x20000015, /* 2M - enc: 0x1 */
7307 0x4000001e /* 1G - enc: 0x2 */
7308 }
7309 };
7310 #endif /* CONFIG_SOFTMMU */
7311
7312 static void init_proc_POWER9(CPUPPCState *env)
7313 {
7314 /* Common Registers */
7315 init_proc_book3s_common(env);
7316 register_book3s_207_dbg_sprs(env);
7317
7318 /* POWER8 Specific Registers */
7319 register_book3s_ids_sprs(env);
7320 register_amr_sprs(env);
7321 register_iamr_sprs(env);
7322 register_book3s_purr_sprs(env);
7323 register_power5p_common_sprs(env);
7324 register_power5p_lpar_sprs(env);
7325 register_power5p_ear_sprs(env);
7326 register_power5p_tb_sprs(env);
7327 register_power6_common_sprs(env);
7328 register_power6_dbg_sprs(env);
7329 register_power8_tce_address_control_sprs(env);
7330 register_power8_ids_sprs(env);
7331 register_power8_ebb_sprs(env);
7332 register_power8_fscr_sprs(env);
7333 register_power8_pmu_sup_sprs(env);
7334 register_power8_pmu_user_sprs(env);
7335 register_power8_tm_sprs(env);
7336 register_power8_pspb_sprs(env);
7337 register_power8_dpdes_sprs(env);
7338 register_vtb_sprs(env);
7339 register_power8_ic_sprs(env);
7340 register_power8_book4_sprs(env);
7341 register_power8_rpr_sprs(env);
7342 register_power9_mmu_sprs(env);
7343
7344 /* POWER9 Specific registers */
7345 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
7346 spr_read_generic, spr_write_generic,
7347 KVM_REG_PPC_TIDR, 0);
7348
7349 /* FIXME: Filter fields properly based on privilege level */
7350 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7351 spr_read_generic, spr_write_generic,
7352 KVM_REG_PPC_PSSCR, 0);
7353
7354 /* env variables */
7355 env->dcache_line_size = 128;
7356 env->icache_line_size = 128;
7357
7358 /* Allocate hardware IRQ controller */
7359 init_excp_POWER9(env);
7360 ppcPOWER9_irq_init(env_archcpu(env));
7361 }
7362
7363 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
7364 {
7365 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) {
7366 return true;
7367 }
7368 return false;
7369 }
7370
7371 static bool cpu_has_work_POWER9(CPUState *cs)
7372 {
7373 PowerPCCPU *cpu = POWERPC_CPU(cs);
7374 CPUPPCState *env = &cpu->env;
7375
7376 if (cs->halted) {
7377 uint64_t psscr = env->spr[SPR_PSSCR];
7378
7379 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7380 return false;
7381 }
7382
7383 /* If EC is clear, just return true on any pending interrupt */
7384 if (!(psscr & PSSCR_EC)) {
7385 return true;
7386 }
7387 /* External Exception */
7388 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7389 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7390 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7391 if (heic == 0 || !msr_hv || msr_pr) {
7392 return true;
7393 }
7394 }
7395 /* Decrementer Exception */
7396 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7397 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7398 return true;
7399 }
7400 /* Machine Check or Hypervisor Maintenance Exception */
7401 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7402 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7403 return true;
7404 }
7405 /* Privileged Doorbell Exception */
7406 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7407 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7408 return true;
7409 }
7410 /* Hypervisor Doorbell Exception */
7411 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7412 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7413 return true;
7414 }
7415 /* Hypervisor virtualization exception */
7416 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7417 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7418 return true;
7419 }
7420 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7421 return true;
7422 }
7423 return false;
7424 } else {
7425 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7426 }
7427 }
7428
7429 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
7430 {
7431 DeviceClass *dc = DEVICE_CLASS(oc);
7432 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7433 CPUClass *cc = CPU_CLASS(oc);
7434
7435 dc->fw_name = "PowerPC,POWER9";
7436 dc->desc = "POWER9";
7437 pcc->pvr_match = ppc_pvr_match_power9;
7438 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
7439 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
7440 PCR_COMPAT_2_05;
7441 pcc->init_proc = init_proc_POWER9;
7442 pcc->check_pow = check_pow_nocheck;
7443 cc->has_work = cpu_has_work_POWER9;
7444 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7445 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7446 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7447 PPC_FLOAT_FRSQRTES |
7448 PPC_FLOAT_STFIWX |
7449 PPC_FLOAT_EXT |
7450 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7451 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7452 PPC_MEM_TLBSYNC |
7453 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7454 PPC_SEGMENT_64B | PPC_SLBI |
7455 PPC_POPCNTB | PPC_POPCNTWD |
7456 PPC_CILDST;
7457 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7458 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7459 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7460 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7461 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7462 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7463 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
7464 pcc->msr_mask = (1ull << MSR_SF) |
7465 (1ull << MSR_HV) |
7466 (1ull << MSR_TM) |
7467 (1ull << MSR_VR) |
7468 (1ull << MSR_VSX) |
7469 (1ull << MSR_EE) |
7470 (1ull << MSR_PR) |
7471 (1ull << MSR_FP) |
7472 (1ull << MSR_ME) |
7473 (1ull << MSR_FE0) |
7474 (1ull << MSR_SE) |
7475 (1ull << MSR_DE) |
7476 (1ull << MSR_FE1) |
7477 (1ull << MSR_IR) |
7478 (1ull << MSR_DR) |
7479 (1ull << MSR_PMM) |
7480 (1ull << MSR_RI) |
7481 (1ull << MSR_LE);
7482 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7483 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7484 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7485 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7486 LPCR_DEE | LPCR_OEE))
7487 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7488 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7489 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7490 pcc->mmu_model = POWERPC_MMU_3_00;
7491 #if defined(CONFIG_SOFTMMU)
7492 /* segment page size remain the same */
7493 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7494 pcc->radix_page_info = &POWER9_radix_page_info;
7495 pcc->lrg_decr_bits = 56;
7496 pcc->n_host_threads = 4;
7497 #endif
7498 pcc->excp_model = POWERPC_EXCP_POWER9;
7499 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7500 pcc->bfd_mach = bfd_mach_ppc64;
7501 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7502 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7503 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7504 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7505 pcc->l1_dcache_size = 0x8000;
7506 pcc->l1_icache_size = 0x8000;
7507 }
7508
7509 #ifdef CONFIG_SOFTMMU
7510 /*
7511 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
7512 * Encoded as array of int_32s in the form:
7513 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
7514 * x -> AP encoding
7515 * y -> radix mode supported page size (encoded as a shift)
7516 */
7517 static struct ppc_radix_page_info POWER10_radix_page_info = {
7518 .count = 4,
7519 .entries = {
7520 0x0000000c, /* 4K - enc: 0x0 */
7521 0xa0000010, /* 64K - enc: 0x5 */
7522 0x20000015, /* 2M - enc: 0x1 */
7523 0x4000001e /* 1G - enc: 0x2 */
7524 }
7525 };
7526 #endif /* CONFIG_SOFTMMU */
7527
7528 static void init_proc_POWER10(CPUPPCState *env)
7529 {
7530 /* Common Registers */
7531 init_proc_book3s_common(env);
7532 register_book3s_207_dbg_sprs(env);
7533
7534 /* POWER8 Specific Registers */
7535 register_book3s_ids_sprs(env);
7536 register_amr_sprs(env);
7537 register_iamr_sprs(env);
7538 register_book3s_purr_sprs(env);
7539 register_power5p_common_sprs(env);
7540 register_power5p_lpar_sprs(env);
7541 register_power5p_ear_sprs(env);
7542 register_power6_common_sprs(env);
7543 register_power6_dbg_sprs(env);
7544 register_power8_tce_address_control_sprs(env);
7545 register_power8_ids_sprs(env);
7546 register_power8_ebb_sprs(env);
7547 register_power8_fscr_sprs(env);
7548 register_power8_pmu_sup_sprs(env);
7549 register_power8_pmu_user_sprs(env);
7550 register_power8_tm_sprs(env);
7551 register_power8_pspb_sprs(env);
7552 register_vtb_sprs(env);
7553 register_power8_ic_sprs(env);
7554 register_power8_book4_sprs(env);
7555 register_power8_rpr_sprs(env);
7556 register_power9_mmu_sprs(env);
7557
7558 /* FIXME: Filter fields properly based on privilege level */
7559 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
7560 spr_read_generic, spr_write_generic,
7561 KVM_REG_PPC_PSSCR, 0);
7562
7563 /* env variables */
7564 env->dcache_line_size = 128;
7565 env->icache_line_size = 128;
7566
7567 /* Allocate hardware IRQ controller */
7568 init_excp_POWER10(env);
7569 ppcPOWER9_irq_init(env_archcpu(env));
7570 }
7571
7572 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
7573 {
7574 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
7575 return true;
7576 }
7577 return false;
7578 }
7579
7580 static bool cpu_has_work_POWER10(CPUState *cs)
7581 {
7582 PowerPCCPU *cpu = POWERPC_CPU(cs);
7583 CPUPPCState *env = &cpu->env;
7584
7585 if (cs->halted) {
7586 uint64_t psscr = env->spr[SPR_PSSCR];
7587
7588 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
7589 return false;
7590 }
7591
7592 /* If EC is clear, just return true on any pending interrupt */
7593 if (!(psscr & PSSCR_EC)) {
7594 return true;
7595 }
7596 /* External Exception */
7597 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
7598 (env->spr[SPR_LPCR] & LPCR_EEE)) {
7599 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
7600 if (heic == 0 || !msr_hv || msr_pr) {
7601 return true;
7602 }
7603 }
7604 /* Decrementer Exception */
7605 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
7606 (env->spr[SPR_LPCR] & LPCR_DEE)) {
7607 return true;
7608 }
7609 /* Machine Check or Hypervisor Maintenance Exception */
7610 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
7611 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
7612 return true;
7613 }
7614 /* Privileged Doorbell Exception */
7615 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
7616 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
7617 return true;
7618 }
7619 /* Hypervisor Doorbell Exception */
7620 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
7621 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
7622 return true;
7623 }
7624 /* Hypervisor virtualization exception */
7625 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
7626 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
7627 return true;
7628 }
7629 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
7630 return true;
7631 }
7632 return false;
7633 } else {
7634 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
7635 }
7636 }
7637
7638 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
7639 {
7640 DeviceClass *dc = DEVICE_CLASS(oc);
7641 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7642 CPUClass *cc = CPU_CLASS(oc);
7643
7644 dc->fw_name = "PowerPC,POWER10";
7645 dc->desc = "POWER10";
7646 pcc->pvr_match = ppc_pvr_match_power10;
7647 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
7648 PCR_COMPAT_3_00;
7649 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
7650 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7651 pcc->init_proc = init_proc_POWER10;
7652 pcc->check_pow = check_pow_nocheck;
7653 cc->has_work = cpu_has_work_POWER10;
7654 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7655 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7656 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7657 PPC_FLOAT_FRSQRTES |
7658 PPC_FLOAT_STFIWX |
7659 PPC_FLOAT_EXT |
7660 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7661 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7662 PPC_MEM_TLBSYNC |
7663 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
7664 PPC_SEGMENT_64B | PPC_SLBI |
7665 PPC_POPCNTB | PPC_POPCNTWD |
7666 PPC_CILDST;
7667 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7668 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7669 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7670 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7671 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7672 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
7673 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
7674 pcc->msr_mask = (1ull << MSR_SF) |
7675 (1ull << MSR_HV) |
7676 (1ull << MSR_TM) |
7677 (1ull << MSR_VR) |
7678 (1ull << MSR_VSX) |
7679 (1ull << MSR_EE) |
7680 (1ull << MSR_PR) |
7681 (1ull << MSR_FP) |
7682 (1ull << MSR_ME) |
7683 (1ull << MSR_FE0) |
7684 (1ull << MSR_SE) |
7685 (1ull << MSR_DE) |
7686 (1ull << MSR_FE1) |
7687 (1ull << MSR_IR) |
7688 (1ull << MSR_DR) |
7689 (1ull << MSR_PMM) |
7690 (1ull << MSR_RI) |
7691 (1ull << MSR_LE);
7692 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
7693 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
7694 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
7695 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
7696 LPCR_DEE | LPCR_OEE))
7697 | LPCR_MER | LPCR_GTSE | LPCR_TC |
7698 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
7699 /* DD2 adds an extra HAIL bit */
7700 pcc->lpcr_mask |= LPCR_HAIL;
7701
7702 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7703 pcc->mmu_model = POWERPC_MMU_3_00;
7704 #if defined(CONFIG_SOFTMMU)
7705 /* segment page size remain the same */
7706 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
7707 pcc->radix_page_info = &POWER10_radix_page_info;
7708 pcc->lrg_decr_bits = 56;
7709 #endif
7710 pcc->excp_model = POWERPC_EXCP_POWER10;
7711 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
7712 pcc->bfd_mach = bfd_mach_ppc64;
7713 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7714 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7715 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7716 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7717 pcc->l1_dcache_size = 0x8000;
7718 pcc->l1_icache_size = 0x8000;
7719 }
7720
7721 #if !defined(CONFIG_USER_ONLY)
7722 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
7723 {
7724 CPUPPCState *env = &cpu->env;
7725
7726 cpu->vhyp = vhyp;
7727
7728 /*
7729 * With a virtual hypervisor mode we never allow the CPU to go
7730 * hypervisor mode itself
7731 */
7732 env->msr_mask &= ~MSR_HVB;
7733 }
7734
7735 #endif /* !defined(CONFIG_USER_ONLY) */
7736
7737 #endif /* defined(TARGET_PPC64) */
7738
7739 /*****************************************************************************/
7740 /* Generic CPU instantiation routine */
7741 static void init_ppc_proc(PowerPCCPU *cpu)
7742 {
7743 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7744 CPUPPCState *env = &cpu->env;
7745 #if !defined(CONFIG_USER_ONLY)
7746 int i;
7747
7748 env->irq_inputs = NULL;
7749 /* Set all exception vectors to an invalid address */
7750 for (i = 0; i < POWERPC_EXCP_NB; i++) {
7751 env->excp_vectors[i] = (target_ulong)(-1ULL);
7752 }
7753 env->ivor_mask = 0x00000000;
7754 env->ivpr_mask = 0x00000000;
7755 /* Default MMU definitions */
7756 env->nb_BATs = 0;
7757 env->nb_tlb = 0;
7758 env->nb_ways = 0;
7759 env->tlb_type = TLB_NONE;
7760 #endif
7761 /* Register SPR common to all PowerPC implementations */
7762 register_generic_sprs(env);
7763 spr_register(env, SPR_PVR, "PVR",
7764 /* Linux permits userspace to read PVR */
7765 #if defined(CONFIG_LINUX_USER)
7766 &spr_read_generic,
7767 #else
7768 SPR_NOACCESS,
7769 #endif
7770 SPR_NOACCESS,
7771 &spr_read_generic, SPR_NOACCESS,
7772 pcc->pvr);
7773 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7774 if (pcc->svr != POWERPC_SVR_NONE) {
7775 if (pcc->svr & POWERPC_SVR_E500) {
7776 spr_register(env, SPR_E500_SVR, "SVR",
7777 SPR_NOACCESS, SPR_NOACCESS,
7778 &spr_read_generic, SPR_NOACCESS,
7779 pcc->svr & ~POWERPC_SVR_E500);
7780 } else {
7781 spr_register(env, SPR_SVR, "SVR",
7782 SPR_NOACCESS, SPR_NOACCESS,
7783 &spr_read_generic, SPR_NOACCESS,
7784 pcc->svr);
7785 }
7786 }
7787 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7788 (*pcc->init_proc)(env);
7789
7790 #if !defined(CONFIG_USER_ONLY)
7791 ppc_gdb_gen_spr_xml(cpu);
7792 #endif
7793
7794 /* MSR bits & flags consistency checks */
7795 if (env->msr_mask & (1 << 25)) {
7796 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7797 case POWERPC_FLAG_SPE:
7798 case POWERPC_FLAG_VRE:
7799 break;
7800 default:
7801 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7802 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7803 exit(1);
7804 }
7805 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7806 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7807 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7808 exit(1);
7809 }
7810 if (env->msr_mask & (1 << 17)) {
7811 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7812 case POWERPC_FLAG_TGPR:
7813 case POWERPC_FLAG_CE:
7814 break;
7815 default:
7816 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7817 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7818 exit(1);
7819 }
7820 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7821 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7822 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7823 exit(1);
7824 }
7825 if (env->msr_mask & (1 << 10)) {
7826 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7827 POWERPC_FLAG_UBLE)) {
7828 case POWERPC_FLAG_SE:
7829 case POWERPC_FLAG_DWE:
7830 case POWERPC_FLAG_UBLE:
7831 break;
7832 default:
7833 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7834 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7835 "POWERPC_FLAG_UBLE\n");
7836 exit(1);
7837 }
7838 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7839 POWERPC_FLAG_UBLE)) {
7840 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7841 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7842 "POWERPC_FLAG_UBLE\n");
7843 exit(1);
7844 }
7845 if (env->msr_mask & (1 << 9)) {
7846 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7847 case POWERPC_FLAG_BE:
7848 case POWERPC_FLAG_DE:
7849 break;
7850 default:
7851 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7852 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7853 exit(1);
7854 }
7855 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7856 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7857 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7858 exit(1);
7859 }
7860 if (env->msr_mask & (1 << 2)) {
7861 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7862 case POWERPC_FLAG_PX:
7863 case POWERPC_FLAG_PMM:
7864 break;
7865 default:
7866 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7867 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7868 exit(1);
7869 }
7870 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7871 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7872 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7873 exit(1);
7874 }
7875 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7876 fprintf(stderr, "PowerPC flags inconsistency\n"
7877 "Should define the time-base and decrementer clock source\n");
7878 exit(1);
7879 }
7880 /* Allocate TLBs buffer when needed */
7881 #if !defined(CONFIG_USER_ONLY)
7882 if (env->nb_tlb != 0) {
7883 int nb_tlb = env->nb_tlb;
7884 if (env->id_tlbs != 0) {
7885 nb_tlb *= 2;
7886 }
7887 switch (env->tlb_type) {
7888 case TLB_6XX:
7889 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
7890 break;
7891 case TLB_EMB:
7892 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
7893 break;
7894 case TLB_MAS:
7895 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
7896 break;
7897 }
7898 /* Pre-compute some useful values */
7899 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7900 }
7901 if (env->irq_inputs == NULL) {
7902 warn_report("no internal IRQ controller registered."
7903 " Attempt QEMU to crash very soon !");
7904 }
7905 #endif
7906 if (env->check_pow == NULL) {
7907 warn_report("no power management check handler registered."
7908 " Attempt QEMU to crash very soon !");
7909 }
7910 }
7911
7912
7913 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
7914 {
7915 CPUState *cs = CPU(dev);
7916 PowerPCCPU *cpu = POWERPC_CPU(dev);
7917 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7918 Error *local_err = NULL;
7919
7920 cpu_exec_realizefn(cs, &local_err);
7921 if (local_err != NULL) {
7922 error_propagate(errp, local_err);
7923 return;
7924 }
7925 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
7926 cpu->vcpu_id = cs->cpu_index;
7927 }
7928
7929 if (tcg_enabled()) {
7930 if (ppc_fixup_cpu(cpu) != 0) {
7931 error_setg(errp, "Unable to emulate selected CPU with TCG");
7932 goto unrealize;
7933 }
7934 }
7935
7936 create_ppc_opcodes(cpu, &local_err);
7937 if (local_err != NULL) {
7938 error_propagate(errp, local_err);
7939 goto unrealize;
7940 }
7941 init_ppc_proc(cpu);
7942
7943 ppc_gdb_init(cs, pcc);
7944 qemu_init_vcpu(cs);
7945
7946 pcc->parent_realize(dev, errp);
7947
7948 return;
7949
7950 unrealize:
7951 cpu_exec_unrealizefn(cs);
7952 }
7953
7954 static void ppc_cpu_unrealize(DeviceState *dev)
7955 {
7956 PowerPCCPU *cpu = POWERPC_CPU(dev);
7957 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7958
7959 pcc->parent_unrealize(dev);
7960
7961 cpu_remove_sync(CPU(cpu));
7962
7963 destroy_ppc_opcodes(cpu);
7964 }
7965
7966 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
7967 {
7968 ObjectClass *oc = (ObjectClass *)a;
7969 uint32_t pvr = *(uint32_t *)b;
7970 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7971
7972 /* -cpu host does a PVR lookup during construction */
7973 if (unlikely(strcmp(object_class_get_name(oc),
7974 TYPE_HOST_POWERPC_CPU) == 0)) {
7975 return -1;
7976 }
7977
7978 return pcc->pvr == pvr ? 0 : -1;
7979 }
7980
7981 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
7982 {
7983 GSList *list, *item;
7984 PowerPCCPUClass *pcc = NULL;
7985
7986 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7987 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7988 if (item != NULL) {
7989 pcc = POWERPC_CPU_CLASS(item->data);
7990 }
7991 g_slist_free(list);
7992
7993 return pcc;
7994 }
7995
7996 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7997 {
7998 ObjectClass *oc = (ObjectClass *)a;
7999 uint32_t pvr = *(uint32_t *)b;
8000 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8001
8002 /* -cpu host does a PVR lookup during construction */
8003 if (unlikely(strcmp(object_class_get_name(oc),
8004 TYPE_HOST_POWERPC_CPU) == 0)) {
8005 return -1;
8006 }
8007
8008 if (pcc->pvr_match(pcc, pvr)) {
8009 return 0;
8010 }
8011
8012 return -1;
8013 }
8014
8015 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8016 {
8017 GSList *list, *item;
8018 PowerPCCPUClass *pcc = NULL;
8019
8020 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8021 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8022 if (item != NULL) {
8023 pcc = POWERPC_CPU_CLASS(item->data);
8024 }
8025 g_slist_free(list);
8026
8027 return pcc;
8028 }
8029
8030 static const char *ppc_cpu_lookup_alias(const char *alias)
8031 {
8032 int ai;
8033
8034 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
8035 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
8036 return ppc_cpu_aliases[ai].model;
8037 }
8038 }
8039
8040 return NULL;
8041 }
8042
8043 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8044 {
8045 char *cpu_model, *typename;
8046 ObjectClass *oc;
8047 const char *p;
8048 unsigned long pvr;
8049
8050 /*
8051 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
8052 * 0x prefix if present)
8053 */
8054 if (!qemu_strtoul(name, &p, 16, &pvr)) {
8055 int len = p - name;
8056 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
8057 if ((len == 8) && (*p == '\0')) {
8058 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
8059 }
8060 }
8061
8062 cpu_model = g_ascii_strdown(name, -1);
8063 p = ppc_cpu_lookup_alias(cpu_model);
8064 if (p) {
8065 g_free(cpu_model);
8066 cpu_model = g_strdup(p);
8067 }
8068
8069 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
8070 oc = object_class_by_name(typename);
8071 g_free(typename);
8072 g_free(cpu_model);
8073
8074 return oc;
8075 }
8076
8077 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
8078 {
8079 ObjectClass *oc = OBJECT_CLASS(pcc);
8080
8081 while (oc && !object_class_is_abstract(oc)) {
8082 oc = object_class_get_parent(oc);
8083 }
8084 assert(oc);
8085
8086 return POWERPC_CPU_CLASS(oc);
8087 }
8088
8089 /* Sort by PVR, ordering special case "host" last. */
8090 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8091 {
8092 ObjectClass *oc_a = (ObjectClass *)a;
8093 ObjectClass *oc_b = (ObjectClass *)b;
8094 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8095 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8096 const char *name_a = object_class_get_name(oc_a);
8097 const char *name_b = object_class_get_name(oc_b);
8098
8099 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8100 return 1;
8101 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8102 return -1;
8103 } else {
8104 /* Avoid an integer overflow during subtraction */
8105 if (pcc_a->pvr < pcc_b->pvr) {
8106 return -1;
8107 } else if (pcc_a->pvr > pcc_b->pvr) {
8108 return 1;
8109 } else {
8110 return 0;
8111 }
8112 }
8113 }
8114
8115 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8116 {
8117 ObjectClass *oc = data;
8118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8119 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
8120 const char *typename = object_class_get_name(oc);
8121 char *name;
8122 int i;
8123
8124 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8125 return;
8126 }
8127
8128 name = g_strndup(typename,
8129 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8130 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
8131 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8132 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8133 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
8134
8135 if (alias_oc != oc) {
8136 continue;
8137 }
8138 /*
8139 * If running with KVM, we might update the family alias later, so
8140 * avoid printing the wrong alias here and use "preferred" instead
8141 */
8142 if (strcmp(alias->alias, family->desc) == 0) {
8143 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
8144 alias->alias, family->desc);
8145 } else {
8146 qemu_printf("PowerPC %-16s (alias for %s)\n",
8147 alias->alias, name);
8148 }
8149 }
8150 g_free(name);
8151 }
8152
8153 void ppc_cpu_list(void)
8154 {
8155 GSList *list;
8156
8157 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8158 list = g_slist_sort(list, ppc_cpu_list_compare);
8159 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
8160 g_slist_free(list);
8161
8162 #ifdef CONFIG_KVM
8163 qemu_printf("\n");
8164 qemu_printf("PowerPC %s\n", "host");
8165 #endif
8166 }
8167
8168 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8169 {
8170 ObjectClass *oc = data;
8171 CpuDefinitionInfoList **first = user_data;
8172 const char *typename;
8173 CpuDefinitionInfo *info;
8174
8175 typename = object_class_get_name(oc);
8176 info = g_malloc0(sizeof(*info));
8177 info->name = g_strndup(typename,
8178 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
8179
8180 QAPI_LIST_PREPEND(*first, info);
8181 }
8182
8183 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
8184 {
8185 CpuDefinitionInfoList *cpu_list = NULL;
8186 GSList *list;
8187 int i;
8188
8189 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8190 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8191 g_slist_free(list);
8192
8193 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8194 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8195 ObjectClass *oc;
8196 CpuDefinitionInfo *info;
8197
8198 oc = ppc_cpu_class_by_name(alias->model);
8199 if (oc == NULL) {
8200 continue;
8201 }
8202
8203 info = g_malloc0(sizeof(*info));
8204 info->name = g_strdup(alias->alias);
8205 info->q_typename = g_strdup(object_class_get_name(oc));
8206
8207 QAPI_LIST_PREPEND(cpu_list, info);
8208 }
8209
8210 return cpu_list;
8211 }
8212
8213 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
8214 {
8215 PowerPCCPU *cpu = POWERPC_CPU(cs);
8216
8217 cpu->env.nip = value;
8218 }
8219
8220 static bool ppc_cpu_has_work(CPUState *cs)
8221 {
8222 PowerPCCPU *cpu = POWERPC_CPU(cs);
8223 CPUPPCState *env = &cpu->env;
8224
8225 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8226 }
8227
8228 static void ppc_cpu_reset(DeviceState *dev)
8229 {
8230 CPUState *s = CPU(dev);
8231 PowerPCCPU *cpu = POWERPC_CPU(s);
8232 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8233 CPUPPCState *env = &cpu->env;
8234 target_ulong msr;
8235 int i;
8236
8237 pcc->parent_reset(dev);
8238
8239 msr = (target_ulong)0;
8240 msr |= (target_ulong)MSR_HVB;
8241 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8242 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8243 msr |= (target_ulong)1 << MSR_EP;
8244 #if defined(DO_SINGLE_STEP) && 0
8245 /* Single step trace mode */
8246 msr |= (target_ulong)1 << MSR_SE;
8247 msr |= (target_ulong)1 << MSR_BE;
8248 #endif
8249 #if defined(CONFIG_USER_ONLY)
8250 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8251 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
8252 msr |= (target_ulong)1 << MSR_FE1;
8253 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8254 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
8255 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8256 msr |= (target_ulong)1 << MSR_PR;
8257 #if defined(TARGET_PPC64)
8258 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
8259 #endif
8260 #if !defined(TARGET_WORDS_BIGENDIAN)
8261 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
8262 if (!((env->msr_mask >> MSR_LE) & 1)) {
8263 fprintf(stderr, "Selected CPU does not support little-endian.\n");
8264 exit(1);
8265 }
8266 #endif
8267 #endif
8268
8269 #if defined(TARGET_PPC64)
8270 if (mmu_is_64bit(env->mmu_model)) {
8271 msr |= (1ULL << MSR_SF);
8272 }
8273 #endif
8274
8275 hreg_store_msr(env, msr, 1);
8276
8277 #if !defined(CONFIG_USER_ONLY)
8278 env->nip = env->hreset_vector | env->excp_prefix;
8279 #if defined(CONFIG_TCG)
8280 if (env->mmu_model != POWERPC_MMU_REAL) {
8281 ppc_tlb_invalidate_all(env);
8282 }
8283 #endif /* CONFIG_TCG */
8284 #endif
8285
8286 hreg_compute_hflags(env);
8287 env->reserve_addr = (target_ulong)-1ULL;
8288 /* Be sure no exception or interrupt is pending */
8289 env->pending_interrupts = 0;
8290 s->exception_index = POWERPC_EXCP_NONE;
8291 env->error_code = 0;
8292 ppc_irq_reset(cpu);
8293
8294 /* tininess for underflow is detected before rounding */
8295 set_float_detect_tininess(float_tininess_before_rounding,
8296 &env->fp_status);
8297
8298 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
8299 ppc_spr_t *spr = &env->spr_cb[i];
8300
8301 if (!spr->name) {
8302 continue;
8303 }
8304 env->spr[i] = spr->default_value;
8305 }
8306 }
8307
8308 #ifndef CONFIG_USER_ONLY
8309
8310 static bool ppc_cpu_is_big_endian(CPUState *cs)
8311 {
8312 PowerPCCPU *cpu = POWERPC_CPU(cs);
8313 CPUPPCState *env = &cpu->env;
8314
8315 cpu_synchronize_state(cs);
8316
8317 return !msr_le;
8318 }
8319
8320 #ifdef CONFIG_TCG
8321 static void ppc_cpu_exec_enter(CPUState *cs)
8322 {
8323 PowerPCCPU *cpu = POWERPC_CPU(cs);
8324
8325 if (cpu->vhyp) {
8326 PPCVirtualHypervisorClass *vhc =
8327 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8328 vhc->cpu_exec_enter(cpu->vhyp, cpu);
8329 }
8330 }
8331
8332 static void ppc_cpu_exec_exit(CPUState *cs)
8333 {
8334 PowerPCCPU *cpu = POWERPC_CPU(cs);
8335
8336 if (cpu->vhyp) {
8337 PPCVirtualHypervisorClass *vhc =
8338 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
8339 vhc->cpu_exec_exit(cpu->vhyp, cpu);
8340 }
8341 }
8342 #endif /* CONFIG_TCG */
8343
8344 #endif /* !CONFIG_USER_ONLY */
8345
8346 static void ppc_cpu_instance_init(Object *obj)
8347 {
8348 PowerPCCPU *cpu = POWERPC_CPU(obj);
8349 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8350 CPUPPCState *env = &cpu->env;
8351
8352 cpu_set_cpustate_pointers(cpu);
8353 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
8354
8355 env->msr_mask = pcc->msr_mask;
8356 env->mmu_model = pcc->mmu_model;
8357 env->excp_model = pcc->excp_model;
8358 env->bus_model = pcc->bus_model;
8359 env->insns_flags = pcc->insns_flags;
8360 env->insns_flags2 = pcc->insns_flags2;
8361 env->flags = pcc->flags;
8362 env->bfd_mach = pcc->bfd_mach;
8363 env->check_pow = pcc->check_pow;
8364
8365 /*
8366 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
8367 * msr_mask. The mask can later be cleared by PAPR mode but the hv
8368 * mode support will remain, thus enforcing that we cannot use
8369 * priv. instructions in guest in PAPR mode. For 970 we currently
8370 * simply don't set HV in msr_mask thus simulating an "Apple mode"
8371 * 970. If we ever want to support 970 HV mode, we'll have to add
8372 * a processor attribute of some sort.
8373 */
8374 #if !defined(CONFIG_USER_ONLY)
8375 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
8376 #endif
8377
8378 ppc_hash64_init(cpu);
8379 }
8380
8381 static void ppc_cpu_instance_finalize(Object *obj)
8382 {
8383 PowerPCCPU *cpu = POWERPC_CPU(obj);
8384
8385 ppc_hash64_finalize(cpu);
8386 }
8387
8388 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
8389 {
8390 return pcc->pvr == pvr;
8391 }
8392
8393 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
8394 {
8395 PowerPCCPU *cpu = POWERPC_CPU(cs);
8396 CPUPPCState *env = &cpu->env;
8397
8398 if ((env->hflags >> MSR_LE) & 1) {
8399 info->endian = BFD_ENDIAN_LITTLE;
8400 }
8401 info->mach = env->bfd_mach;
8402 if (!env->bfd_mach) {
8403 #ifdef TARGET_PPC64
8404 info->mach = bfd_mach_ppc64;
8405 #else
8406 info->mach = bfd_mach_ppc;
8407 #endif
8408 }
8409 info->disassembler_options = (char *)"any";
8410 info->print_insn = print_insn_ppc;
8411
8412 info->cap_arch = CS_ARCH_PPC;
8413 #ifdef TARGET_PPC64
8414 info->cap_mode = CS_MODE_64;
8415 #endif
8416 }
8417
8418 static Property ppc_cpu_properties[] = {
8419 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
8420 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
8421 false),
8422 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
8423 false),
8424 DEFINE_PROP_END_OF_LIST(),
8425 };
8426
8427 #ifndef CONFIG_USER_ONLY
8428 #include "hw/core/sysemu-cpu-ops.h"
8429
8430 static const struct SysemuCPUOps ppc_sysemu_ops = {
8431 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
8432 .write_elf32_note = ppc32_cpu_write_elf32_note,
8433 .write_elf64_note = ppc64_cpu_write_elf64_note,
8434 .virtio_is_big_endian = ppc_cpu_is_big_endian,
8435 .legacy_vmsd = &vmstate_ppc_cpu,
8436 };
8437 #endif
8438
8439 #ifdef CONFIG_TCG
8440 #include "hw/core/tcg-cpu-ops.h"
8441
8442 static const struct TCGCPUOps ppc_tcg_ops = {
8443 .initialize = ppc_translate_init,
8444
8445 #ifdef CONFIG_USER_ONLY
8446 .record_sigsegv = ppc_cpu_record_sigsegv,
8447 #else
8448 .tlb_fill = ppc_cpu_tlb_fill,
8449 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
8450 .do_interrupt = ppc_cpu_do_interrupt,
8451 .cpu_exec_enter = ppc_cpu_exec_enter,
8452 .cpu_exec_exit = ppc_cpu_exec_exit,
8453 .do_unaligned_access = ppc_cpu_do_unaligned_access,
8454 #endif /* !CONFIG_USER_ONLY */
8455 };
8456 #endif /* CONFIG_TCG */
8457
8458 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8459 {
8460 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8461 CPUClass *cc = CPU_CLASS(oc);
8462 DeviceClass *dc = DEVICE_CLASS(oc);
8463
8464 device_class_set_parent_realize(dc, ppc_cpu_realize,
8465 &pcc->parent_realize);
8466 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
8467 &pcc->parent_unrealize);
8468 pcc->pvr_match = ppc_pvr_match_default;
8469 device_class_set_props(dc, ppc_cpu_properties);
8470
8471 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
8472
8473 cc->class_by_name = ppc_cpu_class_by_name;
8474 cc->has_work = ppc_cpu_has_work;
8475 cc->dump_state = ppc_cpu_dump_state;
8476 cc->set_pc = ppc_cpu_set_pc;
8477 cc->gdb_read_register = ppc_cpu_gdb_read_register;
8478 cc->gdb_write_register = ppc_cpu_gdb_write_register;
8479 #ifndef CONFIG_USER_ONLY
8480 cc->sysemu_ops = &ppc_sysemu_ops;
8481 #endif
8482
8483 cc->gdb_num_core_regs = 71;
8484 #ifndef CONFIG_USER_ONLY
8485 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
8486 #endif
8487 #ifdef USE_APPLE_GDB
8488 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
8489 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
8490 cc->gdb_num_core_regs = 71 + 32;
8491 #endif
8492
8493 cc->gdb_arch_name = ppc_gdb_arch_name;
8494 #if defined(TARGET_PPC64)
8495 cc->gdb_core_xml_file = "power64-core.xml";
8496 #else
8497 cc->gdb_core_xml_file = "power-core.xml";
8498 #endif
8499 cc->disas_set_info = ppc_disas_set_info;
8500
8501 dc->fw_name = "PowerPC,UNKNOWN";
8502
8503 #ifdef CONFIG_TCG
8504 cc->tcg_ops = &ppc_tcg_ops;
8505 #endif /* CONFIG_TCG */
8506 }
8507
8508 static const TypeInfo ppc_cpu_type_info = {
8509 .name = TYPE_POWERPC_CPU,
8510 .parent = TYPE_CPU,
8511 .instance_size = sizeof(PowerPCCPU),
8512 .instance_align = __alignof__(PowerPCCPU),
8513 .instance_init = ppc_cpu_instance_init,
8514 .instance_finalize = ppc_cpu_instance_finalize,
8515 .abstract = true,
8516 .class_size = sizeof(PowerPCCPUClass),
8517 .class_init = ppc_cpu_class_init,
8518 };
8519
8520 #ifndef CONFIG_USER_ONLY
8521 static const TypeInfo ppc_vhyp_type_info = {
8522 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
8523 .parent = TYPE_INTERFACE,
8524 .class_size = sizeof(PPCVirtualHypervisorClass),
8525 };
8526 #endif
8527
8528 static void ppc_cpu_register_types(void)
8529 {
8530 type_register_static(&ppc_cpu_type_info);
8531 #ifndef CONFIG_USER_ONLY
8532 type_register_static(&ppc_vhyp_type_info);
8533 #endif
8534 }
8535
8536 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
8537 {
8538 #define RGPL 4
8539 #define RFPL 4
8540
8541 PowerPCCPU *cpu = POWERPC_CPU(cs);
8542 CPUPPCState *env = &cpu->env;
8543 int i;
8544
8545 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
8546 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
8547 env->nip, env->lr, env->ctr, cpu_read_xer(env),
8548 cs->cpu_index);
8549 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
8550 "%08x iidx %d didx %d\n",
8551 env->msr, env->spr[SPR_HID0], env->hflags,
8552 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
8553 #if !defined(NO_TIMER_DUMP)
8554 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
8555 #if !defined(CONFIG_USER_ONLY)
8556 " DECR " TARGET_FMT_lu
8557 #endif
8558 "\n",
8559 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
8560 #if !defined(CONFIG_USER_ONLY)
8561 , cpu_ppc_load_decr(env)
8562 #endif
8563 );
8564 #endif
8565 for (i = 0; i < 32; i++) {
8566 if ((i & (RGPL - 1)) == 0) {
8567 qemu_fprintf(f, "GPR%02d", i);
8568 }
8569 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
8570 if ((i & (RGPL - 1)) == (RGPL - 1)) {
8571 qemu_fprintf(f, "\n");
8572 }
8573 }
8574 qemu_fprintf(f, "CR ");
8575 for (i = 0; i < 8; i++)
8576 qemu_fprintf(f, "%01x", env->crf[i]);
8577 qemu_fprintf(f, " [");
8578 for (i = 0; i < 8; i++) {
8579 char a = '-';
8580 if (env->crf[i] & 0x08) {
8581 a = 'L';
8582 } else if (env->crf[i] & 0x04) {
8583 a = 'G';
8584 } else if (env->crf[i] & 0x02) {
8585 a = 'E';
8586 }
8587 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
8588 }
8589 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
8590 env->reserve_addr);
8591
8592 if (flags & CPU_DUMP_FPU) {
8593 for (i = 0; i < 32; i++) {
8594 if ((i & (RFPL - 1)) == 0) {
8595 qemu_fprintf(f, "FPR%02d", i);
8596 }
8597 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
8598 if ((i & (RFPL - 1)) == (RFPL - 1)) {
8599 qemu_fprintf(f, "\n");
8600 }
8601 }
8602 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
8603 }
8604
8605 #if !defined(CONFIG_USER_ONLY)
8606 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
8607 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
8608 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
8609 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
8610
8611 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
8612 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
8613 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
8614 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
8615
8616 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
8617 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
8618 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
8619 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
8620
8621 #if defined(TARGET_PPC64)
8622 if (env->excp_model == POWERPC_EXCP_POWER7 ||
8623 env->excp_model == POWERPC_EXCP_POWER8 ||
8624 env->excp_model == POWERPC_EXCP_POWER9 ||
8625 env->excp_model == POWERPC_EXCP_POWER10) {
8626 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
8627 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
8628 }
8629 #endif
8630 if (env->excp_model == POWERPC_EXCP_BOOKE) {
8631 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
8632 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
8633 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
8634 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
8635
8636 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
8637 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
8638 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
8639 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
8640
8641 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
8642 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
8643 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
8644 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
8645
8646 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
8647 " EPR " TARGET_FMT_lx "\n",
8648 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
8649 env->spr[SPR_BOOKE_EPR]);
8650
8651 /* FSL-specific */
8652 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
8653 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
8654 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
8655 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
8656
8657 /*
8658 * IVORs are left out as they are large and do not change often --
8659 * they can be read with "p $ivor0", "p $ivor1", etc.
8660 */
8661 }
8662
8663 #if defined(TARGET_PPC64)
8664 if (env->flags & POWERPC_FLAG_CFAR) {
8665 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
8666 }
8667 #endif
8668
8669 if (env->spr_cb[SPR_LPCR].name) {
8670 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
8671 }
8672
8673 switch (env->mmu_model) {
8674 case POWERPC_MMU_32B:
8675 case POWERPC_MMU_601:
8676 case POWERPC_MMU_SOFT_6xx:
8677 #if defined(TARGET_PPC64)
8678 case POWERPC_MMU_64B:
8679 case POWERPC_MMU_2_03:
8680 case POWERPC_MMU_2_06:
8681 case POWERPC_MMU_2_07:
8682 case POWERPC_MMU_3_00:
8683 #endif
8684 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
8685 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
8686 }
8687 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
8688 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
8689 }
8690 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
8691 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
8692 break;
8693 case POWERPC_MMU_BOOKE206:
8694 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
8695 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
8696 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
8697 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
8698
8699 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
8700 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
8701 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
8702 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
8703
8704 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
8705 " TLB1CFG " TARGET_FMT_lx "\n",
8706 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
8707 env->spr[SPR_BOOKE_TLB1CFG]);
8708 break;
8709 default:
8710 break;
8711 }
8712 #endif
8713
8714 #undef RGPL
8715 #undef RFPL
8716 }
8717 type_init(ppc_cpu_register_types)
QEmu