2 * MIPS emulation for qemu: CPU initialisation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* CPU / CPU family specific config register values. */
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
48 #define MIPS_CONFIG4 \
51 #define MIPS_CONFIG5 \
54 /* MMU types, the first four entries have the same layout as the
74 int32_t CP0_Config4_rw_bitmask
;
76 int32_t CP0_Config5_rw_bitmask
;
79 target_ulong CP0_LLAddr_rw_bitmask
;
83 int32_t CP0_Status_rw_bitmask
;
84 int32_t CP0_TCStatus_rw_bitmask
;
90 int32_t CP0_SRSConf0_rw_bitmask
;
92 int32_t CP0_SRSConf1_rw_bitmask
;
94 int32_t CP0_SRSConf2_rw_bitmask
;
96 int32_t CP0_SRSConf3_rw_bitmask
;
98 int32_t CP0_SRSConf4_rw_bitmask
;
100 int32_t CP0_PageGrain_rw_bitmask
;
101 int32_t CP0_PageGrain
;
103 enum mips_mmu_types mmu_type
;
106 /*****************************************************************************/
107 /* MIPS CPU definitions */
108 static const mips_def_t mips_defs
[] =
112 .CP0_PRid
= 0x00018000,
113 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_R4000
<< CP0C0_MT
),
114 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
115 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
116 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
118 .CP0_Config2
= MIPS_CONFIG2
,
119 .CP0_Config3
= MIPS_CONFIG3
,
120 .CP0_LLAddr_rw_bitmask
= 0,
121 .CP0_LLAddr_shift
= 4,
124 .CP0_Status_rw_bitmask
= 0x1278FF17,
127 .insn_flags
= CPU_MIPS32
,
128 .mmu_type
= MMU_TYPE_R4000
,
132 .CP0_PRid
= 0x00018300,
133 /* Config1 implemented, fixed mapping MMU,
134 no virtual icache, uncached coherency. */
135 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_FMT
<< CP0C0_MT
),
136 .CP0_Config1
= MIPS_CONFIG1
|
137 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
138 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
140 .CP0_Config2
= MIPS_CONFIG2
,
141 .CP0_Config3
= MIPS_CONFIG3
,
142 .CP0_LLAddr_rw_bitmask
= 0,
143 .CP0_LLAddr_shift
= 4,
146 .CP0_Status_rw_bitmask
= 0x1258FF17,
149 .insn_flags
= CPU_MIPS32
| ASE_MIPS16
,
150 .mmu_type
= MMU_TYPE_FMT
,
154 .CP0_PRid
= 0x00018400,
155 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_R4000
<< CP0C0_MT
),
156 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
157 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
158 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
160 .CP0_Config2
= MIPS_CONFIG2
,
161 .CP0_Config3
= MIPS_CONFIG3
,
162 .CP0_LLAddr_rw_bitmask
= 0,
163 .CP0_LLAddr_shift
= 4,
166 .CP0_Status_rw_bitmask
= 0x1278FF17,
169 .insn_flags
= CPU_MIPS32
,
170 .mmu_type
= MMU_TYPE_R4000
,
174 .CP0_PRid
= 0x00018500,
175 .CP0_Config0
= MIPS_CONFIG0
| (MMU_TYPE_FMT
<< CP0C0_MT
),
176 .CP0_Config1
= MIPS_CONFIG1
|
177 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
178 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
180 .CP0_Config2
= MIPS_CONFIG2
,
181 .CP0_Config3
= MIPS_CONFIG3
,
182 .CP0_LLAddr_rw_bitmask
= 0,
183 .CP0_LLAddr_shift
= 4,
186 .CP0_Status_rw_bitmask
= 0x1258FF17,
189 .insn_flags
= CPU_MIPS32
| ASE_MIPS16
,
190 .mmu_type
= MMU_TYPE_FMT
,
194 .CP0_PRid
= 0x00019000,
195 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
196 (MMU_TYPE_R4000
<< CP0C0_MT
),
197 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
198 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
199 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
201 .CP0_Config2
= MIPS_CONFIG2
,
202 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
203 .CP0_LLAddr_rw_bitmask
= 0,
204 .CP0_LLAddr_shift
= 4,
207 .CP0_Status_rw_bitmask
= 0x1278FF17,
210 .insn_flags
= CPU_MIPS32R2
,
211 .mmu_type
= MMU_TYPE_R4000
,
215 .CP0_PRid
= 0x00019100,
216 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
217 (MMU_TYPE_FMT
<< CP0C0_MT
),
218 .CP0_Config1
= MIPS_CONFIG1
|
219 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
220 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
222 .CP0_Config2
= MIPS_CONFIG2
,
223 .CP0_Config3
= MIPS_CONFIG3
,
224 .CP0_LLAddr_rw_bitmask
= 0,
225 .CP0_LLAddr_shift
= 4,
228 .CP0_Status_rw_bitmask
= 0x1258FF17,
231 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
232 .mmu_type
= MMU_TYPE_FMT
,
236 .CP0_PRid
= 0x00019300,
237 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
238 (MMU_TYPE_R4000
<< CP0C0_MT
),
239 .CP0_Config1
= MIPS_CONFIG1
| (15 << CP0C1_MMU
) |
240 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
241 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
243 .CP0_Config2
= MIPS_CONFIG2
,
244 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
245 .CP0_LLAddr_rw_bitmask
= 0,
246 .CP0_LLAddr_shift
= 4,
249 /* No DSP implemented. */
250 .CP0_Status_rw_bitmask
= 0x1278FF1F,
253 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
254 .mmu_type
= MMU_TYPE_R4000
,
258 .CP0_PRid
= 0x00019300,
259 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
260 (MMU_TYPE_R4000
<< CP0C0_MT
),
261 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
262 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
263 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
265 .CP0_Config2
= MIPS_CONFIG2
,
266 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
),
267 .CP0_LLAddr_rw_bitmask
= 0,
268 .CP0_LLAddr_shift
= 4,
271 /* No DSP implemented. */
272 .CP0_Status_rw_bitmask
= 0x3678FF1F,
273 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
274 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x93 << FCR0_PRID
),
277 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
,
278 .mmu_type
= MMU_TYPE_R4000
,
282 .CP0_PRid
= 0x00019500,
283 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
284 (MMU_TYPE_R4000
<< CP0C0_MT
),
285 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
286 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
287 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
289 .CP0_Config2
= MIPS_CONFIG2
,
290 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_VInt
) | (1 << CP0C3_MT
) |
292 .CP0_LLAddr_rw_bitmask
= 0,
293 .CP0_LLAddr_shift
= 0,
296 .CP0_Status_rw_bitmask
= 0x3778FF1F,
297 .CP0_TCStatus_rw_bitmask
= (0 << CP0TCSt_TCU3
) | (0 << CP0TCSt_TCU2
) |
298 (1 << CP0TCSt_TCU1
) | (1 << CP0TCSt_TCU0
) |
299 (0 << CP0TCSt_TMX
) | (1 << CP0TCSt_DT
) |
300 (1 << CP0TCSt_DA
) | (1 << CP0TCSt_A
) |
301 (0x3 << CP0TCSt_TKSU
) | (1 << CP0TCSt_IXMT
) |
302 (0xff << CP0TCSt_TASID
),
303 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
304 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x95 << FCR0_PRID
),
305 .CP0_SRSCtl
= (0xf << CP0SRSCtl_HSS
),
306 .CP0_SRSConf0_rw_bitmask
= 0x3fffffff,
307 .CP0_SRSConf0
= (1U << CP0SRSC0_M
) | (0x3fe << CP0SRSC0_SRS3
) |
308 (0x3fe << CP0SRSC0_SRS2
) | (0x3fe << CP0SRSC0_SRS1
),
309 .CP0_SRSConf1_rw_bitmask
= 0x3fffffff,
310 .CP0_SRSConf1
= (1U << CP0SRSC1_M
) | (0x3fe << CP0SRSC1_SRS6
) |
311 (0x3fe << CP0SRSC1_SRS5
) | (0x3fe << CP0SRSC1_SRS4
),
312 .CP0_SRSConf2_rw_bitmask
= 0x3fffffff,
313 .CP0_SRSConf2
= (1U << CP0SRSC2_M
) | (0x3fe << CP0SRSC2_SRS9
) |
314 (0x3fe << CP0SRSC2_SRS8
) | (0x3fe << CP0SRSC2_SRS7
),
315 .CP0_SRSConf3_rw_bitmask
= 0x3fffffff,
316 .CP0_SRSConf3
= (1U << CP0SRSC3_M
) | (0x3fe << CP0SRSC3_SRS12
) |
317 (0x3fe << CP0SRSC3_SRS11
) | (0x3fe << CP0SRSC3_SRS10
),
318 .CP0_SRSConf4_rw_bitmask
= 0x3fffffff,
319 .CP0_SRSConf4
= (0x3fe << CP0SRSC4_SRS15
) |
320 (0x3fe << CP0SRSC4_SRS14
) | (0x3fe << CP0SRSC4_SRS13
),
323 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
| ASE_DSP
| ASE_MT
,
324 .mmu_type
= MMU_TYPE_R4000
,
328 .CP0_PRid
= 0x00019700,
329 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
330 (MMU_TYPE_R4000
<< CP0C0_MT
),
331 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
332 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
333 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
335 .CP0_Config2
= MIPS_CONFIG2
,
336 .CP0_Config3
= MIPS_CONFIG3
| (0 << CP0C3_VInt
) | (1 << CP0C3_DSPP
),
337 .CP0_LLAddr_rw_bitmask
= 0,
338 .CP0_LLAddr_shift
= 4,
341 .CP0_Status_rw_bitmask
= 0x3778FF1F,
342 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
343 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x93 << FCR0_PRID
),
346 .insn_flags
= CPU_MIPS32R2
| ASE_MIPS16
| ASE_DSP
| ASE_DSPR2
,
347 .mmu_type
= MMU_TYPE_R4000
,
350 /* A generic CPU providing MIPS32 Release 5 features.
351 FIXME: Eventually this should be replaced by a real CPU model. */
352 .name
= "mips32r5-generic",
353 .CP0_PRid
= 0x00019700,
354 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) |
355 (MMU_TYPE_R4000
<< CP0C0_MT
),
356 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (15 << CP0C1_MMU
) |
357 (0 << CP0C1_IS
) | (3 << CP0C1_IL
) | (1 << CP0C1_IA
) |
358 (0 << CP0C1_DS
) | (3 << CP0C1_DL
) | (1 << CP0C1_DA
) |
360 .CP0_Config2
= MIPS_CONFIG2
,
361 .CP0_Config3
= MIPS_CONFIG3
| (1U << CP0C3_M
) | (1 << CP0C3_MSAP
),
362 .CP0_Config4
= MIPS_CONFIG4
| (1U << CP0C4_M
),
363 .CP0_Config4_rw_bitmask
= 0,
364 .CP0_Config5
= MIPS_CONFIG5
| (1 << CP0C5_UFR
),
365 .CP0_Config5_rw_bitmask
= (0 << CP0C5_M
) | (1 << CP0C5_K
) |
366 (1 << CP0C5_CV
) | (0 << CP0C5_EVA
) |
367 (1 << CP0C5_MSAEn
) | (1 << CP0C5_UFR
) |
368 (0 << CP0C5_NFExists
),
369 .CP0_LLAddr_rw_bitmask
= 0,
370 .CP0_LLAddr_shift
= 4,
373 .CP0_Status_rw_bitmask
= 0x3778FF1F,
374 .CP1_fcr0
= (1 << FCR0_UFRP
) | (1 << FCR0_F64
) | (1 << FCR0_L
) |
375 (1 << FCR0_W
) | (1 << FCR0_D
) | (1 << FCR0_S
) |
379 .insn_flags
= CPU_MIPS32R5
| ASE_MIPS16
| ASE_DSP
| ASE_DSPR2
| ASE_MSA
,
380 .mmu_type
= MMU_TYPE_R4000
,
382 #if defined(TARGET_MIPS64)
385 .CP0_PRid
= 0x00000400,
386 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
387 .CP0_Config0
= (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0
),
388 /* Note: Config1 is only used internally, the R4000 has only Config0. */
389 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
390 .CP0_LLAddr_rw_bitmask
= 0xFFFFFFFF,
391 .CP0_LLAddr_shift
= 4,
394 .CP0_Status_rw_bitmask
= 0x3678FFFF,
395 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
396 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x0 << FCR0_REV
),
399 .insn_flags
= CPU_MIPS3
,
400 .mmu_type
= MMU_TYPE_R4000
,
404 .CP0_PRid
= 0x00005400,
405 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
406 .CP0_Config0
= (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0
),
407 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
408 .CP0_LLAddr_rw_bitmask
= 0xFFFFFFFFL
,
409 .CP0_LLAddr_shift
= 4,
412 .CP0_Status_rw_bitmask
= 0x3678FFFF,
413 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
414 .CP1_fcr0
= (0x54 << FCR0_PRID
) | (0x0 << FCR0_REV
),
417 .insn_flags
= CPU_VR54XX
,
418 .mmu_type
= MMU_TYPE_R4000
,
422 .CP0_PRid
= 0x00018100,
423 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
424 (MMU_TYPE_R4000
<< CP0C0_MT
),
425 .CP0_Config1
= MIPS_CONFIG1
| (31 << CP0C1_MMU
) |
426 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
427 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
428 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
429 .CP0_Config2
= MIPS_CONFIG2
,
430 .CP0_Config3
= MIPS_CONFIG3
,
431 .CP0_LLAddr_rw_bitmask
= 0,
432 .CP0_LLAddr_shift
= 4,
435 .CP0_Status_rw_bitmask
= 0x32F8FFFF,
438 .insn_flags
= CPU_MIPS64
,
439 .mmu_type
= MMU_TYPE_R4000
,
443 .CP0_PRid
= 0x00018100,
444 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
445 (MMU_TYPE_R4000
<< CP0C0_MT
),
446 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (31 << CP0C1_MMU
) |
447 (1 << CP0C1_IS
) | (4 << CP0C1_IL
) | (1 << CP0C1_IA
) |
448 (1 << CP0C1_DS
) | (4 << CP0C1_DL
) | (1 << CP0C1_DA
) |
449 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
450 .CP0_Config2
= MIPS_CONFIG2
,
451 .CP0_Config3
= MIPS_CONFIG3
,
452 .CP0_LLAddr_rw_bitmask
= 0,
453 .CP0_LLAddr_shift
= 4,
456 .CP0_Status_rw_bitmask
= 0x36F8FFFF,
457 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
458 .CP1_fcr0
= (1 << FCR0_D
) | (1 << FCR0_S
) |
459 (0x81 << FCR0_PRID
) | (0x0 << FCR0_REV
),
462 .insn_flags
= CPU_MIPS64
,
463 .mmu_type
= MMU_TYPE_R4000
,
467 /* We emulate a later version of the 20Kc, earlier ones had a broken
469 .CP0_PRid
= 0x000182a0,
470 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AT
) |
471 (MMU_TYPE_R4000
<< CP0C0_MT
) | (1 << CP0C0_VI
),
472 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (47 << CP0C1_MMU
) |
473 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
474 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
475 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
476 .CP0_Config2
= MIPS_CONFIG2
,
477 .CP0_Config3
= MIPS_CONFIG3
,
478 .CP0_LLAddr_rw_bitmask
= 0,
479 .CP0_LLAddr_shift
= 0,
482 .CP0_Status_rw_bitmask
= 0x36FBFFFF,
483 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
484 .CP1_fcr0
= (1 << FCR0_3D
) | (1 << FCR0_PS
) |
485 (1 << FCR0_D
) | (1 << FCR0_S
) |
486 (0x82 << FCR0_PRID
) | (0x0 << FCR0_REV
),
489 .insn_flags
= CPU_MIPS64
| ASE_MIPS3D
,
490 .mmu_type
= MMU_TYPE_R4000
,
493 /* A generic CPU providing MIPS64 Release 2 features.
494 FIXME: Eventually this should be replaced by a real CPU model. */
495 .name
= "MIPS64R2-generic",
496 .CP0_PRid
= 0x00010000,
497 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
498 (MMU_TYPE_R4000
<< CP0C0_MT
),
499 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (63 << CP0C1_MMU
) |
500 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
501 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
502 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
503 .CP0_Config2
= MIPS_CONFIG2
,
504 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_LPA
),
505 .CP0_LLAddr_rw_bitmask
= 0,
506 .CP0_LLAddr_shift
= 0,
509 .CP0_Status_rw_bitmask
= 0x36FBFFFF,
510 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_3D
) | (1 << FCR0_PS
) |
511 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
512 (1 << FCR0_S
) | (0x00 << FCR0_PRID
) | (0x0 << FCR0_REV
),
514 /* The architectural limit is 59, but we have hardcoded 36 bit
516 .PABITS = 59, */ /* the architectural limit */
518 .insn_flags
= CPU_MIPS64R2
| ASE_MIPS3D
,
519 .mmu_type
= MMU_TYPE_R4000
,
522 /* A generic CPU supporting MIPS64 Release 6 ISA.
523 FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
524 Eventually this should be replaced by a real CPU model. */
525 .name
= "MIPS64R6-generic",
526 .CP0_PRid
= 0x00010000,
527 .CP0_Config0
= MIPS_CONFIG0
| (0x2 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
528 (MMU_TYPE_R4000
<< CP0C0_MT
),
529 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (63 << CP0C1_MMU
) |
530 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
531 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
532 (0 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
533 .CP0_Config2
= MIPS_CONFIG2
,
534 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_RXI
) | (1 << CP0C3_BP
) |
535 (1 << CP0C3_BI
) | (1 << CP0C3_ULRI
) | (1U << CP0C3_M
),
536 .CP0_Config4
= MIPS_CONFIG4
| (0xfc << CP0C4_KScrExist
) |
537 (3 << CP0C4_IE
) | (1 << CP0C4_M
),
538 .CP0_Config5_rw_bitmask
= (1 << CP0C5_SBRI
),
539 .CP0_LLAddr_rw_bitmask
= 0,
540 .CP0_LLAddr_shift
= 0,
543 .CP0_Status_rw_bitmask
= 0x30D8FFFF,
544 .CP0_PageGrain
= (1 << CP0PG_IEC
) | (1 << CP0PG_XIE
) |
546 .CP0_PageGrain_rw_bitmask
= 0,
547 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_L
) | (1 << FCR0_W
) |
548 (1 << FCR0_D
) | (1 << FCR0_S
) | (0x00 << FCR0_PRID
) |
551 /* The architectural limit is 59, but we have hardcoded 36 bit
553 .PABITS = 59, */ /* the architectural limit */
555 .insn_flags
= CPU_MIPS64R6
,
556 .mmu_type
= MMU_TYPE_R4000
,
559 .name
= "Loongson-2E",
561 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
562 .CP0_Config0
= (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
564 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
565 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
568 .CP0_Status_rw_bitmask
= 0x35D0FFFF,
569 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x1 << FCR0_REV
),
572 .insn_flags
= CPU_LOONGSON2E
,
573 .mmu_type
= MMU_TYPE_R4000
,
576 .name
= "Loongson-2F",
578 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
579 .CP0_Config0
= (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
581 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
582 .CP0_Config1
= (1 << CP0C1_FP
) | (47 << CP0C1_MMU
),
585 .CP0_Status_rw_bitmask
= 0xF5D0FF1F, /*bit5:7 not writable*/
586 .CP1_fcr0
= (0x5 << FCR0_PRID
) | (0x1 << FCR0_REV
),
589 .insn_flags
= CPU_LOONGSON2F
,
590 .mmu_type
= MMU_TYPE_R4000
,
593 /* A generic CPU providing MIPS64 ASE DSP 2 features.
594 FIXME: Eventually this should be replaced by a real CPU model. */
595 .name
= "mips64dspr2",
596 .CP0_PRid
= 0x00010000,
597 .CP0_Config0
= MIPS_CONFIG0
| (0x1 << CP0C0_AR
) | (0x2 << CP0C0_AT
) |
598 (MMU_TYPE_R4000
<< CP0C0_MT
),
599 .CP0_Config1
= MIPS_CONFIG1
| (1 << CP0C1_FP
) | (63 << CP0C1_MMU
) |
600 (2 << CP0C1_IS
) | (4 << CP0C1_IL
) | (3 << CP0C1_IA
) |
601 (2 << CP0C1_DS
) | (4 << CP0C1_DL
) | (3 << CP0C1_DA
) |
602 (1 << CP0C1_PC
) | (1 << CP0C1_WR
) | (1 << CP0C1_EP
),
603 .CP0_Config2
= MIPS_CONFIG2
,
604 .CP0_Config3
= MIPS_CONFIG3
| (1 << CP0C3_LPA
),
605 .CP0_LLAddr_rw_bitmask
= 0,
606 .CP0_LLAddr_shift
= 0,
609 .CP0_Status_rw_bitmask
= 0x37FBFFFF,
610 .CP1_fcr0
= (1 << FCR0_F64
) | (1 << FCR0_3D
) | (1 << FCR0_PS
) |
611 (1 << FCR0_L
) | (1 << FCR0_W
) | (1 << FCR0_D
) |
612 (1 << FCR0_S
) | (0x00 << FCR0_PRID
) | (0x0 << FCR0_REV
),
614 /* The architectural limit is 59, but we have hardcoded 36 bit
616 .PABITS = 59, */ /* the architectural limit */
618 .insn_flags
= CPU_MIPS64R2
| ASE_DSP
| ASE_DSPR2
,
619 .mmu_type
= MMU_TYPE_R4000
,
625 static const mips_def_t
*cpu_mips_find_by_name (const char *name
)
629 for (i
= 0; i
< ARRAY_SIZE(mips_defs
); i
++) {
630 if (strcasecmp(name
, mips_defs
[i
].name
) == 0) {
631 return &mips_defs
[i
];
637 void mips_cpu_list (FILE *f
, fprintf_function cpu_fprintf
)
641 for (i
= 0; i
< ARRAY_SIZE(mips_defs
); i
++) {
642 (*cpu_fprintf
)(f
, "MIPS '%s'\n",
647 #ifndef CONFIG_USER_ONLY
648 static void no_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
650 env
->tlb
->nb_tlb
= 1;
651 env
->tlb
->map_address
= &no_mmu_map_address
;
654 static void fixed_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
656 env
->tlb
->nb_tlb
= 1;
657 env
->tlb
->map_address
= &fixed_mmu_map_address
;
660 static void r4k_mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
662 env
->tlb
->nb_tlb
= 1 + ((def
->CP0_Config1
>> CP0C1_MMU
) & 63);
663 env
->tlb
->map_address
= &r4k_map_address
;
664 env
->tlb
->helper_tlbwi
= r4k_helper_tlbwi
;
665 env
->tlb
->helper_tlbwr
= r4k_helper_tlbwr
;
666 env
->tlb
->helper_tlbp
= r4k_helper_tlbp
;
667 env
->tlb
->helper_tlbr
= r4k_helper_tlbr
;
668 env
->tlb
->helper_tlbinv
= r4k_helper_tlbinv
;
669 env
->tlb
->helper_tlbinvf
= r4k_helper_tlbinvf
;
672 static void mmu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
674 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
676 env
->tlb
= g_malloc0(sizeof(CPUMIPSTLBContext
));
678 switch (def
->mmu_type
) {
680 no_mmu_init(env
, def
);
683 r4k_mmu_init(env
, def
);
686 fixed_mmu_init(env
, def
);
692 cpu_abort(CPU(cpu
), "MMU type not supported\n");
695 #endif /* CONFIG_USER_ONLY */
697 static void fpu_init (CPUMIPSState
*env
, const mips_def_t
*def
)
701 for (i
= 0; i
< MIPS_FPU_MAX
; i
++)
702 env
->fpus
[i
].fcr0
= def
->CP1_fcr0
;
704 memcpy(&env
->active_fpu
, &env
->fpus
[0], sizeof(env
->active_fpu
));
707 static void mvp_init (CPUMIPSState
*env
, const mips_def_t
*def
)
709 env
->mvp
= g_malloc0(sizeof(CPUMIPSMVPContext
));
711 /* MVPConf1 implemented, TLB sharable, no gating storage support,
712 programmable cache partitioning implemented, number of allocatable
713 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
714 implemented, 5 TCs implemented. */
715 env
->mvp
->CP0_MVPConf0
= (1U << CP0MVPC0_M
) | (1 << CP0MVPC0_TLBS
) |
716 (0 << CP0MVPC0_GS
) | (1 << CP0MVPC0_PCP
) |
717 // TODO: actually do 2 VPEs.
718 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
719 // (0x04 << CP0MVPC0_PTC);
720 (1 << CP0MVPC0_TCA
) | (0x0 << CP0MVPC0_PVPE
) |
721 (0x00 << CP0MVPC0_PTC
);
722 #if !defined(CONFIG_USER_ONLY)
723 /* Usermode has no TLB support */
724 env
->mvp
->CP0_MVPConf0
|= (env
->tlb
->nb_tlb
<< CP0MVPC0_PTLBE
);
727 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
728 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
729 env
->mvp
->CP0_MVPConf1
= (1U << CP0MVPC1_CIM
) | (1 << CP0MVPC1_CIF
) |
730 (0x0 << CP0MVPC1_PCX
) | (0x0 << CP0MVPC1_PCP2
) |
731 (0x1 << CP0MVPC1_PCP1
);
734 static void msa_reset(CPUMIPSState
*env
)
736 #ifdef CONFIG_USER_ONLY
737 /* MSA access enabled */
738 env
->CP0_Config5
|= 1 << CP0C5_MSAEn
;
739 env
->CP0_Status
|= (1 << CP0St_CU1
) | (1 << CP0St_FR
);
743 - non-signaling floating point exception mode off (NX bit is 0)
744 - Cause, Enables, and Flags are all 0
745 - round to nearest / ties to even (RM bits are 0) */
746 env
->active_tc
.msacsr
= 0;
748 /* tininess detected after rounding.*/
749 set_float_detect_tininess(float_tininess_after_rounding
,
750 &env
->active_tc
.msa_fp_status
);
752 /* clear float_status exception flags */
753 set_float_exception_flags(0, &env
->active_tc
.msa_fp_status
);
755 /* set float_status rounding mode */
756 set_float_rounding_mode(float_round_nearest_even
,
757 &env
->active_tc
.msa_fp_status
);
759 /* set float_status flush modes */
760 set_flush_to_zero(0, &env
->active_tc
.msa_fp_status
);
761 set_flush_inputs_to_zero(0, &env
->active_tc
.msa_fp_status
);
763 /* clear float_status nan mode */
764 set_default_nan_mode(0, &env
->active_tc
.msa_fp_status
);