2 * TI OMAP processors emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "hw/arm/arm.h"
21 #include "hw/arm/omap.h"
22 #include "sysemu/sysemu.h"
23 #include "hw/arm/soc_dma.h"
24 #include "sysemu/block-backend.h"
25 #include "sysemu/blockdev.h"
26 #include "qemu/range.h"
27 #include "hw/sysbus.h"
29 /* Should signal the TCMI/GPMC */
30 uint32_t omap_badwidth_read8(void *opaque
, hwaddr addr
)
35 cpu_physical_memory_read(addr
, &ret
, 1);
39 void omap_badwidth_write8(void *opaque
, hwaddr addr
,
45 cpu_physical_memory_write(addr
, &val8
, 1);
48 uint32_t omap_badwidth_read16(void *opaque
, hwaddr addr
)
53 cpu_physical_memory_read(addr
, &ret
, 2);
57 void omap_badwidth_write16(void *opaque
, hwaddr addr
,
60 uint16_t val16
= value
;
63 cpu_physical_memory_write(addr
, &val16
, 2);
66 uint32_t omap_badwidth_read32(void *opaque
, hwaddr addr
)
71 cpu_physical_memory_read(addr
, &ret
, 4);
75 void omap_badwidth_write32(void *opaque
, hwaddr addr
,
79 cpu_physical_memory_write(addr
, &value
, 4);
83 struct omap_mpu_timer_s
{
101 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s
*timer
)
103 uint64_t distance
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->time
;
105 if (timer
->st
&& timer
->enable
&& timer
->rate
)
106 return timer
->val
- muldiv64(distance
>> (timer
->ptv
+ 1),
107 timer
->rate
, get_ticks_per_sec());
112 static inline void omap_timer_sync(struct omap_mpu_timer_s
*timer
)
114 timer
->val
= omap_timer_read(timer
);
115 timer
->time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
118 static inline void omap_timer_update(struct omap_mpu_timer_s
*timer
)
122 if (timer
->enable
&& timer
->st
&& timer
->rate
) {
123 timer
->val
= timer
->reset_val
; /* Should skip this on clk enable */
124 expires
= muldiv64((uint64_t) timer
->val
<< (timer
->ptv
+ 1),
125 get_ticks_per_sec(), timer
->rate
);
127 /* If timer expiry would be sooner than in about 1 ms and
128 * auto-reload isn't set, then fire immediately. This is a hack
129 * to make systems like PalmOS run in acceptable time. PalmOS
130 * sets the interval to a very low value and polls the status bit
131 * in a busy loop when it wants to sleep just a couple of CPU
133 if (expires
> (get_ticks_per_sec() >> 10) || timer
->ar
)
134 timer_mod(timer
->timer
, timer
->time
+ expires
);
136 qemu_bh_schedule(timer
->tick
);
138 timer_del(timer
->timer
);
141 static void omap_timer_fire(void *opaque
)
143 struct omap_mpu_timer_s
*timer
= opaque
;
151 /* Edge-triggered irq */
152 qemu_irq_pulse(timer
->irq
);
155 static void omap_timer_tick(void *opaque
)
157 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
159 omap_timer_sync(timer
);
160 omap_timer_fire(timer
);
161 omap_timer_update(timer
);
164 static void omap_timer_clk_update(void *opaque
, int line
, int on
)
166 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
168 omap_timer_sync(timer
);
169 timer
->rate
= on
? omap_clk_getrate(timer
->clk
) : 0;
170 omap_timer_update(timer
);
173 static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer
)
175 omap_clk_adduser(timer
->clk
,
176 qemu_allocate_irq(omap_timer_clk_update
, timer
, 0));
177 timer
->rate
= omap_clk_getrate(timer
->clk
);
180 static uint64_t omap_mpu_timer_read(void *opaque
, hwaddr addr
,
183 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
186 return omap_badwidth_read32(opaque
, addr
);
190 case 0x00: /* CNTL_TIMER */
191 return (s
->enable
<< 5) | (s
->ptv
<< 2) | (s
->ar
<< 1) | s
->st
;
193 case 0x04: /* LOAD_TIM */
196 case 0x08: /* READ_TIM */
197 return omap_timer_read(s
);
204 static void omap_mpu_timer_write(void *opaque
, hwaddr addr
,
205 uint64_t value
, unsigned size
)
207 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
210 return omap_badwidth_write32(opaque
, addr
, value
);
214 case 0x00: /* CNTL_TIMER */
216 s
->enable
= (value
>> 5) & 1;
217 s
->ptv
= (value
>> 2) & 7;
218 s
->ar
= (value
>> 1) & 1;
220 omap_timer_update(s
);
223 case 0x04: /* LOAD_TIM */
224 s
->reset_val
= value
;
227 case 0x08: /* READ_TIM */
236 static const MemoryRegionOps omap_mpu_timer_ops
= {
237 .read
= omap_mpu_timer_read
,
238 .write
= omap_mpu_timer_write
,
239 .endianness
= DEVICE_LITTLE_ENDIAN
,
242 static void omap_mpu_timer_reset(struct omap_mpu_timer_s
*s
)
246 s
->reset_val
= 31337;
254 static struct omap_mpu_timer_s
*omap_mpu_timer_init(MemoryRegion
*system_memory
,
256 qemu_irq irq
, omap_clk clk
)
258 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*)
259 g_malloc0(sizeof(struct omap_mpu_timer_s
));
263 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, s
);
264 s
->tick
= qemu_bh_new(omap_timer_fire
, s
);
265 omap_mpu_timer_reset(s
);
266 omap_timer_clk_setup(s
);
268 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpu_timer_ops
, s
,
269 "omap-mpu-timer", 0x100);
271 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
277 struct omap_watchdog_timer_s
{
278 struct omap_mpu_timer_s timer
;
286 static uint64_t omap_wd_timer_read(void *opaque
, hwaddr addr
,
289 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
292 return omap_badwidth_read16(opaque
, addr
);
296 case 0x00: /* CNTL_TIMER */
297 return (s
->timer
.ptv
<< 9) | (s
->timer
.ar
<< 8) |
298 (s
->timer
.st
<< 7) | (s
->free
<< 1);
300 case 0x04: /* READ_TIMER */
301 return omap_timer_read(&s
->timer
);
303 case 0x08: /* TIMER_MODE */
304 return s
->mode
<< 15;
311 static void omap_wd_timer_write(void *opaque
, hwaddr addr
,
312 uint64_t value
, unsigned size
)
314 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
317 return omap_badwidth_write16(opaque
, addr
, value
);
321 case 0x00: /* CNTL_TIMER */
322 omap_timer_sync(&s
->timer
);
323 s
->timer
.ptv
= (value
>> 9) & 7;
324 s
->timer
.ar
= (value
>> 8) & 1;
325 s
->timer
.st
= (value
>> 7) & 1;
326 s
->free
= (value
>> 1) & 1;
327 omap_timer_update(&s
->timer
);
330 case 0x04: /* LOAD_TIMER */
331 s
->timer
.reset_val
= value
& 0xffff;
334 case 0x08: /* TIMER_MODE */
335 if (!s
->mode
&& ((value
>> 15) & 1))
336 omap_clk_get(s
->timer
.clk
);
337 s
->mode
|= (value
>> 15) & 1;
338 if (s
->last_wr
== 0xf5) {
339 if ((value
& 0xff) == 0xa0) {
342 omap_clk_put(s
->timer
.clk
);
345 /* XXX: on T|E hardware somehow this has no effect,
346 * on Zire 71 it works as specified. */
348 qemu_system_reset_request();
351 s
->last_wr
= value
& 0xff;
359 static const MemoryRegionOps omap_wd_timer_ops
= {
360 .read
= omap_wd_timer_read
,
361 .write
= omap_wd_timer_write
,
362 .endianness
= DEVICE_NATIVE_ENDIAN
,
365 static void omap_wd_timer_reset(struct omap_watchdog_timer_s
*s
)
367 timer_del(s
->timer
.timer
);
369 omap_clk_get(s
->timer
.clk
);
375 s
->timer
.reset_val
= 0xffff;
380 omap_timer_update(&s
->timer
);
383 static struct omap_watchdog_timer_s
*omap_wd_timer_init(MemoryRegion
*memory
,
385 qemu_irq irq
, omap_clk clk
)
387 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*)
388 g_malloc0(sizeof(struct omap_watchdog_timer_s
));
392 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
393 omap_wd_timer_reset(s
);
394 omap_timer_clk_setup(&s
->timer
);
396 memory_region_init_io(&s
->iomem
, NULL
, &omap_wd_timer_ops
, s
,
397 "omap-wd-timer", 0x100);
398 memory_region_add_subregion(memory
, base
, &s
->iomem
);
404 struct omap_32khz_timer_s
{
405 struct omap_mpu_timer_s timer
;
409 static uint64_t omap_os_timer_read(void *opaque
, hwaddr addr
,
412 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
413 int offset
= addr
& OMAP_MPUI_REG_MASK
;
416 return omap_badwidth_read32(opaque
, addr
);
421 return s
->timer
.reset_val
;
424 return omap_timer_read(&s
->timer
);
427 return (s
->timer
.ar
<< 3) | (s
->timer
.it_ena
<< 2) | s
->timer
.st
;
436 static void omap_os_timer_write(void *opaque
, hwaddr addr
,
437 uint64_t value
, unsigned size
)
439 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
440 int offset
= addr
& OMAP_MPUI_REG_MASK
;
443 return omap_badwidth_write32(opaque
, addr
, value
);
448 s
->timer
.reset_val
= value
& 0x00ffffff;
456 s
->timer
.ar
= (value
>> 3) & 1;
457 s
->timer
.it_ena
= (value
>> 2) & 1;
458 if (s
->timer
.st
!= (value
& 1) || (value
& 2)) {
459 omap_timer_sync(&s
->timer
);
460 s
->timer
.enable
= value
& 1;
461 s
->timer
.st
= value
& 1;
462 omap_timer_update(&s
->timer
);
471 static const MemoryRegionOps omap_os_timer_ops
= {
472 .read
= omap_os_timer_read
,
473 .write
= omap_os_timer_write
,
474 .endianness
= DEVICE_NATIVE_ENDIAN
,
477 static void omap_os_timer_reset(struct omap_32khz_timer_s
*s
)
479 timer_del(s
->timer
.timer
);
482 s
->timer
.reset_val
= 0x00ffffff;
489 static struct omap_32khz_timer_s
*omap_os_timer_init(MemoryRegion
*memory
,
491 qemu_irq irq
, omap_clk clk
)
493 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*)
494 g_malloc0(sizeof(struct omap_32khz_timer_s
));
498 s
->timer
.timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_timer_tick
, &s
->timer
);
499 omap_os_timer_reset(s
);
500 omap_timer_clk_setup(&s
->timer
);
502 memory_region_init_io(&s
->iomem
, NULL
, &omap_os_timer_ops
, s
,
503 "omap-os-timer", 0x800);
504 memory_region_add_subregion(memory
, base
, &s
->iomem
);
509 /* Ultra Low-Power Device Module */
510 static uint64_t omap_ulpd_pm_read(void *opaque
, hwaddr addr
,
513 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
517 return omap_badwidth_read16(opaque
, addr
);
521 case 0x14: /* IT_STATUS */
522 ret
= s
->ulpd_pm_regs
[addr
>> 2];
523 s
->ulpd_pm_regs
[addr
>> 2] = 0;
524 qemu_irq_lower(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
527 case 0x18: /* Reserved */
528 case 0x1c: /* Reserved */
529 case 0x20: /* Reserved */
530 case 0x28: /* Reserved */
531 case 0x2c: /* Reserved */
534 case 0x00: /* COUNTER_32_LSB */
535 case 0x04: /* COUNTER_32_MSB */
536 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
537 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
538 case 0x10: /* GAUGING_CTRL */
539 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
540 case 0x30: /* CLOCK_CTRL */
541 case 0x34: /* SOFT_REQ */
542 case 0x38: /* COUNTER_32_FIQ */
543 case 0x3c: /* DPLL_CTRL */
544 case 0x40: /* STATUS_REQ */
545 /* XXX: check clk::usecount state for every clock */
546 case 0x48: /* LOCL_TIME */
547 case 0x4c: /* APLL_CTRL */
548 case 0x50: /* POWER_CTRL */
549 return s
->ulpd_pm_regs
[addr
>> 2];
556 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s
*s
,
557 uint16_t diff
, uint16_t value
)
559 if (diff
& (1 << 4)) /* USB_MCLK_EN */
560 omap_clk_onoff(omap_findclk(s
, "usb_clk0"), (value
>> 4) & 1);
561 if (diff
& (1 << 5)) /* DIS_USB_PVCI_CLK */
562 omap_clk_onoff(omap_findclk(s
, "usb_w2fc_ck"), (~value
>> 5) & 1);
565 static inline void omap_ulpd_req_update(struct omap_mpu_state_s
*s
,
566 uint16_t diff
, uint16_t value
)
568 if (diff
& (1 << 0)) /* SOFT_DPLL_REQ */
569 omap_clk_canidle(omap_findclk(s
, "dpll4"), (~value
>> 0) & 1);
570 if (diff
& (1 << 1)) /* SOFT_COM_REQ */
571 omap_clk_canidle(omap_findclk(s
, "com_mclk_out"), (~value
>> 1) & 1);
572 if (diff
& (1 << 2)) /* SOFT_SDW_REQ */
573 omap_clk_canidle(omap_findclk(s
, "bt_mclk_out"), (~value
>> 2) & 1);
574 if (diff
& (1 << 3)) /* SOFT_USB_REQ */
575 omap_clk_canidle(omap_findclk(s
, "usb_clk0"), (~value
>> 3) & 1);
578 static void omap_ulpd_pm_write(void *opaque
, hwaddr addr
,
579 uint64_t value
, unsigned size
)
581 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
584 static const int bypass_div
[4] = { 1, 2, 4, 4 };
588 return omap_badwidth_write16(opaque
, addr
, value
);
592 case 0x00: /* COUNTER_32_LSB */
593 case 0x04: /* COUNTER_32_MSB */
594 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
595 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
596 case 0x14: /* IT_STATUS */
597 case 0x40: /* STATUS_REQ */
601 case 0x10: /* GAUGING_CTRL */
602 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
603 if ((s
->ulpd_pm_regs
[addr
>> 2] ^ value
) & 1) {
604 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
607 s
->ulpd_gauge_start
= now
;
609 now
-= s
->ulpd_gauge_start
;
612 ticks
= muldiv64(now
, 32768, get_ticks_per_sec());
613 s
->ulpd_pm_regs
[0x00 >> 2] = (ticks
>> 0) & 0xffff;
614 s
->ulpd_pm_regs
[0x04 >> 2] = (ticks
>> 16) & 0xffff;
615 if (ticks
>> 32) /* OVERFLOW_32K */
616 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 2;
618 /* High frequency ticks */
619 ticks
= muldiv64(now
, 12000000, get_ticks_per_sec());
620 s
->ulpd_pm_regs
[0x08 >> 2] = (ticks
>> 0) & 0xffff;
621 s
->ulpd_pm_regs
[0x0c >> 2] = (ticks
>> 16) & 0xffff;
622 if (ticks
>> 32) /* OVERFLOW_HI_FREQ */
623 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 1;
625 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
626 qemu_irq_raise(qdev_get_gpio_in(s
->ih
[1], OMAP_INT_GAUGE_32K
));
629 s
->ulpd_pm_regs
[addr
>> 2] = value
;
632 case 0x18: /* Reserved */
633 case 0x1c: /* Reserved */
634 case 0x20: /* Reserved */
635 case 0x28: /* Reserved */
636 case 0x2c: /* Reserved */
639 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
640 case 0x38: /* COUNTER_32_FIQ */
641 case 0x48: /* LOCL_TIME */
642 case 0x50: /* POWER_CTRL */
643 s
->ulpd_pm_regs
[addr
>> 2] = value
;
646 case 0x30: /* CLOCK_CTRL */
647 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
648 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x3f;
649 omap_ulpd_clk_update(s
, diff
, value
);
652 case 0x34: /* SOFT_REQ */
653 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
654 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x1f;
655 omap_ulpd_req_update(s
, diff
, value
);
658 case 0x3c: /* DPLL_CTRL */
659 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
660 * omitted altogether, probably a typo. */
661 /* This register has identical semantics with DPLL(1:3) control
662 * registers, see omap_dpll_write() */
663 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
664 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x2fff;
665 if (diff
& (0x3ff << 2)) {
666 if (value
& (1 << 4)) { /* PLL_ENABLE */
667 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
668 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
670 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
673 omap_clk_setrate(omap_findclk(s
, "dpll4"), div
, mult
);
676 /* Enter the desired mode. */
677 s
->ulpd_pm_regs
[addr
>> 2] =
678 (s
->ulpd_pm_regs
[addr
>> 2] & 0xfffe) |
679 ((s
->ulpd_pm_regs
[addr
>> 2] >> 4) & 1);
681 /* Act as if the lock is restored. */
682 s
->ulpd_pm_regs
[addr
>> 2] |= 2;
685 case 0x4c: /* APLL_CTRL */
686 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
687 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0xf;
688 if (diff
& (1 << 0)) /* APLL_NDPLL_SWITCH */
689 omap_clk_reparent(omap_findclk(s
, "ck_48m"), omap_findclk(s
,
690 (value
& (1 << 0)) ? "apll" : "dpll4"));
698 static const MemoryRegionOps omap_ulpd_pm_ops
= {
699 .read
= omap_ulpd_pm_read
,
700 .write
= omap_ulpd_pm_write
,
701 .endianness
= DEVICE_NATIVE_ENDIAN
,
704 static void omap_ulpd_pm_reset(struct omap_mpu_state_s
*mpu
)
706 mpu
->ulpd_pm_regs
[0x00 >> 2] = 0x0001;
707 mpu
->ulpd_pm_regs
[0x04 >> 2] = 0x0000;
708 mpu
->ulpd_pm_regs
[0x08 >> 2] = 0x0001;
709 mpu
->ulpd_pm_regs
[0x0c >> 2] = 0x0000;
710 mpu
->ulpd_pm_regs
[0x10 >> 2] = 0x0000;
711 mpu
->ulpd_pm_regs
[0x18 >> 2] = 0x01;
712 mpu
->ulpd_pm_regs
[0x1c >> 2] = 0x01;
713 mpu
->ulpd_pm_regs
[0x20 >> 2] = 0x01;
714 mpu
->ulpd_pm_regs
[0x24 >> 2] = 0x03ff;
715 mpu
->ulpd_pm_regs
[0x28 >> 2] = 0x01;
716 mpu
->ulpd_pm_regs
[0x2c >> 2] = 0x01;
717 omap_ulpd_clk_update(mpu
, mpu
->ulpd_pm_regs
[0x30 >> 2], 0x0000);
718 mpu
->ulpd_pm_regs
[0x30 >> 2] = 0x0000;
719 omap_ulpd_req_update(mpu
, mpu
->ulpd_pm_regs
[0x34 >> 2], 0x0000);
720 mpu
->ulpd_pm_regs
[0x34 >> 2] = 0x0000;
721 mpu
->ulpd_pm_regs
[0x38 >> 2] = 0x0001;
722 mpu
->ulpd_pm_regs
[0x3c >> 2] = 0x2211;
723 mpu
->ulpd_pm_regs
[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
724 mpu
->ulpd_pm_regs
[0x48 >> 2] = 0x960;
725 mpu
->ulpd_pm_regs
[0x4c >> 2] = 0x08;
726 mpu
->ulpd_pm_regs
[0x50 >> 2] = 0x08;
727 omap_clk_setrate(omap_findclk(mpu
, "dpll4"), 1, 4);
728 omap_clk_reparent(omap_findclk(mpu
, "ck_48m"), omap_findclk(mpu
, "dpll4"));
731 static void omap_ulpd_pm_init(MemoryRegion
*system_memory
,
733 struct omap_mpu_state_s
*mpu
)
735 memory_region_init_io(&mpu
->ulpd_pm_iomem
, NULL
, &omap_ulpd_pm_ops
, mpu
,
736 "omap-ulpd-pm", 0x800);
737 memory_region_add_subregion(system_memory
, base
, &mpu
->ulpd_pm_iomem
);
738 omap_ulpd_pm_reset(mpu
);
741 /* OMAP Pin Configuration */
742 static uint64_t omap_pin_cfg_read(void *opaque
, hwaddr addr
,
745 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
748 return omap_badwidth_read32(opaque
, addr
);
752 case 0x00: /* FUNC_MUX_CTRL_0 */
753 case 0x04: /* FUNC_MUX_CTRL_1 */
754 case 0x08: /* FUNC_MUX_CTRL_2 */
755 return s
->func_mux_ctrl
[addr
>> 2];
757 case 0x0c: /* COMP_MODE_CTRL_0 */
758 return s
->comp_mode_ctrl
[0];
760 case 0x10: /* FUNC_MUX_CTRL_3 */
761 case 0x14: /* FUNC_MUX_CTRL_4 */
762 case 0x18: /* FUNC_MUX_CTRL_5 */
763 case 0x1c: /* FUNC_MUX_CTRL_6 */
764 case 0x20: /* FUNC_MUX_CTRL_7 */
765 case 0x24: /* FUNC_MUX_CTRL_8 */
766 case 0x28: /* FUNC_MUX_CTRL_9 */
767 case 0x2c: /* FUNC_MUX_CTRL_A */
768 case 0x30: /* FUNC_MUX_CTRL_B */
769 case 0x34: /* FUNC_MUX_CTRL_C */
770 case 0x38: /* FUNC_MUX_CTRL_D */
771 return s
->func_mux_ctrl
[(addr
>> 2) - 1];
773 case 0x40: /* PULL_DWN_CTRL_0 */
774 case 0x44: /* PULL_DWN_CTRL_1 */
775 case 0x48: /* PULL_DWN_CTRL_2 */
776 case 0x4c: /* PULL_DWN_CTRL_3 */
777 return s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2];
779 case 0x50: /* GATE_INH_CTRL_0 */
780 return s
->gate_inh_ctrl
[0];
782 case 0x60: /* VOLTAGE_CTRL_0 */
783 return s
->voltage_ctrl
[0];
785 case 0x70: /* TEST_DBG_CTRL_0 */
786 return s
->test_dbg_ctrl
[0];
788 case 0x80: /* MOD_CONF_CTRL_0 */
789 return s
->mod_conf_ctrl
[0];
796 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s
*s
,
797 uint32_t diff
, uint32_t value
)
800 if (diff
& (1 << 9)) /* BLUETOOTH */
801 omap_clk_onoff(omap_findclk(s
, "bt_mclk_out"),
803 if (diff
& (1 << 7)) /* USB.CLKO */
804 omap_clk_onoff(omap_findclk(s
, "usb.clko"),
809 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s
*s
,
810 uint32_t diff
, uint32_t value
)
813 if (diff
& (1U << 31)) {
814 /* MCBSP3_CLK_HIZ_DI */
815 omap_clk_onoff(omap_findclk(s
, "mcbsp3.clkx"), (value
>> 31) & 1);
817 if (diff
& (1 << 1)) {
819 omap_clk_onoff(omap_findclk(s
, "clk32k_out"), (~value
>> 1) & 1);
824 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s
*s
,
825 uint32_t diff
, uint32_t value
)
827 if (diff
& (1U << 31)) {
828 /* CONF_MOD_UART3_CLK_MODE_R */
829 omap_clk_reparent(omap_findclk(s
, "uart3_ck"),
830 omap_findclk(s
, ((value
>> 31) & 1) ?
831 "ck_48m" : "armper_ck"));
833 if (diff
& (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
834 omap_clk_reparent(omap_findclk(s
, "uart2_ck"),
835 omap_findclk(s
, ((value
>> 30) & 1) ?
836 "ck_48m" : "armper_ck"));
837 if (diff
& (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
838 omap_clk_reparent(omap_findclk(s
, "uart1_ck"),
839 omap_findclk(s
, ((value
>> 29) & 1) ?
840 "ck_48m" : "armper_ck"));
841 if (diff
& (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
842 omap_clk_reparent(omap_findclk(s
, "mmc_ck"),
843 omap_findclk(s
, ((value
>> 23) & 1) ?
844 "ck_48m" : "armper_ck"));
845 if (diff
& (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
846 omap_clk_reparent(omap_findclk(s
, "com_mclk_out"),
847 omap_findclk(s
, ((value
>> 12) & 1) ?
848 "ck_48m" : "armper_ck"));
849 if (diff
& (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
850 omap_clk_onoff(omap_findclk(s
, "usb_hhc_ck"), (value
>> 9) & 1);
853 static void omap_pin_cfg_write(void *opaque
, hwaddr addr
,
854 uint64_t value
, unsigned size
)
856 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
860 return omap_badwidth_write32(opaque
, addr
, value
);
864 case 0x00: /* FUNC_MUX_CTRL_0 */
865 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
866 s
->func_mux_ctrl
[addr
>> 2] = value
;
867 omap_pin_funcmux0_update(s
, diff
, value
);
870 case 0x04: /* FUNC_MUX_CTRL_1 */
871 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
872 s
->func_mux_ctrl
[addr
>> 2] = value
;
873 omap_pin_funcmux1_update(s
, diff
, value
);
876 case 0x08: /* FUNC_MUX_CTRL_2 */
877 s
->func_mux_ctrl
[addr
>> 2] = value
;
880 case 0x0c: /* COMP_MODE_CTRL_0 */
881 s
->comp_mode_ctrl
[0] = value
;
882 s
->compat1509
= (value
!= 0x0000eaef);
883 omap_pin_funcmux0_update(s
, ~0, s
->func_mux_ctrl
[0]);
884 omap_pin_funcmux1_update(s
, ~0, s
->func_mux_ctrl
[1]);
887 case 0x10: /* FUNC_MUX_CTRL_3 */
888 case 0x14: /* FUNC_MUX_CTRL_4 */
889 case 0x18: /* FUNC_MUX_CTRL_5 */
890 case 0x1c: /* FUNC_MUX_CTRL_6 */
891 case 0x20: /* FUNC_MUX_CTRL_7 */
892 case 0x24: /* FUNC_MUX_CTRL_8 */
893 case 0x28: /* FUNC_MUX_CTRL_9 */
894 case 0x2c: /* FUNC_MUX_CTRL_A */
895 case 0x30: /* FUNC_MUX_CTRL_B */
896 case 0x34: /* FUNC_MUX_CTRL_C */
897 case 0x38: /* FUNC_MUX_CTRL_D */
898 s
->func_mux_ctrl
[(addr
>> 2) - 1] = value
;
901 case 0x40: /* PULL_DWN_CTRL_0 */
902 case 0x44: /* PULL_DWN_CTRL_1 */
903 case 0x48: /* PULL_DWN_CTRL_2 */
904 case 0x4c: /* PULL_DWN_CTRL_3 */
905 s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2] = value
;
908 case 0x50: /* GATE_INH_CTRL_0 */
909 s
->gate_inh_ctrl
[0] = value
;
912 case 0x60: /* VOLTAGE_CTRL_0 */
913 s
->voltage_ctrl
[0] = value
;
916 case 0x70: /* TEST_DBG_CTRL_0 */
917 s
->test_dbg_ctrl
[0] = value
;
920 case 0x80: /* MOD_CONF_CTRL_0 */
921 diff
= s
->mod_conf_ctrl
[0] ^ value
;
922 s
->mod_conf_ctrl
[0] = value
;
923 omap_pin_modconf1_update(s
, diff
, value
);
931 static const MemoryRegionOps omap_pin_cfg_ops
= {
932 .read
= omap_pin_cfg_read
,
933 .write
= omap_pin_cfg_write
,
934 .endianness
= DEVICE_NATIVE_ENDIAN
,
937 static void omap_pin_cfg_reset(struct omap_mpu_state_s
*mpu
)
939 /* Start in Compatibility Mode. */
941 omap_pin_funcmux0_update(mpu
, mpu
->func_mux_ctrl
[0], 0);
942 omap_pin_funcmux1_update(mpu
, mpu
->func_mux_ctrl
[1], 0);
943 omap_pin_modconf1_update(mpu
, mpu
->mod_conf_ctrl
[0], 0);
944 memset(mpu
->func_mux_ctrl
, 0, sizeof(mpu
->func_mux_ctrl
));
945 memset(mpu
->comp_mode_ctrl
, 0, sizeof(mpu
->comp_mode_ctrl
));
946 memset(mpu
->pull_dwn_ctrl
, 0, sizeof(mpu
->pull_dwn_ctrl
));
947 memset(mpu
->gate_inh_ctrl
, 0, sizeof(mpu
->gate_inh_ctrl
));
948 memset(mpu
->voltage_ctrl
, 0, sizeof(mpu
->voltage_ctrl
));
949 memset(mpu
->test_dbg_ctrl
, 0, sizeof(mpu
->test_dbg_ctrl
));
950 memset(mpu
->mod_conf_ctrl
, 0, sizeof(mpu
->mod_conf_ctrl
));
953 static void omap_pin_cfg_init(MemoryRegion
*system_memory
,
955 struct omap_mpu_state_s
*mpu
)
957 memory_region_init_io(&mpu
->pin_cfg_iomem
, NULL
, &omap_pin_cfg_ops
, mpu
,
958 "omap-pin-cfg", 0x800);
959 memory_region_add_subregion(system_memory
, base
, &mpu
->pin_cfg_iomem
);
960 omap_pin_cfg_reset(mpu
);
963 /* Device Identification, Die Identification */
964 static uint64_t omap_id_read(void *opaque
, hwaddr addr
,
967 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
970 return omap_badwidth_read32(opaque
, addr
);
974 case 0xfffe1800: /* DIE_ID_LSB */
976 case 0xfffe1804: /* DIE_ID_MSB */
979 case 0xfffe2000: /* PRODUCT_ID_LSB */
981 case 0xfffe2004: /* PRODUCT_ID_MSB */
984 case 0xfffed400: /* JTAG_ID_LSB */
985 switch (s
->mpu_model
) {
991 hw_error("%s: bad mpu model\n", __FUNCTION__
);
995 case 0xfffed404: /* JTAG_ID_MSB */
996 switch (s
->mpu_model
) {
1002 hw_error("%s: bad mpu model\n", __FUNCTION__
);
1011 static void omap_id_write(void *opaque
, hwaddr addr
,
1012 uint64_t value
, unsigned size
)
1015 return omap_badwidth_write32(opaque
, addr
, value
);
1021 static const MemoryRegionOps omap_id_ops
= {
1022 .read
= omap_id_read
,
1023 .write
= omap_id_write
,
1024 .endianness
= DEVICE_NATIVE_ENDIAN
,
1027 static void omap_id_init(MemoryRegion
*memory
, struct omap_mpu_state_s
*mpu
)
1029 memory_region_init_io(&mpu
->id_iomem
, NULL
, &omap_id_ops
, mpu
,
1030 "omap-id", 0x100000000ULL
);
1031 memory_region_init_alias(&mpu
->id_iomem_e18
, NULL
, "omap-id-e18", &mpu
->id_iomem
,
1033 memory_region_add_subregion(memory
, 0xfffe1800, &mpu
->id_iomem_e18
);
1034 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-ed4", &mpu
->id_iomem
,
1036 memory_region_add_subregion(memory
, 0xfffed400, &mpu
->id_iomem_ed4
);
1037 if (!cpu_is_omap15xx(mpu
)) {
1038 memory_region_init_alias(&mpu
->id_iomem_ed4
, NULL
, "omap-id-e20",
1039 &mpu
->id_iomem
, 0xfffe2000, 0x800);
1040 memory_region_add_subregion(memory
, 0xfffe2000, &mpu
->id_iomem_e20
);
1044 /* MPUI Control (Dummy) */
1045 static uint64_t omap_mpui_read(void *opaque
, hwaddr addr
,
1048 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1051 return omap_badwidth_read32(opaque
, addr
);
1055 case 0x00: /* CTRL */
1056 return s
->mpui_ctrl
;
1057 case 0x04: /* DEBUG_ADDR */
1059 case 0x08: /* DEBUG_DATA */
1061 case 0x0c: /* DEBUG_FLAG */
1063 case 0x10: /* STATUS */
1066 /* Not in OMAP310 */
1067 case 0x14: /* DSP_STATUS */
1068 case 0x18: /* DSP_BOOT_CONFIG */
1070 case 0x1c: /* DSP_MPUI_CONFIG */
1078 static void omap_mpui_write(void *opaque
, hwaddr addr
,
1079 uint64_t value
, unsigned size
)
1081 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1084 return omap_badwidth_write32(opaque
, addr
, value
);
1088 case 0x00: /* CTRL */
1089 s
->mpui_ctrl
= value
& 0x007fffff;
1092 case 0x04: /* DEBUG_ADDR */
1093 case 0x08: /* DEBUG_DATA */
1094 case 0x0c: /* DEBUG_FLAG */
1095 case 0x10: /* STATUS */
1096 /* Not in OMAP310 */
1097 case 0x14: /* DSP_STATUS */
1100 case 0x18: /* DSP_BOOT_CONFIG */
1101 case 0x1c: /* DSP_MPUI_CONFIG */
1109 static const MemoryRegionOps omap_mpui_ops
= {
1110 .read
= omap_mpui_read
,
1111 .write
= omap_mpui_write
,
1112 .endianness
= DEVICE_NATIVE_ENDIAN
,
1115 static void omap_mpui_reset(struct omap_mpu_state_s
*s
)
1117 s
->mpui_ctrl
= 0x0003ff1b;
1120 static void omap_mpui_init(MemoryRegion
*memory
, hwaddr base
,
1121 struct omap_mpu_state_s
*mpu
)
1123 memory_region_init_io(&mpu
->mpui_iomem
, NULL
, &omap_mpui_ops
, mpu
,
1124 "omap-mpui", 0x100);
1125 memory_region_add_subregion(memory
, base
, &mpu
->mpui_iomem
);
1127 omap_mpui_reset(mpu
);
1131 struct omap_tipb_bridge_s
{
1139 uint16_t enh_control
;
1142 static uint64_t omap_tipb_bridge_read(void *opaque
, hwaddr addr
,
1145 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1148 return omap_badwidth_read16(opaque
, addr
);
1152 case 0x00: /* TIPB_CNTL */
1154 case 0x04: /* TIPB_BUS_ALLOC */
1156 case 0x08: /* MPU_TIPB_CNTL */
1158 case 0x0c: /* ENHANCED_TIPB_CNTL */
1159 return s
->enh_control
;
1160 case 0x10: /* ADDRESS_DBG */
1161 case 0x14: /* DATA_DEBUG_LOW */
1162 case 0x18: /* DATA_DEBUG_HIGH */
1164 case 0x1c: /* DEBUG_CNTR_SIG */
1172 static void omap_tipb_bridge_write(void *opaque
, hwaddr addr
,
1173 uint64_t value
, unsigned size
)
1175 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1178 return omap_badwidth_write16(opaque
, addr
, value
);
1182 case 0x00: /* TIPB_CNTL */
1183 s
->control
= value
& 0xffff;
1186 case 0x04: /* TIPB_BUS_ALLOC */
1187 s
->alloc
= value
& 0x003f;
1190 case 0x08: /* MPU_TIPB_CNTL */
1191 s
->buffer
= value
& 0x0003;
1194 case 0x0c: /* ENHANCED_TIPB_CNTL */
1195 s
->width_intr
= !(value
& 2);
1196 s
->enh_control
= value
& 0x000f;
1199 case 0x10: /* ADDRESS_DBG */
1200 case 0x14: /* DATA_DEBUG_LOW */
1201 case 0x18: /* DATA_DEBUG_HIGH */
1202 case 0x1c: /* DEBUG_CNTR_SIG */
1211 static const MemoryRegionOps omap_tipb_bridge_ops
= {
1212 .read
= omap_tipb_bridge_read
,
1213 .write
= omap_tipb_bridge_write
,
1214 .endianness
= DEVICE_NATIVE_ENDIAN
,
1217 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s
*s
)
1219 s
->control
= 0xffff;
1222 s
->enh_control
= 0x000f;
1225 static struct omap_tipb_bridge_s
*omap_tipb_bridge_init(
1226 MemoryRegion
*memory
, hwaddr base
,
1227 qemu_irq abort_irq
, omap_clk clk
)
1229 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*)
1230 g_malloc0(sizeof(struct omap_tipb_bridge_s
));
1232 s
->abort
= abort_irq
;
1233 omap_tipb_bridge_reset(s
);
1235 memory_region_init_io(&s
->iomem
, NULL
, &omap_tipb_bridge_ops
, s
,
1236 "omap-tipb-bridge", 0x100);
1237 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1242 /* Dummy Traffic Controller's Memory Interface */
1243 static uint64_t omap_tcmi_read(void *opaque
, hwaddr addr
,
1246 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1250 return omap_badwidth_read32(opaque
, addr
);
1254 case 0x00: /* IMIF_PRIO */
1255 case 0x04: /* EMIFS_PRIO */
1256 case 0x08: /* EMIFF_PRIO */
1257 case 0x0c: /* EMIFS_CONFIG */
1258 case 0x10: /* EMIFS_CS0_CONFIG */
1259 case 0x14: /* EMIFS_CS1_CONFIG */
1260 case 0x18: /* EMIFS_CS2_CONFIG */
1261 case 0x1c: /* EMIFS_CS3_CONFIG */
1262 case 0x24: /* EMIFF_MRS */
1263 case 0x28: /* TIMEOUT1 */
1264 case 0x2c: /* TIMEOUT2 */
1265 case 0x30: /* TIMEOUT3 */
1266 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1267 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1268 return s
->tcmi_regs
[addr
>> 2];
1270 case 0x20: /* EMIFF_SDRAM_CONFIG */
1271 ret
= s
->tcmi_regs
[addr
>> 2];
1272 s
->tcmi_regs
[addr
>> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1273 /* XXX: We can try using the VGA_DIRTY flag for this */
1281 static void omap_tcmi_write(void *opaque
, hwaddr addr
,
1282 uint64_t value
, unsigned size
)
1284 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1287 return omap_badwidth_write32(opaque
, addr
, value
);
1291 case 0x00: /* IMIF_PRIO */
1292 case 0x04: /* EMIFS_PRIO */
1293 case 0x08: /* EMIFF_PRIO */
1294 case 0x10: /* EMIFS_CS0_CONFIG */
1295 case 0x14: /* EMIFS_CS1_CONFIG */
1296 case 0x18: /* EMIFS_CS2_CONFIG */
1297 case 0x1c: /* EMIFS_CS3_CONFIG */
1298 case 0x20: /* EMIFF_SDRAM_CONFIG */
1299 case 0x24: /* EMIFF_MRS */
1300 case 0x28: /* TIMEOUT1 */
1301 case 0x2c: /* TIMEOUT2 */
1302 case 0x30: /* TIMEOUT3 */
1303 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1304 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1305 s
->tcmi_regs
[addr
>> 2] = value
;
1307 case 0x0c: /* EMIFS_CONFIG */
1308 s
->tcmi_regs
[addr
>> 2] = (value
& 0xf) | (1 << 4);
1316 static const MemoryRegionOps omap_tcmi_ops
= {
1317 .read
= omap_tcmi_read
,
1318 .write
= omap_tcmi_write
,
1319 .endianness
= DEVICE_NATIVE_ENDIAN
,
1322 static void omap_tcmi_reset(struct omap_mpu_state_s
*mpu
)
1324 mpu
->tcmi_regs
[0x00 >> 2] = 0x00000000;
1325 mpu
->tcmi_regs
[0x04 >> 2] = 0x00000000;
1326 mpu
->tcmi_regs
[0x08 >> 2] = 0x00000000;
1327 mpu
->tcmi_regs
[0x0c >> 2] = 0x00000010;
1328 mpu
->tcmi_regs
[0x10 >> 2] = 0x0010fffb;
1329 mpu
->tcmi_regs
[0x14 >> 2] = 0x0010fffb;
1330 mpu
->tcmi_regs
[0x18 >> 2] = 0x0010fffb;
1331 mpu
->tcmi_regs
[0x1c >> 2] = 0x0010fffb;
1332 mpu
->tcmi_regs
[0x20 >> 2] = 0x00618800;
1333 mpu
->tcmi_regs
[0x24 >> 2] = 0x00000037;
1334 mpu
->tcmi_regs
[0x28 >> 2] = 0x00000000;
1335 mpu
->tcmi_regs
[0x2c >> 2] = 0x00000000;
1336 mpu
->tcmi_regs
[0x30 >> 2] = 0x00000000;
1337 mpu
->tcmi_regs
[0x3c >> 2] = 0x00000003;
1338 mpu
->tcmi_regs
[0x40 >> 2] = 0x00000000;
1341 static void omap_tcmi_init(MemoryRegion
*memory
, hwaddr base
,
1342 struct omap_mpu_state_s
*mpu
)
1344 memory_region_init_io(&mpu
->tcmi_iomem
, NULL
, &omap_tcmi_ops
, mpu
,
1345 "omap-tcmi", 0x100);
1346 memory_region_add_subregion(memory
, base
, &mpu
->tcmi_iomem
);
1347 omap_tcmi_reset(mpu
);
1350 /* Digital phase-locked loops control */
1357 static uint64_t omap_dpll_read(void *opaque
, hwaddr addr
,
1360 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1363 return omap_badwidth_read16(opaque
, addr
);
1366 if (addr
== 0x00) /* CTL_REG */
1373 static void omap_dpll_write(void *opaque
, hwaddr addr
,
1374 uint64_t value
, unsigned size
)
1376 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1378 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1382 return omap_badwidth_write16(opaque
, addr
, value
);
1385 if (addr
== 0x00) { /* CTL_REG */
1386 /* See omap_ulpd_pm_write() too */
1387 diff
= s
->mode
& value
;
1388 s
->mode
= value
& 0x2fff;
1389 if (diff
& (0x3ff << 2)) {
1390 if (value
& (1 << 4)) { /* PLL_ENABLE */
1391 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1392 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1394 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1397 omap_clk_setrate(s
->dpll
, div
, mult
);
1400 /* Enter the desired mode. */
1401 s
->mode
= (s
->mode
& 0xfffe) | ((s
->mode
>> 4) & 1);
1403 /* Act as if the lock is restored. */
1410 static const MemoryRegionOps omap_dpll_ops
= {
1411 .read
= omap_dpll_read
,
1412 .write
= omap_dpll_write
,
1413 .endianness
= DEVICE_NATIVE_ENDIAN
,
1416 static void omap_dpll_reset(struct dpll_ctl_s
*s
)
1419 omap_clk_setrate(s
->dpll
, 1, 1);
1422 static struct dpll_ctl_s
*omap_dpll_init(MemoryRegion
*memory
,
1423 hwaddr base
, omap_clk clk
)
1425 struct dpll_ctl_s
*s
= g_malloc0(sizeof(*s
));
1426 memory_region_init_io(&s
->iomem
, NULL
, &omap_dpll_ops
, s
, "omap-dpll", 0x100);
1431 memory_region_add_subregion(memory
, base
, &s
->iomem
);
1435 /* MPU Clock/Reset/Power Mode Control */
1436 static uint64_t omap_clkm_read(void *opaque
, hwaddr addr
,
1439 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1442 return omap_badwidth_read16(opaque
, addr
);
1446 case 0x00: /* ARM_CKCTL */
1447 return s
->clkm
.arm_ckctl
;
1449 case 0x04: /* ARM_IDLECT1 */
1450 return s
->clkm
.arm_idlect1
;
1452 case 0x08: /* ARM_IDLECT2 */
1453 return s
->clkm
.arm_idlect2
;
1455 case 0x0c: /* ARM_EWUPCT */
1456 return s
->clkm
.arm_ewupct
;
1458 case 0x10: /* ARM_RSTCT1 */
1459 return s
->clkm
.arm_rstct1
;
1461 case 0x14: /* ARM_RSTCT2 */
1462 return s
->clkm
.arm_rstct2
;
1464 case 0x18: /* ARM_SYSST */
1465 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
;
1467 case 0x1c: /* ARM_CKOUT1 */
1468 return s
->clkm
.arm_ckout1
;
1470 case 0x20: /* ARM_CKOUT2 */
1478 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s
*s
,
1479 uint16_t diff
, uint16_t value
)
1483 if (diff
& (1 << 14)) { /* ARM_INTHCK_SEL */
1484 if (value
& (1 << 14))
1487 clk
= omap_findclk(s
, "arminth_ck");
1488 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1491 if (diff
& (1 << 12)) { /* ARM_TIMXO */
1492 clk
= omap_findclk(s
, "armtim_ck");
1493 if (value
& (1 << 12))
1494 omap_clk_reparent(clk
, omap_findclk(s
, "clkin"));
1496 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1499 if (diff
& (3 << 10)) { /* DSPMMUDIV */
1500 clk
= omap_findclk(s
, "dspmmu_ck");
1501 omap_clk_setrate(clk
, 1 << ((value
>> 10) & 3), 1);
1503 if (diff
& (3 << 8)) { /* TCDIV */
1504 clk
= omap_findclk(s
, "tc_ck");
1505 omap_clk_setrate(clk
, 1 << ((value
>> 8) & 3), 1);
1507 if (diff
& (3 << 6)) { /* DSPDIV */
1508 clk
= omap_findclk(s
, "dsp_ck");
1509 omap_clk_setrate(clk
, 1 << ((value
>> 6) & 3), 1);
1511 if (diff
& (3 << 4)) { /* ARMDIV */
1512 clk
= omap_findclk(s
, "arm_ck");
1513 omap_clk_setrate(clk
, 1 << ((value
>> 4) & 3), 1);
1515 if (diff
& (3 << 2)) { /* LCDDIV */
1516 clk
= omap_findclk(s
, "lcd_ck");
1517 omap_clk_setrate(clk
, 1 << ((value
>> 2) & 3), 1);
1519 if (diff
& (3 << 0)) { /* PERDIV */
1520 clk
= omap_findclk(s
, "armper_ck");
1521 omap_clk_setrate(clk
, 1 << ((value
>> 0) & 3), 1);
1525 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s
*s
,
1526 uint16_t diff
, uint16_t value
)
1530 if (value
& (1 << 11)) { /* SETARM_IDLE */
1531 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HALT
);
1533 if (!(value
& (1 << 10))) /* WKUP_MODE */
1534 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
1536 #define SET_CANIDLE(clock, bit) \
1537 if (diff & (1 << bit)) { \
1538 clk = omap_findclk(s, clock); \
1539 omap_clk_canidle(clk, (value >> bit) & 1); \
1541 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
1542 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
1543 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
1544 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
1545 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
1546 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
1547 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
1548 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
1549 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
1550 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
1551 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
1552 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
1553 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
1554 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
1557 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s
*s
,
1558 uint16_t diff
, uint16_t value
)
1562 #define SET_ONOFF(clock, bit) \
1563 if (diff & (1 << bit)) { \
1564 clk = omap_findclk(s, clock); \
1565 omap_clk_onoff(clk, (value >> bit) & 1); \
1567 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
1568 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
1569 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
1570 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
1571 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
1572 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
1573 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
1574 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
1575 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
1576 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
1577 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
1580 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s
*s
,
1581 uint16_t diff
, uint16_t value
)
1585 if (diff
& (3 << 4)) { /* TCLKOUT */
1586 clk
= omap_findclk(s
, "tclk_out");
1587 switch ((value
>> 4) & 3) {
1589 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen3"));
1590 omap_clk_onoff(clk
, 1);
1593 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
1594 omap_clk_onoff(clk
, 1);
1597 omap_clk_onoff(clk
, 0);
1600 if (diff
& (3 << 2)) { /* DCLKOUT */
1601 clk
= omap_findclk(s
, "dclk_out");
1602 switch ((value
>> 2) & 3) {
1604 omap_clk_reparent(clk
, omap_findclk(s
, "dspmmu_ck"));
1607 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen2"));
1610 omap_clk_reparent(clk
, omap_findclk(s
, "dsp_ck"));
1613 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1617 if (diff
& (3 << 0)) { /* ACLKOUT */
1618 clk
= omap_findclk(s
, "aclk_out");
1619 switch ((value
>> 0) & 3) {
1621 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
1622 omap_clk_onoff(clk
, 1);
1625 omap_clk_reparent(clk
, omap_findclk(s
, "arm_ck"));
1626 omap_clk_onoff(clk
, 1);
1629 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
1630 omap_clk_onoff(clk
, 1);
1633 omap_clk_onoff(clk
, 0);
1638 static void omap_clkm_write(void *opaque
, hwaddr addr
,
1639 uint64_t value
, unsigned size
)
1641 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1644 static const char *clkschemename
[8] = {
1645 "fully synchronous", "fully asynchronous", "synchronous scalable",
1646 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
1650 return omap_badwidth_write16(opaque
, addr
, value
);
1654 case 0x00: /* ARM_CKCTL */
1655 diff
= s
->clkm
.arm_ckctl
^ value
;
1656 s
->clkm
.arm_ckctl
= value
& 0x7fff;
1657 omap_clkm_ckctl_update(s
, diff
, value
);
1660 case 0x04: /* ARM_IDLECT1 */
1661 diff
= s
->clkm
.arm_idlect1
^ value
;
1662 s
->clkm
.arm_idlect1
= value
& 0x0fff;
1663 omap_clkm_idlect1_update(s
, diff
, value
);
1666 case 0x08: /* ARM_IDLECT2 */
1667 diff
= s
->clkm
.arm_idlect2
^ value
;
1668 s
->clkm
.arm_idlect2
= value
& 0x07ff;
1669 omap_clkm_idlect2_update(s
, diff
, value
);
1672 case 0x0c: /* ARM_EWUPCT */
1673 s
->clkm
.arm_ewupct
= value
& 0x003f;
1676 case 0x10: /* ARM_RSTCT1 */
1677 diff
= s
->clkm
.arm_rstct1
^ value
;
1678 s
->clkm
.arm_rstct1
= value
& 0x0007;
1680 qemu_system_reset_request();
1681 s
->clkm
.cold_start
= 0xa;
1683 if (diff
& ~value
& 4) { /* DSP_RST */
1685 omap_tipb_bridge_reset(s
->private_tipb
);
1686 omap_tipb_bridge_reset(s
->public_tipb
);
1688 if (diff
& 2) { /* DSP_EN */
1689 clk
= omap_findclk(s
, "dsp_ck");
1690 omap_clk_canidle(clk
, (~value
>> 1) & 1);
1694 case 0x14: /* ARM_RSTCT2 */
1695 s
->clkm
.arm_rstct2
= value
& 0x0001;
1698 case 0x18: /* ARM_SYSST */
1699 if ((s
->clkm
.clocking_scheme
^ (value
>> 11)) & 7) {
1700 s
->clkm
.clocking_scheme
= (value
>> 11) & 7;
1701 printf("%s: clocking scheme set to %s\n", __FUNCTION__
,
1702 clkschemename
[s
->clkm
.clocking_scheme
]);
1704 s
->clkm
.cold_start
&= value
& 0x3f;
1707 case 0x1c: /* ARM_CKOUT1 */
1708 diff
= s
->clkm
.arm_ckout1
^ value
;
1709 s
->clkm
.arm_ckout1
= value
& 0x003f;
1710 omap_clkm_ckout1_update(s
, diff
, value
);
1713 case 0x20: /* ARM_CKOUT2 */
1719 static const MemoryRegionOps omap_clkm_ops
= {
1720 .read
= omap_clkm_read
,
1721 .write
= omap_clkm_write
,
1722 .endianness
= DEVICE_NATIVE_ENDIAN
,
1725 static uint64_t omap_clkdsp_read(void *opaque
, hwaddr addr
,
1728 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1729 CPUState
*cpu
= CPU(s
->cpu
);
1732 return omap_badwidth_read16(opaque
, addr
);
1736 case 0x04: /* DSP_IDLECT1 */
1737 return s
->clkm
.dsp_idlect1
;
1739 case 0x08: /* DSP_IDLECT2 */
1740 return s
->clkm
.dsp_idlect2
;
1742 case 0x14: /* DSP_RSTCT2 */
1743 return s
->clkm
.dsp_rstct2
;
1745 case 0x18: /* DSP_SYSST */
1747 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
|
1748 (cpu
->halted
<< 6); /* Quite useless... */
1755 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s
*s
,
1756 uint16_t diff
, uint16_t value
)
1760 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
1763 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s
*s
,
1764 uint16_t diff
, uint16_t value
)
1768 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
1771 static void omap_clkdsp_write(void *opaque
, hwaddr addr
,
1772 uint64_t value
, unsigned size
)
1774 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1778 return omap_badwidth_write16(opaque
, addr
, value
);
1782 case 0x04: /* DSP_IDLECT1 */
1783 diff
= s
->clkm
.dsp_idlect1
^ value
;
1784 s
->clkm
.dsp_idlect1
= value
& 0x01f7;
1785 omap_clkdsp_idlect1_update(s
, diff
, value
);
1788 case 0x08: /* DSP_IDLECT2 */
1789 s
->clkm
.dsp_idlect2
= value
& 0x0037;
1790 diff
= s
->clkm
.dsp_idlect1
^ value
;
1791 omap_clkdsp_idlect2_update(s
, diff
, value
);
1794 case 0x14: /* DSP_RSTCT2 */
1795 s
->clkm
.dsp_rstct2
= value
& 0x0001;
1798 case 0x18: /* DSP_SYSST */
1799 s
->clkm
.cold_start
&= value
& 0x3f;
1807 static const MemoryRegionOps omap_clkdsp_ops
= {
1808 .read
= omap_clkdsp_read
,
1809 .write
= omap_clkdsp_write
,
1810 .endianness
= DEVICE_NATIVE_ENDIAN
,
1813 static void omap_clkm_reset(struct omap_mpu_state_s
*s
)
1815 if (s
->wdt
&& s
->wdt
->reset
)
1816 s
->clkm
.cold_start
= 0x6;
1817 s
->clkm
.clocking_scheme
= 0;
1818 omap_clkm_ckctl_update(s
, ~0, 0x3000);
1819 s
->clkm
.arm_ckctl
= 0x3000;
1820 omap_clkm_idlect1_update(s
, s
->clkm
.arm_idlect1
^ 0x0400, 0x0400);
1821 s
->clkm
.arm_idlect1
= 0x0400;
1822 omap_clkm_idlect2_update(s
, s
->clkm
.arm_idlect2
^ 0x0100, 0x0100);
1823 s
->clkm
.arm_idlect2
= 0x0100;
1824 s
->clkm
.arm_ewupct
= 0x003f;
1825 s
->clkm
.arm_rstct1
= 0x0000;
1826 s
->clkm
.arm_rstct2
= 0x0000;
1827 s
->clkm
.arm_ckout1
= 0x0015;
1828 s
->clkm
.dpll1_mode
= 0x2002;
1829 omap_clkdsp_idlect1_update(s
, s
->clkm
.dsp_idlect1
^ 0x0040, 0x0040);
1830 s
->clkm
.dsp_idlect1
= 0x0040;
1831 omap_clkdsp_idlect2_update(s
, ~0, 0x0000);
1832 s
->clkm
.dsp_idlect2
= 0x0000;
1833 s
->clkm
.dsp_rstct2
= 0x0000;
1836 static void omap_clkm_init(MemoryRegion
*memory
, hwaddr mpu_base
,
1837 hwaddr dsp_base
, struct omap_mpu_state_s
*s
)
1839 memory_region_init_io(&s
->clkm_iomem
, NULL
, &omap_clkm_ops
, s
,
1840 "omap-clkm", 0x100);
1841 memory_region_init_io(&s
->clkdsp_iomem
, NULL
, &omap_clkdsp_ops
, s
,
1842 "omap-clkdsp", 0x1000);
1844 s
->clkm
.arm_idlect1
= 0x03ff;
1845 s
->clkm
.arm_idlect2
= 0x0100;
1846 s
->clkm
.dsp_idlect1
= 0x0002;
1848 s
->clkm
.cold_start
= 0x3a;
1850 memory_region_add_subregion(memory
, mpu_base
, &s
->clkm_iomem
);
1851 memory_region_add_subregion(memory
, dsp_base
, &s
->clkdsp_iomem
);
1855 struct omap_mpuio_s
{
1859 qemu_irq handler
[16];
1881 static void omap_mpuio_set(void *opaque
, int line
, int level
)
1883 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1884 uint16_t prev
= s
->inputs
;
1887 s
->inputs
|= 1 << line
;
1889 s
->inputs
&= ~(1 << line
);
1891 if (((1 << line
) & s
->dir
& ~s
->mask
) && s
->clk
) {
1892 if ((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) {
1893 s
->ints
|= 1 << line
;
1894 qemu_irq_raise(s
->irq
);
1897 if ((s
->event
& (1 << 0)) && /* SET_GPIO_EVENT_MODE */
1898 (s
->event
>> 1) == line
) /* PIN_SELECT */
1899 s
->latch
= s
->inputs
;
1903 static void omap_mpuio_kbd_update(struct omap_mpuio_s
*s
)
1906 uint8_t *row
, rows
= 0, cols
= ~s
->cols
;
1908 for (row
= s
->buttons
+ 4, i
= 1 << 4; i
; row
--, i
>>= 1)
1912 qemu_set_irq(s
->kbd_irq
, rows
&& !s
->kbd_mask
&& s
->clk
);
1913 s
->row_latch
= ~rows
;
1916 static uint64_t omap_mpuio_read(void *opaque
, hwaddr addr
,
1919 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1920 int offset
= addr
& OMAP_MPUI_REG_MASK
;
1924 return omap_badwidth_read16(opaque
, addr
);
1928 case 0x00: /* INPUT_LATCH */
1931 case 0x04: /* OUTPUT_REG */
1934 case 0x08: /* IO_CNTL */
1937 case 0x10: /* KBR_LATCH */
1938 return s
->row_latch
;
1940 case 0x14: /* KBC_REG */
1943 case 0x18: /* GPIO_EVENT_MODE_REG */
1946 case 0x1c: /* GPIO_INT_EDGE_REG */
1949 case 0x20: /* KBD_INT */
1950 return (~s
->row_latch
& 0x1f) && !s
->kbd_mask
;
1952 case 0x24: /* GPIO_INT */
1956 qemu_irq_lower(s
->irq
);
1959 case 0x28: /* KBD_MASKIT */
1962 case 0x2c: /* GPIO_MASKIT */
1965 case 0x30: /* GPIO_DEBOUNCING_REG */
1968 case 0x34: /* GPIO_LATCH_REG */
1976 static void omap_mpuio_write(void *opaque
, hwaddr addr
,
1977 uint64_t value
, unsigned size
)
1979 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
1980 int offset
= addr
& OMAP_MPUI_REG_MASK
;
1985 return omap_badwidth_write16(opaque
, addr
, value
);
1989 case 0x04: /* OUTPUT_REG */
1990 diff
= (s
->outputs
^ value
) & ~s
->dir
;
1992 while ((ln
= ffs(diff
))) {
1995 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2000 case 0x08: /* IO_CNTL */
2001 diff
= s
->outputs
& (s
->dir
^ value
);
2004 value
= s
->outputs
& ~s
->dir
;
2005 while ((ln
= ffs(diff
))) {
2008 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2013 case 0x14: /* KBC_REG */
2015 omap_mpuio_kbd_update(s
);
2018 case 0x18: /* GPIO_EVENT_MODE_REG */
2019 s
->event
= value
& 0x1f;
2022 case 0x1c: /* GPIO_INT_EDGE_REG */
2026 case 0x28: /* KBD_MASKIT */
2027 s
->kbd_mask
= value
& 1;
2028 omap_mpuio_kbd_update(s
);
2031 case 0x2c: /* GPIO_MASKIT */
2035 case 0x30: /* GPIO_DEBOUNCING_REG */
2036 s
->debounce
= value
& 0x1ff;
2039 case 0x00: /* INPUT_LATCH */
2040 case 0x10: /* KBR_LATCH */
2041 case 0x20: /* KBD_INT */
2042 case 0x24: /* GPIO_INT */
2043 case 0x34: /* GPIO_LATCH_REG */
2053 static const MemoryRegionOps omap_mpuio_ops
= {
2054 .read
= omap_mpuio_read
,
2055 .write
= omap_mpuio_write
,
2056 .endianness
= DEVICE_NATIVE_ENDIAN
,
2059 static void omap_mpuio_reset(struct omap_mpuio_s
*s
)
2071 s
->row_latch
= 0x1f;
2075 static void omap_mpuio_onoff(void *opaque
, int line
, int on
)
2077 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2081 omap_mpuio_kbd_update(s
);
2084 static struct omap_mpuio_s
*omap_mpuio_init(MemoryRegion
*memory
,
2086 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
2089 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*)
2090 g_malloc0(sizeof(struct omap_mpuio_s
));
2093 s
->kbd_irq
= kbd_int
;
2095 s
->in
= qemu_allocate_irqs(omap_mpuio_set
, s
, 16);
2096 omap_mpuio_reset(s
);
2098 memory_region_init_io(&s
->iomem
, NULL
, &omap_mpuio_ops
, s
,
2099 "omap-mpuio", 0x800);
2100 memory_region_add_subregion(memory
, base
, &s
->iomem
);
2102 omap_clk_adduser(clk
, qemu_allocate_irq(omap_mpuio_onoff
, s
, 0));
2107 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
)
2112 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
)
2114 if (line
>= 16 || line
< 0)
2115 hw_error("%s: No GPIO line %i\n", __FUNCTION__
, line
);
2116 s
->handler
[line
] = handler
;
2119 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
)
2121 if (row
>= 5 || row
< 0)
2122 hw_error("%s: No key %i-%i\n", __FUNCTION__
, col
, row
);
2125 s
->buttons
[row
] |= 1 << col
;
2127 s
->buttons
[row
] &= ~(1 << col
);
2129 omap_mpuio_kbd_update(s
);
2132 /* MicroWire Interface */
2133 struct omap_uwire_s
{
2144 uWireSlave
*chip
[4];
2147 static void omap_uwire_transfer_start(struct omap_uwire_s
*s
)
2149 int chipselect
= (s
->control
>> 10) & 3; /* INDEX */
2150 uWireSlave
*slave
= s
->chip
[chipselect
];
2152 if ((s
->control
>> 5) & 0x1f) { /* NB_BITS_WR */
2153 if (s
->control
& (1 << 12)) /* CS_CMD */
2154 if (slave
&& slave
->send
)
2155 slave
->send(slave
->opaque
,
2156 s
->txbuf
>> (16 - ((s
->control
>> 5) & 0x1f)));
2157 s
->control
&= ~(1 << 14); /* CSRB */
2158 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2159 * a DRQ. When is the level IRQ supposed to be reset? */
2162 if ((s
->control
>> 0) & 0x1f) { /* NB_BITS_RD */
2163 if (s
->control
& (1 << 12)) /* CS_CMD */
2164 if (slave
&& slave
->receive
)
2165 s
->rxbuf
= slave
->receive(slave
->opaque
);
2166 s
->control
|= 1 << 15; /* RDRB */
2167 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2168 * a DRQ. When is the level IRQ supposed to be reset? */
2172 static uint64_t omap_uwire_read(void *opaque
, hwaddr addr
,
2175 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2176 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2179 return omap_badwidth_read16(opaque
, addr
);
2183 case 0x00: /* RDR */
2184 s
->control
&= ~(1 << 15); /* RDRB */
2187 case 0x04: /* CSR */
2190 case 0x08: /* SR1 */
2192 case 0x0c: /* SR2 */
2194 case 0x10: /* SR3 */
2196 case 0x14: /* SR4 */
2198 case 0x18: /* SR5 */
2206 static void omap_uwire_write(void *opaque
, hwaddr addr
,
2207 uint64_t value
, unsigned size
)
2209 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
2210 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2213 return omap_badwidth_write16(opaque
, addr
, value
);
2217 case 0x00: /* TDR */
2218 s
->txbuf
= value
; /* TD */
2219 if ((s
->setup
[4] & (1 << 2)) && /* AUTO_TX_EN */
2220 ((s
->setup
[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
2221 (s
->control
& (1 << 12)))) { /* CS_CMD */
2222 s
->control
|= 1 << 14; /* CSRB */
2223 omap_uwire_transfer_start(s
);
2227 case 0x04: /* CSR */
2228 s
->control
= value
& 0x1fff;
2229 if (value
& (1 << 13)) /* START */
2230 omap_uwire_transfer_start(s
);
2233 case 0x08: /* SR1 */
2234 s
->setup
[0] = value
& 0x003f;
2237 case 0x0c: /* SR2 */
2238 s
->setup
[1] = value
& 0x0fc0;
2241 case 0x10: /* SR3 */
2242 s
->setup
[2] = value
& 0x0003;
2245 case 0x14: /* SR4 */
2246 s
->setup
[3] = value
& 0x0001;
2249 case 0x18: /* SR5 */
2250 s
->setup
[4] = value
& 0x000f;
2259 static const MemoryRegionOps omap_uwire_ops
= {
2260 .read
= omap_uwire_read
,
2261 .write
= omap_uwire_write
,
2262 .endianness
= DEVICE_NATIVE_ENDIAN
,
2265 static void omap_uwire_reset(struct omap_uwire_s
*s
)
2275 static struct omap_uwire_s
*omap_uwire_init(MemoryRegion
*system_memory
,
2277 qemu_irq txirq
, qemu_irq rxirq
,
2281 struct omap_uwire_s
*s
= (struct omap_uwire_s
*)
2282 g_malloc0(sizeof(struct omap_uwire_s
));
2287 omap_uwire_reset(s
);
2289 memory_region_init_io(&s
->iomem
, NULL
, &omap_uwire_ops
, s
, "omap-uwire", 0x800);
2290 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2295 void omap_uwire_attach(struct omap_uwire_s
*s
,
2296 uWireSlave
*slave
, int chipselect
)
2298 if (chipselect
< 0 || chipselect
> 3) {
2299 fprintf(stderr
, "%s: Bad chipselect %i\n", __FUNCTION__
, chipselect
);
2303 s
->chip
[chipselect
] = slave
;
2306 /* Pseudonoise Pulse-Width Light Modulator */
2315 static void omap_pwl_update(struct omap_pwl_s
*s
)
2317 int output
= (s
->clk
&& s
->enable
) ? s
->level
: 0;
2319 if (output
!= s
->output
) {
2321 printf("%s: Backlight now at %i/256\n", __FUNCTION__
, output
);
2325 static uint64_t omap_pwl_read(void *opaque
, hwaddr addr
,
2328 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2329 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2332 return omap_badwidth_read8(opaque
, addr
);
2336 case 0x00: /* PWL_LEVEL */
2338 case 0x04: /* PWL_CTRL */
2345 static void omap_pwl_write(void *opaque
, hwaddr addr
,
2346 uint64_t value
, unsigned size
)
2348 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2349 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2352 return omap_badwidth_write8(opaque
, addr
, value
);
2356 case 0x00: /* PWL_LEVEL */
2360 case 0x04: /* PWL_CTRL */
2361 s
->enable
= value
& 1;
2370 static const MemoryRegionOps omap_pwl_ops
= {
2371 .read
= omap_pwl_read
,
2372 .write
= omap_pwl_write
,
2373 .endianness
= DEVICE_NATIVE_ENDIAN
,
2376 static void omap_pwl_reset(struct omap_pwl_s
*s
)
2385 static void omap_pwl_clk_update(void *opaque
, int line
, int on
)
2387 struct omap_pwl_s
*s
= (struct omap_pwl_s
*) opaque
;
2393 static struct omap_pwl_s
*omap_pwl_init(MemoryRegion
*system_memory
,
2397 struct omap_pwl_s
*s
= g_malloc0(sizeof(*s
));
2401 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwl_ops
, s
,
2403 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2405 omap_clk_adduser(clk
, qemu_allocate_irq(omap_pwl_clk_update
, s
, 0));
2409 /* Pulse-Width Tone module */
2418 static uint64_t omap_pwt_read(void *opaque
, hwaddr addr
,
2421 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2422 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2425 return omap_badwidth_read8(opaque
, addr
);
2429 case 0x00: /* FRC */
2431 case 0x04: /* VCR */
2433 case 0x08: /* GCR */
2440 static void omap_pwt_write(void *opaque
, hwaddr addr
,
2441 uint64_t value
, unsigned size
)
2443 struct omap_pwt_s
*s
= (struct omap_pwt_s
*) opaque
;
2444 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2447 return omap_badwidth_write8(opaque
, addr
, value
);
2451 case 0x00: /* FRC */
2452 s
->frc
= value
& 0x3f;
2454 case 0x04: /* VRC */
2455 if ((value
^ s
->vrc
) & 1) {
2457 printf("%s: %iHz buzz on\n", __FUNCTION__
, (int)
2458 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
2459 ((omap_clk_getrate(s
->clk
) >> 3) /
2460 /* Pre-multiplexer divider */
2461 ((s
->gcr
& 2) ? 1 : 154) /
2462 /* Octave multiplexer */
2463 (2 << (value
& 3)) *
2464 /* 101/107 divider */
2465 ((value
& (1 << 2)) ? 101 : 107) *
2467 ((value
& (1 << 3)) ? 49 : 55) *
2469 ((value
& (1 << 4)) ? 50 : 63) *
2470 /* 80/127 divider */
2471 ((value
& (1 << 5)) ? 80 : 127) /
2472 (107 * 55 * 63 * 127)));
2474 printf("%s: silence!\n", __FUNCTION__
);
2476 s
->vrc
= value
& 0x7f;
2478 case 0x08: /* GCR */
2487 static const MemoryRegionOps omap_pwt_ops
= {
2488 .read
=omap_pwt_read
,
2489 .write
= omap_pwt_write
,
2490 .endianness
= DEVICE_NATIVE_ENDIAN
,
2493 static void omap_pwt_reset(struct omap_pwt_s
*s
)
2500 static struct omap_pwt_s
*omap_pwt_init(MemoryRegion
*system_memory
,
2504 struct omap_pwt_s
*s
= g_malloc0(sizeof(*s
));
2508 memory_region_init_io(&s
->iomem
, NULL
, &omap_pwt_ops
, s
,
2510 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2514 /* Real-time Clock module */
2531 struct tm current_tm
;
2536 static void omap_rtc_interrupts_update(struct omap_rtc_s
*s
)
2538 /* s->alarm is level-triggered */
2539 qemu_set_irq(s
->alarm
, (s
->status
>> 6) & 1);
2542 static void omap_rtc_alarm_update(struct omap_rtc_s
*s
)
2544 s
->alarm_ti
= mktimegm(&s
->alarm_tm
);
2545 if (s
->alarm_ti
== -1)
2546 printf("%s: conversion failed\n", __FUNCTION__
);
2549 static uint64_t omap_rtc_read(void *opaque
, hwaddr addr
,
2552 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2553 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2557 return omap_badwidth_read8(opaque
, addr
);
2561 case 0x00: /* SECONDS_REG */
2562 return to_bcd(s
->current_tm
.tm_sec
);
2564 case 0x04: /* MINUTES_REG */
2565 return to_bcd(s
->current_tm
.tm_min
);
2567 case 0x08: /* HOURS_REG */
2569 return ((s
->current_tm
.tm_hour
> 11) << 7) |
2570 to_bcd(((s
->current_tm
.tm_hour
- 1) % 12) + 1);
2572 return to_bcd(s
->current_tm
.tm_hour
);
2574 case 0x0c: /* DAYS_REG */
2575 return to_bcd(s
->current_tm
.tm_mday
);
2577 case 0x10: /* MONTHS_REG */
2578 return to_bcd(s
->current_tm
.tm_mon
+ 1);
2580 case 0x14: /* YEARS_REG */
2581 return to_bcd(s
->current_tm
.tm_year
% 100);
2583 case 0x18: /* WEEK_REG */
2584 return s
->current_tm
.tm_wday
;
2586 case 0x20: /* ALARM_SECONDS_REG */
2587 return to_bcd(s
->alarm_tm
.tm_sec
);
2589 case 0x24: /* ALARM_MINUTES_REG */
2590 return to_bcd(s
->alarm_tm
.tm_min
);
2592 case 0x28: /* ALARM_HOURS_REG */
2594 return ((s
->alarm_tm
.tm_hour
> 11) << 7) |
2595 to_bcd(((s
->alarm_tm
.tm_hour
- 1) % 12) + 1);
2597 return to_bcd(s
->alarm_tm
.tm_hour
);
2599 case 0x2c: /* ALARM_DAYS_REG */
2600 return to_bcd(s
->alarm_tm
.tm_mday
);
2602 case 0x30: /* ALARM_MONTHS_REG */
2603 return to_bcd(s
->alarm_tm
.tm_mon
+ 1);
2605 case 0x34: /* ALARM_YEARS_REG */
2606 return to_bcd(s
->alarm_tm
.tm_year
% 100);
2608 case 0x40: /* RTC_CTRL_REG */
2609 return (s
->pm_am
<< 3) | (s
->auto_comp
<< 2) |
2610 (s
->round
<< 1) | s
->running
;
2612 case 0x44: /* RTC_STATUS_REG */
2617 case 0x48: /* RTC_INTERRUPTS_REG */
2618 return s
->interrupts
;
2620 case 0x4c: /* RTC_COMP_LSB_REG */
2621 return ((uint16_t) s
->comp_reg
) & 0xff;
2623 case 0x50: /* RTC_COMP_MSB_REG */
2624 return ((uint16_t) s
->comp_reg
) >> 8;
2631 static void omap_rtc_write(void *opaque
, hwaddr addr
,
2632 uint64_t value
, unsigned size
)
2634 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
2635 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2640 return omap_badwidth_write8(opaque
, addr
, value
);
2644 case 0x00: /* SECONDS_REG */
2646 printf("RTC SEC_REG <-- %02x\n", value
);
2648 s
->ti
-= s
->current_tm
.tm_sec
;
2649 s
->ti
+= from_bcd(value
);
2652 case 0x04: /* MINUTES_REG */
2654 printf("RTC MIN_REG <-- %02x\n", value
);
2656 s
->ti
-= s
->current_tm
.tm_min
* 60;
2657 s
->ti
+= from_bcd(value
) * 60;
2660 case 0x08: /* HOURS_REG */
2662 printf("RTC HRS_REG <-- %02x\n", value
);
2664 s
->ti
-= s
->current_tm
.tm_hour
* 3600;
2666 s
->ti
+= (from_bcd(value
& 0x3f) & 12) * 3600;
2667 s
->ti
+= ((value
>> 7) & 1) * 43200;
2669 s
->ti
+= from_bcd(value
& 0x3f) * 3600;
2672 case 0x0c: /* DAYS_REG */
2674 printf("RTC DAY_REG <-- %02x\n", value
);
2676 s
->ti
-= s
->current_tm
.tm_mday
* 86400;
2677 s
->ti
+= from_bcd(value
) * 86400;
2680 case 0x10: /* MONTHS_REG */
2682 printf("RTC MTH_REG <-- %02x\n", value
);
2684 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2685 new_tm
.tm_mon
= from_bcd(value
);
2686 ti
[0] = mktimegm(&s
->current_tm
);
2687 ti
[1] = mktimegm(&new_tm
);
2689 if (ti
[0] != -1 && ti
[1] != -1) {
2693 /* A less accurate version */
2694 s
->ti
-= s
->current_tm
.tm_mon
* 2592000;
2695 s
->ti
+= from_bcd(value
) * 2592000;
2699 case 0x14: /* YEARS_REG */
2701 printf("RTC YRS_REG <-- %02x\n", value
);
2703 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
2704 new_tm
.tm_year
+= from_bcd(value
) - (new_tm
.tm_year
% 100);
2705 ti
[0] = mktimegm(&s
->current_tm
);
2706 ti
[1] = mktimegm(&new_tm
);
2708 if (ti
[0] != -1 && ti
[1] != -1) {
2712 /* A less accurate version */
2713 s
->ti
-= (time_t)(s
->current_tm
.tm_year
% 100) * 31536000;
2714 s
->ti
+= (time_t)from_bcd(value
) * 31536000;
2718 case 0x18: /* WEEK_REG */
2719 return; /* Ignored */
2721 case 0x20: /* ALARM_SECONDS_REG */
2723 printf("ALM SEC_REG <-- %02x\n", value
);
2725 s
->alarm_tm
.tm_sec
= from_bcd(value
);
2726 omap_rtc_alarm_update(s
);
2729 case 0x24: /* ALARM_MINUTES_REG */
2731 printf("ALM MIN_REG <-- %02x\n", value
);
2733 s
->alarm_tm
.tm_min
= from_bcd(value
);
2734 omap_rtc_alarm_update(s
);
2737 case 0x28: /* ALARM_HOURS_REG */
2739 printf("ALM HRS_REG <-- %02x\n", value
);
2742 s
->alarm_tm
.tm_hour
=
2743 ((from_bcd(value
& 0x3f)) % 12) +
2744 ((value
>> 7) & 1) * 12;
2746 s
->alarm_tm
.tm_hour
= from_bcd(value
);
2747 omap_rtc_alarm_update(s
);
2750 case 0x2c: /* ALARM_DAYS_REG */
2752 printf("ALM DAY_REG <-- %02x\n", value
);
2754 s
->alarm_tm
.tm_mday
= from_bcd(value
);
2755 omap_rtc_alarm_update(s
);
2758 case 0x30: /* ALARM_MONTHS_REG */
2760 printf("ALM MON_REG <-- %02x\n", value
);
2762 s
->alarm_tm
.tm_mon
= from_bcd(value
);
2763 omap_rtc_alarm_update(s
);
2766 case 0x34: /* ALARM_YEARS_REG */
2768 printf("ALM YRS_REG <-- %02x\n", value
);
2770 s
->alarm_tm
.tm_year
= from_bcd(value
);
2771 omap_rtc_alarm_update(s
);
2774 case 0x40: /* RTC_CTRL_REG */
2776 printf("RTC CONTROL <-- %02x\n", value
);
2778 s
->pm_am
= (value
>> 3) & 1;
2779 s
->auto_comp
= (value
>> 2) & 1;
2780 s
->round
= (value
>> 1) & 1;
2781 s
->running
= value
& 1;
2783 s
->status
|= s
->running
<< 1;
2786 case 0x44: /* RTC_STATUS_REG */
2788 printf("RTC STATUSL <-- %02x\n", value
);
2790 s
->status
&= ~((value
& 0xc0) ^ 0x80);
2791 omap_rtc_interrupts_update(s
);
2794 case 0x48: /* RTC_INTERRUPTS_REG */
2796 printf("RTC INTRS <-- %02x\n", value
);
2798 s
->interrupts
= value
;
2801 case 0x4c: /* RTC_COMP_LSB_REG */
2803 printf("RTC COMPLSB <-- %02x\n", value
);
2805 s
->comp_reg
&= 0xff00;
2806 s
->comp_reg
|= 0x00ff & value
;
2809 case 0x50: /* RTC_COMP_MSB_REG */
2811 printf("RTC COMPMSB <-- %02x\n", value
);
2813 s
->comp_reg
&= 0x00ff;
2814 s
->comp_reg
|= 0xff00 & (value
<< 8);
2823 static const MemoryRegionOps omap_rtc_ops
= {
2824 .read
= omap_rtc_read
,
2825 .write
= omap_rtc_write
,
2826 .endianness
= DEVICE_NATIVE_ENDIAN
,
2829 static void omap_rtc_tick(void *opaque
)
2831 struct omap_rtc_s
*s
= opaque
;
2834 /* Round to nearest full minute. */
2835 if (s
->current_tm
.tm_sec
< 30)
2836 s
->ti
-= s
->current_tm
.tm_sec
;
2838 s
->ti
+= 60 - s
->current_tm
.tm_sec
;
2843 localtime_r(&s
->ti
, &s
->current_tm
);
2845 if ((s
->interrupts
& 0x08) && s
->ti
== s
->alarm_ti
) {
2847 omap_rtc_interrupts_update(s
);
2850 if (s
->interrupts
& 0x04)
2851 switch (s
->interrupts
& 3) {
2854 qemu_irq_pulse(s
->irq
);
2857 if (s
->current_tm
.tm_sec
)
2860 qemu_irq_pulse(s
->irq
);
2863 if (s
->current_tm
.tm_sec
|| s
->current_tm
.tm_min
)
2866 qemu_irq_pulse(s
->irq
);
2869 if (s
->current_tm
.tm_sec
||
2870 s
->current_tm
.tm_min
|| s
->current_tm
.tm_hour
)
2873 qemu_irq_pulse(s
->irq
);
2883 * Every full hour add a rough approximation of the compensation
2884 * register to the 32kHz Timer (which drives the RTC) value.
2886 if (s
->auto_comp
&& !s
->current_tm
.tm_sec
&& !s
->current_tm
.tm_min
)
2887 s
->tick
+= s
->comp_reg
* 1000 / 32768;
2889 timer_mod(s
->clk
, s
->tick
);
2892 static void omap_rtc_reset(struct omap_rtc_s
*s
)
2902 s
->tick
= qemu_clock_get_ms(rtc_clock
);
2903 memset(&s
->alarm_tm
, 0, sizeof(s
->alarm_tm
));
2904 s
->alarm_tm
.tm_mday
= 0x01;
2906 qemu_get_timedate(&tm
, 0);
2907 s
->ti
= mktimegm(&tm
);
2909 omap_rtc_alarm_update(s
);
2913 static struct omap_rtc_s
*omap_rtc_init(MemoryRegion
*system_memory
,
2915 qemu_irq timerirq
, qemu_irq alarmirq
,
2918 struct omap_rtc_s
*s
= (struct omap_rtc_s
*)
2919 g_malloc0(sizeof(struct omap_rtc_s
));
2922 s
->alarm
= alarmirq
;
2923 s
->clk
= timer_new_ms(rtc_clock
, omap_rtc_tick
, s
);
2927 memory_region_init_io(&s
->iomem
, NULL
, &omap_rtc_ops
, s
,
2929 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
2934 /* Multi-channel Buffered Serial Port interfaces */
2935 struct omap_mcbsp_s
{
2956 QEMUTimer
*source_timer
;
2957 QEMUTimer
*sink_timer
;
2960 static void omap_mcbsp_intr_update(struct omap_mcbsp_s
*s
)
2964 switch ((s
->spcr
[0] >> 4) & 3) { /* RINTM */
2966 irq
= (s
->spcr
[0] >> 1) & 1; /* RRDY */
2969 irq
= (s
->spcr
[0] >> 3) & 1; /* RSYNCERR */
2977 qemu_irq_pulse(s
->rxirq
);
2979 switch ((s
->spcr
[1] >> 4) & 3) { /* XINTM */
2981 irq
= (s
->spcr
[1] >> 1) & 1; /* XRDY */
2984 irq
= (s
->spcr
[1] >> 3) & 1; /* XSYNCERR */
2992 qemu_irq_pulse(s
->txirq
);
2995 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s
*s
)
2997 if ((s
->spcr
[0] >> 1) & 1) /* RRDY */
2998 s
->spcr
[0] |= 1 << 2; /* RFULL */
2999 s
->spcr
[0] |= 1 << 1; /* RRDY */
3000 qemu_irq_raise(s
->rxdrq
);
3001 omap_mcbsp_intr_update(s
);
3004 static void omap_mcbsp_source_tick(void *opaque
)
3006 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3007 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3012 printf("%s: Rx FIFO overrun\n", __FUNCTION__
);
3014 s
->rx_req
= s
->rx_rate
<< bps
[(s
->rcr
[0] >> 5) & 7];
3016 omap_mcbsp_rx_newdata(s
);
3017 timer_mod(s
->source_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3018 get_ticks_per_sec());
3021 static void omap_mcbsp_rx_start(struct omap_mcbsp_s
*s
)
3023 if (!s
->codec
|| !s
->codec
->rts
)
3024 omap_mcbsp_source_tick(s
);
3025 else if (s
->codec
->in
.len
) {
3026 s
->rx_req
= s
->codec
->in
.len
;
3027 omap_mcbsp_rx_newdata(s
);
3031 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s
*s
)
3033 timer_del(s
->source_timer
);
3036 static void omap_mcbsp_rx_done(struct omap_mcbsp_s
*s
)
3038 s
->spcr
[0] &= ~(1 << 1); /* RRDY */
3039 qemu_irq_lower(s
->rxdrq
);
3040 omap_mcbsp_intr_update(s
);
3043 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s
*s
)
3045 s
->spcr
[1] |= 1 << 1; /* XRDY */
3046 qemu_irq_raise(s
->txdrq
);
3047 omap_mcbsp_intr_update(s
);
3050 static void omap_mcbsp_sink_tick(void *opaque
)
3052 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3053 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3058 printf("%s: Tx FIFO underrun\n", __FUNCTION__
);
3060 s
->tx_req
= s
->tx_rate
<< bps
[(s
->xcr
[0] >> 5) & 7];
3062 omap_mcbsp_tx_newdata(s
);
3063 timer_mod(s
->sink_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
3064 get_ticks_per_sec());
3067 static void omap_mcbsp_tx_start(struct omap_mcbsp_s
*s
)
3069 if (!s
->codec
|| !s
->codec
->cts
)
3070 omap_mcbsp_sink_tick(s
);
3071 else if (s
->codec
->out
.size
) {
3072 s
->tx_req
= s
->codec
->out
.size
;
3073 omap_mcbsp_tx_newdata(s
);
3077 static void omap_mcbsp_tx_done(struct omap_mcbsp_s
*s
)
3079 s
->spcr
[1] &= ~(1 << 1); /* XRDY */
3080 qemu_irq_lower(s
->txdrq
);
3081 omap_mcbsp_intr_update(s
);
3082 if (s
->codec
&& s
->codec
->cts
)
3083 s
->codec
->tx_swallow(s
->codec
->opaque
);
3086 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s
*s
)
3089 omap_mcbsp_tx_done(s
);
3090 timer_del(s
->sink_timer
);
3093 static void omap_mcbsp_req_update(struct omap_mcbsp_s
*s
)
3095 int prev_rx_rate
, prev_tx_rate
;
3096 int rx_rate
= 0, tx_rate
= 0;
3097 int cpu_rate
= 1500000; /* XXX */
3099 /* TODO: check CLKSTP bit */
3100 if (s
->spcr
[1] & (1 << 6)) { /* GRST */
3101 if (s
->spcr
[0] & (1 << 0)) { /* RRST */
3102 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3103 (s
->pcr
& (1 << 8))) { /* CLKRM */
3104 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3105 rx_rate
= cpu_rate
/
3106 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3109 rx_rate
= s
->codec
->rx_rate
;
3112 if (s
->spcr
[1] & (1 << 0)) { /* XRST */
3113 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3114 (s
->pcr
& (1 << 9))) { /* CLKXM */
3115 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3116 tx_rate
= cpu_rate
/
3117 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3120 tx_rate
= s
->codec
->tx_rate
;
3123 prev_tx_rate
= s
->tx_rate
;
3124 prev_rx_rate
= s
->rx_rate
;
3125 s
->tx_rate
= tx_rate
;
3126 s
->rx_rate
= rx_rate
;
3129 s
->codec
->set_rate(s
->codec
->opaque
, rx_rate
, tx_rate
);
3131 if (!prev_tx_rate
&& tx_rate
)
3132 omap_mcbsp_tx_start(s
);
3133 else if (s
->tx_rate
&& !tx_rate
)
3134 omap_mcbsp_tx_stop(s
);
3136 if (!prev_rx_rate
&& rx_rate
)
3137 omap_mcbsp_rx_start(s
);
3138 else if (prev_tx_rate
&& !tx_rate
)
3139 omap_mcbsp_rx_stop(s
);
3142 static uint64_t omap_mcbsp_read(void *opaque
, hwaddr addr
,
3145 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3146 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3150 return omap_badwidth_read16(opaque
, addr
);
3154 case 0x00: /* DRR2 */
3155 if (((s
->rcr
[0] >> 5) & 7) < 3) /* RWDLEN1 */
3158 case 0x02: /* DRR1 */
3159 if (s
->rx_req
< 2) {
3160 printf("%s: Rx FIFO underrun\n", __FUNCTION__
);
3161 omap_mcbsp_rx_done(s
);
3164 if (s
->codec
&& s
->codec
->in
.len
>= 2) {
3165 ret
= s
->codec
->in
.fifo
[s
->codec
->in
.start
++] << 8;
3166 ret
|= s
->codec
->in
.fifo
[s
->codec
->in
.start
++];
3167 s
->codec
->in
.len
-= 2;
3171 omap_mcbsp_rx_done(s
);
3176 case 0x04: /* DXR2 */
3177 case 0x06: /* DXR1 */
3180 case 0x08: /* SPCR2 */
3182 case 0x0a: /* SPCR1 */
3184 case 0x0c: /* RCR2 */
3186 case 0x0e: /* RCR1 */
3188 case 0x10: /* XCR2 */
3190 case 0x12: /* XCR1 */
3192 case 0x14: /* SRGR2 */
3194 case 0x16: /* SRGR1 */
3196 case 0x18: /* MCR2 */
3198 case 0x1a: /* MCR1 */
3200 case 0x1c: /* RCERA */
3202 case 0x1e: /* RCERB */
3204 case 0x20: /* XCERA */
3206 case 0x22: /* XCERB */
3208 case 0x24: /* PCR0 */
3210 case 0x26: /* RCERC */
3212 case 0x28: /* RCERD */
3214 case 0x2a: /* XCERC */
3216 case 0x2c: /* XCERD */
3218 case 0x2e: /* RCERE */
3220 case 0x30: /* RCERF */
3222 case 0x32: /* XCERE */
3224 case 0x34: /* XCERF */
3226 case 0x36: /* RCERG */
3228 case 0x38: /* RCERH */
3230 case 0x3a: /* XCERG */
3232 case 0x3c: /* XCERH */
3240 static void omap_mcbsp_writeh(void *opaque
, hwaddr addr
,
3243 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3244 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3247 case 0x00: /* DRR2 */
3248 case 0x02: /* DRR1 */
3252 case 0x04: /* DXR2 */
3253 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3256 case 0x06: /* DXR1 */
3257 if (s
->tx_req
> 1) {
3259 if (s
->codec
&& s
->codec
->cts
) {
3260 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 8) & 0xff;
3261 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 0) & 0xff;
3264 omap_mcbsp_tx_done(s
);
3266 printf("%s: Tx FIFO overrun\n", __FUNCTION__
);
3269 case 0x08: /* SPCR2 */
3270 s
->spcr
[1] &= 0x0002;
3271 s
->spcr
[1] |= 0x03f9 & value
;
3272 s
->spcr
[1] |= 0x0004 & (value
<< 2); /* XEMPTY := XRST */
3273 if (~value
& 1) /* XRST */
3275 omap_mcbsp_req_update(s
);
3277 case 0x0a: /* SPCR1 */
3278 s
->spcr
[0] &= 0x0006;
3279 s
->spcr
[0] |= 0xf8f9 & value
;
3280 if (value
& (1 << 15)) /* DLB */
3281 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__
);
3282 if (~value
& 1) { /* RRST */
3285 omap_mcbsp_rx_done(s
);
3287 omap_mcbsp_req_update(s
);
3290 case 0x0c: /* RCR2 */
3291 s
->rcr
[1] = value
& 0xffff;
3293 case 0x0e: /* RCR1 */
3294 s
->rcr
[0] = value
& 0x7fe0;
3296 case 0x10: /* XCR2 */
3297 s
->xcr
[1] = value
& 0xffff;
3299 case 0x12: /* XCR1 */
3300 s
->xcr
[0] = value
& 0x7fe0;
3302 case 0x14: /* SRGR2 */
3303 s
->srgr
[1] = value
& 0xffff;
3304 omap_mcbsp_req_update(s
);
3306 case 0x16: /* SRGR1 */
3307 s
->srgr
[0] = value
& 0xffff;
3308 omap_mcbsp_req_update(s
);
3310 case 0x18: /* MCR2 */
3311 s
->mcr
[1] = value
& 0x03e3;
3312 if (value
& 3) /* XMCM */
3313 printf("%s: Tx channel selection mode enable attempt\n",
3316 case 0x1a: /* MCR1 */
3317 s
->mcr
[0] = value
& 0x03e1;
3318 if (value
& 1) /* RMCM */
3319 printf("%s: Rx channel selection mode enable attempt\n",
3322 case 0x1c: /* RCERA */
3323 s
->rcer
[0] = value
& 0xffff;
3325 case 0x1e: /* RCERB */
3326 s
->rcer
[1] = value
& 0xffff;
3328 case 0x20: /* XCERA */
3329 s
->xcer
[0] = value
& 0xffff;
3331 case 0x22: /* XCERB */
3332 s
->xcer
[1] = value
& 0xffff;
3334 case 0x24: /* PCR0 */
3335 s
->pcr
= value
& 0x7faf;
3337 case 0x26: /* RCERC */
3338 s
->rcer
[2] = value
& 0xffff;
3340 case 0x28: /* RCERD */
3341 s
->rcer
[3] = value
& 0xffff;
3343 case 0x2a: /* XCERC */
3344 s
->xcer
[2] = value
& 0xffff;
3346 case 0x2c: /* XCERD */
3347 s
->xcer
[3] = value
& 0xffff;
3349 case 0x2e: /* RCERE */
3350 s
->rcer
[4] = value
& 0xffff;
3352 case 0x30: /* RCERF */
3353 s
->rcer
[5] = value
& 0xffff;
3355 case 0x32: /* XCERE */
3356 s
->xcer
[4] = value
& 0xffff;
3358 case 0x34: /* XCERF */
3359 s
->xcer
[5] = value
& 0xffff;
3361 case 0x36: /* RCERG */
3362 s
->rcer
[6] = value
& 0xffff;
3364 case 0x38: /* RCERH */
3365 s
->rcer
[7] = value
& 0xffff;
3367 case 0x3a: /* XCERG */
3368 s
->xcer
[6] = value
& 0xffff;
3370 case 0x3c: /* XCERH */
3371 s
->xcer
[7] = value
& 0xffff;
3378 static void omap_mcbsp_writew(void *opaque
, hwaddr addr
,
3381 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3382 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3384 if (offset
== 0x04) { /* DXR */
3385 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
3387 if (s
->tx_req
> 3) {
3389 if (s
->codec
&& s
->codec
->cts
) {
3390 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3391 (value
>> 24) & 0xff;
3392 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3393 (value
>> 16) & 0xff;
3394 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3395 (value
>> 8) & 0xff;
3396 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
3397 (value
>> 0) & 0xff;
3400 omap_mcbsp_tx_done(s
);
3402 printf("%s: Tx FIFO overrun\n", __FUNCTION__
);
3406 omap_badwidth_write16(opaque
, addr
, value
);
3409 static void omap_mcbsp_write(void *opaque
, hwaddr addr
,
3410 uint64_t value
, unsigned size
)
3413 case 2: return omap_mcbsp_writeh(opaque
, addr
, value
);
3414 case 4: return omap_mcbsp_writew(opaque
, addr
, value
);
3415 default: return omap_badwidth_write16(opaque
, addr
, value
);
3419 static const MemoryRegionOps omap_mcbsp_ops
= {
3420 .read
= omap_mcbsp_read
,
3421 .write
= omap_mcbsp_write
,
3422 .endianness
= DEVICE_NATIVE_ENDIAN
,
3425 static void omap_mcbsp_reset(struct omap_mcbsp_s
*s
)
3427 memset(&s
->spcr
, 0, sizeof(s
->spcr
));
3428 memset(&s
->rcr
, 0, sizeof(s
->rcr
));
3429 memset(&s
->xcr
, 0, sizeof(s
->xcr
));
3430 s
->srgr
[0] = 0x0001;
3431 s
->srgr
[1] = 0x2000;
3432 memset(&s
->mcr
, 0, sizeof(s
->mcr
));
3433 memset(&s
->pcr
, 0, sizeof(s
->pcr
));
3434 memset(&s
->rcer
, 0, sizeof(s
->rcer
));
3435 memset(&s
->xcer
, 0, sizeof(s
->xcer
));
3440 timer_del(s
->source_timer
);
3441 timer_del(s
->sink_timer
);
3444 static struct omap_mcbsp_s
*omap_mcbsp_init(MemoryRegion
*system_memory
,
3446 qemu_irq txirq
, qemu_irq rxirq
,
3447 qemu_irq
*dma
, omap_clk clk
)
3449 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*)
3450 g_malloc0(sizeof(struct omap_mcbsp_s
));
3456 s
->sink_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_sink_tick
, s
);
3457 s
->source_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, omap_mcbsp_source_tick
, s
);
3458 omap_mcbsp_reset(s
);
3460 memory_region_init_io(&s
->iomem
, NULL
, &omap_mcbsp_ops
, s
, "omap-mcbsp", 0x800);
3461 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3466 static void omap_mcbsp_i2s_swallow(void *opaque
, int line
, int level
)
3468 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3471 s
->rx_req
= s
->codec
->in
.len
;
3472 omap_mcbsp_rx_newdata(s
);
3476 static void omap_mcbsp_i2s_start(void *opaque
, int line
, int level
)
3478 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3481 s
->tx_req
= s
->codec
->out
.size
;
3482 omap_mcbsp_tx_newdata(s
);
3486 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, I2SCodec
*slave
)
3489 slave
->rx_swallow
= qemu_allocate_irq(omap_mcbsp_i2s_swallow
, s
, 0);
3490 slave
->tx_start
= qemu_allocate_irq(omap_mcbsp_i2s_start
, s
, 0);
3493 /* LED Pulse Generators */
3506 static void omap_lpg_tick(void *opaque
)
3508 struct omap_lpg_s
*s
= opaque
;
3511 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->period
- s
->on
);
3513 timer_mod(s
->tm
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + s
->on
);
3515 s
->cycle
= !s
->cycle
;
3516 printf("%s: LED is %s\n", __FUNCTION__
, s
->cycle
? "on" : "off");
3519 static void omap_lpg_update(struct omap_lpg_s
*s
)
3521 int64_t on
, period
= 1, ticks
= 1000;
3522 static const int per
[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
3524 if (~s
->control
& (1 << 6)) /* LPGRES */
3526 else if (s
->control
& (1 << 7)) /* PERM_ON */
3529 period
= muldiv64(ticks
, per
[s
->control
& 7], /* PERCTRL */
3531 on
= (s
->clk
&& s
->power
) ? muldiv64(ticks
,
3532 per
[(s
->control
>> 3) & 7], 256) : 0; /* ONCTRL */
3536 if (on
== period
&& s
->on
< s
->period
)
3537 printf("%s: LED is on\n", __FUNCTION__
);
3538 else if (on
== 0 && s
->on
)
3539 printf("%s: LED is off\n", __FUNCTION__
);
3540 else if (on
&& (on
!= s
->on
|| period
!= s
->period
)) {
3552 static void omap_lpg_reset(struct omap_lpg_s
*s
)
3560 static uint64_t omap_lpg_read(void *opaque
, hwaddr addr
,
3563 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3564 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3567 return omap_badwidth_read8(opaque
, addr
);
3571 case 0x00: /* LCR */
3574 case 0x04: /* PMR */
3582 static void omap_lpg_write(void *opaque
, hwaddr addr
,
3583 uint64_t value
, unsigned size
)
3585 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3586 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3589 return omap_badwidth_write8(opaque
, addr
, value
);
3593 case 0x00: /* LCR */
3594 if (~value
& (1 << 6)) /* LPGRES */
3596 s
->control
= value
& 0xff;
3600 case 0x04: /* PMR */
3601 s
->power
= value
& 0x01;
3611 static const MemoryRegionOps omap_lpg_ops
= {
3612 .read
= omap_lpg_read
,
3613 .write
= omap_lpg_write
,
3614 .endianness
= DEVICE_NATIVE_ENDIAN
,
3617 static void omap_lpg_clk_update(void *opaque
, int line
, int on
)
3619 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
3625 static struct omap_lpg_s
*omap_lpg_init(MemoryRegion
*system_memory
,
3626 hwaddr base
, omap_clk clk
)
3628 struct omap_lpg_s
*s
= (struct omap_lpg_s
*)
3629 g_malloc0(sizeof(struct omap_lpg_s
));
3631 s
->tm
= timer_new_ms(QEMU_CLOCK_VIRTUAL
, omap_lpg_tick
, s
);
3635 memory_region_init_io(&s
->iomem
, NULL
, &omap_lpg_ops
, s
, "omap-lpg", 0x800);
3636 memory_region_add_subregion(system_memory
, base
, &s
->iomem
);
3638 omap_clk_adduser(clk
, qemu_allocate_irq(omap_lpg_clk_update
, s
, 0));
3643 /* MPUI Peripheral Bridge configuration */
3644 static uint64_t omap_mpui_io_read(void *opaque
, hwaddr addr
,
3648 return omap_badwidth_read16(opaque
, addr
);
3651 if (addr
== OMAP_MPUI_BASE
) /* CMR */
3658 static void omap_mpui_io_write(void *opaque
, hwaddr addr
,
3659 uint64_t value
, unsigned size
)
3661 /* FIXME: infinite loop */
3662 omap_badwidth_write16(opaque
, addr
, value
);
3665 static const MemoryRegionOps omap_mpui_io_ops
= {
3666 .read
= omap_mpui_io_read
,
3667 .write
= omap_mpui_io_write
,
3668 .endianness
= DEVICE_NATIVE_ENDIAN
,
3671 static void omap_setup_mpui_io(MemoryRegion
*system_memory
,
3672 struct omap_mpu_state_s
*mpu
)
3674 memory_region_init_io(&mpu
->mpui_io_iomem
, NULL
, &omap_mpui_io_ops
, mpu
,
3675 "omap-mpui-io", 0x7fff);
3676 memory_region_add_subregion(system_memory
, OMAP_MPUI_BASE
,
3677 &mpu
->mpui_io_iomem
);
3680 /* General chip reset */
3681 static void omap1_mpu_reset(void *opaque
)
3683 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3685 omap_dma_reset(mpu
->dma
);
3686 omap_mpu_timer_reset(mpu
->timer
[0]);
3687 omap_mpu_timer_reset(mpu
->timer
[1]);
3688 omap_mpu_timer_reset(mpu
->timer
[2]);
3689 omap_wd_timer_reset(mpu
->wdt
);
3690 omap_os_timer_reset(mpu
->os_timer
);
3691 omap_lcdc_reset(mpu
->lcd
);
3692 omap_ulpd_pm_reset(mpu
);
3693 omap_pin_cfg_reset(mpu
);
3694 omap_mpui_reset(mpu
);
3695 omap_tipb_bridge_reset(mpu
->private_tipb
);
3696 omap_tipb_bridge_reset(mpu
->public_tipb
);
3697 omap_dpll_reset(mpu
->dpll
[0]);
3698 omap_dpll_reset(mpu
->dpll
[1]);
3699 omap_dpll_reset(mpu
->dpll
[2]);
3700 omap_uart_reset(mpu
->uart
[0]);
3701 omap_uart_reset(mpu
->uart
[1]);
3702 omap_uart_reset(mpu
->uart
[2]);
3703 omap_mmc_reset(mpu
->mmc
);
3704 omap_mpuio_reset(mpu
->mpuio
);
3705 omap_uwire_reset(mpu
->microwire
);
3706 omap_pwl_reset(mpu
->pwl
);
3707 omap_pwt_reset(mpu
->pwt
);
3708 omap_rtc_reset(mpu
->rtc
);
3709 omap_mcbsp_reset(mpu
->mcbsp1
);
3710 omap_mcbsp_reset(mpu
->mcbsp2
);
3711 omap_mcbsp_reset(mpu
->mcbsp3
);
3712 omap_lpg_reset(mpu
->led
[0]);
3713 omap_lpg_reset(mpu
->led
[1]);
3714 omap_clkm_reset(mpu
);
3715 cpu_reset(CPU(mpu
->cpu
));
3718 static const struct omap_map_s
{
3723 } omap15xx_dsp_mm
[] = {
3725 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
3726 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
3727 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
3728 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
3729 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
3730 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
3731 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
3732 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
3733 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
3734 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
3735 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
3736 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
3737 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
3738 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
3739 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
3740 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
3741 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
3743 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
3748 static void omap_setup_dsp_mapping(MemoryRegion
*system_memory
,
3749 const struct omap_map_s
*map
)
3753 for (; map
->phys_dsp
; map
++) {
3754 io
= g_new(MemoryRegion
, 1);
3755 memory_region_init_alias(io
, NULL
, map
->name
,
3756 system_memory
, map
->phys_mpu
, map
->size
);
3757 memory_region_add_subregion(system_memory
, map
->phys_dsp
, io
);
3761 void omap_mpu_wakeup(void *opaque
, int irq
, int req
)
3763 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
3764 CPUState
*cpu
= CPU(mpu
->cpu
);
3767 cpu_interrupt(cpu
, CPU_INTERRUPT_EXITTB
);
3771 static const struct dma_irq_map omap1_dma_irq_map
[] = {
3772 { 0, OMAP_INT_DMA_CH0_6
},
3773 { 0, OMAP_INT_DMA_CH1_7
},
3774 { 0, OMAP_INT_DMA_CH2_8
},
3775 { 0, OMAP_INT_DMA_CH3
},
3776 { 0, OMAP_INT_DMA_CH4
},
3777 { 0, OMAP_INT_DMA_CH5
},
3778 { 1, OMAP_INT_1610_DMA_CH6
},
3779 { 1, OMAP_INT_1610_DMA_CH7
},
3780 { 1, OMAP_INT_1610_DMA_CH8
},
3781 { 1, OMAP_INT_1610_DMA_CH9
},
3782 { 1, OMAP_INT_1610_DMA_CH10
},
3783 { 1, OMAP_INT_1610_DMA_CH11
},
3784 { 1, OMAP_INT_1610_DMA_CH12
},
3785 { 1, OMAP_INT_1610_DMA_CH13
},
3786 { 1, OMAP_INT_1610_DMA_CH14
},
3787 { 1, OMAP_INT_1610_DMA_CH15
}
3790 /* DMA ports for OMAP1 */
3791 static int omap_validate_emiff_addr(struct omap_mpu_state_s
*s
,
3794 return range_covers_byte(OMAP_EMIFF_BASE
, s
->sdram_size
, addr
);
3797 static int omap_validate_emifs_addr(struct omap_mpu_state_s
*s
,
3800 return range_covers_byte(OMAP_EMIFS_BASE
, OMAP_EMIFF_BASE
- OMAP_EMIFS_BASE
,
3804 static int omap_validate_imif_addr(struct omap_mpu_state_s
*s
,
3807 return range_covers_byte(OMAP_IMIF_BASE
, s
->sram_size
, addr
);
3810 static int omap_validate_tipb_addr(struct omap_mpu_state_s
*s
,
3813 return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr
);
3816 static int omap_validate_local_addr(struct omap_mpu_state_s
*s
,
3819 return range_covers_byte(OMAP_LOCALBUS_BASE
, 0x1000000, addr
);
3822 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s
*s
,
3825 return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr
);
3828 struct omap_mpu_state_s
*omap310_mpu_init(MemoryRegion
*system_memory
,
3829 unsigned long sdram_size
,
3833 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*)
3834 g_malloc0(sizeof(struct omap_mpu_state_s
));
3835 qemu_irq dma_irqs
[6];
3837 SysBusDevice
*busdev
;
3843 s
->mpu_model
= omap310
;
3844 s
->cpu
= cpu_arm_init(core
);
3845 if (s
->cpu
== NULL
) {
3846 fprintf(stderr
, "Unable to find CPU definition\n");
3849 s
->sdram_size
= sdram_size
;
3850 s
->sram_size
= OMAP15XX_SRAM_SIZE
;
3852 s
->wakeup
= qemu_allocate_irq(omap_mpu_wakeup
, s
, 0);
3857 /* Memory-mapped stuff */
3858 memory_region_init_ram(&s
->emiff_ram
, NULL
, "omap1.dram", s
->sdram_size
,
3860 vmstate_register_ram_global(&s
->emiff_ram
);
3861 memory_region_add_subregion(system_memory
, OMAP_EMIFF_BASE
, &s
->emiff_ram
);
3862 memory_region_init_ram(&s
->imif_ram
, NULL
, "omap1.sram", s
->sram_size
,
3864 vmstate_register_ram_global(&s
->imif_ram
);
3865 memory_region_add_subregion(system_memory
, OMAP_IMIF_BASE
, &s
->imif_ram
);
3867 omap_clkm_init(system_memory
, 0xfffece00, 0xe1008000, s
);
3869 s
->ih
[0] = qdev_create(NULL
, "omap-intc");
3870 qdev_prop_set_uint32(s
->ih
[0], "size", 0x100);
3871 qdev_prop_set_ptr(s
->ih
[0], "clk", omap_findclk(s
, "arminth_ck"));
3872 qdev_init_nofail(s
->ih
[0]);
3873 busdev
= SYS_BUS_DEVICE(s
->ih
[0]);
3874 sysbus_connect_irq(busdev
, 0,
3875 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
));
3876 sysbus_connect_irq(busdev
, 1,
3877 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
));
3878 sysbus_mmio_map(busdev
, 0, 0xfffecb00);
3879 s
->ih
[1] = qdev_create(NULL
, "omap-intc");
3880 qdev_prop_set_uint32(s
->ih
[1], "size", 0x800);
3881 qdev_prop_set_ptr(s
->ih
[1], "clk", omap_findclk(s
, "arminth_ck"));
3882 qdev_init_nofail(s
->ih
[1]);
3883 busdev
= SYS_BUS_DEVICE(s
->ih
[1]);
3884 sysbus_connect_irq(busdev
, 0,
3885 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_15XX_IH2_IRQ
));
3886 /* The second interrupt controller's FIQ output is not wired up */
3887 sysbus_mmio_map(busdev
, 0, 0xfffe0000);
3889 for (i
= 0; i
< 6; i
++) {
3890 dma_irqs
[i
] = qdev_get_gpio_in(s
->ih
[omap1_dma_irq_map
[i
].ih
],
3891 omap1_dma_irq_map
[i
].intr
);
3893 s
->dma
= omap_dma_init(0xfffed800, dma_irqs
, system_memory
,
3894 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_DMA_LCD
),
3895 s
, omap_findclk(s
, "dma_ck"), omap_dma_3_1
);
3897 s
->port
[emiff
].addr_valid
= omap_validate_emiff_addr
;
3898 s
->port
[emifs
].addr_valid
= omap_validate_emifs_addr
;
3899 s
->port
[imif
].addr_valid
= omap_validate_imif_addr
;
3900 s
->port
[tipb
].addr_valid
= omap_validate_tipb_addr
;
3901 s
->port
[local
].addr_valid
= omap_validate_local_addr
;
3902 s
->port
[tipb_mpui
].addr_valid
= omap_validate_tipb_mpui_addr
;
3904 /* Register SDRAM and SRAM DMA ports for fast transfers. */
3905 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->emiff_ram
),
3906 OMAP_EMIFF_BASE
, s
->sdram_size
);
3907 soc_dma_port_add_mem(s
->dma
, memory_region_get_ram_ptr(&s
->imif_ram
),
3908 OMAP_IMIF_BASE
, s
->sram_size
);
3910 s
->timer
[0] = omap_mpu_timer_init(system_memory
, 0xfffec500,
3911 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER1
),
3912 omap_findclk(s
, "mputim_ck"));
3913 s
->timer
[1] = omap_mpu_timer_init(system_memory
, 0xfffec600,
3914 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER2
),
3915 omap_findclk(s
, "mputim_ck"));
3916 s
->timer
[2] = omap_mpu_timer_init(system_memory
, 0xfffec700,
3917 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_TIMER3
),
3918 omap_findclk(s
, "mputim_ck"));
3920 s
->wdt
= omap_wd_timer_init(system_memory
, 0xfffec800,
3921 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_WD_TIMER
),
3922 omap_findclk(s
, "armwdt_ck"));
3924 s
->os_timer
= omap_os_timer_init(system_memory
, 0xfffb9000,
3925 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OS_TIMER
),
3926 omap_findclk(s
, "clk32-kHz"));
3928 s
->lcd
= omap_lcdc_init(system_memory
, 0xfffec000,
3929 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_LCD_CTRL
),
3930 omap_dma_get_lcdch(s
->dma
),
3931 omap_findclk(s
, "lcd_ck"));
3933 omap_ulpd_pm_init(system_memory
, 0xfffe0800, s
);
3934 omap_pin_cfg_init(system_memory
, 0xfffe1000, s
);
3935 omap_id_init(system_memory
, s
);
3937 omap_mpui_init(system_memory
, 0xfffec900, s
);
3939 s
->private_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffeca00,
3940 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PRIV
),
3941 omap_findclk(s
, "tipb_ck"));
3942 s
->public_tipb
= omap_tipb_bridge_init(system_memory
, 0xfffed300,
3943 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_BRIDGE_PUB
),
3944 omap_findclk(s
, "tipb_ck"));
3946 omap_tcmi_init(system_memory
, 0xfffecc00, s
);
3948 s
->uart
[0] = omap_uart_init(0xfffb0000,
3949 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART1
),
3950 omap_findclk(s
, "uart1_ck"),
3951 omap_findclk(s
, "uart1_ck"),
3952 s
->drq
[OMAP_DMA_UART1_TX
], s
->drq
[OMAP_DMA_UART1_RX
],
3955 s
->uart
[1] = omap_uart_init(0xfffb0800,
3956 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_UART2
),
3957 omap_findclk(s
, "uart2_ck"),
3958 omap_findclk(s
, "uart2_ck"),
3959 s
->drq
[OMAP_DMA_UART2_TX
], s
->drq
[OMAP_DMA_UART2_RX
],
3961 serial_hds
[0] ? serial_hds
[1] : NULL
);
3962 s
->uart
[2] = omap_uart_init(0xfffb9800,
3963 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_UART3
),
3964 omap_findclk(s
, "uart3_ck"),
3965 omap_findclk(s
, "uart3_ck"),
3966 s
->drq
[OMAP_DMA_UART3_TX
], s
->drq
[OMAP_DMA_UART3_RX
],
3968 serial_hds
[0] && serial_hds
[1] ? serial_hds
[2] : NULL
);
3970 s
->dpll
[0] = omap_dpll_init(system_memory
, 0xfffecf00,
3971 omap_findclk(s
, "dpll1"));
3972 s
->dpll
[1] = omap_dpll_init(system_memory
, 0xfffed000,
3973 omap_findclk(s
, "dpll2"));
3974 s
->dpll
[2] = omap_dpll_init(system_memory
, 0xfffed100,
3975 omap_findclk(s
, "dpll3"));
3977 dinfo
= drive_get(IF_SD
, 0, 0);
3979 fprintf(stderr
, "qemu: missing SecureDigital device\n");
3982 s
->mmc
= omap_mmc_init(0xfffb7800, system_memory
,
3983 blk_by_legacy_dinfo(dinfo
),
3984 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_OQN
),
3985 &s
->drq
[OMAP_DMA_MMC_TX
],
3986 omap_findclk(s
, "mmc_ck"));
3988 s
->mpuio
= omap_mpuio_init(system_memory
, 0xfffb5000,
3989 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_KEYBOARD
),
3990 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_MPUIO
),
3991 s
->wakeup
, omap_findclk(s
, "clk32-kHz"));
3993 s
->gpio
= qdev_create(NULL
, "omap-gpio");
3994 qdev_prop_set_int32(s
->gpio
, "mpu_model", s
->mpu_model
);
3995 qdev_prop_set_ptr(s
->gpio
, "clk", omap_findclk(s
, "arm_gpio_ck"));
3996 qdev_init_nofail(s
->gpio
);
3997 sysbus_connect_irq(SYS_BUS_DEVICE(s
->gpio
), 0,
3998 qdev_get_gpio_in(s
->ih
[0], OMAP_INT_GPIO_BANK1
));
3999 sysbus_mmio_map(SYS_BUS_DEVICE(s
->gpio
), 0, 0xfffce000);
4001 s
->microwire
= omap_uwire_init(system_memory
, 0xfffb3000,
4002 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireTX
),
4003 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_uWireRX
),
4004 s
->drq
[OMAP_DMA_UWIRE_TX
], omap_findclk(s
, "mpuper_ck"));
4006 s
->pwl
= omap_pwl_init(system_memory
, 0xfffb5800,
4007 omap_findclk(s
, "armxor_ck"));
4008 s
->pwt
= omap_pwt_init(system_memory
, 0xfffb6000,
4009 omap_findclk(s
, "armxor_ck"));
4011 s
->i2c
[0] = qdev_create(NULL
, "omap_i2c");
4012 qdev_prop_set_uint8(s
->i2c
[0], "revision", 0x11);
4013 qdev_prop_set_ptr(s
->i2c
[0], "fclk", omap_findclk(s
, "mpuper_ck"));
4014 qdev_init_nofail(s
->i2c
[0]);
4015 busdev
= SYS_BUS_DEVICE(s
->i2c
[0]);
4016 sysbus_connect_irq(busdev
, 0, qdev_get_gpio_in(s
->ih
[1], OMAP_INT_I2C
));
4017 sysbus_connect_irq(busdev
, 1, s
->drq
[OMAP_DMA_I2C_TX
]);
4018 sysbus_connect_irq(busdev
, 2, s
->drq
[OMAP_DMA_I2C_RX
]);
4019 sysbus_mmio_map(busdev
, 0, 0xfffb3800);
4021 s
->rtc
= omap_rtc_init(system_memory
, 0xfffb4800,
4022 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_TIMER
),
4023 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_RTC_ALARM
),
4024 omap_findclk(s
, "clk32-kHz"));
4026 s
->mcbsp1
= omap_mcbsp_init(system_memory
, 0xfffb1800,
4027 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1TX
),
4028 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP1RX
),
4029 &s
->drq
[OMAP_DMA_MCBSP1_TX
], omap_findclk(s
, "dspxor_ck"));
4030 s
->mcbsp2
= omap_mcbsp_init(system_memory
, 0xfffb1000,
4031 qdev_get_gpio_in(s
->ih
[0],
4032 OMAP_INT_310_McBSP2_TX
),
4033 qdev_get_gpio_in(s
->ih
[0],
4034 OMAP_INT_310_McBSP2_RX
),
4035 &s
->drq
[OMAP_DMA_MCBSP2_TX
], omap_findclk(s
, "mpuper_ck"));
4036 s
->mcbsp3
= omap_mcbsp_init(system_memory
, 0xfffb7000,
4037 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3TX
),
4038 qdev_get_gpio_in(s
->ih
[1], OMAP_INT_McBSP3RX
),
4039 &s
->drq
[OMAP_DMA_MCBSP3_TX
], omap_findclk(s
, "dspxor_ck"));
4041 s
->led
[0] = omap_lpg_init(system_memory
,
4042 0xfffbd000, omap_findclk(s
, "clk32-kHz"));
4043 s
->led
[1] = omap_lpg_init(system_memory
,
4044 0xfffbd800, omap_findclk(s
, "clk32-kHz"));
4046 /* Register mappings not currenlty implemented:
4047 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4048 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4049 * USB W2FC fffb4000 - fffb47ff
4050 * Camera Interface fffb6800 - fffb6fff
4051 * USB Host fffba000 - fffba7ff
4052 * FAC fffba800 - fffbafff
4053 * HDQ/1-Wire fffbc000 - fffbc7ff
4054 * TIPB switches fffbc800 - fffbcfff
4055 * Mailbox fffcf000 - fffcf7ff
4056 * Local bus IF fffec100 - fffec1ff
4057 * Local bus MMU fffec200 - fffec2ff
4058 * DSP MMU fffed200 - fffed2ff
4061 omap_setup_dsp_mapping(system_memory
, omap15xx_dsp_mm
);
4062 omap_setup_mpui_io(system_memory
, s
);
4064 qemu_register_reset(omap1_mpu_reset
, s
);