2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 #define HW_MOUSE_ACCEL
39 struct vmsvga_state_s
{
61 ram_addr_t vram_offset
;
64 target_phys_addr_t vram_base
;
81 struct __attribute__((__packed__
)) {
86 /* Add registers here when adding capabilities. */
91 #define REDRAW_FIFO_LEN 512
92 struct vmsvga_rect_s
{
94 } redraw_fifo
[REDRAW_FIFO_LEN
];
95 int redraw_fifo_first
, redraw_fifo_last
;
98 struct pci_vmsvga_state_s
{
100 struct vmsvga_state_s chip
;
103 #define SVGA_MAGIC 0x900000UL
104 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
105 #define SVGA_ID_0 SVGA_MAKE_ID(0)
106 #define SVGA_ID_1 SVGA_MAKE_ID(1)
107 #define SVGA_ID_2 SVGA_MAKE_ID(2)
109 #define SVGA_LEGACY_BASE_PORT 0x4560
110 #define SVGA_INDEX_PORT 0x0
111 #define SVGA_VALUE_PORT 0x1
112 #define SVGA_BIOS_PORT 0x2
114 #define SVGA_VERSION_2
116 #ifdef SVGA_VERSION_2
117 # define SVGA_ID SVGA_ID_2
118 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
119 # define SVGA_IO_MUL 1
120 # define SVGA_FIFO_SIZE 0x10000
121 # define SVGA_MEM_BASE 0xe0000000
122 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
124 # define SVGA_ID SVGA_ID_1
125 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
126 # define SVGA_IO_MUL 4
127 # define SVGA_FIFO_SIZE 0x10000
128 # define SVGA_MEM_BASE 0xe0000000
129 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
133 /* ID 0, 1 and 2 registers */
138 SVGA_REG_MAX_WIDTH
= 4,
139 SVGA_REG_MAX_HEIGHT
= 5,
141 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
142 SVGA_REG_PSEUDOCOLOR
= 8,
143 SVGA_REG_RED_MASK
= 9,
144 SVGA_REG_GREEN_MASK
= 10,
145 SVGA_REG_BLUE_MASK
= 11,
146 SVGA_REG_BYTES_PER_LINE
= 12,
147 SVGA_REG_FB_START
= 13,
148 SVGA_REG_FB_OFFSET
= 14,
149 SVGA_REG_VRAM_SIZE
= 15,
150 SVGA_REG_FB_SIZE
= 16,
152 /* ID 1 and 2 registers */
153 SVGA_REG_CAPABILITIES
= 17,
154 SVGA_REG_MEM_START
= 18, /* Memory for command FIFO */
155 SVGA_REG_MEM_SIZE
= 19,
156 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
157 SVGA_REG_SYNC
= 21, /* Write to force synchronization */
158 SVGA_REG_BUSY
= 22, /* Read to check if sync is done */
159 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
160 SVGA_REG_CURSOR_ID
= 24, /* ID of cursor */
161 SVGA_REG_CURSOR_X
= 25, /* Set cursor X position */
162 SVGA_REG_CURSOR_Y
= 26, /* Set cursor Y position */
163 SVGA_REG_CURSOR_ON
= 27, /* Turn cursor on/off */
164 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* Current bpp in the host */
165 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
166 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
167 SVGA_REG_NUM_DISPLAYS
= 31, /* Number of guest displays */
168 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
170 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
171 SVGA_PALETTE_END
= SVGA_PALETTE_BASE
+ 767,
172 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ 768,
175 #define SVGA_CAP_NONE 0
176 #define SVGA_CAP_RECT_FILL (1 << 0)
177 #define SVGA_CAP_RECT_COPY (1 << 1)
178 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
179 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
180 #define SVGA_CAP_RASTER_OP (1 << 4)
181 #define SVGA_CAP_CURSOR (1 << 5)
182 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
183 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
184 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
185 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
186 #define SVGA_CAP_GLYPH (1 << 10)
187 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
188 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
189 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
190 #define SVGA_CAP_3D (1 << 14)
191 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
192 #define SVGA_CAP_MULTIMON (1 << 16)
193 #define SVGA_CAP_PITCHLOCK (1 << 17)
196 * FIFO offsets (seen as an array of 32-bit words)
200 * The original defined FIFO offsets
203 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
208 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
210 SVGA_FIFO_CAPABILITIES
= 4,
213 SVGA_FIFO_3D_HWVERSION
,
217 #define SVGA_FIFO_CAP_NONE 0
218 #define SVGA_FIFO_CAP_FENCE (1 << 0)
219 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
220 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
222 #define SVGA_FIFO_FLAG_NONE 0
223 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
225 /* These values can probably be changed arbitrarily. */
226 #define SVGA_SCRATCH_SIZE 0x8000
227 #define SVGA_MAX_WIDTH 2360
228 #define SVGA_MAX_HEIGHT 1770
231 # define GUEST_OS_BASE 0x5001
232 static const char *vmsvga_guest_id
[] = {
234 [0x01] = "Windows 3.1",
235 [0x02] = "Windows 95",
236 [0x03] = "Windows 98",
237 [0x04] = "Windows ME",
238 [0x05] = "Windows NT",
239 [0x06] = "Windows 2000",
242 [0x09] = "an unknown OS",
245 [0x0c] = "an unknown OS",
246 [0x0d] = "an unknown OS",
247 [0x0e] = "an unknown OS",
248 [0x0f] = "an unknown OS",
249 [0x10] = "an unknown OS",
250 [0x11] = "an unknown OS",
251 [0x12] = "an unknown OS",
252 [0x13] = "an unknown OS",
253 [0x14] = "an unknown OS",
254 [0x15] = "Windows 2003",
259 SVGA_CMD_INVALID_CMD
= 0,
261 SVGA_CMD_RECT_FILL
= 2,
262 SVGA_CMD_RECT_COPY
= 3,
263 SVGA_CMD_DEFINE_BITMAP
= 4,
264 SVGA_CMD_DEFINE_BITMAP_SCANLINE
= 5,
265 SVGA_CMD_DEFINE_PIXMAP
= 6,
266 SVGA_CMD_DEFINE_PIXMAP_SCANLINE
= 7,
267 SVGA_CMD_RECT_BITMAP_FILL
= 8,
268 SVGA_CMD_RECT_PIXMAP_FILL
= 9,
269 SVGA_CMD_RECT_BITMAP_COPY
= 10,
270 SVGA_CMD_RECT_PIXMAP_COPY
= 11,
271 SVGA_CMD_FREE_OBJECT
= 12,
272 SVGA_CMD_RECT_ROP_FILL
= 13,
273 SVGA_CMD_RECT_ROP_COPY
= 14,
274 SVGA_CMD_RECT_ROP_BITMAP_FILL
= 15,
275 SVGA_CMD_RECT_ROP_PIXMAP_FILL
= 16,
276 SVGA_CMD_RECT_ROP_BITMAP_COPY
= 17,
277 SVGA_CMD_RECT_ROP_PIXMAP_COPY
= 18,
278 SVGA_CMD_DEFINE_CURSOR
= 19,
279 SVGA_CMD_DISPLAY_CURSOR
= 20,
280 SVGA_CMD_MOVE_CURSOR
= 21,
281 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
282 SVGA_CMD_DRAW_GLYPH
= 23,
283 SVGA_CMD_DRAW_GLYPH_CLIPPED
= 24,
284 SVGA_CMD_UPDATE_VERBOSE
= 25,
285 SVGA_CMD_SURFACE_FILL
= 26,
286 SVGA_CMD_SURFACE_COPY
= 27,
287 SVGA_CMD_SURFACE_ALPHA_BLEND
= 28,
288 SVGA_CMD_FRONT_ROP_FILL
= 29,
292 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
294 SVGA_CURSOR_ON_HIDE
= 0,
295 SVGA_CURSOR_ON_SHOW
= 1,
296 SVGA_CURSOR_ON_REMOVE_FROM_FB
= 2,
297 SVGA_CURSOR_ON_RESTORE_TO_FB
= 3,
300 static inline void vmsvga_update_rect(struct vmsvga_state_s
*s
,
301 int x
, int y
, int w
, int h
)
311 if (x
+ w
> s
->width
) {
312 fprintf(stderr
, "%s: update width too large x: %d, w: %d\n",
314 x
= MIN(x
, s
->width
);
318 if (y
+ h
> s
->height
) {
319 fprintf(stderr
, "%s: update height too large y: %d, h: %d\n",
321 y
= MIN(y
, s
->height
);
326 bypl
= s
->bypp
* s
->width
;
328 start
= s
->bypp
* x
+ bypl
* y
;
329 src
= s
->vga
.vram_ptr
+ start
;
330 dst
= ds_get_data(s
->vga
.ds
) + start
;
332 for (; line
> 0; line
--, src
+= bypl
, dst
+= bypl
)
333 memcpy(dst
, src
, width
);
336 dpy_update(s
->vga
.ds
, x
, y
, w
, h
);
339 static inline void vmsvga_update_screen(struct vmsvga_state_s
*s
)
342 memcpy(ds_get_data(s
->vga
.ds
), s
->vga
.vram_ptr
, s
->bypp
* s
->width
* s
->height
);
345 dpy_update(s
->vga
.ds
, 0, 0, s
->width
, s
->height
);
349 # define vmsvga_update_rect_delayed vmsvga_update_rect
351 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s
*s
,
352 int x
, int y
, int w
, int h
)
354 struct vmsvga_rect_s
*rect
= &s
->redraw_fifo
[s
->redraw_fifo_last
++];
355 s
->redraw_fifo_last
&= REDRAW_FIFO_LEN
- 1;
363 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s
*s
)
365 struct vmsvga_rect_s
*rect
;
366 if (s
->invalidated
) {
367 s
->redraw_fifo_first
= s
->redraw_fifo_last
;
370 /* Overlapping region updates can be optimised out here - if someone
371 * knows a smart algorithm to do that, please share. */
372 while (s
->redraw_fifo_first
!= s
->redraw_fifo_last
) {
373 rect
= &s
->redraw_fifo
[s
->redraw_fifo_first
++];
374 s
->redraw_fifo_first
&= REDRAW_FIFO_LEN
- 1;
375 vmsvga_update_rect(s
, rect
->x
, rect
->y
, rect
->w
, rect
->h
);
380 static inline void vmsvga_copy_rect(struct vmsvga_state_s
*s
,
381 int x0
, int y0
, int x1
, int y1
, int w
, int h
)
384 uint8_t *vram
= ds_get_data(s
->ds
);
386 uint8_t *vram
= s
->vga
.vram_ptr
;
388 int bypl
= s
->bypp
* s
->width
;
389 int width
= s
->bypp
* w
;
395 qemu_console_copy(s
->ds
, x0
, y0
, x1
, y1
, w
, h
);
400 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* (y0
+ h
- 1);
401 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* (y1
+ h
- 1);
402 for (; line
> 0; line
--, ptr
[0] -= bypl
, ptr
[1] -= bypl
)
403 memmove(ptr
[1], ptr
[0], width
);
405 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* y0
;
406 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* y1
;
407 for (; line
> 0; line
--, ptr
[0] += bypl
, ptr
[1] += bypl
)
408 memmove(ptr
[1], ptr
[0], width
);
412 vmsvga_update_rect_delayed(s
, x1
, y1
, w
, h
);
417 static inline void vmsvga_fill_rect(struct vmsvga_state_s
*s
,
418 uint32_t c
, int x
, int y
, int w
, int h
)
421 uint8_t *vram
= ds_get_data(s
->ds
);
423 uint8_t *vram
= s
->vga
.vram_ptr
;
426 int bypl
= bypp
* s
->width
;
427 int width
= bypp
* w
;
430 uint8_t *fst
= vram
+ bypp
* x
+ bypl
* y
;
437 s
->ds
->dpy_fill(s
->ds
, x
, y
, w
, h
, c
);
449 for (column
= width
; column
> 0; column
--) {
450 *(dst
++) = *(src
++);
451 if (src
- col
== bypp
)
455 for (; line
> 0; line
--) {
457 memcpy(dst
, fst
, width
);
462 vmsvga_update_rect_delayed(s
, x
, y
, w
, h
);
466 struct vmsvga_cursor_definition_s
{
474 uint32_t image
[1024];
477 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
478 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
480 #ifdef HW_MOUSE_ACCEL
481 static inline void vmsvga_cursor_define(struct vmsvga_state_s
*s
,
482 struct vmsvga_cursor_definition_s
*c
)
485 for (i
= SVGA_BITMAP_SIZE(c
->width
, c
->height
) - 1; i
>= 0; i
--)
486 c
->mask
[i
] = ~c
->mask
[i
];
488 if (s
->vga
.ds
->cursor_define
)
489 s
->vga
.ds
->cursor_define(c
->width
, c
->height
, c
->bpp
, c
->hot_x
, c
->hot_y
,
490 (uint8_t *) c
->image
, (uint8_t *) c
->mask
);
494 #define CMD(f) le32_to_cpu(s->cmd->f)
496 static inline int vmsvga_fifo_empty(struct vmsvga_state_s
*s
)
498 if (!s
->config
|| !s
->enable
)
500 return (s
->cmd
->next_cmd
== s
->cmd
->stop
);
503 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s
*s
)
505 uint32_t cmd
= s
->fifo
[CMD(stop
) >> 2];
506 s
->cmd
->stop
= cpu_to_le32(CMD(stop
) + 4);
507 if (CMD(stop
) >= CMD(max
))
508 s
->cmd
->stop
= s
->cmd
->min
;
512 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s
*s
)
514 return le32_to_cpu(vmsvga_fifo_read_raw(s
));
517 static void vmsvga_fifo_run(struct vmsvga_state_s
*s
)
519 uint32_t cmd
, colour
;
521 int x
, y
, dx
, dy
, width
, height
;
522 struct vmsvga_cursor_definition_s cursor
;
523 while (!vmsvga_fifo_empty(s
))
524 switch (cmd
= vmsvga_fifo_read(s
)) {
525 case SVGA_CMD_UPDATE
:
526 case SVGA_CMD_UPDATE_VERBOSE
:
527 x
= vmsvga_fifo_read(s
);
528 y
= vmsvga_fifo_read(s
);
529 width
= vmsvga_fifo_read(s
);
530 height
= vmsvga_fifo_read(s
);
531 vmsvga_update_rect_delayed(s
, x
, y
, width
, height
);
534 case SVGA_CMD_RECT_FILL
:
535 colour
= vmsvga_fifo_read(s
);
536 x
= vmsvga_fifo_read(s
);
537 y
= vmsvga_fifo_read(s
);
538 width
= vmsvga_fifo_read(s
);
539 height
= vmsvga_fifo_read(s
);
541 vmsvga_fill_rect(s
, colour
, x
, y
, width
, height
);
547 case SVGA_CMD_RECT_COPY
:
548 x
= vmsvga_fifo_read(s
);
549 y
= vmsvga_fifo_read(s
);
550 dx
= vmsvga_fifo_read(s
);
551 dy
= vmsvga_fifo_read(s
);
552 width
= vmsvga_fifo_read(s
);
553 height
= vmsvga_fifo_read(s
);
555 vmsvga_copy_rect(s
, x
, y
, dx
, dy
, width
, height
);
561 case SVGA_CMD_DEFINE_CURSOR
:
562 cursor
.id
= vmsvga_fifo_read(s
);
563 cursor
.hot_x
= vmsvga_fifo_read(s
);
564 cursor
.hot_y
= vmsvga_fifo_read(s
);
565 cursor
.width
= x
= vmsvga_fifo_read(s
);
566 cursor
.height
= y
= vmsvga_fifo_read(s
);
568 cursor
.bpp
= vmsvga_fifo_read(s
);
569 for (args
= 0; args
< SVGA_BITMAP_SIZE(x
, y
); args
++)
570 cursor
.mask
[args
] = vmsvga_fifo_read_raw(s
);
571 for (args
= 0; args
< SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
); args
++)
572 cursor
.image
[args
] = vmsvga_fifo_read_raw(s
);
573 #ifdef HW_MOUSE_ACCEL
574 vmsvga_cursor_define(s
, &cursor
);
582 * Other commands that we at least know the number of arguments
583 * for so we can avoid FIFO desync if driver uses them illegally.
585 case SVGA_CMD_DEFINE_ALPHA_CURSOR
:
589 x
= vmsvga_fifo_read(s
);
590 y
= vmsvga_fifo_read(s
);
593 case SVGA_CMD_RECT_ROP_FILL
:
596 case SVGA_CMD_RECT_ROP_COPY
:
599 case SVGA_CMD_DRAW_GLYPH_CLIPPED
:
602 args
= 7 + (vmsvga_fifo_read(s
) >> 2);
604 case SVGA_CMD_SURFACE_ALPHA_BLEND
:
609 * Other commands that are not listed as depending on any
610 * CAPABILITIES bits, but are not described in the README either.
612 case SVGA_CMD_SURFACE_FILL
:
613 case SVGA_CMD_SURFACE_COPY
:
614 case SVGA_CMD_FRONT_ROP_FILL
:
616 case SVGA_CMD_INVALID_CMD
:
623 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
631 static uint32_t vmsvga_index_read(void *opaque
, uint32_t address
)
633 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
637 static void vmsvga_index_write(void *opaque
, uint32_t address
, uint32_t index
)
639 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
643 static uint32_t vmsvga_value_read(void *opaque
, uint32_t address
)
646 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
651 case SVGA_REG_ENABLE
:
657 case SVGA_REG_HEIGHT
:
660 case SVGA_REG_MAX_WIDTH
:
661 return SVGA_MAX_WIDTH
;
663 case SVGA_REG_MAX_HEIGHT
:
664 return SVGA_MAX_HEIGHT
;
669 case SVGA_REG_BITS_PER_PIXEL
:
670 return (s
->depth
+ 7) & ~7;
672 case SVGA_REG_PSEUDOCOLOR
:
675 case SVGA_REG_RED_MASK
:
677 case SVGA_REG_GREEN_MASK
:
679 case SVGA_REG_BLUE_MASK
:
682 case SVGA_REG_BYTES_PER_LINE
:
683 return ((s
->depth
+ 7) >> 3) * s
->new_width
;
685 case SVGA_REG_FB_START
:
688 case SVGA_REG_FB_OFFSET
:
691 case SVGA_REG_VRAM_SIZE
:
692 return s
->vga
.vram_size
- SVGA_FIFO_SIZE
;
694 case SVGA_REG_FB_SIZE
:
697 case SVGA_REG_CAPABILITIES
:
698 caps
= SVGA_CAP_NONE
;
700 caps
|= SVGA_CAP_RECT_COPY
;
703 caps
|= SVGA_CAP_RECT_FILL
;
705 #ifdef HW_MOUSE_ACCEL
706 if (s
->vga
.ds
->mouse_set
)
707 caps
|= SVGA_CAP_CURSOR
| SVGA_CAP_CURSOR_BYPASS_2
|
708 SVGA_CAP_CURSOR_BYPASS
;
712 case SVGA_REG_MEM_START
:
713 return s
->vram_base
+ s
->vga
.vram_size
- SVGA_FIFO_SIZE
;
715 case SVGA_REG_MEM_SIZE
:
716 return SVGA_FIFO_SIZE
;
718 case SVGA_REG_CONFIG_DONE
:
725 case SVGA_REG_GUEST_ID
:
728 case SVGA_REG_CURSOR_ID
:
731 case SVGA_REG_CURSOR_X
:
734 case SVGA_REG_CURSOR_Y
:
737 case SVGA_REG_CURSOR_ON
:
740 case SVGA_REG_HOST_BITS_PER_PIXEL
:
741 return (s
->depth
+ 7) & ~7;
743 case SVGA_REG_SCRATCH_SIZE
:
744 return s
->scratch_size
;
746 case SVGA_REG_MEM_REGS
:
747 case SVGA_REG_NUM_DISPLAYS
:
748 case SVGA_REG_PITCHLOCK
:
749 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
753 if (s
->index
>= SVGA_SCRATCH_BASE
&&
754 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
)
755 return s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
];
756 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
762 static void vmsvga_value_write(void *opaque
, uint32_t address
, uint32_t value
)
764 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
767 if (value
== SVGA_ID_2
|| value
== SVGA_ID_1
|| value
== SVGA_ID_0
)
771 case SVGA_REG_ENABLE
:
773 s
->config
&= !!value
;
778 s
->vga
.invalidate(&s
->vga
);
781 s
->fb_size
= ((s
->depth
+ 7) >> 3) * s
->new_width
* s
->new_height
;
785 s
->new_width
= value
;
789 case SVGA_REG_HEIGHT
:
790 s
->new_height
= value
;
795 case SVGA_REG_BITS_PER_PIXEL
:
796 if (value
!= s
->depth
) {
797 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__
, value
);
802 case SVGA_REG_CONFIG_DONE
:
804 s
->fifo
= (uint32_t *) &s
->vga
.vram_ptr
[s
->vga
.vram_size
- SVGA_FIFO_SIZE
];
805 /* Check range and alignment. */
806 if ((CMD(min
) | CMD(max
) |
807 CMD(next_cmd
) | CMD(stop
)) & 3)
809 if (CMD(min
) < (uint8_t *) s
->cmd
->fifo
- (uint8_t *) s
->fifo
)
811 if (CMD(max
) > SVGA_FIFO_SIZE
)
813 if (CMD(max
) < CMD(min
) + 10 * 1024)
821 vmsvga_fifo_run(s
); /* Or should we just wait for update_display? */
824 case SVGA_REG_GUEST_ID
:
827 if (value
>= GUEST_OS_BASE
&& value
< GUEST_OS_BASE
+
828 ARRAY_SIZE(vmsvga_guest_id
))
829 printf("%s: guest runs %s.\n", __FUNCTION__
,
830 vmsvga_guest_id
[value
- GUEST_OS_BASE
]);
834 case SVGA_REG_CURSOR_ID
:
835 s
->cursor
.id
= value
;
838 case SVGA_REG_CURSOR_X
:
842 case SVGA_REG_CURSOR_Y
:
846 case SVGA_REG_CURSOR_ON
:
847 s
->cursor
.on
|= (value
== SVGA_CURSOR_ON_SHOW
);
848 s
->cursor
.on
&= (value
!= SVGA_CURSOR_ON_HIDE
);
849 #ifdef HW_MOUSE_ACCEL
850 if (s
->vga
.ds
->mouse_set
&& value
<= SVGA_CURSOR_ON_SHOW
)
851 s
->vga
.ds
->mouse_set(s
->cursor
.x
, s
->cursor
.y
, s
->cursor
.on
);
855 case SVGA_REG_MEM_REGS
:
856 case SVGA_REG_NUM_DISPLAYS
:
857 case SVGA_REG_PITCHLOCK
:
858 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
862 if (s
->index
>= SVGA_SCRATCH_BASE
&&
863 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
864 s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
] = value
;
867 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
871 static uint32_t vmsvga_bios_read(void *opaque
, uint32_t address
)
873 printf("%s: what are we supposed to return?\n", __FUNCTION__
);
877 static void vmsvga_bios_write(void *opaque
, uint32_t address
, uint32_t data
)
879 printf("%s: what are we supposed to do with (%08x)?\n",
883 static inline void vmsvga_size(struct vmsvga_state_s
*s
)
885 if (s
->new_width
!= s
->width
|| s
->new_height
!= s
->height
) {
886 s
->width
= s
->new_width
;
887 s
->height
= s
->new_height
;
888 qemu_console_resize(s
->vga
.ds
, s
->width
, s
->height
);
893 static void vmsvga_update_display(void *opaque
)
895 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
898 s
->vga
.update(&s
->vga
);
906 vmsvga_update_rect_flush(s
);
909 * Is it more efficient to look at vram VGA-dirty bits or wait
910 * for the driver to issue SVGA_CMD_UPDATE?
912 if (s
->invalidated
) {
914 vmsvga_update_screen(s
);
918 static void vmsvga_reset(struct vmsvga_state_s
*s
)
927 s
->bypp
= (s
->depth
+ 7) >> 3;
929 s
->redraw_fifo_first
= 0;
930 s
->redraw_fifo_last
= 0;
933 s
->wred
= 0x00000007;
934 s
->wgreen
= 0x00000038;
935 s
->wblue
= 0x000000c0;
938 s
->wred
= 0x0000001f;
939 s
->wgreen
= 0x000003e0;
940 s
->wblue
= 0x00007c00;
943 s
->wred
= 0x0000001f;
944 s
->wgreen
= 0x000007e0;
945 s
->wblue
= 0x0000f800;
948 s
->wred
= 0x00ff0000;
949 s
->wgreen
= 0x0000ff00;
950 s
->wblue
= 0x000000ff;
953 s
->wred
= 0x00ff0000;
954 s
->wgreen
= 0x0000ff00;
955 s
->wblue
= 0x000000ff;
961 static void vmsvga_invalidate_display(void *opaque
)
963 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
966 s
->vga
.invalidate(&s
->vga
);
974 /* save the vga display in a PPM image even if no display is
976 static void vmsvga_screen_dump(void *opaque
, const char *filename
)
978 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
981 s
->vga
.screen_dump(&s
->vga
, filename
);
986 if (s
->depth
== 32) {
987 DisplaySurface
*ds
= qemu_create_displaysurface_from(s
->width
,
988 s
->height
, 32, ds_get_linesize(s
->vga
.ds
), s
->vga
.vram_ptr
);
989 ppm_save(filename
, ds
);
994 static void vmsvga_text_update(void *opaque
, console_ch_t
*chardata
)
996 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
998 if (s
->vga
.text_update
)
999 s
->vga
.text_update(&s
->vga
, chardata
);
1003 static uint32_t vmsvga_vram_readb(void *opaque
, target_phys_addr_t addr
)
1005 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1006 if (addr
< s
->fb_size
)
1007 return *(uint8_t *) (ds_get_data(s
->ds
) + addr
);
1009 return *(uint8_t *) (s
->vram_ptr
+ addr
);
1012 static uint32_t vmsvga_vram_readw(void *opaque
, target_phys_addr_t addr
)
1014 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1015 if (addr
< s
->fb_size
)
1016 return *(uint16_t *) (ds_get_data(s
->ds
) + addr
);
1018 return *(uint16_t *) (s
->vram_ptr
+ addr
);
1021 static uint32_t vmsvga_vram_readl(void *opaque
, target_phys_addr_t addr
)
1023 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1024 if (addr
< s
->fb_size
)
1025 return *(uint32_t *) (ds_get_data(s
->ds
) + addr
);
1027 return *(uint32_t *) (s
->vram_ptr
+ addr
);
1030 static void vmsvga_vram_writeb(void *opaque
, target_phys_addr_t addr
,
1033 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1034 if (addr
< s
->fb_size
)
1035 *(uint8_t *) (ds_get_data(s
->ds
) + addr
) = value
;
1037 *(uint8_t *) (s
->vram_ptr
+ addr
) = value
;
1040 static void vmsvga_vram_writew(void *opaque
, target_phys_addr_t addr
,
1043 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1044 if (addr
< s
->fb_size
)
1045 *(uint16_t *) (ds_get_data(s
->ds
) + addr
) = value
;
1047 *(uint16_t *) (s
->vram_ptr
+ addr
) = value
;
1050 static void vmsvga_vram_writel(void *opaque
, target_phys_addr_t addr
,
1053 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1054 if (addr
< s
->fb_size
)
1055 *(uint32_t *) (ds_get_data(s
->ds
) + addr
) = value
;
1057 *(uint32_t *) (s
->vram_ptr
+ addr
) = value
;
1060 static CPUReadMemoryFunc
* const vmsvga_vram_read
[] = {
1066 static CPUWriteMemoryFunc
* const vmsvga_vram_write
[] = {
1073 static void vmsvga_save(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1075 qemu_put_be32(f
, s
->depth
);
1076 qemu_put_be32(f
, s
->enable
);
1077 qemu_put_be32(f
, s
->config
);
1078 qemu_put_be32(f
, s
->cursor
.id
);
1079 qemu_put_be32(f
, s
->cursor
.x
);
1080 qemu_put_be32(f
, s
->cursor
.y
);
1081 qemu_put_be32(f
, s
->cursor
.on
);
1082 qemu_put_be32(f
, s
->index
);
1083 qemu_put_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1084 qemu_put_be32(f
, s
->new_width
);
1085 qemu_put_be32(f
, s
->new_height
);
1086 qemu_put_be32s(f
, &s
->guest
);
1087 qemu_put_be32s(f
, &s
->svgaid
);
1088 qemu_put_be32(f
, s
->syncing
);
1089 qemu_put_be32(f
, s
->fb_size
);
1092 static int vmsvga_load(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1095 depth
=qemu_get_be32(f
);
1096 s
->enable
=qemu_get_be32(f
);
1097 s
->config
=qemu_get_be32(f
);
1098 s
->cursor
.id
=qemu_get_be32(f
);
1099 s
->cursor
.x
=qemu_get_be32(f
);
1100 s
->cursor
.y
=qemu_get_be32(f
);
1101 s
->cursor
.on
=qemu_get_be32(f
);
1102 s
->index
=qemu_get_be32(f
);
1103 qemu_get_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1104 s
->new_width
=qemu_get_be32(f
);
1105 s
->new_height
=qemu_get_be32(f
);
1106 qemu_get_be32s(f
, &s
->guest
);
1107 qemu_get_be32s(f
, &s
->svgaid
);
1108 s
->syncing
=qemu_get_be32(f
);
1109 s
->fb_size
=qemu_get_be32(f
);
1111 if (s
->enable
&& depth
!= s
->depth
) {
1112 printf("%s: need colour depth of %i bits to resume operation.\n",
1113 __FUNCTION__
, depth
);
1119 s
->fifo
= (uint32_t *) &s
->vga
.vram_ptr
[s
->vga
.vram_size
- SVGA_FIFO_SIZE
];
1124 static void vmsvga_init(struct vmsvga_state_s
*s
, int vga_ram_size
)
1126 s
->scratch_size
= SVGA_SCRATCH_SIZE
;
1127 s
->scratch
= (uint32_t *) qemu_malloc(s
->scratch_size
* 4);
1132 vga_common_init(&s
->vga
, vga_ram_size
);
1134 vmstate_register(0, &vmstate_vga_common
, &s
->vga
);
1136 s
->vram_size
= vga_ram_size
;
1137 s
->vram_offset
= qemu_ram_alloc(vga_ram_size
);
1138 s
->vram_ptr
= qemu_get_ram_ptr(s
->vram_offset
);
1141 s
->vga
.ds
= graphic_console_init(vmsvga_update_display
,
1142 vmsvga_invalidate_display
,
1144 vmsvga_text_update
, s
);
1146 #ifdef CONFIG_BOCHS_VBE
1147 /* XXX: use optimized standard vga accesses */
1148 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS
,
1149 vga_ram_size
, s
->vga
.vram_offset
);
1153 static void pci_vmsvga_save(QEMUFile
*f
, void *opaque
)
1155 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1156 pci_device_save(&s
->card
, f
);
1157 vmsvga_save(&s
->chip
, f
);
1160 static int pci_vmsvga_load(QEMUFile
*f
, void *opaque
, int version_id
)
1162 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1165 ret
= pci_device_load(&s
->card
, f
);
1169 ret
= vmsvga_load(&s
->chip
, f
);
1176 static void pci_vmsvga_map_ioport(PCIDevice
*pci_dev
, int region_num
,
1177 uint32_t addr
, uint32_t size
, int type
)
1179 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1180 struct vmsvga_state_s
*s
= &d
->chip
;
1182 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1183 1, 4, vmsvga_index_read
, s
);
1184 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1185 1, 4, vmsvga_index_write
, s
);
1186 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1187 1, 4, vmsvga_value_read
, s
);
1188 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1189 1, 4, vmsvga_value_write
, s
);
1190 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1191 1, 4, vmsvga_bios_read
, s
);
1192 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1193 1, 4, vmsvga_bios_write
, s
);
1196 static void pci_vmsvga_map_mem(PCIDevice
*pci_dev
, int region_num
,
1197 uint32_t addr
, uint32_t size
, int type
)
1199 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1200 struct vmsvga_state_s
*s
= &d
->chip
;
1201 ram_addr_t iomemtype
;
1203 s
->vram_base
= addr
;
1205 iomemtype
= cpu_register_io_memory(vmsvga_vram_read
,
1206 vmsvga_vram_write
, s
);
1208 iomemtype
= s
->vga
.vram_offset
| IO_MEM_RAM
;
1210 cpu_register_physical_memory(s
->vram_base
, s
->vga
.vram_size
,
1214 static int pci_vmsvga_initfn(PCIDevice
*dev
)
1216 struct pci_vmsvga_state_s
*s
=
1217 DO_UPCAST(struct pci_vmsvga_state_s
, card
, dev
);
1219 pci_config_set_vendor_id(s
->card
.config
, PCI_VENDOR_ID_VMWARE
);
1220 pci_config_set_device_id(s
->card
.config
, SVGA_PCI_DEVICE_ID
);
1221 s
->card
.config
[PCI_COMMAND
] = 0x07; /* I/O + Memory */
1222 pci_config_set_class(s
->card
.config
, PCI_CLASS_DISPLAY_VGA
);
1223 s
->card
.config
[0x0c] = 0x08; /* Cache line size */
1224 s
->card
.config
[0x0d] = 0x40; /* Latency timer */
1225 s
->card
.config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
;
1226 s
->card
.config
[0x2c] = PCI_VENDOR_ID_VMWARE
& 0xff;
1227 s
->card
.config
[0x2d] = PCI_VENDOR_ID_VMWARE
>> 8;
1228 s
->card
.config
[0x2e] = SVGA_PCI_DEVICE_ID
& 0xff;
1229 s
->card
.config
[0x2f] = SVGA_PCI_DEVICE_ID
>> 8;
1230 s
->card
.config
[0x3c] = 0xff; /* End */
1232 pci_register_bar(&s
->card
, 0, 0x10,
1233 PCI_ADDRESS_SPACE_IO
, pci_vmsvga_map_ioport
);
1234 pci_register_bar(&s
->card
, 1, VGA_RAM_SIZE
,
1235 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_vmsvga_map_mem
);
1237 vmsvga_init(&s
->chip
, VGA_RAM_SIZE
);
1239 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save
, pci_vmsvga_load
, s
);
1243 void pci_vmsvga_init(PCIBus
*bus
)
1245 pci_create_simple(bus
, -1, "QEMUware SVGA");
1248 static PCIDeviceInfo vmsvga_info
= {
1249 .qdev
.name
= "QEMUware SVGA",
1250 .qdev
.size
= sizeof(struct pci_vmsvga_state_s
),
1251 .init
= pci_vmsvga_initfn
,
1254 static void vmsvga_register(void)
1256 pci_qdev_register(&vmsvga_info
);
1258 device_init(vmsvga_register
);