hw/sd/pxa2xx_mmci.c

   1 /*
   2  * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "hw/hw.h"
  14 #include "hw/arm/pxa.h"
  15 #include "hw/sd.h"
  16 #include "hw/qdev.h"
  17
  18 struct PXA2xxMMCIState {
  19     MemoryRegion iomem;
  20     qemu_irq irq;
  21     qemu_irq rx_dma;
  22     qemu_irq tx_dma;
  23
  24     SDState *card;
  25
  26     uint32_t status;
  27     uint32_t clkrt;
  28     uint32_t spi;
  29     uint32_t cmdat;
  30     uint32_t resp_tout;
  31     uint32_t read_tout;
  32     int blklen;
  33     int numblk;
  34     uint32_t intmask;
  35     uint32_t intreq;
  36     int cmd;
  37     uint32_t arg;
  38
  39     int active;
  40     int bytesleft;
  41     uint8_t tx_fifo[64];
  42     int tx_start;
  43     int tx_len;
  44     uint8_t rx_fifo[32];
  45     int rx_start;
  46     int rx_len;
  47     uint16_t resp_fifo[9];
  48     int resp_len;
  49
  50     int cmdreq;
  51 };
  52
  53 #define MMC_STRPCL      0x00    /* MMC Clock Start/Stop register */
  54 #define MMC_STAT        0x04    /* MMC Status register */
  55 #define MMC_CLKRT       0x08    /* MMC Clock Rate register */
  56 #define MMC_SPI         0x0c    /* MMC SPI Mode register */
  57 #define MMC_CMDAT       0x10    /* MMC Command/Data register */
  58 #define MMC_RESTO       0x14    /* MMC Response Time-Out register */
  59 #define MMC_RDTO        0x18    /* MMC Read Time-Out register */
  60 #define MMC_BLKLEN      0x1c    /* MMC Block Length register */
  61 #define MMC_NUMBLK      0x20    /* MMC Number of Blocks register */
  62 #define MMC_PRTBUF      0x24    /* MMC Buffer Partly Full register */
  63 #define MMC_I_MASK      0x28    /* MMC Interrupt Mask register */
  64 #define MMC_I_REG       0x2c    /* MMC Interrupt Request register */
  65 #define MMC_CMD         0x30    /* MMC Command register */
  66 #define MMC_ARGH        0x34    /* MMC Argument High register */
  67 #define MMC_ARGL        0x38    /* MMC Argument Low register */
  68 #define MMC_RES         0x3c    /* MMC Response FIFO */
  69 #define MMC_RXFIFO      0x40    /* MMC Receive FIFO */
  70 #define MMC_TXFIFO      0x44    /* MMC Transmit FIFO */
  71 #define MMC_RDWAIT      0x48    /* MMC RD_WAIT register */
  72 #define MMC_BLKS_REM    0x4c    /* MMC Blocks Remaining register */
  73
  74 /* Bitfield masks */
  75 #define STRPCL_STOP_CLK (1 << 0)
  76 #define STRPCL_STRT_CLK (1 << 1)
  77 #define STAT_TOUT_RES   (1 << 1)
  78 #define STAT_CLK_EN     (1 << 8)
  79 #define STAT_DATA_DONE  (1 << 11)
  80 #define STAT_PRG_DONE   (1 << 12)
  81 #define STAT_END_CMDRES (1 << 13)
  82 #define SPI_SPI_MODE    (1 << 0)
  83 #define CMDAT_RES_TYPE  (3 << 0)
  84 #define CMDAT_DATA_EN   (1 << 2)
  85 #define CMDAT_WR_RD     (1 << 3)
  86 #define CMDAT_DMA_EN    (1 << 7)
  87 #define CMDAT_STOP_TRAN (1 << 10)
  88 #define INT_DATA_DONE   (1 << 0)
  89 #define INT_PRG_DONE    (1 << 1)
  90 #define INT_END_CMD     (1 << 2)
  91 #define INT_STOP_CMD    (1 << 3)
  92 #define INT_CLK_OFF     (1 << 4)
  93 #define INT_RXFIFO_REQ  (1 << 5)
  94 #define INT_TXFIFO_REQ  (1 << 6)
  95 #define INT_TINT        (1 << 7)
  96 #define INT_DAT_ERR     (1 << 8)
  97 #define INT_RES_ERR     (1 << 9)
  98 #define INT_RD_STALLED  (1 << 10)
  99 #define INT_SDIO_INT    (1 << 11)
 100 #define INT_SDIO_SACK   (1 << 12)
 101 #define PRTBUF_PRT_BUF  (1 << 0)
 102
 103 /* Route internal interrupt lines to the global IC and DMA */
 104 static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
 105 {
 106     uint32_t mask = s->intmask;
 107     if (s->cmdat & CMDAT_DMA_EN) {
 108         mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
 109
 110         qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
 111         qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
 112     }
 113
 114     qemu_set_irq(s->irq, !!(s->intreq & ~mask));
 115 }
 116
 117 static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
 118 {
 119     if (!s->active)
 120         return;
 121
 122     if (s->cmdat & CMDAT_WR_RD) {
 123         while (s->bytesleft && s->tx_len) {
 124             sd_write_data(s->card, s->tx_fifo[s->tx_start ++]);
 125             s->tx_start &= 0x1f;
 126             s->tx_len --;
 127             s->bytesleft --;
 128         }
 129         if (s->bytesleft)
 130             s->intreq |= INT_TXFIFO_REQ;
 131     } else
 132         while (s->bytesleft && s->rx_len < 32) {
 133             s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
 134                 sd_read_data(s->card);
 135             s->bytesleft --;
 136             s->intreq |= INT_RXFIFO_REQ;
 137         }
 138
 139     if (!s->bytesleft) {
 140         s->active = 0;
 141         s->intreq |= INT_DATA_DONE;
 142         s->status |= STAT_DATA_DONE;
 143
 144         if (s->cmdat & CMDAT_WR_RD) {
 145             s->intreq |= INT_PRG_DONE;
 146             s->status |= STAT_PRG_DONE;
 147         }
 148     }
 149
 150     pxa2xx_mmci_int_update(s);
 151 }
 152
 153 static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
 154 {
 155     int rsplen, i;
 156     SDRequest request;
 157     uint8_t response[16];
 158
 159     s->active = 1;
 160     s->rx_len = 0;
 161     s->tx_len = 0;
 162     s->cmdreq = 0;
 163
 164     request.cmd = s->cmd;
 165     request.arg = s->arg;
 166     request.crc = 0;    /* FIXME */
 167
 168     rsplen = sd_do_command(s->card, &request, response);
 169     s->intreq |= INT_END_CMD;
 170
 171     memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
 172     switch (s->cmdat & CMDAT_RES_TYPE) {
 173 #define PXAMMCI_RESP(wd, value0, value1)        \
 174         s->resp_fifo[(wd) + 0] |= (value0);     \
 175         s->resp_fifo[(wd) + 1] |= (value1) << 8;
 176     case 0:     /* No response */
 177         goto complete;
 178
 179     case 1:     /* R1, R4, R5 or R6 */
 180         if (rsplen < 4)
 181             goto timeout;
 182         goto complete;
 183
 184     case 2:     /* R2 */
 185         if (rsplen < 16)
 186             goto timeout;
 187         goto complete;
 188
 189     case 3:     /* R3 */
 190         if (rsplen < 4)
 191             goto timeout;
 192         goto complete;
 193
 194     complete:
 195         for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
 196             PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
 197         }
 198         s->status |= STAT_END_CMDRES;
 199
 200         if (!(s->cmdat & CMDAT_DATA_EN))
 201             s->active = 0;
 202         else
 203             s->bytesleft = s->numblk * s->blklen;
 204
 205         s->resp_len = 0;
 206         break;
 207
 208     timeout:
 209         s->active = 0;
 210         s->status |= STAT_TOUT_RES;
 211         break;
 212     }
 213
 214     pxa2xx_mmci_fifo_update(s);
 215 }
 216
 217 static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
 218 {
 219     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 220     uint32_t ret;
 221
 222     switch (offset) {
 223     case MMC_STRPCL:
 224         return 0;
 225     case MMC_STAT:
 226         return s->status;
 227     case MMC_CLKRT:
 228         return s->clkrt;
 229     case MMC_SPI:
 230         return s->spi;
 231     case MMC_CMDAT:
 232         return s->cmdat;
 233     case MMC_RESTO:
 234         return s->resp_tout;
 235     case MMC_RDTO:
 236         return s->read_tout;
 237     case MMC_BLKLEN:
 238         return s->blklen;
 239     case MMC_NUMBLK:
 240         return s->numblk;
 241     case MMC_PRTBUF:
 242         return 0;
 243     case MMC_I_MASK:
 244         return s->intmask;
 245     case MMC_I_REG:
 246         return s->intreq;
 247     case MMC_CMD:
 248         return s->cmd | 0x40;
 249     case MMC_ARGH:
 250         return s->arg >> 16;
 251     case MMC_ARGL:
 252         return s->arg & 0xffff;
 253     case MMC_RES:
 254         if (s->resp_len < 9)
 255             return s->resp_fifo[s->resp_len ++];
 256         return 0;
 257     case MMC_RXFIFO:
 258         ret = 0;
 259         while (size-- && s->rx_len) {
 260             ret |= s->rx_fifo[s->rx_start++] << (size << 3);
 261             s->rx_start &= 0x1f;
 262             s->rx_len --;
 263         }
 264         s->intreq &= ~INT_RXFIFO_REQ;
 265         pxa2xx_mmci_fifo_update(s);
 266         return ret;
 267     case MMC_RDWAIT:
 268         return 0;
 269     case MMC_BLKS_REM:
 270         return s->numblk;
 271     default:
 272         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 273     }
 274
 275     return 0;
 276 }
 277
 278 static void pxa2xx_mmci_write(void *opaque,
 279                               hwaddr offset, uint64_t value, unsigned size)
 280 {
 281     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 282
 283     switch (offset) {
 284     case MMC_STRPCL:
 285         if (value & STRPCL_STRT_CLK) {
 286             s->status |= STAT_CLK_EN;
 287             s->intreq &= ~INT_CLK_OFF;
 288
 289             if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
 290                 s->status &= STAT_CLK_EN;
 291                 pxa2xx_mmci_wakequeues(s);
 292             }
 293         }
 294
 295         if (value & STRPCL_STOP_CLK) {
 296             s->status &= ~STAT_CLK_EN;
 297             s->intreq |= INT_CLK_OFF;
 298             s->active = 0;
 299         }
 300
 301         pxa2xx_mmci_int_update(s);
 302         break;
 303
 304     case MMC_CLKRT:
 305         s->clkrt = value & 7;
 306         break;
 307
 308     case MMC_SPI:
 309         s->spi = value & 0xf;
 310         if (value & SPI_SPI_MODE)
 311             printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
 312         break;
 313
 314     case MMC_CMDAT:
 315         s->cmdat = value & 0x3dff;
 316         s->active = 0;
 317         s->cmdreq = 1;
 318         if (!(value & CMDAT_STOP_TRAN)) {
 319             s->status &= STAT_CLK_EN;
 320
 321             if (s->status & STAT_CLK_EN)
 322                 pxa2xx_mmci_wakequeues(s);
 323         }
 324
 325         pxa2xx_mmci_int_update(s);
 326         break;
 327
 328     case MMC_RESTO:
 329         s->resp_tout = value & 0x7f;
 330         break;
 331
 332     case MMC_RDTO:
 333         s->read_tout = value & 0xffff;
 334         break;
 335
 336     case MMC_BLKLEN:
 337         s->blklen = value & 0xfff;
 338         break;
 339
 340     case MMC_NUMBLK:
 341         s->numblk = value & 0xffff;
 342         break;
 343
 344     case MMC_PRTBUF:
 345         if (value & PRTBUF_PRT_BUF) {
 346             s->tx_start ^= 32;
 347             s->tx_len = 0;
 348         }
 349         pxa2xx_mmci_fifo_update(s);
 350         break;
 351
 352     case MMC_I_MASK:
 353         s->intmask = value & 0x1fff;
 354         pxa2xx_mmci_int_update(s);
 355         break;
 356
 357     case MMC_CMD:
 358         s->cmd = value & 0x3f;
 359         break;
 360
 361     case MMC_ARGH:
 362         s->arg &= 0x0000ffff;
 363         s->arg |= value << 16;
 364         break;
 365
 366     case MMC_ARGL:
 367         s->arg &= 0xffff0000;
 368         s->arg |= value & 0x0000ffff;
 369         break;
 370
 371     case MMC_TXFIFO:
 372         while (size-- && s->tx_len < 0x20)
 373             s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
 374                     (value >> (size << 3)) & 0xff;
 375         s->intreq &= ~INT_TXFIFO_REQ;
 376         pxa2xx_mmci_fifo_update(s);
 377         break;
 378
 379     case MMC_RDWAIT:
 380     case MMC_BLKS_REM:
 381         break;
 382
 383     default:
 384         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 385     }
 386 }
 387
 388 static const MemoryRegionOps pxa2xx_mmci_ops = {
 389     .read = pxa2xx_mmci_read,
 390     .write = pxa2xx_mmci_write,
 391     .endianness = DEVICE_NATIVE_ENDIAN,
 392 };
 393
 394 static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
 395 {
 396     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 397     int i;
 398
 399     qemu_put_be32s(f, &s->status);
 400     qemu_put_be32s(f, &s->clkrt);
 401     qemu_put_be32s(f, &s->spi);
 402     qemu_put_be32s(f, &s->cmdat);
 403     qemu_put_be32s(f, &s->resp_tout);
 404     qemu_put_be32s(f, &s->read_tout);
 405     qemu_put_be32(f, s->blklen);
 406     qemu_put_be32(f, s->numblk);
 407     qemu_put_be32s(f, &s->intmask);
 408     qemu_put_be32s(f, &s->intreq);
 409     qemu_put_be32(f, s->cmd);
 410     qemu_put_be32s(f, &s->arg);
 411     qemu_put_be32(f, s->cmdreq);
 412     qemu_put_be32(f, s->active);
 413     qemu_put_be32(f, s->bytesleft);
 414
 415     qemu_put_byte(f, s->tx_len);
 416     for (i = 0; i < s->tx_len; i ++)
 417         qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
 418
 419     qemu_put_byte(f, s->rx_len);
 420     for (i = 0; i < s->rx_len; i ++)
 421         qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
 422
 423     qemu_put_byte(f, s->resp_len);
 424     for (i = s->resp_len; i < 9; i ++)
 425         qemu_put_be16s(f, &s->resp_fifo[i]);
 426 }
 427
 428 static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
 429 {
 430     PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
 431     int i;
 432
 433     qemu_get_be32s(f, &s->status);
 434     qemu_get_be32s(f, &s->clkrt);
 435     qemu_get_be32s(f, &s->spi);
 436     qemu_get_be32s(f, &s->cmdat);
 437     qemu_get_be32s(f, &s->resp_tout);
 438     qemu_get_be32s(f, &s->read_tout);
 439     s->blklen = qemu_get_be32(f);
 440     s->numblk = qemu_get_be32(f);
 441     qemu_get_be32s(f, &s->intmask);
 442     qemu_get_be32s(f, &s->intreq);
 443     s->cmd = qemu_get_be32(f);
 444     qemu_get_be32s(f, &s->arg);
 445     s->cmdreq = qemu_get_be32(f);
 446     s->active = qemu_get_be32(f);
 447     s->bytesleft = qemu_get_be32(f);
 448
 449     s->tx_len = qemu_get_byte(f);
 450     s->tx_start = 0;
 451     if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
 452         return -EINVAL;
 453     for (i = 0; i < s->tx_len; i ++)
 454         s->tx_fifo[i] = qemu_get_byte(f);
 455
 456     s->rx_len = qemu_get_byte(f);
 457     s->rx_start = 0;
 458     if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
 459         return -EINVAL;
 460     for (i = 0; i < s->rx_len; i ++)
 461         s->rx_fifo[i] = qemu_get_byte(f);
 462
 463     s->resp_len = qemu_get_byte(f);
 464     if (s->resp_len > 9 || s->resp_len < 0)
 465         return -EINVAL;
 466     for (i = s->resp_len; i < 9; i ++)
 467          qemu_get_be16s(f, &s->resp_fifo[i]);
 468
 469     return 0;
 470 }
 471
 472 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
 473                 hwaddr base,
 474                 BlockBackend *blk, qemu_irq irq,
 475                 qemu_irq rx_dma, qemu_irq tx_dma)
 476 {
 477     PXA2xxMMCIState *s;
 478
 479     s = (PXA2xxMMCIState *) g_malloc0(sizeof(PXA2xxMMCIState));
 480     s->irq = irq;
 481     s->rx_dma = rx_dma;
 482     s->tx_dma = tx_dma;
 483
 484     memory_region_init_io(&s->iomem, NULL, &pxa2xx_mmci_ops, s,
 485                           "pxa2xx-mmci", 0x00100000);
 486     memory_region_add_subregion(sysmem, base, &s->iomem);
 487
 488     /* Instantiate the actual storage */
 489     s->card = sd_init(blk, false);
 490     if (s->card == NULL) {
 491         exit(1);
 492     }
 493
 494     register_savevm(NULL, "pxa2xx_mmci", 0, 0,
 495                     pxa2xx_mmci_save, pxa2xx_mmci_load, s);
 496
 497     return s;
 498 }
 499
 500 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
 501                 qemu_irq coverswitch)
 502 {
 503     sd_set_cb(s->card, readonly, coverswitch);
 504 }