ne2000: Drop ne2000_can_receive
[qemu.git] / hw / ppc / prep.c
blob45b5f62d6e25d6d776f643c94ba22b281e984f68
1 /*
2 * QEMU PPC PREP hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw/hw.h"
25 #include "hw/timer/m48t59.h"
26 #include "hw/i386/pc.h"
27 #include "hw/char/serial.h"
28 #include "hw/block/fdc.h"
29 #include "net/net.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/isa/isa.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/ppc/ppc.h"
35 #include "hw/boards.h"
36 #include "qemu/log.h"
37 #include "hw/ide.h"
38 #include "hw/loader.h"
39 #include "hw/timer/mc146818rtc.h"
40 #include "hw/isa/pc87312.h"
41 #include "sysemu/block-backend.h"
42 #include "sysemu/arch_init.h"
43 #include "sysemu/qtest.h"
44 #include "exec/address-spaces.h"
45 #include "elf.h"
47 //#define HARD_DEBUG_PPC_IO
48 //#define DEBUG_PPC_IO
50 /* SMP is not enabled, for now */
51 #define MAX_CPUS 1
53 #define MAX_IDE_BUS 2
55 #define BIOS_SIZE (1024 * 1024)
56 #define BIOS_FILENAME "ppc_rom.bin"
57 #define KERNEL_LOAD_ADDR 0x01000000
58 #define INITRD_LOAD_ADDR 0x01800000
60 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
61 #define DEBUG_PPC_IO
62 #endif
64 #if defined (HARD_DEBUG_PPC_IO)
65 #define PPC_IO_DPRINTF(fmt, ...) \
66 do { \
67 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
68 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
69 } else { \
70 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
71 } \
72 } while (0)
73 #elif defined (DEBUG_PPC_IO)
74 #define PPC_IO_DPRINTF(fmt, ...) \
75 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
76 #else
77 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
78 #endif
80 /* Constants for devices init */
81 static const int ide_iobase[2] = { 0x1f0, 0x170 };
82 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
83 static const int ide_irq[2] = { 13, 13 };
85 #define NE2000_NB_MAX 6
87 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
88 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
90 /* ISA IO ports bridge */
91 #define PPC_IO_BASE 0x80000000
93 /* PowerPC control and status registers */
94 #if 0 // Not used
95 static struct {
96 /* IDs */
97 uint32_t veni_devi;
98 uint32_t revi;
99 /* Control and status */
100 uint32_t gcsr;
101 uint32_t xcfr;
102 uint32_t ct32;
103 uint32_t mcsr;
104 /* General purpose registers */
105 uint32_t gprg[6];
106 /* Exceptions */
107 uint32_t feen;
108 uint32_t fest;
109 uint32_t fema;
110 uint32_t fecl;
111 uint32_t eeen;
112 uint32_t eest;
113 uint32_t eecl;
114 uint32_t eeint;
115 uint32_t eemck0;
116 uint32_t eemck1;
117 /* Error diagnostic */
118 } XCSR;
120 static void PPC_XCSR_writeb (void *opaque,
121 hwaddr addr, uint32_t value)
123 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
124 value);
127 static void PPC_XCSR_writew (void *opaque,
128 hwaddr addr, uint32_t value)
130 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
131 value);
134 static void PPC_XCSR_writel (void *opaque,
135 hwaddr addr, uint32_t value)
137 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
138 value);
141 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
143 uint32_t retval = 0;
145 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
146 retval);
148 return retval;
151 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
153 uint32_t retval = 0;
155 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
156 retval);
158 return retval;
161 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
163 uint32_t retval = 0;
165 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
166 retval);
168 return retval;
171 static const MemoryRegionOps PPC_XCSR_ops = {
172 .old_mmio = {
173 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
174 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
176 .endianness = DEVICE_LITTLE_ENDIAN,
179 #endif
181 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
182 typedef struct sysctrl_t {
183 qemu_irq reset_irq;
184 Nvram *nvram;
185 uint8_t state;
186 uint8_t syscontrol;
187 int contiguous_map;
188 qemu_irq contiguous_map_irq;
189 int endian;
190 } sysctrl_t;
192 enum {
193 STATE_HARDFILE = 0x01,
196 static sysctrl_t *sysctrl;
198 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
200 sysctrl_t *sysctrl = opaque;
202 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
203 addr - PPC_IO_BASE, val);
204 switch (addr) {
205 case 0x0092:
206 /* Special port 92 */
207 /* Check soft reset asked */
208 if (val & 0x01) {
209 qemu_irq_raise(sysctrl->reset_irq);
210 } else {
211 qemu_irq_lower(sysctrl->reset_irq);
213 /* Check LE mode */
214 if (val & 0x02) {
215 sysctrl->endian = 1;
216 } else {
217 sysctrl->endian = 0;
219 break;
220 case 0x0800:
221 /* Motorola CPU configuration register : read-only */
222 break;
223 case 0x0802:
224 /* Motorola base module feature register : read-only */
225 break;
226 case 0x0803:
227 /* Motorola base module status register : read-only */
228 break;
229 case 0x0808:
230 /* Hardfile light register */
231 if (val & 1)
232 sysctrl->state |= STATE_HARDFILE;
233 else
234 sysctrl->state &= ~STATE_HARDFILE;
235 break;
236 case 0x0810:
237 /* Password protect 1 register */
238 if (sysctrl->nvram != NULL) {
239 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
240 (k->toggle_lock)(sysctrl->nvram, 1);
242 break;
243 case 0x0812:
244 /* Password protect 2 register */
245 if (sysctrl->nvram != NULL) {
246 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
247 (k->toggle_lock)(sysctrl->nvram, 2);
249 break;
250 case 0x0814:
251 /* L2 invalidate register */
252 // tlb_flush(first_cpu, 1);
253 break;
254 case 0x081C:
255 /* system control register */
256 sysctrl->syscontrol = val & 0x0F;
257 break;
258 case 0x0850:
259 /* I/O map type register */
260 sysctrl->contiguous_map = val & 0x01;
261 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
262 break;
263 default:
264 printf("ERROR: unaffected IO port write: %04" PRIx32
265 " => %02" PRIx32"\n", addr, val);
266 break;
270 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
272 sysctrl_t *sysctrl = opaque;
273 uint32_t retval = 0xFF;
275 switch (addr) {
276 case 0x0092:
277 /* Special port 92 */
278 retval = sysctrl->endian << 1;
279 break;
280 case 0x0800:
281 /* Motorola CPU configuration register */
282 retval = 0xEF; /* MPC750 */
283 break;
284 case 0x0802:
285 /* Motorola Base module feature register */
286 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
287 break;
288 case 0x0803:
289 /* Motorola base module status register */
290 retval = 0xE0; /* Standard MPC750 */
291 break;
292 case 0x080C:
293 /* Equipment present register:
294 * no L2 cache
295 * no upgrade processor
296 * no cards in PCI slots
297 * SCSI fuse is bad
299 retval = 0x3C;
300 break;
301 case 0x0810:
302 /* Motorola base module extended feature register */
303 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
304 break;
305 case 0x0814:
306 /* L2 invalidate: don't care */
307 break;
308 case 0x0818:
309 /* Keylock */
310 retval = 0x00;
311 break;
312 case 0x081C:
313 /* system control register
314 * 7 - 6 / 1 - 0: L2 cache enable
316 retval = sysctrl->syscontrol;
317 break;
318 case 0x0823:
319 /* */
320 retval = 0x03; /* no L2 cache */
321 break;
322 case 0x0850:
323 /* I/O map type register */
324 retval = sysctrl->contiguous_map;
325 break;
326 default:
327 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
328 break;
330 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
331 addr - PPC_IO_BASE, retval);
333 return retval;
337 #define NVRAM_SIZE 0x2000
339 static void cpu_request_exit(void *opaque, int irq, int level)
341 CPUState *cpu = current_cpu;
343 if (cpu && level) {
344 cpu_exit(cpu);
348 static void ppc_prep_reset(void *opaque)
350 PowerPCCPU *cpu = opaque;
352 cpu_reset(CPU(cpu));
355 static const MemoryRegionPortio prep_portio_list[] = {
356 /* System control ports */
357 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
358 { 0x0800, 0x52, 1,
359 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
360 /* Special port to get debug messages from Open-Firmware */
361 { 0x0F00, 4, 1, .write = PPC_debug_write, },
362 PORTIO_END_OF_LIST(),
365 static PortioList prep_port_list;
367 /*****************************************************************************/
368 /* NVRAM helpers */
369 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
371 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
372 return (k->read)(nvram, addr);
375 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
377 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
378 (k->write)(nvram, addr, val);
381 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
383 nvram_write(nvram, addr, value);
386 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
388 return nvram_read(nvram, addr);
391 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
393 nvram_write(nvram, addr, value >> 8);
394 nvram_write(nvram, addr + 1, value & 0xFF);
397 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
399 uint16_t tmp;
401 tmp = nvram_read(nvram, addr) << 8;
402 tmp |= nvram_read(nvram, addr + 1);
404 return tmp;
407 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
409 nvram_write(nvram, addr, value >> 24);
410 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
411 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
412 nvram_write(nvram, addr + 3, value & 0xFF);
415 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
416 uint32_t max)
418 int i;
420 for (i = 0; i < max && str[i] != '\0'; i++) {
421 nvram_write(nvram, addr + i, str[i]);
423 nvram_write(nvram, addr + i, str[i]);
424 nvram_write(nvram, addr + max - 1, '\0');
427 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
429 uint16_t tmp;
430 uint16_t pd, pd1, pd2;
432 tmp = prev >> 8;
433 pd = prev ^ value;
434 pd1 = pd & 0x000F;
435 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
436 tmp ^= (pd1 << 3) | (pd1 << 8);
437 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
439 return tmp;
442 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
444 uint32_t i;
445 uint16_t crc = 0xFFFF;
446 int odd;
448 odd = count & 1;
449 count &= ~1;
450 for (i = 0; i != count; i++) {
451 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
453 if (odd) {
454 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
457 return crc;
460 #define CMDLINE_ADDR 0x017ff000
462 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
463 const char *arch,
464 uint32_t RAM_size, int boot_device,
465 uint32_t kernel_image, uint32_t kernel_size,
466 const char *cmdline,
467 uint32_t initrd_image, uint32_t initrd_size,
468 uint32_t NVRAM_image,
469 int width, int height, int depth)
471 uint16_t crc;
473 /* Set parameters for Open Hack'Ware BIOS */
474 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
475 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
476 NVRAM_set_word(nvram, 0x14, NVRAM_size);
477 NVRAM_set_string(nvram, 0x20, arch, 16);
478 NVRAM_set_lword(nvram, 0x30, RAM_size);
479 NVRAM_set_byte(nvram, 0x34, boot_device);
480 NVRAM_set_lword(nvram, 0x38, kernel_image);
481 NVRAM_set_lword(nvram, 0x3C, kernel_size);
482 if (cmdline) {
483 /* XXX: put the cmdline in NVRAM too ? */
484 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
485 cmdline);
486 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
487 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
488 } else {
489 NVRAM_set_lword(nvram, 0x40, 0);
490 NVRAM_set_lword(nvram, 0x44, 0);
492 NVRAM_set_lword(nvram, 0x48, initrd_image);
493 NVRAM_set_lword(nvram, 0x4C, initrd_size);
494 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
496 NVRAM_set_word(nvram, 0x54, width);
497 NVRAM_set_word(nvram, 0x56, height);
498 NVRAM_set_word(nvram, 0x58, depth);
499 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
500 NVRAM_set_word(nvram, 0xFC, crc);
502 return 0;
505 /* PowerPC PREP hardware initialisation */
506 static void ppc_prep_init(MachineState *machine)
508 ram_addr_t ram_size = machine->ram_size;
509 const char *kernel_filename = machine->kernel_filename;
510 const char *kernel_cmdline = machine->kernel_cmdline;
511 const char *initrd_filename = machine->initrd_filename;
512 const char *boot_device = machine->boot_order;
513 MemoryRegion *sysmem = get_system_memory();
514 PowerPCCPU *cpu = NULL;
515 CPUPPCState *env = NULL;
516 Nvram *m48t59;
517 #if 0
518 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
519 #endif
520 int linux_boot, i, nb_nics1;
521 MemoryRegion *ram = g_new(MemoryRegion, 1);
522 uint32_t kernel_base, initrd_base;
523 long kernel_size, initrd_size;
524 DeviceState *dev;
525 PCIHostState *pcihost;
526 PCIBus *pci_bus;
527 PCIDevice *pci;
528 ISABus *isa_bus;
529 ISADevice *isa;
530 int ppc_boot_device;
531 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
533 sysctrl = g_malloc0(sizeof(sysctrl_t));
535 linux_boot = (kernel_filename != NULL);
537 /* init CPUs */
538 if (machine->cpu_model == NULL)
539 machine->cpu_model = "602";
540 for (i = 0; i < smp_cpus; i++) {
541 cpu = cpu_ppc_init(machine->cpu_model);
542 if (cpu == NULL) {
543 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
544 exit(1);
546 env = &cpu->env;
548 if (env->flags & POWERPC_FLAG_RTC_CLK) {
549 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
550 cpu_ppc_tb_init(env, 7812500UL);
551 } else {
552 /* Set time-base frequency to 100 Mhz */
553 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
555 qemu_register_reset(ppc_prep_reset, cpu);
558 /* allocate RAM */
559 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
560 memory_region_add_subregion(sysmem, 0, ram);
562 if (linux_boot) {
563 kernel_base = KERNEL_LOAD_ADDR;
564 /* now we can load the kernel */
565 kernel_size = load_image_targphys(kernel_filename, kernel_base,
566 ram_size - kernel_base);
567 if (kernel_size < 0) {
568 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
569 exit(1);
571 /* load initrd */
572 if (initrd_filename) {
573 initrd_base = INITRD_LOAD_ADDR;
574 initrd_size = load_image_targphys(initrd_filename, initrd_base,
575 ram_size - initrd_base);
576 if (initrd_size < 0) {
577 hw_error("qemu: could not load initial ram disk '%s'\n",
578 initrd_filename);
580 } else {
581 initrd_base = 0;
582 initrd_size = 0;
584 ppc_boot_device = 'm';
585 } else {
586 kernel_base = 0;
587 kernel_size = 0;
588 initrd_base = 0;
589 initrd_size = 0;
590 ppc_boot_device = '\0';
591 /* For now, OHW cannot boot from the network. */
592 for (i = 0; boot_device[i] != '\0'; i++) {
593 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
594 ppc_boot_device = boot_device[i];
595 break;
598 if (ppc_boot_device == '\0') {
599 fprintf(stderr, "No valid boot device for Mac99 machine\n");
600 exit(1);
604 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
605 hw_error("Only 6xx bus is supported on PREP machine\n");
608 dev = qdev_create(NULL, "raven-pcihost");
609 if (bios_name == NULL) {
610 bios_name = BIOS_FILENAME;
612 qdev_prop_set_string(dev, "bios-name", bios_name);
613 qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE);
614 pcihost = PCI_HOST_BRIDGE(dev);
615 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
616 qdev_init_nofail(dev);
617 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
618 if (pci_bus == NULL) {
619 fprintf(stderr, "Couldn't create PCI host controller.\n");
620 exit(1);
622 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
624 /* PCI -> ISA bridge */
625 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
626 cpu = POWERPC_CPU(first_cpu);
627 qdev_connect_gpio_out(&pci->qdev, 0,
628 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
629 qdev_connect_gpio_out(&pci->qdev, 1,
630 qemu_allocate_irq(cpu_request_exit, NULL, 0));
631 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
632 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
633 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
634 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
635 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
637 /* Super I/O (parallel + serial ports) */
638 isa = isa_create(isa_bus, TYPE_PC87312);
639 dev = DEVICE(isa);
640 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
641 qdev_init_nofail(dev);
643 /* init basic PC hardware */
644 pci_vga_init(pci_bus);
646 nb_nics1 = nb_nics;
647 if (nb_nics1 > NE2000_NB_MAX)
648 nb_nics1 = NE2000_NB_MAX;
649 for(i = 0; i < nb_nics1; i++) {
650 if (nd_table[i].model == NULL) {
651 nd_table[i].model = g_strdup("ne2k_isa");
653 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
654 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
655 &nd_table[i]);
656 } else {
657 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
661 ide_drive_get(hd, ARRAY_SIZE(hd));
662 for(i = 0; i < MAX_IDE_BUS; i++) {
663 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
664 hd[2 * i],
665 hd[2 * i + 1]);
667 isa_create_simple(isa_bus, "i8042");
669 cpu = POWERPC_CPU(first_cpu);
670 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
672 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
673 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
675 /* PowerPC control and status register group */
676 #if 0
677 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
678 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
679 #endif
681 if (usb_enabled()) {
682 pci_create_simple(pci_bus, -1, "pci-ohci");
685 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
686 if (m48t59 == NULL)
687 return;
688 sysctrl->nvram = m48t59;
690 /* Initialise NVRAM */
691 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
692 ppc_boot_device,
693 kernel_base, kernel_size,
694 kernel_cmdline,
695 initrd_base, initrd_size,
696 /* XXX: need an option to load a NVRAM image */
698 graphic_width, graphic_height, graphic_depth);
701 static QEMUMachine prep_machine = {
702 .name = "prep",
703 .desc = "PowerPC PREP platform",
704 .init = ppc_prep_init,
705 .max_cpus = MAX_CPUS,
706 .default_boot_order = "cad",
709 static void prep_machine_init(void)
711 qemu_register_machine(&prep_machine);
714 machine_init(prep_machine_init);