2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "hw/sysbus.h"
32 #include "hw/arm/arm.h"
33 #include "hw/arm/primecell.h"
34 #include "hw/arm/virt.h"
35 #include "hw/devices.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/device_tree.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/kvm.h"
41 #include "hw/boards.h"
42 #include "hw/loader.h"
43 #include "exec/address-spaces.h"
44 #include "qemu/bitops.h"
45 #include "qemu/error-report.h"
46 #include "hw/pci-host/gpex.h"
47 #include "hw/arm/virt-acpi-build.h"
48 #include "hw/arm/sysbus-fdt.h"
49 #include "hw/platform-bus.h"
50 #include "hw/arm/fdt.h"
51 #include "hw/intc/arm_gic_common.h"
54 /* Number of external interrupt lines to configure the GIC with */
57 #define PLATFORM_BUS_NUM_IRQS 64
59 static ARMPlatformBusSystemParams platform_bus_params
;
61 typedef struct VirtBoardInfo
{
62 struct arm_boot_info bootinfo
;
63 const char *cpu_model
;
64 const MemMapEntry
*memmap
;
69 uint32_t clock_phandle
;
76 VirtBoardInfo
*daughterboard
;
84 #define TYPE_VIRT_MACHINE "virt"
85 #define VIRT_MACHINE(obj) \
86 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
87 #define VIRT_MACHINE_GET_CLASS(obj) \
88 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
89 #define VIRT_MACHINE_CLASS(klass) \
90 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
92 /* Addresses and sizes of our components.
93 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
94 * 128MB..256MB is used for miscellaneous device I/O.
95 * 256MB..1GB is reserved for possible future PCI support (ie where the
96 * PCI memory window will go if we add a PCI host controller).
97 * 1GB and up is RAM (which may happily spill over into the
98 * high memory region beyond 4GB).
99 * This represents a compromise between how much RAM can be given to
100 * a 32 bit VM and leaving space for expansion and in particular for PCI.
101 * Note that devices should generally be placed at multiples of 0x10000,
102 * to accommodate guests using 64K pages.
104 static const MemMapEntry a15memmap
[] = {
105 /* Space up to 0x8000000 is reserved for a boot ROM */
106 [VIRT_FLASH
] = { 0, 0x08000000 },
107 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
108 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
109 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
110 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
111 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
112 [VIRT_UART
] = { 0x09000000, 0x00001000 },
113 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
114 [VIRT_FW_CFG
] = { 0x09020000, 0x0000000a },
115 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
116 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
117 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
118 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
119 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
120 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
121 [VIRT_MEM
] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
124 static const int a15irqmap
[] = {
127 [VIRT_PCIE
] = 3, /* ... to 6 */
128 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
129 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
130 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
133 static VirtBoardInfo machines
[] = {
135 .cpu_model
= "cortex-a15",
140 .cpu_model
= "cortex-a53",
145 .cpu_model
= "cortex-a57",
156 static VirtBoardInfo
*find_machine_info(const char *cpu
)
160 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
161 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
168 static void create_fdt(VirtBoardInfo
*vbi
)
170 void *fdt
= create_device_tree(&vbi
->fdt_size
);
173 error_report("create_device_tree() failed");
180 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
181 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
182 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
185 * /chosen and /memory nodes must exist for load_dtb
186 * to fill in necessary properties later
188 qemu_fdt_add_subnode(fdt
, "/chosen");
189 qemu_fdt_add_subnode(fdt
, "/memory");
190 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
192 /* Clock node, for the benefit of the UART. The kernel device tree
193 * binding documentation claims the PL011 node clock properties are
194 * optional but in practice if you omit them the kernel refuses to
195 * probe for the device.
197 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
198 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
199 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
200 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
201 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
202 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
204 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
208 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
210 uint32_t cpu_suspend_fn
;
214 void *fdt
= vbi
->fdt
;
215 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
217 qemu_fdt_add_subnode(fdt
, "/psci");
218 if (armcpu
->psci_version
== 2) {
219 const char comp
[] = "arm,psci-0.2\0arm,psci";
220 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
222 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
223 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
224 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
225 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
226 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
228 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
229 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
230 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
233 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
235 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
236 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
237 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
238 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
241 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
242 * to the instruction that should be used to invoke PSCI functions.
243 * However, the device tree binding uses 'method' instead, so that is
244 * what we should use here.
246 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
248 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
249 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
250 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
251 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
254 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
)
256 /* Note that on A15 h/w these interrupts are level-triggered,
257 * but for the GIC implementation provided by both QEMU and KVM
258 * they are edge-triggered.
261 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
263 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
264 GIC_FDT_IRQ_PPI_CPU_WIDTH
, (1 << vbi
->smp_cpus
) - 1);
266 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
268 armcpu
= ARM_CPU(qemu_get_cpu(0));
269 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
270 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
271 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
272 compat
, sizeof(compat
));
274 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
277 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
278 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
279 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
280 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
281 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
284 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
288 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
289 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", 0x1);
290 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
292 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
293 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
294 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
296 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
297 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
298 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
299 armcpu
->dtb_compatible
);
301 if (vbi
->smp_cpus
> 1) {
302 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
303 "enable-method", "psci");
306 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg", armcpu
->mp_affinity
);
311 static void fdt_add_v2m_gic_node(VirtBoardInfo
*vbi
)
313 vbi
->v2m_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
314 qemu_fdt_add_subnode(vbi
->fdt
, "/intc/v2m");
315 qemu_fdt_setprop_string(vbi
->fdt
, "/intc/v2m", "compatible",
316 "arm,gic-v2m-frame");
317 qemu_fdt_setprop(vbi
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
318 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc/v2m", "reg",
319 2, vbi
->memmap
[VIRT_GIC_V2M
].base
,
320 2, vbi
->memmap
[VIRT_GIC_V2M
].size
);
321 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc/v2m", "phandle", vbi
->v2m_phandle
);
324 static void fdt_add_gic_node(VirtBoardInfo
*vbi
)
326 vbi
->gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
327 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", vbi
->gic_phandle
);
329 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
330 /* 'cortex-a15-gic' means 'GIC v2' */
331 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
332 "arm,cortex-a15-gic");
333 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
334 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
335 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
336 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
337 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
338 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
339 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
340 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#address-cells", 0x2);
341 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#size-cells", 0x2);
342 qemu_fdt_setprop(vbi
->fdt
, "/intc", "ranges", NULL
, 0);
343 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", vbi
->gic_phandle
);
346 static void create_v2m(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
349 int irq
= vbi
->irqmap
[VIRT_GIC_V2M
];
352 dev
= qdev_create(NULL
, "arm-gicv2m");
353 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vbi
->memmap
[VIRT_GIC_V2M
].base
);
354 qdev_prop_set_uint32(dev
, "base-spi", irq
);
355 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
356 qdev_init_nofail(dev
);
358 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
359 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
362 fdt_add_v2m_gic_node(vbi
);
365 static void create_gic(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
367 /* We create a standalone GIC v2 */
369 SysBusDevice
*gicbusdev
;
373 gictype
= gic_class_name();
375 gicdev
= qdev_create(NULL
, gictype
);
376 qdev_prop_set_uint32(gicdev
, "revision", 2);
377 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
378 /* Note that the num-irq property counts both internal and external
379 * interrupts; there are always 32 of the former (mandated by GIC spec).
381 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
382 qdev_init_nofail(gicdev
);
383 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
384 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
385 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
387 /* Wire the outputs from each CPU's generic timer to the
388 * appropriate GIC PPI inputs, and the GIC's IRQ output to
389 * the CPU's IRQ input.
391 for (i
= 0; i
< smp_cpus
; i
++) {
392 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
393 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
395 /* Mapping from the output timer irq lines from the CPU to the
396 * GIC PPI inputs we use for the virt board.
398 const int timer_irq
[] = {
399 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
400 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
401 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
402 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
405 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
406 qdev_connect_gpio_out(cpudev
, irq
,
407 qdev_get_gpio_in(gicdev
,
408 ppibase
+ timer_irq
[irq
]));
411 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
412 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
413 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
416 for (i
= 0; i
< NUM_IRQS
; i
++) {
417 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
420 fdt_add_gic_node(vbi
);
422 create_v2m(vbi
, pic
);
425 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
428 hwaddr base
= vbi
->memmap
[VIRT_UART
].base
;
429 hwaddr size
= vbi
->memmap
[VIRT_UART
].size
;
430 int irq
= vbi
->irqmap
[VIRT_UART
];
431 const char compat
[] = "arm,pl011\0arm,primecell";
432 const char clocknames
[] = "uartclk\0apb_pclk";
434 sysbus_create_simple("pl011", base
, pic
[irq
]);
436 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
437 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
438 /* Note that we can't use setprop_string because of the embedded NUL */
439 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
440 compat
, sizeof(compat
));
441 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
443 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
444 GIC_FDT_IRQ_TYPE_SPI
, irq
,
445 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
446 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
447 vbi
->clock_phandle
, vbi
->clock_phandle
);
448 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
449 clocknames
, sizeof(clocknames
));
451 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "stdout-path", nodename
);
455 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
458 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
459 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
460 int irq
= vbi
->irqmap
[VIRT_RTC
];
461 const char compat
[] = "arm,pl031\0arm,primecell";
463 sysbus_create_simple("pl031", base
, pic
[irq
]);
465 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
466 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
467 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
468 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
470 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
471 GIC_FDT_IRQ_TYPE_SPI
, irq
,
472 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
473 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
474 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
478 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
481 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
483 /* We create the transports in forwards order. Since qbus_realize()
484 * prepends (not appends) new child buses, the incrementing loop below will
485 * create a list of virtio-mmio buses with decreasing base addresses.
487 * When a -device option is processed from the command line,
488 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
489 * order. The upshot is that -device options in increasing command line
490 * order are mapped to virtio-mmio buses with decreasing base addresses.
492 * When this code was originally written, that arrangement ensured that the
493 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
494 * the first -device on the command line. (The end-to-end order is a
495 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
496 * guest kernel's name-to-address assignment strategy.)
498 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
499 * the message, if not necessarily the code, of commit 70161ff336.
500 * Therefore the loop now establishes the inverse of the original intent.
502 * Unfortunately, we can't counteract the kernel change by reversing the
503 * loop; it would break existing command lines.
505 * In any case, the kernel makes no guarantee about the stability of
506 * enumeration order of virtio devices (as demonstrated by it changing
507 * between kernel versions). For reliable and stable identification
508 * of disks users must use UUIDs or similar mechanisms.
510 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
511 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
512 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
514 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
517 /* We add dtb nodes in reverse order so that they appear in the finished
518 * device tree lowest address first.
520 * Note that this mapping is independent of the loop above. The previous
521 * loop influences virtio device to virtio transport assignment, whereas
522 * this loop controls how virtio transports are laid out in the dtb.
524 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
526 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
527 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
529 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
530 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
531 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
532 "compatible", "virtio,mmio");
533 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
535 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
536 GIC_FDT_IRQ_TYPE_SPI
, irq
,
537 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
542 static void create_one_flash(const char *name
, hwaddr flashbase
,
545 /* Create and map a single flash device. We use the same
546 * parameters as the flash devices on the Versatile Express board.
548 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
549 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
550 const uint64_t sectorlength
= 256 * 1024;
553 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
557 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
558 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
559 qdev_prop_set_uint8(dev
, "width", 4);
560 qdev_prop_set_uint8(dev
, "device-width", 2);
561 qdev_prop_set_bit(dev
, "big-endian", false);
562 qdev_prop_set_uint16(dev
, "id0", 0x89);
563 qdev_prop_set_uint16(dev
, "id1", 0x18);
564 qdev_prop_set_uint16(dev
, "id2", 0x00);
565 qdev_prop_set_uint16(dev
, "id3", 0x00);
566 qdev_prop_set_string(dev
, "name", name
);
567 qdev_init_nofail(dev
);
569 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, flashbase
);
572 static void create_flash(const VirtBoardInfo
*vbi
)
574 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
575 * Any file passed via -bios goes in the first of these.
577 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
578 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
585 if (drive_get(IF_PFLASH
, 0, 0)) {
586 error_report("The contents of the first flash device may be "
587 "specified with -bios or with -drive if=pflash... "
588 "but you cannot use both options at once");
591 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
593 error_report("Could not find ROM image '%s'", bios_name
);
596 image_size
= load_image_targphys(fn
, flashbase
, flashsize
);
598 if (image_size
< 0) {
599 error_report("Could not load ROM image '%s'", bios_name
);
604 create_one_flash("virt.flash0", flashbase
, flashsize
);
605 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
);
607 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
608 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
609 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
610 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
611 2, flashbase
, 2, flashsize
,
612 2, flashbase
+ flashsize
, 2, flashsize
);
613 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
617 static void create_fw_cfg(const VirtBoardInfo
*vbi
)
619 hwaddr base
= vbi
->memmap
[VIRT_FW_CFG
].base
;
620 hwaddr size
= vbi
->memmap
[VIRT_FW_CFG
].size
;
623 fw_cfg_init_mem_wide(base
+ 8, base
, 8);
625 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
626 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
627 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
628 "compatible", "qemu,fw-cfg-mmio");
629 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
634 static void create_pcie_irq_map(const VirtBoardInfo
*vbi
, uint32_t gic_phandle
,
635 int first_irq
, const char *nodename
)
638 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
639 uint32_t *irq_map
= full_irq_map
;
641 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
642 for (pin
= 0; pin
< 4; pin
++) {
643 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
644 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
645 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
649 devfn
<< 8, 0, 0, /* devfn */
650 pin
+ 1, /* PCI pin */
651 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
653 /* Convert map to big endian */
654 for (i
= 0; i
< 10; i
++) {
655 irq_map
[i
] = cpu_to_be32(map
[i
]);
661 qemu_fdt_setprop(vbi
->fdt
, nodename
, "interrupt-map",
662 full_irq_map
, sizeof(full_irq_map
));
664 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupt-map-mask",
665 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
669 static void create_pcie(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
671 hwaddr base_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].base
;
672 hwaddr size_mmio
= vbi
->memmap
[VIRT_PCIE_MMIO
].size
;
673 hwaddr base_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].base
;
674 hwaddr size_pio
= vbi
->memmap
[VIRT_PCIE_PIO
].size
;
675 hwaddr base_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].base
;
676 hwaddr size_ecam
= vbi
->memmap
[VIRT_PCIE_ECAM
].size
;
677 hwaddr base
= base_mmio
;
678 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
679 int irq
= vbi
->irqmap
[VIRT_PCIE
];
680 MemoryRegion
*mmio_alias
;
681 MemoryRegion
*mmio_reg
;
682 MemoryRegion
*ecam_alias
;
683 MemoryRegion
*ecam_reg
;
688 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
689 qdev_init_nofail(dev
);
691 /* Map only the first size_ecam bytes of ECAM space */
692 ecam_alias
= g_new0(MemoryRegion
, 1);
693 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
694 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
695 ecam_reg
, 0, size_ecam
);
696 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
698 /* Map the MMIO window into system address space so as to expose
699 * the section of PCI MMIO space which starts at the same base address
700 * (ie 1:1 mapping for that part of PCI MMIO space visible through
703 mmio_alias
= g_new0(MemoryRegion
, 1);
704 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
705 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
706 mmio_reg
, base_mmio
, size_mmio
);
707 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
709 /* Map IO port space */
710 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
712 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
713 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
716 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
717 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
718 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
719 "compatible", "pci-host-ecam-generic");
720 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "pci");
721 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#address-cells", 3);
722 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#size-cells", 2);
723 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "bus-range", 0,
726 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "msi-parent", vbi
->v2m_phandle
);
728 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
729 2, base_ecam
, 2, size_ecam
);
730 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "ranges",
731 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
732 2, base_pio
, 2, size_pio
,
733 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
734 2, base_mmio
, 2, size_mmio
);
736 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "#interrupt-cells", 1);
737 create_pcie_irq_map(vbi
, vbi
->gic_phandle
, irq
, nodename
);
742 static void create_platform_bus(VirtBoardInfo
*vbi
, qemu_irq
*pic
)
747 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
748 MemoryRegion
*sysmem
= get_system_memory();
750 platform_bus_params
.platform_bus_base
= vbi
->memmap
[VIRT_PLATFORM_BUS
].base
;
751 platform_bus_params
.platform_bus_size
= vbi
->memmap
[VIRT_PLATFORM_BUS
].size
;
752 platform_bus_params
.platform_bus_first_irq
= vbi
->irqmap
[VIRT_PLATFORM_BUS
];
753 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
755 fdt_params
->system_params
= &platform_bus_params
;
756 fdt_params
->binfo
= &vbi
->bootinfo
;
757 fdt_params
->intc
= "/intc";
759 * register a machine init done notifier that creates the device tree
760 * nodes of the platform bus and its children dynamic sysbus devices
762 arm_register_platform_bus_fdt_creator(fdt_params
);
764 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
765 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
766 qdev_prop_set_uint32(dev
, "num_irqs",
767 platform_bus_params
.platform_bus_num_irqs
);
768 qdev_prop_set_uint32(dev
, "mmio_size",
769 platform_bus_params
.platform_bus_size
);
770 qdev_init_nofail(dev
);
771 s
= SYS_BUS_DEVICE(dev
);
773 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
774 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
775 sysbus_connect_irq(s
, i
, pic
[irqn
]);
778 memory_region_add_subregion(sysmem
,
779 platform_bus_params
.platform_bus_base
,
780 sysbus_mmio_get_region(s
, 0));
783 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
785 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
787 *fdt_size
= board
->fdt_size
;
792 void virt_guest_info_machine_done(Notifier
*notifier
, void *data
)
794 VirtGuestInfoState
*guest_info_state
= container_of(notifier
,
795 VirtGuestInfoState
, machine_done
);
796 virt_acpi_setup(&guest_info_state
->info
);
799 static void machvirt_init(MachineState
*machine
)
801 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
802 qemu_irq pic
[NUM_IRQS
];
803 MemoryRegion
*sysmem
= get_system_memory();
805 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
806 const char *cpu_model
= machine
->cpu_model
;
808 VirtGuestInfoState
*guest_info_state
= g_malloc0(sizeof *guest_info_state
);
809 VirtGuestInfo
*guest_info
= &guest_info_state
->info
;
813 cpu_model
= "cortex-a15";
816 /* Separate the actual CPU model name from any appended features */
817 cpustr
= g_strsplit(cpu_model
, ",", 2);
819 vbi
= find_machine_info(cpustr
[0]);
822 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
826 vbi
->smp_cpus
= smp_cpus
;
828 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
829 error_report("mach-virt: cannot model more than 30GB RAM");
835 for (n
= 0; n
< smp_cpus
; n
++) {
836 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
837 CPUClass
*cc
= CPU_CLASS(oc
);
840 char *cpuopts
= g_strdup(cpustr
[1]);
843 fprintf(stderr
, "Unable to find CPU definition\n");
846 cpuobj
= object_new(object_class_get_name(oc
));
848 /* Handle any CPU options specified by the user */
849 cc
->parse_features(CPU(cpuobj
), cpuopts
, &err
);
852 error_report_err(err
);
857 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
860 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
, "psci-conduit",
863 /* Secondary CPUs start in PSCI powered-down state */
865 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
868 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
869 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
870 "reset-cbar", &error_abort
);
873 object_property_set_bool(cpuobj
, true, "realized", NULL
);
876 fdt_add_timer_nodes(vbi
);
877 fdt_add_cpu_nodes(vbi
);
878 fdt_add_psci_node(vbi
);
880 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
882 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
886 create_gic(vbi
, pic
);
888 create_uart(vbi
, pic
);
890 create_rtc(vbi
, pic
);
892 create_pcie(vbi
, pic
);
894 /* Create mmio transports, so the user can create virtio backends
895 * (which will be automatically plugged in to the transports). If
896 * no backend is created the transport will just sit harmlessly idle.
898 create_virtio_devices(vbi
, pic
);
901 rom_set_fw(fw_cfg_find());
903 guest_info
->smp_cpus
= smp_cpus
;
904 guest_info
->fw_cfg
= fw_cfg_find();
905 guest_info
->memmap
= vbi
->memmap
;
906 guest_info
->irqmap
= vbi
->irqmap
;
907 guest_info_state
->machine_done
.notify
= virt_guest_info_machine_done
;
908 qemu_add_machine_init_done_notifier(&guest_info_state
->machine_done
);
910 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
911 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
912 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
913 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
914 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
915 vbi
->bootinfo
.board_id
= -1;
916 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
917 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
918 vbi
->bootinfo
.firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
919 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
922 * arm_load_kernel machine init done notifier registration must
923 * happen before the platform_bus_create call. In this latter,
924 * another notifier is registered which adds platform bus nodes.
925 * Notifiers are executed in registration reverse order.
927 create_platform_bus(vbi
, pic
);
930 static bool virt_get_secure(Object
*obj
, Error
**errp
)
932 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
937 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
939 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
944 static void virt_instance_init(Object
*obj
)
946 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
948 /* EL3 is enabled by default on virt */
950 object_property_add_bool(obj
, "secure", virt_get_secure
,
951 virt_set_secure
, NULL
);
952 object_property_set_description(obj
, "secure",
953 "Set on/off to enable/disable the ARM "
954 "Security Extensions (TrustZone)",
958 static void virt_class_init(ObjectClass
*oc
, void *data
)
960 MachineClass
*mc
= MACHINE_CLASS(oc
);
962 mc
->name
= TYPE_VIRT_MACHINE
;
963 mc
->desc
= "ARM Virtual Machine",
964 mc
->init
= machvirt_init
;
966 mc
->has_dynamic_sysbus
= true;
967 mc
->block_default_type
= IF_VIRTIO
;
971 static const TypeInfo machvirt_info
= {
972 .name
= TYPE_VIRT_MACHINE
,
973 .parent
= TYPE_MACHINE
,
974 .instance_size
= sizeof(VirtMachineState
),
975 .instance_init
= virt_instance_init
,
976 .class_size
= sizeof(VirtMachineClass
),
977 .class_init
= virt_class_init
,
980 static void machvirt_machine_init(void)
982 type_register_static(&machvirt_info
);
985 machine_init(machvirt_machine_init
);